DE4042522C2 - Memory cell circuit with at least two capacitors - Google Patents

Abstract

The RAM is coupled to two word lines (WL1,2) and a bit line (BL) (BL) for receiving two types of signals. It contains two capacitors (3,4) for storage of a data signal, a first switch (1) between the bit line and the first capacitor (3). It responds to a first signal on the first word line.A second switch (2) is coupled over the first switch between the bit line and the second capacitor (4), responding to the second signal on the second word line. Pref. the two switches are FETs of a given conductivity type. The memory cell circuit is formed on a semiconductor substrate, while the capacitors may contain buried and stacked capacitor units

Description

The invention relates to a memory cell. The invention is ins special to a dynamic storage device with optional Access applicable for storing data in a numbersy stem of base N is suitable.  

Fig. 6 shows a block diagram illustrating a known conventional DRAM. Such a device is e.g. As shown in IEEE 1985 International Solid-State Circuits Conference, pp. 252-253. Referring to Fig. 6, the DRAM comprises a memory array 51 having memory cells for storing data signals, a row address buffer 52 and a column address buffer 53, a memory cell is close applies the signals for selecting a row decoder 54 and a column decoder 55 signals for decoding the address , a sense amplifier 56 connected to the memory array 51 for amplifying signals stored in the memory cells, an input / output buffer 57 connected to the sense amplifier 56 for exchanging data with the environment, and one of external signals such as e.g. B. clock signals, chip select signals and read / write control signals dependent control circuit 58 for controlling the DRAM.

Fig. 6 is also a schematic diagram showing a memory cell of a conventional DRAM. Referring to Fig. 6 comprises the SpeI cherzelle a transistor 60 and a condenser 61. The gate electrode of transistor 60 is connected to a word line WL and an electrode to a bit line BL. The capacitor 61 is connected to the other electrode of the transistor 60 .

The write / read operation of the conventional DRAM will be described below with reference to FIG. 6. First, address signals for selecting a memory cell are externally applied to the row address buffer 52 and the column address buffer 53 . The address signals applied to the row address buffer 52 and the column address buffer 53 are decoded by the row decoder and the column decoder, respectively. As a result, a word line and a bit line are defined and a memory cell is thus selected. When writing, an externally created input data is written into the memory cell via the input / output buffer 57 . More specifically, transistor 60 turns on in response to a signal on word line WL and the charges on the selected bit line are stored in capacitor 61 , completing the write operation. When reading, as with writing, a word line is defined as a function of an externally applied address signal and the memory cell storing the data is selected. The transistor 60 then switches in response to the signal on the word line WL and the charges in the capacitor 61 are transferred to the bit line BL. The change in the potential on the bit line BL is amplified by the sense amplifier 56 . The stored charges are read out as output data via the input / output buffer 57 .

In the conventional dynamic RAM shown in Fig. 6, a memory cell includes a transistor and a capacitor as described above. Therefore, only two levels, ie, H level and L level, of the data can be processed. A method for storing three or more different charge levels in a memory cell has therefore been proposed. Namely, by controlling the voltage for writing to a memory cell so that the voltage has three or more different levels, three or more different data can be stored in one capacitor. By providing memory cells with a transistor and a capacitor in the DRAM, data processing for base N can thus be implemented, as z. B. in IEEE 1988 Custom Integrated Circuits Conference, pp. 4.4.1-4.4.4. According to this method, however, it is very difficult to write data to a capacitor at three or more different levels. A circuit for dividing a signal voltage into three or more signal levels must be created to write data. This makes the circuitry as a whole complicated.

From IBM TDB, Volume 18, No. 5, October 1974, pages 1356, 1357 known, signals with more than two levels by FETs with ver process different threshold voltages.

If the data registration with one in three or more span voltage level divided signal voltage is executed Reading the data more difficult than in the event that the signal voltage is divided into two voltage levels.

The object of the invention is therefore to create a device with the data represented in a system based on N, in a simple manner without complicated circuitry in the memory dynamic memory cell with random access can be saved, including the accuracy when reading data should be improved.

The object is achieved by the memory cell according to the claim 1 solved.

Advantageous further developments are in the dependent claims wrote.  

In operation, three or more different data can be in one Memory cell can be stored without a circuit for Control the voltage level of the data signals to be written is required because each of the memory cells of dynamic RAM two or more transistors and two or more capacitors includes.

The following is a description of exemplary embodiments with reference to the figures. From the figures show:

Fig. 1 is a schematic diagram of a memory cell in a DRAM according to a first embodiment of the invention;

Fig. 2 is a block diagram showing an example of a DRAM to which the memory cell of Fig. 1 is applied;

Fig. 3A, 3B are timing charts showing a write Opera tion of the memory cell shown in Fig. 14;

FIGS. 4A, 4B are timing diagrams illustrating a read operation of the memory cell shown in Fig. 1;

Fig. 5 is a block diagram showing the state of the memory cell when reading the output data from the memory cell shown in Fig. 1; and

Fig. 6 is a block diagram of a conventional DRAM, and a memory cell of this DRAMs.

Referring to Fig. 1 includes the memory cell transistors 301 and 302 and capacitors 303 and 304. One electrode of transistor 301 is connected to bit line BL and its gate electrode is connected to word line WL. The gate electrode of transistor 302 is connected to the word line WL and an electrode to the transistor 301 . Capacitors 303 and 304 are connected to the other electrode of transistors 301 and 302 , respectively. The threshold voltage Va of the transistor 301 and the threshold voltage Vb of the transistor satisfy the following equation (1).

0 <Va <Vb <5 [V] (1)

Referring to Fig. 2 includes the DRAM, a memory array 306 having memory cells for storing data signals, a row address buffer 52 and a column address buffer 53, the address signals for selecting a memory cell to be created, a row decoder 54 and a column decoder 55 for decoding the address signals, a driver 305 , which is dependent on the signals decoded by the row decoder 54 and a word line voltage control signal for controlling the voltage on the word line, a sense amplifier 307 connected to the memory array 306 for amplifying the signals stored in the memory cells, one with the sense amplifier 307 connected input / output buffer 57 for exchanging data with the environment, a bit line voltage control circuit 8 , which is connected to the input / output buffer 57 and is dependent on the data signals input from the input / output buffer 57 , for controlling the voltage to be applied to the bit line , a tax circuit which is control signal dependent on external signals such as a clock signal, a chip select signal, a read / write 9, for controlling the DRAM, and a word line voltage control circuit 310, depending on the signals from the control circuit 9 and the input / output buffer 57 for applying a word line voltage control signal to driver 305 .

The write operation will now be described with reference to Figs. 1, 2, 3A and 3B. A memory cell is determined as a function of an externally applied address signal. Two alternative write processes are prepared for the write operation. One of the two writing processes is selected on the basis of the input data. More specifically, a first processing group of the input data +2, 0 and -2 or a second processing group of the input data +1 and -1 is selected depending on the input data. A different write operation is carried out in each group.

Namely, if the date to be written is +2, 0 or -2, the date is stored in the first processing group according to the write operation shown in Fig. 3A in the following manner. In the first cycle, the driver 305 shown in FIG. 2 controls the voltage Vwl on the word line WL to a level defined by the following inequality ( 2 ) in response to the rise of the signal and the word line voltage control signal from the word line voltage control circuit 310 .

Va <Vb Vwl (2)

Then falls off. Transistors 301 and 302 both turn on and capacitors 303 and 304 are both charged with the electrical charges of the same H or L level.

In the second cycle, the signals and fall again. Depending on the signal and the voltage control signal from the word line voltage control circuit 301 , the driver 305 controls the voltage Vwl on the word line WL to a level defined by the following inequality ( 3 ).

Va Vwl <Vb (3)  

In this case, only transistor 301 turns on and only capacitor 303 is charged with the H or L level electric charges. In the first and second cycles, the electric charges for charging the capacitors 303 and 304 are controlled by the bit line voltage control circuit 8 as in the first embodiment depending on the data signals input from the input / output buffer 57 .

The write operation of the corresponding data will now be described. If the input data is +2, the bit line BL is set to the H level in response to the drop of the signal in the first cycle. As a result, the two capacitors 303 and 304 are both charged with the H level charges. In the second cycle, bit line BL is set to H level in response to the drop in signal. In this case, since only the transistor 301 is turned on, only the capacitor 303 is charged with electrical charges of the H level. In this way, if the input date is +2, both capacitors 303 and 304 are charged with H-level electric charges.

If the input data is 0, the bit line BL is set to H or L level in response to the drop of the signal in the first cycle. As a result, capacitors 303 and 304 are both charged with L or H level electrical charges. If the H-level has been stored in the first cycle, the bit line BL is set to the H-level in the second cycle in response to the drop in the signal. As a result, capacitor 303 is charged with L level charges. If charges of the L level have been stored in the first cycle, the bit line BL is set to the H level. As a result, capacitor 303 is charged with H level charges. If the input date is 0, the capacitors 303 and 304 are each charged with charges of different levels.

If the input data is -2, the bit line BL is set to the L level in both the first and the second cycle, in contrast to the case in which the data is +2. As a result, capacitors 303 and 304 are charged with L-level charges.

If the data to be written is -1 or +1, that is, in the second processing group, the data is processed according to the write operation shown in Fig. 16B. Namely, in the first cycle, the voltage Vwl on the word line WL is controlled by the word line voltage control circuit 301 in a range defined by the following inequality ( 3 ) in response to the drop of the signal and the voltage control signal.

Va Vwl <Vb (3)

The signal then drops. Only transistor 301 switches through and only capacitor 303 is charged with electrical charges of the H or L level. In the second cycle the signals and fall again. Depending on the signal and the voltage control signal from the word line voltage control circuit 310 , the driver 305 controls the voltage Vwl on the word line WL to a level defined by the following inequality ( 3 ).

Va Vwl <Vb (3)

In this case, as in the first cycle, only transistor 301 turns on. As a result, as in the first cycle, capacitor 303 is charged with electrical charges of the same level (H or L level). The charges for charging the capacitors 303 and 304 are controlled by the bit line voltage control circuit 8 in response to the data signals input from the input / output buffer 57 .

Now the write operation of the respective input data is described. If the input data is +1, the bit line BL is set to the H level in response to the drop of the signal in the first cycle. In this case, only transistor 301 turns on, so that only capacitor 303 is charged with the H-level charges. In the second cycle, bit line BL is set to H level in response to the signal drop, and only capacitor 303 is charged with the H level charges.

If the input data is -1, the bit line BL is set to the L level in response to the drop of the signal in the first cycle. As a result, only the capacitor 3 is charged with the charges of the L level. In the second cycle, bit line BL is set to L level in response to the drop in signal and only capacitor 303 is charged with L level charges. In this way, data is stored in the capacitor 303 if the input date is +1 or -1.

As described above, data +2, +1, 0, -1 and -2 are stored in the memory cells of FIG. 1. In contrast, a write flag indicating whether the write process for the first or second group has been used for the data is stored in a separately prepared memory area (not shown). The read operation is carried out according to the write flag stored during the write operation.

FIG. 4A is a timing chart showing the read operation if the issue date is +2, 0, or -2 (ie, the process for the first group), and FIG. 4B is a timing chart showing the read operation if that Issue date is +1 or -1 (that is, the process for the second group). The reading operation will now be described with reference to Figs. 1, 2, 4A and 4B. With reference to Figure 4A, the read operation is described if the issue date is +2, 0, or -2, that is, if the write flag indicates the process for the first group. Depending on an externally applied address signal, a memory cell is selected. Read control signals and are applied from the outside. According to the write flag stored during the write and in response to the drop of the signal, the voltage Vwl on the word line is set to a level determined by the following inequality ( 2 ).

Va <Vb Vwl (2)

In this case, transistors 301 and 302 both turn on. As a result, the charges in capacitors 303 and 304 are applied to bit line BL. In response to the drop in the signal, the voltage on the bit line BL is read out via the sense amplifier 307 . If the output date is +2, the voltage on the bit line BL reaches V5 as shown in Fig. 4A (a). If the output date is 0, the voltage on the bit line BL reaches V3 as shown in (c) and (d) of Fig. 4A. If the output date is -2, the voltage on the bit line BL becomes V1 as shown in (f).

Referring to Fig. 4B, the readout operation in the case that the output date is +1 or -1 will be described, that is, if the write flag indicates the process for the second group. A memory cell is determined as a function of an externally applied address signal. Read control signals and are applied from the outside. In response to the drop of the signal and the write flag stored during the write, the voltage Vwl on the word line WL is controlled into the range defined by the following inequality ( 3 ).

Va Vwl <Vb (3)

In this case, only transistor 301 turns on. When transistor 301 is turned on, the charges in capacitor 303 are applied to bit line BL. In response to the drop in the signal, the voltage on the bit line BL is read out via the sense amplifier 307 . If the output date is +1, the voltage on the bit line BL becomes V4 as shown in (b) of Fig. 4B. If the output date is -1, the voltage on the bit line BL becomes V2 as shown in (e) of FIG. 4B. In this way, only the charges stored in the capacitor 303 are read out when the output date is +1 or -1.

As shown in Fig. 5, the voltage Vwl on the word line WL is controlled to be higher than when the output date is +2, 0 or -2, that is, in a process of the first group the threshold voltages Va of transistor 301 and Vb of transistor 302 , so that the conditions in the two capacitors 303 and 304 are read out. In contrast, the voltage Vwl of the word line WL is controlled so that when the output date is +1 or -1, that is, for a process of the second group, that it is higher than the threshold voltage Va of the transistor 301 and lower than that Threshold voltage Vb of the transistor 302 is, so that only the transistor 301 is turned on, whereby only the charges of the capacitor 303 are read out. As described above, the charges of the capacitor 304 are not read out if the output date is +1 or -1. Therefore, the issue date is not affected by whether the charges in capacitor 304 are at H or L level.

In the described embodiment, as with the first off five different data into the memory cells of the dynamic RAMs can be written or read from it. It can be used to process data that has been processed in the binary system be processed in a four or five system, whatever the data processability remarkably improved.

In the described embodiment, there are two methods for realizing the relationship between the threshold voltage Va of transistor 301 and the threshold voltage Vb of transistor 302 (0 <Va <5 [V]). One is a method of increasing the threshold voltage Vb by matching the impurity dose to the channel region of transistor 302 . In the other method, the threshold voltage Va of the transistor 301 is reduced by shortening the gate length of the transistor 301 compared to that of the transistor 302 , whereby the effect of a short channel is used.

In the embodiment, if the data to be stored is +2, 0 or -2, the word line potential is set to a value higher than the threshold voltage of the transistors 301 and 302 as shown in FIG. 3A. As a result, the charges corresponding to the respective date are stored in the two capacitors 303 and 304 . If the data to be stored is +1 or -1, the word line potential is controlled to be higher than the threshold voltage of transistor 301 and lower than the threshold voltage of transistor 302 , as shown in FIG. 3B. As a result, the charges corresponding to the respective date are only stored in the capacitor 303 . As described above, no circuit is required to convert the five different data into five corresponding different voltage levels, so that data shown in the five system can be easily stored in the memory cell. In other words, each memory cell of a dynamic random access memory device comprises two or more transistors and two or more capacitors, so that a memory cell circuit of a dynamic random access device which is capable of storing three or more different data in a memory cell, can be created in a simple way.

Claims (3)

1. A dynamic RAM memory cell, which is connected to a word line (WL) and a bit line (BL) and receives a signal with a first and a second signal level from a word line control device, having a first and a second capacitance device ( 303 , 304 ) for storing a data signal, a first switching device ( 301 ) connected between the bit line (BL) and the first capacitance device ( 303 ), which switches on depending on the first signal level on the word line (WL), and one via the first switching device ( 301 ) between the bit line (BL) and the second capacitance device ( 304 ) connected second switching device ( 302 ), which also turns on depending on the second signal level on the word line (WL). 2. Memory cell according to claim 1, characterized in that the first and the second switching device comprises a first and a second field effect transistor ( 1 , 2 ) of a certain Lei device type. 3. The memory cell of claim 1 or 2, characterized in that a first line electrode of the first Feldef fekttransistors (301) generating electrode to the bit line (BL), a second Lei the first field effect transistor (301) with which it most capacitor (303) and a control electrode of the first field effect transistor ( 301 ) is connected to the word line (WL), and a first line electrode of the second field effect transistor ( 302 ) is connected to the second line electrode of the first field effect transistor ( 301 ), a second line electrode of the second field effect transistor ( 302 ) is connected to the second capacitor ( 304 ) and a control electrode of the second field effect transistor ( 302 ) to the word line (WL).