DE3739481A1 - Method for obtaining a frame clock in electrical communications - Google Patents

Abstract

The invention relates to a method for obtaining a frame clock (RT) from a line signal (s) and from a sampling clock (AT) in electrical communications, the line signal (s) consisting of a sequence of frames, each frame exhibiting a number (z) of symbols, a sequence of some of these symbols forming a frame alignment word. From the line signal (s) and a stored nominal frame alignment word, a correlator output signal (w mu ) is obtained which is used for synchronising a modulo-z counter via further method steps. The method should be applicable to two-wire lines with arbitrary polarisation. For this purpose, the correlator output signal (w mu ) monitors for a positive and a negative threshold value. When the transmission path exhibits a pulse response with a first extreme value and a second extreme value, the extreme values having different polarity from one another, the modulo-z counter is to be synchronised to the first extreme value. This is achieved by using a time window in accordance with the further development according to Claim 2 (Figure 1). <IMAGE>

Description

The invention relates to a method for obtaining a Frame clock from an input signal and from a Sampling clock in electrical communications technology according to the The preamble of claim 1. Such a method is out German Patent 32 27 151 known.

In electrical communications technology digital signals transmitted from a transmitter to a receiver by each combined several symbols into a frame become. In the example described in DE-PS 32 27 151 Such a frame comprises 108 symbols. A series of one Part of these symbols represents a frame code word. The other symbols are used to transmit the actual Message, the payload. The frame code word points a specific symbol pattern. The same symbol pattern is stored in the receiver as a target frame code word.

In order to properly recover the payload in the receiver, a sampling clock and a frame clock is needed. The sampling clock is generated in a receiver-side clock synchronization circuit. The period is such that each symbol is sampled at least once. The frame clock is obtained by counting the periods of the sample clock. With only one sample of each symbol, that is, if the sample clock is equal to the symbol clock, this count is done by modulo z- counting, where z equals the number of symbols in a frame.

The frame clock must have a fixed phase position relative to the Have frame identifier words, d. h., it has to be synchronism consist. From the above-mentioned document it is known to from the received signal in the receiver and the Set frame code word to form a correlation signal and to evaluate its amplitude by looking for maxima. It however, it does not specify how these maxima are searched.

Due to interference, a frame code word can be falsified that it is not more than such is recognized. Furthermore, outside the Frame Identifier words occur at random symbol patterns that simulate the receipt of a frame code word. Both Cases should not disturb an existing synchronism. If no synchronism is reached, the second should Case pretend no synchronism.

Transmitter and receiver are via a two-wire cable connected. For the signal transmitted over the line, the Line signal, a ternary code is used. It facilitates assembly and maintenance when working on the line itself and when connecting the line to the Transmitter and the receiver the wires arbitrarily among themselves or with the respective terminals on the transmitter and the Receiver can connect.

The invention is based on the object, a method of above type, which also occasionally occurring falsified or simulated Frame identifier words and at any connection of the two Veins the wire works properly.  

This task is characterized by the characterizing features of Claim 1 solved.

A method for obtaining a frame clock, in which a received signal with a desired frame code word is compared in the book: Hölzler, Holzwarth, Pulstechnik, Volume II, Springer-Verlag 1976 pp 77 to 81 described. However, there will be regenerated by one Input signal, which only the logical values yes or no has assumed. The comparison does not happen Cross-correlation. It is known from this document in itself the results from such a comparison in one Result counter (there called left-right shift register) to count.

German Auslegeschrift 30 32 296 is also concerned with the acquisition of a frame clock, there Called block synchronization. It is a correlator there provided and a threshold detector, which the Correlator output signal with only one threshold compares.

The essay by Robert A. Scholtz, "Frame Synchronization Techniques" in the journal IEEE TRANSACTIONS ON COMMUNICATIONS; VOL. COM-28, NO. 8, AUGUST 1980, pages 1204 to 1212, also deals with the acquisition of a frame clock. The line signal is sampled according to FIG . In a correlator consisting of a shift register, some multipliers and an adder, a correlator output signal is obtained. This is evaluated in a threshold value circuit (TRESHOLD).

With the task to achieve a perfect function even when Vernevertauschung, already the German patent application 33 33 714. However, the solution described there is very expensive. Thus, two circuits for detecting the maxima and two modulo for counter are provided there.

The transmission path can be an impulse response with a Extreme value of the first kind and a following extreme value second type. Under "transmission path" is the Line including in the transmitter and in the receiver located modules for analog signal processing, such as z. As hybrid circuits, transformers, filters understood. The Further development according to claim 2 also ensures this a perfect synchronization.

The claim 3 teaches an advantageous development.

The invention will be described with reference to the figures Examples explained, where the following assignment applies:

First, Fig. 1 will be described. In it mean:

E : an input for a line signal s , A : a scanner, s _μ: a sampled line signal, SP : a memory for a desired frame code word, K : a correlator, w _μ : a correlator output, SD : a threshold detector, SDA : an output of the threshold detector, ZST : a counter control, EZ : a result counter, Z _on , Z _off : Control inputs of the result counter, RS : a reset control, RASYN : an output for a frame sync signal, APh : an evaluation phase control, ÜT : a line for a monitoring clock, RZ : a frame counter, R , T : a reset or clock input, G : a clock synchronization circuit, AT : a line for the sampling clock, RT : a line for a frame clock, ATA , RTA : one output for the sampling or frame clock.

The line signal s is sampled in the sampler A in the sampling clock AT . The analog samples thus obtained are digitized, ie converted into data words consisting of several bits. This produces the sampled line signal s _μ , which is thus represented by a sequence of such data words.

In the memory SP , the target frame code word is stored. In the correlator K , the correlator output signal w _{μ is} formed from the sampled line signal s _μ and the desired frame code word. This is also represented by a sequence of discrete-time values, each time-discrete value being represented by a data word consisting of several bits.

The correlator output _signal w _μ enters the threshold value detector SD . It will be described with reference to FIG. 2. In it mean:

SW 1 , SW 2 : one memory each for a positive and a negative threshold,
V 1 , V 2 : a first and a second comparator.

The two comparators have the same structure. Such a comparator works as follows: If a higher value is present at its input E 2 than at its input E 1 , its output VA emits a yes signal.

In the first comparator V 1 , the positive threshold value is input to the input E 1 and the correlator output _signal w _{μ is} supplied to the input E 2 . Its output VA thus outputs a yes signal if the correlator output signal exceeds this positive threshold. In contrast, in the second comparator V 2, the correlator output _signal w _{μ is} supplied to the input E 1 and the negative threshold value to the input E 2 . Accordingly, its output VA outputs a yes signal when the correlator output signal w _μ falls below the negative threshold.

The outputs VA of the two comparators are connected via an OR circuit 11 to the output SDA . This output thus leads to a yes signal if the correlator output signal either exceeds the positive threshold value or falls below the negative threshold value. The outputs + SW and - SW are described in connection with FIG .

The amplitude of the correlator output signal w _μ is a measure of the correspondence of the respective received symbol sequence and the desired frame code word. By means of the threshold value detector SD , the correlator output _signal w _{μ is} then monitored as to whether it expresses correspondence between the desired frame code word and the respective symbol sequence. The correlator output signal is thus also monitored for exceeding a positive threshold value and for falling below a negative threshold value, whereby both exceeding and falling short of the respective received symbol sequence with the target frame code word applies. Such a match can mean the following:

• a) a frame code word was sent on the transmission side, and this one was recognized right here, or
• b) in the payload, a symbol sequence appeared, the one Frame code word has faked. So it became one Pseudo frame code recognized.

By analogy, mismatch can mean:

• a) no frame code word was sent, or
• b) although a frame code word was sent because of a disturbance on the line or Intersymbol interference, however, has been falsified so far that it could no longer be recognized as such.

By applying a correlator and a positive and a negative threshold, the required independence of the polarity of the wires of the line is achieved. In the case of a wire exchange, the sign of the correlator output signal changes, ie, either the positive threshold value is exceeded or the negative threshold value is undershot. By the OR circuit 11 , a yes signal is then obtained at the output SDA in any case.

These yes or no signals at the output SDA are the results of monitoring the correlator output signal w _μ for correspondence between the desired frame code word and the respective symbol sequence. These results are counted in the result counter EZ (see Fig. 1). This counter has a basic position 0, a maximum position NR and several intermediate positions, of which only the positions 1, 2, NR " and NR 'are designated. He can count up and down. With a YES signal to the control input _on Z or Z _ab is incremented by one step up or down respectively. It may also be provided that not only is counted by one step but equal to several steps, wherein the number of steps in the count up can be different from the counting down.

After the device has been put into operation, the result counter EZ is in the basic position 0. Counting up means counting away from the basic position in the direction of maximum position NR . Count down accordingly means counting toward the home position. If the result counter is already in the basic position, yes signals on the control input Z _{ab are} ineffective. The same applies mutatis mutandis to the maximum position NR .

Whether the result counter counts up or down is determined by the counter control ZST . It consists of two AND circuits 12 and 13 and an inverter 14th However, if the monitoring cycle UT has yes level reaches the control input _Z, or Z _from a yes signal, on Z _to at a yes signal on output SDA or on Z _off in a no-signal at the output SDA ,

The frame counter RZ is a constantly circulating in the direction of the arrow, z positions having ring counter. There is therefore a modulo for counter. The number z is equal to the number of symbols in a frame. About the clock input T of the sampling clock AT is supplied. Whenever the sampling clock AT has a yes level, the frame counter goes from one position to the next. The individual positions are designated as follows:

z -1: initial position z -2, etc., 5,4,3,2,1: intermediate positions 0: end position

The end position 0 is connected to the line for the frame clock RT . As a result, the frame clock RT always assumes yes level when the frame counter is in the end position 0. Because the control of the sampling clock AT can also say that the frame clock RT is obtained by modulo z-counting the sampling clock.

A yes signal at the reset input R puts the frame counter RZ in its initial position z -1. Such a reset signal is generated in the reset control RS when the result counter EZ changes from the basic position 0 to the position 1. That is, if the starting position is left 0 in the result count in the modulo z-counting is changed to the initial position.

The monitoring clock UT is generated in the evaluation phase controller APh . It consists of two AND circuits 15 and 16 and of the OR circuit 17th The AND circuit 15 is connected to the basic position 0 of the result counter. If the result counter is in its basic position 0, then the monitoring clock ÜT is equal to the sampling clock AT , and the correlator output signal w _μ is thus monitored in the sampling clock AT . This condition is called a search phase.

If the result counter EZ has left the basic position 0, the monitoring clock UT assumes only yes level via the AND circuit 16 if the frame clock RT and the sampling clock AT have a yes level. This condition is called the test phase, and it monitors the correlator output in the frame clock.

At the beginning of a signal transmission, the search phase is effective. With the first recognized in her frame code word is switched to the test phase. If frame recognition words are now recognized again, the result counter first reaches the positions NR " and NR ' and finally its maximum position NR . About the output RASYN the frame sync signal is delivered in these positions to not subscribed modules. This has the meaning that synchronism is achieved.

If individual frame code words are not recognized in the test phase, then the result counter counts towards the basic position. However, since the number of unrecognized frame identifier words is likely to be smaller than the number of recognized frame identifier words, the result counter still reaches its maximum NR .

If the first frame code word recognized in the search phase is a pseudo frame code word, the test phase is also switched over. However, it is unlikely that there will be enough pseudo frame recognition words in the frame clock right now to let the result counter reach its maximum NR . Rather, he will reach the basic position again.

About the outputs RTA and ATA the frame clock or the sampling clock is delivered to the not shown here assemblies for obtaining the payload.

The method described above works satisfactorily if the impulse response of the transmission path has only one extreme value. However, the transmission path can also have an impulse response with an extreme value of the first type and a second value following this extreme value. Such an impulse response is shown in FIG . The extreme value of the first type is designated EW 1 . The extreme value of the second type is denoted by EW 2 and has a reverse polarity to that of the first type.

With a suitable choice of the frame code word, the correlator output signal approximately reproduces the impulse response of the transmission path. As a result, as shown in FIG. 4, the correlator output signal likewise has two extreme values in each case. A digital correlator is assumed, ie the correlator output signal is represented as a result of time-discrete values w _μ . Furthermore, the representation is highly idealized in that all signal components caused by the payload have been omitted. Thus, the correlator output signal has extreme values of the first type EW 1 at the times t ₁ and t ₃ and extreme values of the second type EW 2 at the times t ₂ and t ₄. Since the frame code word is sent in the frame clock, the respective extreme values also occur with the period duration T _{R of} the frame clock. Furthermore, the positive threshold value SW 1 and the negative threshold value SW 2 are shown.

With such a correlator output, the frame counter must be synchronized with the extreme values of the first type. This succeeds with a method according to claim 1 imperfect, as the following consideration shows. For this purpose, it is assumed that the search phase between the times t ₂ and t ₃ starts and the extreme value of the second kind EW 1 at the time t ₃ due to intersymbol interference or a fault the associated threshold, here SW 2 , not above or below. The first detected by the threshold detector threshold crossing occurs so at the time t ₄, and it is now switched to the test phase. As extreme values of the second type occur again and again in the frame cycle, the result counter finally reaches its maximum position. However, the frame counter is undesirably synchronized with the extreme values of the second kind.

The same may occur if the extreme value of the second type at the time t ₃, although sufficiently large, but the search phase begins between the times t ₃ and t ₄.

This unwanted synchronization with the extreme values of the second type is avoided by a method according to claim 2. A corresponding circuit arrangement is shown in FIG. 5.

It differs from the circuit arrangement according to FIG. 1 as follows:

• a) A second evaluation phase control APh 2 is provided.
• b) Some assemblies have been modified according to the following table:

Through the OR circuit 21 and the connection of their inputs with the intermediate positions 2, 3 and 4 of the frame counter RZ ' a time window ZF is determined during the test. It includes the time during which the frame counter is in intermediate positions 2, 3 or 4.

The second evaluation phase control APh 2 has three signal outputs A 1 to A 3 , via which the result counter EZ controlled upwards or downwards and the monitoring clock ÜT can be suppressed. It is also connected via a bidirectional connection A 4 with the reset control RS ' . Thus, the aforementioned functions can be controlled in dependence on the position of the result counter EZ ; and the frame counter RZ ' can be set to its initial position z -1 depending on functions of the second evaluation phase control.

During the time window ZF second Auswertephasensteuerung APh 2 monitors the outputs + SW and - SW of the threshold SD in sampling, where two cases are important:

• a) The + SW output carries a yes signal during the ZF time window, after the output - SW Yes signal has passed during the last monitoring clock pulse or
• b) The output - SW carries a yes signal during the time window ZF after the output + SW has carried yes signal during the last monitoring clock pulse.

Due to the above functions, so happens Monitoring the correlator output signal during the Time window in sampling clock, the time window only during the test phase is effective.

If any of the above cases a) or b) has been recognized, the following happens:

• c) Via the output A 3 and the AND circuit 20 , the monitoring clock is suppressed during the next frame clock pulse, ie, in the subsequent test phase, the first monitoring fails
• d) via the output A 2 and the OR circuit 19 , the result counter is controlled by a position down. It is therefore counted towards the basic position. If you change from position 1 to basic position 0, the following happens:
  • d1) The reset control RS ' sets the frame counter RZ' in its initial position z -1, and
  • d2) the result counter EZ is immediately put back into position 1. However, the frame counter RZ 'is not put back into its initial position.

The functions c), d) and optionally also d1) and d2) become only once within the same time window executed after the cases were first identified a) and b).

The above-mentioned functions will be described in detail with reference to FIGS . 6a to 6c. These figures are placed next to each other, starting on the left with 6a. These figures again show in the first line, as in FIG. 4, the correlator output _signal w _μ and the threshold values SW 1 and SW 2 . The second line shows the monitoring clock ÜT . The next two lines represent the signal levels at the outputs + SW and - SW . The next line indicates the respective position of the frame counter RZ ' . In this case, boxes without specifying a counter position mean that here the frame counter can assume any desired counter positions, that is, it still runs without a specific phase position to the correlator output signal w _μ .

In the next line is indicated by a hatched block the respective position of the time window. In further lines of the frame clock and the signal level of the outputs A 1 , A 2 and A 3 are given. The output A 3 almost always has a yes signal and only a short no signal.

In Fig. 6a, the time t ₅ is shown at which between the reception of frame identifier words, the search phase begins, ie, the monitoring clock ÜT is equal to the sampling clock. At the next reception of a frame code word due to intersymbol interference, the extreme value of the first type is formed only slightly, so that the associated threshold value SW 2 is not fallen below (time t ₆). So the next threshold crossing takes place at the extreme value of the second kind, ie at time t ₇. The result counter EZ counts from its basic position 0 to position 1, and the frame counter is set to its initial position z -1. The search phase is over, and now the test phase is in effect.

Upon receipt of the next frame code word ( FIG. 6b, left), the extreme value of the first type does not coincidentally fall short of the associated threshold value SW 2 again at time t ₈. Only at the time t ₉ is the threshold value SW 1 exceeded by the extreme value of the second type. The frame counter RZ ' and the frame clock RT are thus synchronized with the extreme value of the second kind. The result counter EZ counts from 1 to 2.

Only at the next frame code word of the extreme value of the first kind during the time window ZF the associated threshold SW 2 is undershot (time t ₁₀), and at the output A 2 , a yes signal occurs. As a result, the result counter EZ counts from 2 to 1. During the next frame clock pulse (time t ₁₁), the output A 3 no-level. As a result, the evaluation of the threshold crossing is suppressed by the extreme value of the second type and the result counter maintains its position.

During the next frame code word ( FIG. 6 c, left), the threshold value SW 2 is again undershot during the time window ZF , time t ₁₂. By means of the yes signal at the output A 2, the result counter EZ counts from 1 to its basic position 0. As a result, the frame counter RZ 'is set to its initial position z -1. He is properly synchronized with that. So that now does not start the search phase again, the result counter EZ is then offset by a yes signal at the output A 1 back to the position 1 (time t ₁₃).

The correct synchronization of the frame counter RZ ' is clearly shown in Fig. 6c, right. The frame clock RT coincides desirably with the extreme value of the first kind (time t ₁₅). During the time window ZF (time t ₁₄) no threshold is exceeded or fallen below. The result counter EZ counts from 1 to 2. When receiving further frame code words, it first reaches the positions NR " and NR ' and finally the maximum position NR .

The fact that a threshold overshoot or undershoot first controls the result counter during the time window has the following meaning: If, as shown in FIG. 6c on the right, synchronism is achieved, threshold overruns or undershoots can nevertheless occur during the time window if the payload randomly occurs a symbol sequence primes a frame code word. But this should not disturb the achieved synchronism.

The time window is measured according to the impulse response of the transmission path. As shown to the right in FIG. 6b, the samples of the extreme value of the first kind must fall within the time window when the frame counter is synchronized to the extreme value of the second kind. Accordingly, the intermediate positions of the frame counter to be connected to the OR circuit 21 must be determined.

Claims (4)

A method for obtaining a frame clock (RT) from a line signal (s) and from a sampling clock (AT) in electrical engineering, wherein the line signal (s) consists of a sequence of frames, each frame having a number (z) of symbols in which a sequence of a part of these symbols form a frame code word, having the following features:

• a) From the line signal (s) and a stored nominal frame code word, a correlator output signal ( w _μ ) is obtained by correlation.
• b) The correlator output signal ( w _μ ) is then monitored as to whether it expresses correspondence between the desired frame code word and the respective symbol sequence.
• c) The correlator output signal ( w _μ ) is monitored for exceeding of a positive threshold value ( SW 1 ) and below a negative threshold value ( SW 2 ), whereby both overshoot and undershoot are considered as coincidence.
• d) The monitoring of the correlator output signal is done in a search phase in the sampling clock (AT) and in a test phase in the frame clock (RT) .
• e) The results of the monitoring of the correlator output signal ( w _μ ) are counted in a result count, starting with a basic position.
  • e1) If a match has been found, it is counted away from the home position.
  • e2) If mismatch has been detected, it is counted towards the basic position.
  • e3) In the initial position the search phase is effective, otherwise the test phase is effective.
• f) The frame clock is obtained by a modulo z-counting the sampling clock, where z is equal to the number of symbols in a frame.
• g) will leave the basic position in the result of counting, so the modulo z-counting is changed to an initial position (z -1).

The generic term forms the features a, b and f. The remaining features form the characterizing part. 2. The method according to claim 1, characterized by the following features:

• h) During the test phase, a time window (ZF) is provided during which the monitoring takes place in the sampling clock (AT) .
  • h1) The time window (ZF), during at least one intermediate position (2, 3, 4) the modulo z-counting effective.
  • h2) If an overshoot or undershoot of a threshold value is detected for the first time during the time window (ZF) and this overshoot or undershoot compared to the immediately preceding overshoot or undershoot detected during a frame clock pulse ( z = 0) has reverse polarity, then the following process steps are carried out:
    • h2a) In the result count is counted towards the basic position. Herein, if the home position is reached, in the z modulo-counting is changed to the initial position (z -1).
    • h2b) In the next following test phase, the first monitoring fails.

3. The method according to claim 2, characterized by the following features:

• i) The method steps h2a) and h2b) are executed only once within the same time window, namely after the first determination of an overshoot or undershoot.