DE3736387A1 - NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Google Patents

Description

The invention relates to a non-volatile Semiconductor memory device and in particular one erasable, programmable read-only memory.

It has already become an erasable, programmable Read-only memory proposed (which is subsequently called "EPROM" is referred to) in which each Memory cell transistor a "double gate arrangement" one Has sliding gates (floating gates) and a control gate, which over a Channel area are arranged side by side. At this type of EPROM has been proposed to gain access to make memory by using the functions of Source and drain the two diffusion layers of each Memory cell between a data write mode and a Data reading mode were reversed. In particular, the  first diffusion layer, which acts as a drain in data write mode serves as the source in data read mode, while the second diffusion layer, which acts as the source in data write mode serves as a drain in data read mode. At the Access to the memory cell can increase the efficiency of the Reading and writing data improves and occurrence can be suppressed by the functions of Source and drain of a cell transistor between the data read and data write mode can be switched.

However, when using such an access technology neither of the two diffusion layers of each Cell transistor with a common connecting line get connected. This forces the use of a "Double bit line arrangement" in an EPROM that has two Diffusion layers of each cell transistor with independent bit lines. In this case must have contact holes separate for the two diffusion layers each cell are provided and these diffusion layers should be through the contact holes with the first and the second bit line to be connected separately run on a chip substrate. This leads to difficulties in designing the optimal wiring pattern for the Memory cells on the substrate and at the same time one undesirable increase in cell area. The complex Wiring patterns deteriorate the access speed of the EPROM.

The invention is therefore based on the object of a new one and improved non-volatile semiconductor memory device to create the excellent data reading and  Has data write characteristics and their element Space requirements were kept to a minimum to improve the density of indications.

To solve the tasks listed above The invention relates to a memory cell arrangement for a non-volatile semiconductor memory that a A semiconductor substrate of a first conductivity type; a first and second semiconductor diffusion layers one second conduction type that is removed on the substrate are formed from each other, the first and second Semiconductor diffusion layer reversed as source and Drain the memory cell array between one Data write mode and a data read mode of the Semiconductor memory are used; a first senior Layer that is applied in an insulated manner over the substrate, to serve as a sliding gate, the information representing Carrier stores; and a second conductive layer, the insulated above the substrate is attached to act as a control gate to serve.

According to the invention, the memory cell arrangement is thereby characterized that they also a Power supply device comprising the first and second diffusion layer and the second conductive layer is connected to in one of the data write and Data reading modes of the first and second diffusion layers to supply a bias voltage while a ground voltage is initially introduced into the second conductive layer, and to select a memory cell by the bias at the second diffusion layer is changed to itself  to approximate the ground voltage, so that a voltage potential is kept unchanged on the second diffusion layer, constant around the preload maintain even when the memory cell array is selected, whereby the first diffusion layer on a common connection line together with the assigned first diffusion layers of the other Memory cells of the semiconductor memory are connected can.

Both in data write mode and in data read mode of a semiconductor memory while the second Conductor layer is initially supplied with ground potential, the first and second diffusion layers with a Provide preload. The memory cell is selected by biasing the second diffusion layer is reduced. The potential at the first Diffusion layer does not change, but keeps it input preload constant when the Memory cell is selected. Hence the first Diffusion layer together with first diffusion layers from other memory cells of the semiconductor memory be connected to a common connecting line, whereby the above, on which the invention is based Task is solved.

More preferred in the description below Embodiments of the invention are based on the Reference to drawings; it shows  

Fig. 1 is a schematic representation of the plane structure of an essential part of a conventional EPROMs,

Fig. 2 is a cross-sectional view of the conventional EPROM shown in Fig. 1, taken along the line II-II,

Fig. 3 is a schematic representation of the plane structure of an essential part of an EPROM according to the first embodiment of the invention,

Fig. 4 is a sectional view of the EPROM of Fig. 3, taken along the line IV-IV,

Fig. 5A to 5D are diagrams showing equivalent circuits constitute a substantial portion of the EPROM of the first embodiment for explaining the data write and data read mode, this EPROMs,

FIGS. 6 and 7 characteristic curves representing the outstanding data write characteristics of the EPROM of the first embodiment,

Fig. 8 is a schematic representation of the plane structure of an essential part of an EPROM according to the second embodiment of the invention,

Fig. 9 is a cross-sectional view of the EPROM of Fig. 8 taken along the line IX-IX,

FIG. 10A to 10D are circuit diagrams indicating the equivalent circuits of an essential part of the EPROM in the second embodiment for explaining the data write and data read mode, this EPROMs,

Fig. 11 is a schematic view showing the planar structure of an essential portion of an EPROM according to the third embodiment of the invention,

Fig. 12 is a cross-sectional view of the EPROM of Fig. 11, taken along the line XII-XII,

Fig. 13 is a schematic representation of the plane structure of an essential part of an EPROM according to the fourth embodiment of the invention,

Fig. 14 is a cross-sectional view of the EPROM of Fig. 13, taken along the line XIV-XIV, and

Fig. 15 to 17 are sectional views respectively showing modifications of the memory cell array of EPROM according to the invention.

The preferred embodiments will now be described in detail. Before an erasable, programmable read-only memory or EPROM according to the present invention is explained, a known EPROM is explained with reference to FIGS. 1 and 2 in order to facilitate an understanding of the arrangement according to the invention. (In Fig. 1, the insulating layers are omitted for the sake of schematic simplification.)

Fig. 2 shows the cross section of a memory cell of the known EPROM. Two heavily doped semiconductor diffusion layers of the n-type (n⁺-type) ( 2, 3 ) are arranged on a silicon substrate of a p-type spaced apart. A sliding gate electrode ( 4 ) and a control gate electrode ( 5 ) are insulated from the substrate ( 1 ). These gate electrodes ( 4, 5 ) consist of polycrystalline silicon and are essentially self-aligned with the diffusion layers ( 2, 3 ).

Contact holes ( 7, 8 ) are provided separately for the first and second diffusion layers ( 2, 3 ) in an insulating layer ( 6 ) which covers the gate electrodes ( 4, 5 ). As can be seen from FIG. 1, the first and the second diffusion layer ( 2, 3 ) are connected to two separate bit lines (Ba, Bb) via the contact holes ( 7, 8 ). In FIG. 1, word lines (W) run over the substrate ( 1 ) and cross the first and second bit lines (Ba, Bb) with appropriate insulation.

To write data into this memory cell, the first diffusion layer ( 2 ) is used as the drain and the second diffusion layer ( 3 ) as the source. If the first diffusion layer ( 2 ) and the control gate ( 5 ) are supplied with a positive voltage, hot carriers (in this case electrons) are generated by impact ionization on the drain side of a channel region (CH) . Some of these electrons are detected by the sliding gate ( 4 ) to store binary bit data.

In the data read mode of this memory cell, in reverse to the case of the data write mode, the first diffusion layer ( 2 ) is used as the source and the second diffusion layer ( 3 ) as the drain. If a suitable voltage (for example +3 V) is applied between the source and drain, the control gate ( 5 ) is supplied with a proper readout voltage (for example +3 V). At this point, it is determined which logic level "1" or "0" the stored data bit has by detecting whether or not a current flows between the source and drain.

The reason below is given as to why the source and drain of a cell transistor are reversed between the data write and the data read mode when accessing the memory cell. Since data writing uses initiation of hot carriers into the sliding gate ( 4 ), the writing efficiency can be improved by placing the first diffusion layer ( 2 ) close to the sliding gate ( 4 ), which stores the carriers to serve as a drain. If, however, this first diffusion layer ( 2 ) is also used as a drain in the data reading mode, a cell current initially flows in an undesirable manner if no carriers are stored in the sliding gate ( 4 ), in order to thereby cause shock ionization on the drain side of the channel region (CH) cause, which leads to an unintentional write in the memory cell. Furthermore, the sliding gate ( 4 ) which stores the carriers moves away from the source, so that it is difficult to determine the logic level "1" or "0" of the stored data bit. This can cause the memory to malfunction. In contrast, in the data reading mode, if the first diffusion layer ( 2 ) is used as the source, the space between the sliding gate ( 4 ) and source can be reduced. Therefore, if a depletion layer expands in the reverse direction as a result of operation, the efficiency of the data readout can be improved on the drain side of the channel region (CH) at the time the data is read out.

When using the access technology listed above, which involves switching the source and drain in an EPROM, it is not possible to connect one of the two diffusion layers ( 2, 3 ) in a fixed manner to a common wiring line. This is because the potential of each diffusion layer is to be changed between the idle state and the cell select state in each mode of operation. To overcome this difficulty, conventional EPROMs mostly use the "double bit line arrangement", in which these diffusion layers ( 2, 3 ) are connected separately to the first and second bit lines (Ba, Bb) according to FIG. 1. In this case, it is necessary to provide two types of bit lines on the substrate and two separate contact holes ( 7, 8 ) for each memory cell, which complicates the cell layout and wiring patterns and increases the area requirement for the elements. This leads to a deterioration in the access speed and the integration density of the EPROM.

The known difficulties listed above can be effective by the invention, below explained EPROMs can be overcome.

FIGS. 3 and 4 illustrate an EPROM according to a first embodiment of the invention. Fig. 3 shows the planar structure of an essential part of the EPROMs, wherein insulating layers are omitted merely for the sake of diagrammatic simplicity. Fig. 4 shows a cross section of Fig. 3 along the line IV-IV. In Fig. 4, two adjacent memory cells are formed on a silicon substrate ( 10 ) of a p-conduction type. Two heavily doped diffusion layers ( 12, 14 ) of the n-conductivity type (n ⁺ type) are formed in a memory cell with a given space between them. A control gate ( 16 ) and a sliding gate ( 18 ) are arranged insulated above the substrate ( 10 ). As shown, these gates ( 16, 18 ) are attached in parallel. The gate layers ( 16, 18 ), which consist of polycrystalline silicon, are essentially self-aligned with diffusion layers ( 12, 14 ).

As shown in Fig. 3, the control gate ( 16 ) extends elongated across a series of memory cells to form a word line (W) . The sliding gate ( 18 ) is independent in each memory cell. The manufacturing process for the control gate ( 16 ) and the parallel sliding gate ( 18 ) is described, for example, in the article "A New EPROM Cell With A Side-Wall Floating Gate For High-Density And High-Performance Device" by Yoshihisa Mizutani and Kohi Makita, International Electron Devices Meeting, Washington, DC, December 1985, pages 636-637 (Fig. 3).

An insulating layer ( 20 ) is applied to the substrate ( 10 ) in such a way that the gate layers ( 16, 18 ) are embedded in the insulating layer ( 20 ). A contact hole ( 22 ) is formed in the insulating layer ( 20 ). The first diffusion layer ( 12 ) is connected to an elongated diffusion layer ( 24 ) which is formed in the substrate ( 10 ) and serves as a common wiring line (C) . The diffusion layer ( 24 ) as a common wiring line is commonly connected to the first diffusion layers ( 12 ) of all memory cells (including those not shown in Fig. 3), which are provided on the substrate ( 10 ). (Only three memory cells are shown in FIG. 3, so that only that section of the common wiring line (C) in the substrate ( 10 ) that runs parallel to the word line (W) is shown.) The second diffusion layer ( 14 ) is electrically over the contact hole ( 22 ) is connected to a metal layer ( 26 ) formed on the insulating layer ( 20 ) and insulates the common wiring line (C) , crosses and serves as an EPROM. It is pointed out that in this memory cell the control gate ( 16 ) is arranged close to the first diffusion layer ( 12 ) which is connected to a diffusion layer ( 24 ) which serves as a common connecting line (C) , while the sliding gate ( 18 ) is close to the second diffusion layer ( 14 ) which is connected to the bit line (B) .

Referring to Figs. 5A to 5D, the operation of the thus-constructed EPROM of the first embodiment for data write / read using the "source / drain reversal" access method will be explained below. Each representation of FIG. 5A to 5D shows an equivalent circuit of four memory cells of the EPROM shown in Fig. 3. The equivalent circuits clearly illustrate that the first diffusion layers ( 12 ) of all memory cells are connected to the common connecting line (C) . FIG. 5A shows the application of a voltage to the word lines (W) , the bit lines (B) and the common connecting line (C) in the idle state (initial state) in the data write mode of the EPROM. Fig. 5B shows the application of a voltage to the word lines (W) , the bit lines (B) and to the common connection line (C) in the cell selection state in the data write mode. FIG. 5C shows the application of a voltage to the word lines (W), the bit lines (B) and the common connecting line (C) in the rest state (initial state) in the data write mode of the EPROM. Fig. 5D shows the application of a voltage to the word lines (W) , the bit lines (B) and the common connection line (C) in the cell selection state in the data read mode. In FIGS. 5A to 5D are the "" mark to each memory cell transistor constituting a character is added to, where the Gleitgate (18) is located.

In the data write mode of the EPROM (the mode in which data bits with either a logical "1" or "0" are electrically written into a selected memory cell), the first diffusion layer ( 12 ), which is connected to the common connecting line (C) , used as a source and the second diffusion layer ( 14 ) is used as a drain. In the idle state of the data write mode, the ground potential (0 volt) is applied to all bit lines (Bi) (i = 1, 2, ...) , All word lines (Wj) (j = 1, 2, ... ) And the common wiring line ( C) placed as indicated in Fig. 5A. In this state, positive voltages (Vdp, Vgp) are applied to the bit line (B 1 ) and the word line (W 1 ), for example, to select a memory cell. As a result, the positive voltages (Vdp, Vgp) are respectively applied to the second diffusion layer ( 14 ) (which serves as a drain) and to the control gate (see Fig. 4) of the selected memory cell, and hot carriers (electrons in this embodiment) become in the vicinity of the second diffusion layer ( 14 ) of the channel region (CH) (see FIG. 4) and then injected into the sliding gate ( 18 ) and collected there. This stores the data in the sliding gate ( 18 ) of the selected memory cell with respect to the voltage. (As shown in Figs. 5A and 5B, the common lead (C) is kept at the ground voltage during the waiting state and the cell selection state of the writing mode.)

In the data read mode of the EPROM (the mode in which data bits with either a logical "1" or "0" are read electrically from a selected memory cell), the functions of the first diffusion layer ( 12 ) connected to the common connecting line (C ) and the Reverse second diffusion layer ( 14 ) in the above data writing mode: The first diffusion layer ( 12 ) now serves as a drain and the second diffusion layer ( 14 ) serves as a source. In the waiting state of the data read mode, the ground potential (0 volt) according to FIG. 5C is supplied to all word lines (Wj) (j = 1, 2, ...) . At this time, the bit lines (Bi) (i = 1, 2,...) And the common connecting line (C ) are supplied with a positive voltage (Vdr) which is higher than the ground voltage by a given level. The potential of the bit line (B 1 ) that is present at the selected memory cell (a target object for access for data reading) is reduced from (Vdr) to ground potential (or 0 volts) and at the same time the word line (W 1 ) connected to the selected memory cell raised from the ground potential (0 volts) to a positive voltage (Vgr) , then the second diffusion layer ( 14 ) (which now serves as the source) of the selected memory cell is connected to ground so that its control gate ( 16 ) (see FIG. 4 ) receives positive voltage (Vgr) . As a result, the data stored in the selected memory cell is read out. In the data readout process, the logic level of the data bits stored in the selected cell is determined by determining whether the potential of the bit line (B 1 ) lowered to ground potential maintains or increases its potential, i. h, whether there is a current flow between the first and second diffusion layers ( 12, 14 ) or not (according to FIGS. 5C and 5D, the common connecting line (C) is at the positive voltage (Vdr ) held).

In the embodiment constructed and operated in the manner described above, all bit lines (Bi) are initially brought up to the positive voltage (Vdr) in the rest position of the data read mode , and the cell selection takes place by the potential of a desired bit line being at ground potential is lowered. Therefore, in the data write and data read modes, using the "source / drain reverse" access method, it is possible to eliminate the need to change the potential of the first diffusion layer ( 12 ) of each memory cell between the idle state and the cell select state of each of the two modes . In other words, in the quiescent state and in the cell selection state of the data write mode, the potential of the first diffusion layer ( 12 ) (which serves as the source) of the memory cell can be set to ground potential (0 volt), while in the quiescent state and cell selection state of the data reading mode the potential of the layer ( 12 ) (which serves as a drain ) can stay at the positive voltage (Vdr) . This means that the first diffusion layers ( 12 ) of all memory cells of the EPROM can be connected together to the common connecting line (C) . Therefore, in contrast to the known EPROM shown in FIGS. 1 and 2, the EPROM according to the invention does not need to use a "double bit line arrangement".

This eliminates the need to provide separate vias ( 7, 8 in Fig. 2) in the first and second diffusion layers ( 12, 14 ) of each memory cell and can reduce the amount of bit lines required, thereby significantly reducing the area of the device used by the device EPROMs and a simplification of the wiring pattern is guaranteed. This effect can be easily understood by a simple visual comparison between the planar arrangements shown in FIGS. 1 and 3.

Further, according to the invention, since the potential of the diffusion layer pattern ( 24 ), which serves as a common connecting line (C) , does not change in any operating mode during the idle state and the cell selection state, the access speed can be improved. This is because if the potential of the common lead pattern ( 24 ), which generally has a relatively high capacitance and high resistance, changes between the idle state and the cell select state, charging and discharging on the common lead pattern ( 24 ) is inevitable. occurs, which affects a high-speed access process.

It is pointed out that in the EPROM according to the invention the control gate ( 16 ) of each memory cell is close to the first diffusion layer ( 12 ) which is connected to the common connecting line (C) . It can therefore be expected that the efficiency for writing data carriers will increase.

This is because, due to the positional relationship between the control gate ( 16 ) and the sliding gate ( 18 ) shown in Fig. 4 and the use of the above-mentioned voltage supply method for cell access, which was explained in connection with Figs. 5A to 5D, the Substrate voltage (Vsub) can be reduced exactly to 0 volts in data write mode . This phenomenon is explained in more detail below. In the data write mode, the first diffusion layer ( 12 ) of each memory cell is connected to ground potential with that of the other memory cells. At this time, the bias voltage corresponding to the threshold voltage of the transistors constituting an accompaniment selection circuit is maximally prevented from being added to the substrate voltage (Vsub) . Therefore, the substrate voltage (Vsub) can be lowered exactly to 0 volts. As a result, the voltage tolerance can be increased. This allows a larger drain current to be supplied to the selected memory cell and a larger amount of hot carriers to be supplied to the sliding gate.

Attention is drawn to the following: since, in the data reading mode, the potential of the second diffusion layer (which serves as the source) of the selected memory cell is reduced to ground level, as explained above, according to the invention, a negative bias voltage is applied to the substrate ( 10 ) due to the presence of the bit line selection circuit and the substrate voltage (Vsub) is lowered to correspondingly have a negative voltage level.

However, this fact also contributes to the Improve the write characteristics of the EPROM because of this The process serves to improve the writing efficiency.

The above-mentioned effects according to the invention are supported by the curves of FIGS. 6 and 7, which represent measured values for the write characteristic. In each curve, the horizontal coordinate represents the time required to write data into an n-channel memory cell, while the vertical coordinate represents the ratio (Iw / Iini) of the cell current (Iw) flowing after the data was written to the initial cell current ( Iini) before entering the data. In the experiments, the write gate voltage (Vgp) and the write drain voltage (Vdp) were each set to 8 volts and the read gate voltage (Vgr) was 3 volts each. The width (Wmask) and the length (Lmask) of a memory cell mask were set to 2.0 µm and 1.0 µm, respectively. It is evident from Fig. 6 that when the substrate voltage (Vsub) of the EPROM is set to 0 volts (see the curve whose measurements are marked with "o" ), the data write time is the shortest. Likewise, it is evident from FIG. 7 that the data writing process takes place fastest when the substrate voltage (Vsub ) is strongly negatively biased at the time of reading out the data (see the curve marked " Δ "). This means that a negative bias of the substrate voltage (Vsub) in the data read mode is preferable in view of the improvement of the write characteristic obtained.

FIGS. 8 and 9 illustrate an EPROM according to the second embodiment of the invention. Fig. 8 shows the planar structure of the essential portion of the EPROM, and Fig. 9 shows a cross section of Fig. 8 taken along the line IX-IX. In In these illustrations, the same reference numerals are used to denote components which correspond to or are similar to those of the first embodiment, so that their explanation can be omitted.

According to the second embodiment according to FIG. 9, the sliding gate ( 18 ) of each memory cell is arranged near the first diffusion layer ( 12 ), which is connected to the diffusion layer ( 24 ), which serves as a common connecting line (C) , and the control gate ( 16 ) is arranged close to the second diffusion layer ( 14 ) which is connected to the bit line (B) . The access method according to the invention described above can also be used with an EPROM which has memory cells with the structure shown.

In the idle state of the data write mode, since the positional relationship between the control gate ( 16 ) and the sliding gate ( 18 ) of the second embodiment is reversed from that of the first embodiment, the bit lines (B 1 , B 2 ,...) And the common connecting line ( C ) supplied with a positive high voltage (Vdp) according to FIG. 10A. At this point in time, the word lines (W 1 , W 2 ,...) Are at ground potential. As a result, the first diffusion layer ( 12 ) in the memory cell, which serves as a drain this time, is at the positive voltage (Vdp) , while the second diffusion layer as source is also at the positive voltage (Vdp) . In the cell selection state, the bit line (for example (B 1 )) connected to the desired memory cell is grounded and at the same time the potential of the word line (for example (W 1 )) connected to this memory cell is raised to the positive voltage (Vgp) . As a result, hot carriers are injected into the sliding gate ( 18 ) of the selected memory cell and accumulated there for writing data.

In the idle state of the data reading mode, all bit lines (B 1 , B 2 ,...), Word lines (W 1 , W 2 ,...) And the common connecting line (C) are connected to ground potential according to FIG. 10C. As a result, the first (serving as source) diffusion layer ( 12 ) and the second (serving as drain) diffusion layer ( 14 ) of each memory cell are grounded. In Zellenzählzustand Fig invention. 10D, the potential of the associated with the desired memory cell bit line (for example, (B 1)) to the positive voltage (VGR), starting from ground potential is raised while the potential of the associated with this memory cell word line (for example, ( W 1 )) raised to the positive voltage (Vgr) . As a result, the hot carriers stored in the sliding gate ( 18 ) of the selected memory cell are read out. At this time, the logic level of the read data is determined by determining whether the potential of the bit line (B 1 ) remains at (Vdr) or decreases to the ground level.

Reference is now made to FIGS. 11 and 12, in which an EPROM according to the third embodiment is shown in which each memory cell has a laminated (or divided) double-gate arrangement. FIG. 12 shows the cross section of the planar arrangement according to FIG. 11 along the line XII-XII, which has two adjacent cells. Referring to FIG. 12, a silicon substrate (50) having a p-conduction type. A first and a second diffusion layer ( 52, 54 ) of the n⁺ conductivity type are formed on the substrate ( 50 ). A n-type diffusion layer ( 53 ) is formed in the substrate surface area between these diffusion layers ( 52, 54 ) so as to be connected to the first diffusion layer ( 52 ), thereby forming a "lightly doped drain arrangement (LDD)" is obtained. (The substrate surface area forms a channel area (CH) .) Above the channel area (CH) of the substrate ( 50 ) there is an insulated sliding gate layer ( 58 ) over which an isolated control gate layer ( 56 ) is stacked.

An insulating layer ( 60 ) is applied to the substrate ( 50 ) in such a way that it covers the control gate ( 56 ) and the sliding gate ( 58 ). The control gate ( 56 ) extends over a series of memory cells to form a word line (W) . The sliding gate ( 58 ) is independent in each cell. The insulating layer ( 60 ) is formed over the second diffusion layer ( 54 ) with a contact hole ( 62 ). The first diffusion layer ( 52 ) is connected to an elongated diffusion layer ( 64 ) of the n-conductivity type, which is formed on a surface area of the substrate ( 50 ) and serves as a common connecting line (C) . A second diffusion layer ( 54 ) is connected via the contact hole ( 62 ) to a linear, conductive layer ( 66 ) which is formed on the insulating layer ( 60 ) and serves as a bit line (B) .

The EPROM designed in this way in accordance with the third embodiment is operated using the access technology for the data write / read process already described in connection with FIGS. 5A to 5D. The above arrangement can provide an EPROM with high integration density and high performance, that is, an EPROM which has an excellent data write / read characteristic and a high access speed.

According to a fourth embodiment, shown in FIGS . 13 and 14, each memory cell with a laminated double gate arrangement has a first and a second diffusion layer ( 52, 54 ) which are arranged in reverse localization compared to the third embodiment. In particular, the first diffusion layer ( 52 ) and the layer ( 53 ) of the n-type are connected to a layer ( 66 ) which serves as a bit line (B) , while the second diffusion layer ( 54 ) is connected to the layer ( 64 ), which serves as a common write line (C) . The other portion of the arrangement of the fourth embodiment is the same as that of the third embodiment. Access to the EPROM of the fourth embodiment for the data write / read operation takes place using the access method already described in connection with FIGS. 10A to 10D. This arrangement can provide an EPROM with high integration density and high performance, that is, an EPROM which has an excellent data write / read characteristic and a high access speed.

Although the invention is related to a specific Embodiment has been described, it is for the skilled person obvious that countless changes are possible which includes within the scope of the claims of the invention will.

For example, the memory cell having the laminated double gate arrangement according to the third and fourth embodiments can be modified in various ways as described below. According to the modification shown in Fig. 15, the second diffusion layer of each memory cell consists of a lamination of a diffusion layer ( 52 ' ) of an n⁺-type and a diffusion layer ( 53' ) of an n-type. The diffusion layer ( 52 ′ ) of the n⁺-conduction type has an impurity concentration of 10 ¹⁹ to 10 ²⁰ / cm ³ and the diffusion layer ( 53 ′ ) of the n-conduction type has an impurity concentration of approximately 10 ¹⁷ / cm ³ . According to a further modification shown in FIG. 16, the second diffusion layer of each memory cell consists of a diffusion layer ( 70 ) of an n + conductivity type, which is flatter than the first diffusion layer ( 52 ). According to another modification shown in FIG. 17, the second diffusion layer of each memory cell consists of a conductive layer ( 72 ) made of metal or metal silicide deposited on the substrate ( 50 ). This conductive layer ( 72 ) forms a Schottky junction between itself and the silicon substrate ( 50 ).

In all of the foregoing embodiments, a p-type substrate is used, but an n-type substrate may also be used. In this case, only the polarity of the bit lines (B) , the word lines (W) and the common connecting line (C) need to be reversed for the memory access compared to the information in the preceding description.

Claims (17)

A memory cell arrangement for a non-volatile semiconductor memory, which comprises a semiconductor substrate of a first conductivity type ( 10, 50 ); first and second semiconductor diffusion layers ( 12, 14; 52, 54 ) of a second conductivity type, which are formed on the substrate at a distance from one another, the first and second semiconductor diffusion layers being used conversely as the source and drain of the memory cell arrangement between a data write mode and a data read mode of the semiconductor memory ; a first conductive layer ( 18, 58 ) insulated over the substrate ( 10, 50 ) to serve as a sliding gate that stores information-bearing media; and a second conductive layer ( 16, 56 ) insulated over the substrate ( 10, 50 ) to serve as a control gate, characterized in that the device further comprises a voltage supply device (B, W, C) associated with the first and second diffusion layers ( 12, 14; 52, 54 ) and the second conductive layer ( 16, 56 ) are connected to one in one of the data writing and data reading modes of the first and second diffusion layers ( 12, 14; 52, 54 ) Supplying bias voltage (Vdr, Vdp) while introducing a ground voltage to the second conductive layer ( 16, 56 ) and selecting a memory cell by changing the bias voltage (Vdr, Vdp) on the second diffusion layer ( 14, 54 ), to approximate the ground voltage so that a voltage potential on the second diffusion layer ( 12, 52 ) is kept unchanged in order to maintain the preload voltage (Vdr, Vdp) supplied constantly, even when the memory cell arrangement is out e is selected, whereby the first diffusion layer ( 12, 52 ) can be connected to a common connecting line together with the assigned first diffusion layers of the other memory cells of the semiconductor memory. 2. Memory cell arrangement according to claim 1, characterized in that the first and second conductive layers ( 12, 14 ) are arranged in parallel over the substrate. 3. Memory cell arrangement according to claim 2, characterized in that in the data reading mode of the semiconductor memory, the voltage supply device (B, W, C) supplies a bias voltage (Vdr) to the first and second diffusion layers ( 12, 14 ), while initially a ground voltage to the second conductive layer ( 16 ) and the bias voltage (Vdr) on the second diffusion layer ( 14 ) is lowered to select the memory cell, whereby a potential of the first diffusion layer ( 12 ) is kept fixed on the bias voltage (Vdr) when the memory cell is selected. 4. Memory cell arrangement according to claim 1, characterized in that in the data write mode of the semiconductor memory, the voltage supply device (B, W, C) introduces a ground voltage to the first and second diffusion layer ( 12, 14 ) and the second conductive layer ( 16 ) and the voltage level changes on the second diffusion layer ( 14 ) and the second conductive layer ( 16 ) to select the memory cell, wherein a potential of the first diffusion layer ( 12 ) is kept fixed on the ground voltage when the memory cell is selected. 5. Memory cell arrangement according to claim 4, characterized in that the first conductive layer ( 18 ) is arranged close to the first diffusion layer ( 12 ), and that the second conductive layer ( 16 ) is close to the second diffusion layer ( 14 ). 6. Memory cell arrangement according to claim 2, characterized in that in the data write mode of the semiconductor memory, the voltage supply device (B, W, C) to the first and second diffusion layer ( 12, 14 ) applies a bias voltage (Vdp) and initially to the second conductive layer ( 16 ) applies a ground voltage and lowers the bias voltage (Vdp) on the second diffusion layer ( 14 ) in order to select the memory cell, a potential of the first diffusion layer ( 12 ) being kept fixed on the bias voltage (Vdp) when the memory cell is selected. 7. Memory cell arrangement according to claim 6, characterized in that in the data read mode of the semiconductor memory, the voltage supply device (B, W, C) introduces a ground voltage to the first and second diffusion layer ( 12, 14 ) and the second conductive layer ( 16 ), and the voltage level on the second diffusion layer ( 14 ) and the second conductive layer ( 16 ) to select the memory cell, keeping a potential of the first diffusion layer ( 12 ) fixed at the ground voltage when the memory cell is selected. 8. Memory cell arrangement according to claim 7, characterized in that the first conductive layer ( 18 ) is close to the first diffusion layer ( 12 ) and that the second conductive layer ( 16 ) is close to the second diffusion layer ( 14 ). 9. The memory cell arrangement as claimed in claim 1, characterized in that the first and second conductive layers ( 56, 58 ) are stacked in an insulated manner above the substrate ( 50 ). 10. A memory cell arrangement according to claim 9, characterized in that the first active layer comprises a heavily doped semiconductor diffusion layer ( 52, 52 ' ) of the second conductivity type and a lightly doped semiconductor diffusion layer ( 53, 53' ) of the second conductivity type. 11. Memory cell arrangement according to claim 10, characterized in that the heavily doped semiconductor layer ( 52 ' ) and the lightly doped semiconductor layer ( 53' ) are stacked isolated in the substrate ( 50 ). 12. A semiconductor cell arrangement according to claim 9, characterized in that the first and second semiconductor layers comprise first and second diffusion layers ( 54, 70 ) which are arranged at different depths. 13. The memory cell arrangement according to claim 9, characterized in that the first semiconductor layer comprises a metal layer ( 72 ) formed on the substrate ( 50 ) in order to form a Schottky transition zone between the metal layer and the substrate. 14. Non-volatile semiconductor arrangement with a semiconductor substrate ( 10, 50 ) of a first conductivity type, parallel bit lines (B) arranged on the substrate ( 10, 50 ) , parallel word lines (W) which isolate the bit lines (B) on the substrate ( 10, 50 ) and memory cells formed on the substrate ( 10, 50 ) so as to be connected to the crossing points between the bit lines (B) and the word lines (W) , each memory cell having first and second semiconductors diffusion layer ( 12, 14; 52, 54 ) of the second conductivity type, which are formed on the substrate at a certain distance from one another and which are used in reverse as a source and drain between a data write mode and a data read mode of the semiconductor arrangement, with a sliding gate layer ( 18, 58 ), which is arranged in isolation above the substrate ( 10, 50 ) to store data-representing carriers, and with a control gate layer ( 15, 56 ) which is isolated arranged above the substrate ( 10, 50 ) and connected to one of the word lines (W) , characterized in that the arrangement further comprises a third diffusion layer ( 24, 64 ) of the second conductivity type provided on the substrate ( 10, 50 ) to serve as a common connection line (C) , that the first diffusion layer ( 12, 52 ) is connected to the common connection line and that the second diffusion layer ( 14, 54 ) is connected to one of the bit lines (B) , and that a Voltage supply device ( 24, 26, 64, 66 ) is connected to the memory cells to preliminarily supply the bit lines (B) and the common connection line (C) with a bias voltage (Vdr, Vdp) while the word lines (W) are in a data write mode or data read mode of the memory array are grounded, and to select a desired memory cell by lowering the voltage supplied to that bit line connected to the desired memory cell t. 15. Memory cell arrangement according to claim 14, characterized in that the sliding gate layer ( 18 ) and the control gate layer ( 16 ) are arranged in parallel over the substrate ( 10 ). 16. Memory cell arrangement according to claim 15, characterized in that the sliding gate layer ( 18 ) is close to the second diffusion layer ( 14 ) and that the control gate layer ( 16 ) is close to the first diffusion layer ( 12 ). 17. Memory cell arrangement according to claim 14, characterized in that the control gate layer ( 56 ) is stacked in isolation over the sliding gate layer ( 58 ).