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DE3783418D1 - Verfahren zur herstellung einer halbleiterschaltung mit hoher durchbruchspannung. - Google Patents

Verfahren zur herstellung einer halbleiterschaltung mit hoher durchbruchspannung.

Info

Publication number
DE3783418D1
DE3783418D1 DE8787114619T DE3783418T DE3783418D1 DE 3783418 D1 DE3783418 D1 DE 3783418D1 DE 8787114619 T DE8787114619 T DE 8787114619T DE 3783418 T DE3783418 T DE 3783418T DE 3783418 D1 DE3783418 D1 DE 3783418D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor circuit
breakthrough voltage
high breakthrough
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787114619T
Other languages
English (en)
Other versions
DE3783418T2 (de
Inventor
Yutaka C O Patent Divi Koshino
Yoshiro C O Patent Divisi Baba
Jiro C O Patent Divisi Ohshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3783418D1 publication Critical patent/DE3783418D1/de
Publication of DE3783418T2 publication Critical patent/DE3783418T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE8787114619T 1986-10-07 1987-10-07 Verfahren zur herstellung einer halbleiterschaltung mit hoher durchbruchspannung. Expired - Fee Related DE3783418T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61238388A JPS6393153A (ja) 1986-10-07 1986-10-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3783418D1 true DE3783418D1 (de) 1993-02-18
DE3783418T2 DE3783418T2 (de) 1993-05-27

Family

ID=17029453

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787114619T Expired - Fee Related DE3783418T2 (de) 1986-10-07 1987-10-07 Verfahren zur herstellung einer halbleiterschaltung mit hoher durchbruchspannung.

Country Status (4)

Country Link
US (1) US4780426A (de)
EP (1) EP0263504B1 (de)
JP (1) JPS6393153A (de)
DE (1) DE3783418T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529329A (ja) * 1991-07-24 1993-02-05 Canon Inc 半導体装置の製造方法
JP2748898B2 (ja) * 1995-08-31 1998-05-13 日本電気株式会社 半導体装置およびその製造方法
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
US6806197B2 (en) * 2001-08-07 2004-10-19 Micron Technology, Inc. Method of forming integrated circuitry, and method of forming a contact opening
US8106487B2 (en) 2008-12-23 2012-01-31 Pratt & Whitney Rocketdyne, Inc. Semiconductor device having an inorganic coating layer applied over a junction termination extension
JP5452062B2 (ja) * 2009-04-08 2014-03-26 三菱電機株式会社 炭化珪素半導体装置の製造方法
JP5223773B2 (ja) 2009-05-14 2013-06-26 三菱電機株式会社 炭化珪素半導体装置の製造方法
EP3046149B1 (de) * 2013-09-09 2019-08-21 Hitachi, Ltd. Halbleiterbauelement, verfahren zur herstellung davon, stromwandlervorrichtung, drehstrommotorsystem, fahrzeug und schienenfahrzeug
CN113178385B (zh) * 2021-03-31 2022-12-23 青岛惠科微电子有限公司 一种芯片的制造方法、制造设备和芯片

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3834953A (en) * 1970-02-07 1974-09-10 Tokyo Shibaura Electric Co Semiconductor devices containing as impurities as and p or b and the method of manufacturing the same
FR2154294B1 (de) * 1971-09-27 1974-01-04 Silec Semi Conducteurs
JPS5538823B2 (de) * 1971-12-22 1980-10-07
US4060427A (en) * 1976-04-05 1977-11-29 Ibm Corporation Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
GB1548520A (en) * 1976-08-27 1979-07-18 Tokyo Shibaura Electric Co Method of manufacturing a semiconductor device
JPS5388579A (en) * 1977-01-13 1978-08-04 Nec Corp Production of semiconductor device
JPS5671933A (en) * 1979-11-19 1981-06-15 Toshiba Corp Impurity diffusion to semiconductor substrate
JPS5795625A (en) * 1980-12-04 1982-06-14 Toshiba Corp Manufacture of semiconductor device
JPS57124427A (en) * 1981-01-26 1982-08-03 Toshiba Corp Manufacture of semiconductor device
JPS5831519A (ja) * 1981-08-18 1983-02-24 Toshiba Corp 半導体装置の製造方法
DE3219888A1 (de) * 1982-05-27 1983-12-01 Deutsche Itt Industries Gmbh, 7800 Freiburg Planares halbleiterbauelement und verfahren zur herstellung
JPS59210666A (ja) * 1983-05-16 1984-11-29 Nec Corp 半導体装置
JPS60117765A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd 半導体装置の製造方法
JPS6151912A (ja) * 1984-08-22 1986-03-14 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US4780426A (en) 1988-10-25
JPS6393153A (ja) 1988-04-23
DE3783418T2 (de) 1993-05-27
JPH0467781B2 (de) 1992-10-29
EP0263504A3 (en) 1989-10-18
EP0263504B1 (de) 1993-01-07
EP0263504A2 (de) 1988-04-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee