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DE3675120D1 - Verfahren zur zeichnung eines musters auf einer halbleiterplatte mittels geladenes teilchenstrahls. - Google Patents

Verfahren zur zeichnung eines musters auf einer halbleiterplatte mittels geladenes teilchenstrahls.

Info

Publication number
DE3675120D1
DE3675120D1 DE8686306579T DE3675120T DE3675120D1 DE 3675120 D1 DE3675120 D1 DE 3675120D1 DE 8686306579 T DE8686306579 T DE 8686306579T DE 3675120 T DE3675120 T DE 3675120T DE 3675120 D1 DE3675120 D1 DE 3675120D1
Authority
DE
Germany
Prior art keywords
pattern
charged particle
semiconductor board
particle ray
ray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686306579T
Other languages
English (en)
Inventor
Osamu C O Patent Divis Ikenaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3675120D1 publication Critical patent/DE3675120D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/302—Controlling tubes by external information, e.g. programme control
    • H01J37/3023—Programme control
    • H01J37/3026—Patterning strategy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)
DE8686306579T 1985-08-23 1986-08-26 Verfahren zur zeichnung eines musters auf einer halbleiterplatte mittels geladenes teilchenstrahls. Expired - Lifetime DE3675120D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60185530A JPS6246518A (ja) 1985-08-23 1985-08-23 荷電ビ−ム描画方法

Publications (1)

Publication Number Publication Date
DE3675120D1 true DE3675120D1 (de) 1990-11-29

Family

ID=16172412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686306579T Expired - Lifetime DE3675120D1 (de) 1985-08-23 1986-08-26 Verfahren zur zeichnung eines musters auf einer halbleiterplatte mittels geladenes teilchenstrahls.

Country Status (5)

Country Link
US (1) US4989156A (de)
EP (1) EP0213920B1 (de)
JP (1) JPS6246518A (de)
KR (1) KR900001983B1 (de)
DE (1) DE3675120D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309354A (en) * 1991-10-30 1994-05-03 International Business Machines Corporation Electron beam exposure method
US5446649A (en) * 1992-12-31 1995-08-29 International Business Machines Corporation Data-hiding and skew scan for unioning of shapes in electron beam lithography post-processing
JP3601630B2 (ja) * 1995-11-01 2004-12-15 株式会社ニコン 荷電粒子線転写方法
US6091072A (en) * 1997-10-23 2000-07-18 International Business Machines Corporation Piece-wise processing of very large semiconductor designs
JP4206192B2 (ja) * 2000-11-09 2009-01-07 株式会社日立製作所 パターン検査方法及び装置
DE19911372A1 (de) * 1999-03-15 2000-09-28 Pms Gmbh Vorrichtung zum Steuern eines Strahls aus elektrisch geladenen Teilchen
US7412676B2 (en) * 2000-06-13 2008-08-12 Nicolas B Cobb Integrated OPC verification tool
US6425113B1 (en) * 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US7861207B2 (en) * 2004-02-25 2010-12-28 Mentor Graphics Corporation Fragmentation point and simulation site adjustment for resolution enhancement techniques
US7234130B2 (en) * 2004-02-25 2007-06-19 James Word Long range corrections in integrated circuit layout designs
US7493587B2 (en) * 2005-03-02 2009-02-17 James Word Chromeless phase shifting mask for integrated circuits using interior region
US8037429B2 (en) * 2005-03-02 2011-10-11 Mentor Graphics Corporation Model-based SRAF insertion
US7506285B2 (en) 2006-02-17 2009-03-17 Mohamed Al-Imam Multi-dimensional analysis for predicting RET model accuracy
JP2008010547A (ja) * 2006-06-28 2008-01-17 Elpida Memory Inc 電子線描画方法、電子線描画装置、及び電子線描画プログラム
US7799487B2 (en) * 2007-02-09 2010-09-21 Ayman Yehia Hamouda Dual metric OPC

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132898A (en) * 1977-11-01 1979-01-02 Fujitsu Limited Overlapping boundary electron exposure system method and apparatus
EP0053225B1 (de) * 1980-11-28 1985-03-13 International Business Machines Corporation Elektronenstrahlsystem und Verwendungsverfahren
US4430571A (en) * 1981-04-16 1984-02-07 Control Data Corporation Method and apparatus for exposing multi-level registered patterns interchangeably between stations of a multi-station electron-beam array lithography (EBAL) system
JPS57204125A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Electron-ray drawing device
DD203429A1 (de) * 1981-08-03 1983-10-19 Eichhorn Hans Guenther Schaltungsanordnung zur steuerung eines korpuskularstrahls
JPS5957431A (ja) * 1982-09-27 1984-04-03 Fujitsu Ltd 電子ビ−ム露光装置
JPS59114818A (ja) * 1982-12-21 1984-07-03 Toshiba Corp 電子ビ−ムパタ−ン描画方法
JPS59125622A (ja) * 1982-12-29 1984-07-20 Fujitsu Ltd 電子ビ−ム露光方法
US4692579A (en) * 1984-05-18 1987-09-08 Hitachi, Ltd. Electron beam lithography apparatus
US4628466A (en) * 1984-10-29 1986-12-09 Excellon Industries Method and apparatus for pattern forming

Also Published As

Publication number Publication date
EP0213920B1 (de) 1990-10-24
JPS6246518A (ja) 1987-02-28
EP0213920A2 (de) 1987-03-11
KR870002639A (ko) 1987-04-06
EP0213920A3 (en) 1989-01-18
JPH0357608B2 (de) 1991-09-02
KR900001983B1 (ko) 1990-03-30
US4989156A (en) 1991-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)