DE3485520D1 - Herstellungsverfahren fuer halbleitervorrichtung. - Google Patents
Herstellungsverfahren fuer halbleitervorrichtung.Info
- Publication number
- DE3485520D1 DE3485520D1 DE8484902071T DE3485520T DE3485520D1 DE 3485520 D1 DE3485520 D1 DE 3485520D1 DE 8484902071 T DE8484902071 T DE 8484902071T DE 3485520 T DE3485520 T DE 3485520T DE 3485520 D1 DE3485520 D1 DE 3485520D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/026—Deposition thru hole in mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58092697A JPS59217364A (ja) | 1983-05-26 | 1983-05-26 | 半導体装置の製法 |
PCT/JP1984/000271 WO1984004853A1 (fr) | 1983-05-26 | 1984-05-25 | Procede de fabrication d'un dispositif a semi-conducteur |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3485520D1 true DE3485520D1 (de) | 1992-04-02 |
Family
ID=14061686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484902071T Expired - Lifetime DE3485520D1 (de) | 1983-05-26 | 1984-05-25 | Herstellungsverfahren fuer halbleitervorrichtung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4591398A (de) |
EP (1) | EP0144444B1 (de) |
JP (1) | JPS59217364A (de) |
DE (1) | DE3485520D1 (de) |
WO (1) | WO1984004853A1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60113467A (ja) * | 1983-11-24 | 1985-06-19 | Nec Corp | 半導体装置の製法 |
JPS61166071A (ja) * | 1985-01-17 | 1986-07-26 | Toshiba Corp | 半導体装置及びその製造方法 |
JPS61164262A (ja) * | 1985-01-17 | 1986-07-24 | Toshiba Corp | 半導体装置 |
EP0199497B1 (de) * | 1985-04-10 | 1992-01-02 | Fujitsu Limited | Verfahren zum Herstellen eines selbtsausrichtenden Bipolartransistors |
JPS62290173A (ja) * | 1986-06-09 | 1987-12-17 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPS6381855A (ja) * | 1986-09-25 | 1988-04-12 | Mitsubishi Electric Corp | ヘテロ接合バイポ−ラトランジスタの製造方法 |
JP2615646B2 (ja) * | 1987-08-11 | 1997-06-04 | ソニー株式会社 | バイポーラトランジスタの製造方法 |
US5001533A (en) * | 1988-12-22 | 1991-03-19 | Kabushiki Kaisha Toshiba | Bipolar transistor with side wall base contacts |
JPH10303195A (ja) * | 1997-04-23 | 1998-11-13 | Toshiba Corp | 半導体装置の製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3611067A (en) * | 1970-04-20 | 1971-10-05 | Fairchild Camera Instr Co | Complementary npn/pnp structure for monolithic integrated circuits |
JPS5011676A (de) * | 1973-06-01 | 1975-02-06 | ||
US4127931A (en) * | 1974-10-04 | 1978-12-05 | Nippon Electric Co., Ltd. | Semiconductor device |
US4278987A (en) * | 1977-10-17 | 1981-07-14 | Hitachi, Ltd. | Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations |
JPS5539677A (en) * | 1978-09-14 | 1980-03-19 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device and its manufacturing |
US4168999A (en) * | 1978-12-26 | 1979-09-25 | Fairchild Camera And Instrument Corporation | Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques |
US4251300A (en) * | 1979-05-14 | 1981-02-17 | Fairchild Camera And Instrument Corporation | Method for forming shaped buried layers in semiconductor devices utilizing etching, epitaxial deposition and oxide formation |
JPS5734365A (en) * | 1980-08-08 | 1982-02-24 | Ibm | Symmetrical bipolar transistor |
FR2508704B1 (fr) * | 1981-06-26 | 1985-06-07 | Thomson Csf | Procede de fabrication de transistors bipolaires integres de tres petites dimensions |
-
1983
- 1983-05-26 JP JP58092697A patent/JPS59217364A/ja active Granted
-
1984
- 1984-05-25 DE DE8484902071T patent/DE3485520D1/de not_active Expired - Lifetime
- 1984-05-25 EP EP84902071A patent/EP0144444B1/de not_active Expired
- 1984-05-25 WO PCT/JP1984/000271 patent/WO1984004853A1/ja active IP Right Grant
- 1984-05-25 US US06/700,707 patent/US4591398A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4591398A (en) | 1986-05-27 |
WO1984004853A1 (fr) | 1984-12-06 |
JPH0340938B2 (de) | 1991-06-20 |
EP0144444A1 (de) | 1985-06-19 |
JPS59217364A (ja) | 1984-12-07 |
EP0144444A4 (de) | 1987-12-08 |
EP0144444B1 (de) | 1992-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |