DE3314002A1 - CLOCK AND DYNAMIC MEMORY WORKING WITH IT - Google Patents

Description

OO IHUU ^.

DESCRIPTION

The present invention relates to a clock generator or clock pulse generator made up of field effect transistors of the insulated gate electrode type (hereinafter referred to as "IGFET" or "MOSFET" for short) is and on a dynamic memory, which the clock pulse generator used.

Prior to the present invention, there was such a clock pulse generator represented as shown in FIG. This clock pulse generator is structured as follows:

A MOSFET Q ₁ is a component which, together with a MOSFET Q ₂ and a bootstrap capacitor C _ß, builds a bootstrap circuit and has a gate to which an input pulse <$ _{IN is to be} applied _{via a MOSFET Q 5 with a transmission gate} . The bootstrap capacitor C_ is connected between the gate and source terminals of the MOSFET Q ₁ . The MOSFET Q ₂ is connected between the source terminal of the MOSFET Q ₁ and the ground point of the clock generator. The output MOSFETs Q ₃ and Q. are components that make up a push-pull output circuit. _{The output MOSFETs Q 1} and Q 1 are connected in series between the terminal V " _cc , a supply source and the ground point. Their respective gate connections are usually connected to the gates of the MOSFETs Q 1 and Q".

The respective operating states of the MOSFETs Q-, Q, and Qc are controlled by a delay circuit which. is composed of de: n MOSFETs Q ₁₁ to Q _{15 in} order to maintain the charging time of the bootstrap capacitor C ^. The MOSFET Qi ο 'on the side of the connection of the supply source, whose gate is acted upon by the input pulse <i>", _{and the MOSFET Q 1} 3 r on the side of the ground connection, whose gate is subjected to a precharge (or reset) pulse Φ, are between the connection 'of the supply source and between the ground connection

ORIGINAL JNSPECTED

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connected in series. The MOSFET Q ₁₅ on the side of the ground connection, the gate of which receives a signal at the node N _{2 of} these serial MOSFETs Q-2 ^and Q ₁ 3, and the MOSFET Q ₁₄ on the side of the connection of the supply source, the gate of which with the precharge pulse Φ is applied, are connected in series with each other. A delay signal that is to be generated at the common node N_ of the serial MOSFETs Q ₁₄ and Q ₁ , - is sent to the gates of the MOSFETs Q ₂ and Q ₄ on the one hand and to the gate of the MOSFET Q ₅ via the interrupting MOSFET Q- - Transmitted, the gate of which is acted upon by the voltage of the supply source V _nn.

The delay time (ie the charging time of the capacitor C ₀ ) of the clock pulse generator constructed in this way is determined by the MOSFETs QI ₂ '° -i 5 ^{etc. in} a 1: 1 ratio. The clock has the following shortcomings: 1. In the event that the rate of increase of the charging voltage on the bootstrap capacitor C, charged _{by the MOSFET Q 5}

Is as high as shown in curve A in FIG. 2, the power consumption is increased and the low level of a. The output pulse $ _on m is raised to a higher level, so that the tolerance limit for a low level cannot be maintained. If, in the opposite case, the rise in the charging voltage at a node N- is as low as shown in a curve B in the same figure, the rise in the output pulse <& OUT is also delayed.

In particular, the nodes N ₂ and N_, which have been _{charged in advance to the low and high levels by the MOSFETs Q 13} and Q ₁₄ , the gates of which are applied with the precharge pulse Φ, respectively, are designed to be in response to the fact that the input pulse Φ "assumes the high level, have the high or low level. The delay time from the point in time at which the input _{pulse Φ ΤΝ is set} to the high level to the point in time at which the node N ₃ on the

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is set low, is through the on-resistance of the MOSFET Q ₁ ? ' ^a capacitance such as the parasitic capacitance, not shown, which _{is coupled to node N 2} , the on-resistance of MOSFET Q15 / a capacitance such as the parasitic capacitance, not shown, which _{is coupled to node N 3} , and so on.

In the case of a high rate of rise of the input _pulse Φ χΝ, the charging voltage of the node N- is increased to a large extent. In contrast to this, the node N- should have the low level after a predetermined delay time. As a. As a result, the time span from the point in time at which the node N. is to assume a sufficiently high level to the point in time at which the node N ₃ is intended to assume the low level is extended. As a result of the times required _{to render MOSFETs Q 1} and Q ₂ conductive at the same time and to render MOSFETs Q ₃ and Q- simultaneously conductive, respectively, the currents through the MOSFETs are increased Q and Q ₂ and by the MOSFETs Q ₃ and Q. increased. On the other hand, the level of the output pulse Φ _{ηπφ is} slightly increased before it is changed to the high level, since the output MOSFET Q _{3 is} made sufficiently conductive at a too early point in time in response to the potential of the node N-.

In other words, the low level of the output pulse Φ_ is set to an undesirable level.

Conversely, if the rate of rise of the charge voltage at node N- is low in response to the fact that the rate of rise of the input pulse Φ ™ is low, node N ₃ is caused to go low before the charge voltage at node N- is set to the sufficiently high level. The MOSFET Qr, which is to apply the charging voltage to the bootstrap capacitor Cg, is turned off in response to the node N _{3 being set} to the low level. As a result, ^ di ^ e charging voltage of the boot

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strap capacitor C-. not set to the sufficiently high level. Since the charging voltage of the bootstrap capacitor C _ß assumes an insufficient level, the output MOSFET Q ~ is not made sufficiently conductive. As a result, the rising rate of the output pulse $ _on m is decreased.

A similar undesirable operation of the clock pulse generator is caused even if the rate of rise of the input pulse Φ is constant, because with respect to the rate of rise and the delay time of the node Ν., In response to the dispersion in the characteristic features of the MOSFETs Qr, Q ^ 2 ^and & Q-15 deviations occur.

2. If the delay time from the input pulse Φ to

Output pulse _Φ ητττ ^o f a high value to be set, collapse of the charging time of node Ν ,, and the delay time of node N ^ can be achieved only under unusual difficulties because they are affected in the "high degree by the scattering of the characteristic component features .

3. If the rate of rise of the input pulse Φ ~~ is changed, this results in an increase in power consumption, which is primarily caused by the narrowing of the tolerance range for the low level and by the reduction in the driving capacity of the not shown - load during the output pulse so that the desired stable operating conditions cannot be expected.

It is therefore an object of the present invention to provide a clock pulse generator, its Operating condition of the influences of the scatter and the Fluctuation in the rise of an input pulse is exempt.

Another object of the present invention is to provide a clock pulse generator which is shown in FIG is able to generate an output pulse that is so

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is placed that it has a longer delay time than the input pulse.

Yet another object of the present invention is to provide a clock pulse generator with a low To provide power consumption.

Another object of the present invention is to provide a clock pulse generator which is shown in FIG is able to generate a signal at an appropriate level.

Another object of the present invention is to provide a clock pulse generator which can be used for a dynamic memory with direct access (dynamic random access memory D-RAM) in MOS technology is.

Further objects of the present invention will become apparent from The following description is apparent, which is made with reference to the accompanying drawings.

Figure 1 shows the circuit diagram of a clock, · like him was shown prior to the present invention; FIG. 2 illustrates using a pulse diagram clock pulse generator shown in Figure 1;

Figure 3 shows the 'circuit diagram of a clock according to an embodiment of the present invention; Figure 4 is a timing diagram for explaining the operation of the clock pulse generator of Figure 3;

FIG. 5 shows in a block diagram a D-RAM which provided with the clock embodying the present invention;

Figures 6 and 7 are Impulsdiagra.mme showing the mode of operation of the D-RAM of Figure 5;

FIG. 8 shows a circuit diagram of an essential part of the D-RAM to which the present invention is based Applies; and

Figure 9 is a timing chart for explaining the operation of the same.

The present invention is described in detail below in connection with its technical realization.

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In Figure 3 is the circuit diagram of the embodiment
of the present invention.

According to this embodiment is a voltage detector which, as set forth below, composed of the MOSFETs Q ₆ and Q ₁₀ connected to the bootstrap output circuit, as shown in Figure 1, of the MOSFETs Q ₁ to Q ₅ and the Bootstrap capacitor C _D should be composed.

JD

The voltage detector in the embodiment according to FIG. 3
is made up of MOSFETs Qg to Q ₁ and takes the place of the delay circuit as shown in FIG

is a. In the bootstrap output circuit, the MOSFETs Q ₁ and Q ₂ essentially form the bootstrap capacitor
driving circuit. In the clock generator of Figure 3, the voltage detector and the bootstrap capacitor drive circuit can be designed so that they are essentially
build a driver.

In the voltage detector, the MOSFET Q ₇ on the side of the ground potential is connected to that on the side of the
Connection of the supply source lying MOSFET Qg in

Connected in series, whose; gate with the gate voltage that is connected to
the MOSFET Q _{1 is} applied, is applied. In other
In other words, the MOSFET Q ₇ is between the source terminal of the
MOSFET Qg and the ground point of the voltage detector switched. _{The MOSFET Q g} on the ground potential side has its gate and drain connections crossed with the corresponding connections of the MOSFET Q ₇ . The MOSFET Qg on the side of the connection of the supply source is with the MOSFET
Qg is connected in series and its gate receives the precharge pulse Φ. The MOSFET Q ₁₀ is parallel to the MOSFET Q ₇

peeled, the gate of which is applied with the precharge pulse Φ. The drain output signal of the MOSFET Q _g is on the one hand to the gates of the MOSFETs Q ₂ and Q ₄ and on the other hand to the gate of the MOSFET Q ₅ via the interruption MOSFET Q ₁₁ , the gate of which is supplied with the voltage V ^ p of the supply source, given. .

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_{The MOSF 1} ETs described so far. clad is designed as an N-channel type, although there is no particular restriction on it. The MOSFETs and the boctstrap capacitor C _n / as shown are formed in accordance with well-known MOS technology for integrated circuits "on such a semiconductor substrate as is made of N-doped single crystal silicon. The bootstrap capacitor C _β is composed of the MOS capacitor which is designed to have a structure similar to that of the MOSFET, although there is no particular limitation thereto, the gate electrode of the capacitor C _R is connected to the point N ₁ and its source and The drain electrode is connected to the common node of the source electrode of the MOSFET Q ₁ and the drain electrode of the MOSFET Q ₂ .

The operation of the generator according to this embodiment will be explained with reference to the timing diagram described according to Figure 4. · ■ ·

The precharge pulse Φ and the input pulse Φ ™ / which are to be applied to the generator shown in Figure 3, are supplied by a suitable circuit not shown. "- ■ The precharge pulse Φ is set in advance to a high level which, as shown in FIG. 4, is approximately at the level of the voltage of the supply source V_ and it is reduced to a low level of approximately zero volts before the input pulse Φ _ΤΝ "is to be the delay, is received, that is, before the input pulse Φ is raised to the high level. Moreover, the precharge pulse Φ in synchronization with the fact that the input pulse Φ ^ _Ν is reset to the low level, on is raised to the high level, although there is no particular limitation. When the precharge pulse Φ is at the high level, the MOSFETs Q ₈ and Q _{1 are} accordingly conductive, and when the MOSFETs Qg and Q _{1 become} conductive, becomes

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the MOSFET Q _{7 is made} conductive, whereas the MOSFET Q _{g is made} non-conductive. At this time, since the MOSFET Q _{g is} non-conductive while the MOSFET Qo is conductive, the gates of the MOSFETs Q 1, Q and Q _{5 are} precharged to the high level via 5. the MOSFET Q g, which is approximately the same the voltage of the supply source V _, _, - V _mtJ (threshold

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voltage of the MOSFET). As a result, these MOSFETs Q ₂ / Q ₄ and Q _{5 are made} conductive. The level at the node N is lowered to the same level as that of the input pulse Φ-j- · »·, / ie, to the low level, since the MOSFET Q _{5 is} conductive. The MOSFETs Q ₆ , Q ₁ and Q ₃ , the respective gates of which _{are connected to the node N 1} , are rendered non-conductive because the node N ₁ is at the low level. The output pulse Φ ^ ·, which is fed from the common node of the source connection of the output MOSFET Q_ and the drain connection of the output MOSFET Q ₄ , is at the 'low level because the output MOSFET Q _{4 is} conductive . • Under these circumstances, the non-conductive state is maintained at least on one of the paired MOSFETs which are connected in series between the connection of the supply source and the ground connection, such as MOSFETs Q ₃ and Q ₄ . As a result, the power consumption of the clock pulse generator is reduced to essentially zero in this state.

The precharge mode is then terminated as a result of the precharge pulse Φ being changed to the low level. If the input pulse Φ is raised to the high level, the bootstrap capacitor C ″ is then _{charged by the MOSFET Q 1} -. The potential at the node N ₁ is increased in accordance with the charge on the bootstrap capacitor C-. Here the

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MOSFET Qc / which has been made conductive by the precharge, a MOS capacitor which essentially acts like the bootstrap capacitor. The gate electrode of the MOSFET Q ₅ is designed as an electrode of the MOS capacitor, where-

* _ ₁₆ "_ ■""33U002

on the other hand, the channel induced under the gate electrode aes MOSFET Q _{5 is formed} as the other electrode of the MOS capacitor. This MOS capacitor, which is composed essentially of the MOSFET Q ₅ , charges during the precharge, that is, when the precharge pulse Φ is set to the high level. The channel voltage of the conductive MOSFET Qr is raised to the high level in accordance with the aforementioned rise of the input pulse Φ _Ν. The MOS capacitor between the gate electrode and the channel of the MOSFET Q ₅ has been charged during the precharge period, so that the gate voltage of the MOSFET Q ₅ is raised in response to the rise in voltage of the input pulse Φ. In other words, the gate potential of the MOSFET Q ₅ , which has been raised to the high level by the precharging, is raised to such a high level by the so-called "self-bootstrap" effect that it is the voltage level of the supply source exceeds. The MOSFET Qc then starts to show the satisfactory ON characteristics when its gate potential is raised sufficiently.

As a result, it becomes the input pulse. Φ transferred to node N ₁ without his. To have lost level significantly. Immediately after the input _{pulse Φ ΙΝ is raised} to the high level, the _{node N 3 is} still left at the high level; The electrode of the interruption MOSFET Q ₁₁ , which is connected to the gate of the MOSFET Q ₅ , acts as the drain electrode when the bootstrap voltage is applied to _{it via the MOSFET Q 5.} At this point in time, the voltage to be applied between the gate electrode of the interrupting MOSFET Q- and the electrode which essentially serves as the source electrode (ie, the electrode connected to node N ₃ ) , sufficiently small because node N _{3 is} held high. As a result, the interruption MOSFET Q _{11 is activated} in accordance with the fact that the bootstrap voltage / voltage caused by the

MOSFET Qc generated-, rises to a level higher than the voltage of the supply source, is automatically rendered non-conductive. In this way it is prevented that creep losses, the bootstrap voltage, occur. 'The MOSFET Q _ß, which has been made non-conductive during the precharge is rendered conductive to have an increased · conductivity in accordance with the increase of the potential of node N-. The potential at the node N2 rises, as shown in FIG. 4, in accordance with the ratio of the conductivities of the MOSFETs Q ₆ and Q ₇ , which are now conductive.

If the voltage at the node N ₂ exceeds the threshold voltage V of the MOSFET Qq in accordance with the rise in potential of the node N ₁ , the MOSFET Q _{g is} accordingly switched from its non-conductive to its conductive state. At this moment the conductive state of the MOSFETs Q ₇ and Q _g is suddenly reversed by the effect of the positive feedback or positive feedback, which is established by the cross-connected MOSFETs Q ₇ and Q _g. In detail, the MOSFET Q _{9 is switched} from "off" to "on", whereas the MOSFET Q _{7 is switched} from "on" to "off".

The _{node N 3} is changed from the precharge level, that is, from the high level to the low level, as a result of the fact that the MOSFET Q "is made conductive. As a result of causing node N ^ to go low, MOSFETs Q ₂ and Q ^ are rendered non-conductive. Break MOSFET Q ₁ - is rendered conductive when node N _{3 is} caused to take the low level because the voltage to be applied between its gate electrode and the electrode which is substantially the source electrode CLent is raised in accordance therewith. The MOSFET Qc is made non-conductive because its gate potential is charged to the low level by the interruption MOSFET Q- in the conductive state.

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The common node of the MOSFETs Q ₁ and Q ₂ is raised to the high level as a result of the MOSFET Q ₃ being rendered non-conductive. Because the bootstrap capacitor C "is precharged, the potential of the interconnected gates of the MOSFETs Q ₁ and Q", that is, the potential at _{the node N 1} becomes high in accordance with the increase in the potential at the common node to the high level Raised level, which is higher than the voltage of the supply source V _cc . The MOSFET Q ₅ is made non-conductive when the voltage of the hold point N _{1 is} raised. As a result, losses of the charge to maintain the bootstrap voltage of the node N ₁ in the direction of the input _{pulse Φ through the MOSFET Q 5 are} avoided.

If the potential of the node N ₁ is raised sufficiently by the bootstrap mode of action, the result is that the output MOSFET Q ₃ assumes a sufficiently low on-resistance. As a result · the _{output pulse} $ nnT rises steeply to the. high level even if the load capacitor, not shown, is connected to the common connection point of the output MOSFETs Q ₃ and Q ₄ , that is, to the output terminal.

In the present embodiment, the level raising voltage, the level of which has been raised to a value corresponding to the conductivity ratio of the MOSFETs Q ₆ and Q ₇ in consideration of the charging voltage applied to the bootstrap capacitor C _n , is generated at the common node of these MOSFETs. The magnitude of this level boosting voltage is compared _{by the MOSFET Q g.} In this case, the threshold voltage of the MOSFET Q is designed as the reference voltage for the voltage comparison. If the potential at the node N _{1 is raised} to a predetermined value, as described above, the "on" and "off" states of the MOSFETs Q ₇ and Q _{9 are} accordingly abruptly reversed. The bootstrap voltage on the bootstrap

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. Capacitor C _n is correspondingly applied to node N-.

This value of the charging voltage of the bootstrap capacitor C ₁ , which is to be determined, can be set at a suitable level by a corresponding definition of the circuit constants which are determined by these MOSFETs. As a result, in accordance with the present embodiment, the bootstrap. Capacitor C _{ß / has been} charged to the appropriate charging voltage, enabled to start the bootstrap mode of action at the most suitable time. Even if the charge rate of the bootstrap capacitor C_ changes due to fluctuations, such as changes in the charge rate of the input pulse $ _IN /, the MOSFETs Q ₂ and Q _{4, in} addition to these fluctuations, are switched from their conductive to their non- switched to conductive state. As a result, there is no power loss that is greater than necessary. In addition, it is possible to increase the tolerance limit for the low level and to ensure sufficient control capacity.

The generation of the output pulse Φ _ουτ after a long delay time compared to the input pulse Φ can be realized remarkably easily by reducing the conductivity of the MOSFET Q ₅ or by _{delaying the input pulse} Φ ΤΝ itself.

Because, according to the present embodiment, the operating time of the bootstrap circuit is determined by the control value the charging voltage of the bootstrap capacitor CL · regulated is, the influences of the scattering of the components are so considerably reduced that a pleasantly large one Degree of freedom in design is available.

The clock pulse generator according to this embodiment can be used as a clock generator of such a dynamic RAM (hereinafter referred to as D-RAM for short), such as it is described below, although it is not specifically limited to it.

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The circuit block of the D-RAM is shown in FIG. In this figure, each of the circuit blocks delimited by dashed lines is as an integrated one Circuit (hereinafter referred to as "IC" for short) is formed on a semiconductor substrate (not shown).

Each circuit of the.IC is made up of a dynamic circuit. The IC adopts an address multiplex system to reduce the number of its external connections. The IC is made ready for operation in that its supply source connection and its ground connection with the voltage of the supply source V _cc , which is generated by the supply source unit, not shown, and a ground voltage V are applied. The external connections of the IC are connected to the row address strobe signal RAS, the column address strobe signal CAS, the write enable signal WE, the row address signals A _Q to A. Column _{address signals A. +1} to A. and the input data signal D., which from an electronic.

Unit such as the CPU, not shown, is applied. The external connection of the IC generates a data signal D. With which an electronic unit such as the CPU is to be charged.

In the IC, the block delimited by double-dotted lines is the clock pulse generator, which consists of a Circuitry is constructed for generating a signal which is used to regulate the modes of operation of the corresponding circuits of the D-RAM is used.

Figs. 6 and 7 are timing diagrams illustrating the operations of the read and write cycle of the in Fig D-RAM shown in Figure 5.

At this point, the output of the D-RAM in this embodiment will be explained with reference to the block diagram of FIG Figure 5 and the timing diagrams of Figures 6 and 7 are described.

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First, the levels of the respective row address signals A to A. are set to such levels that they select the row address of a desired memory cell in a memory array (hereinafter referred to as M-ARY for short). Thereafter, the RAS signal is set to the low level. The clock pulse generator (hereinafter referred to as "TGB" for short) provides a control signal Φ in response to the. Fall of the RAS signal. When the signal Φ is available, a row address buffer (hereinafter referred to as "ADB" for short), which has been held in the precharged state in advance, is put into the operating state. As a result, the row address signals A to A. are applied to the ADB and captured therein. In response to the row address signals A _Q to A. The ADB generates internal address signals .a-, a _o to a., A. with levels corresponding to the dual one (true levels) and levels corresponding to the dual zero (false levels). The reason why the RAS signal is generated later than the row address signals A_ to A ^ is that / the ADB is reliably supplied with the row address signals A to A. as the row address in the memory arrangement. ". '

After the generation of the signal Φ, .-, the

ADB produced internal address signals a, äT to a., A ..

on one. Row and column decoder and transferred to a driver circuit (hereinafter referred to as "RC-DCR" for short). The RC-DCR decodes the internal address signals. a _Q , a _Q to a., a .. Among the decoded signals of the RC-DCR, only one to be selected is left at the high level, while the others not to be selected are left at the low level will.

Thereupon a signal Φ, which is delayed for a predetermined period of time, _{taking into account the signal Φ ΑΤ, is supplied by the TGB.} After the generation of the signal Φ, the decoded signals, which are generated by the RC-DCR, are transferred to the row address lines of the memory

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order M-ARY transferred. The reason that the signal Φ _{ν is} delayed taking into account the signal <i> _D is here to operate the RC-DCR after the operation of the ADB has ended. In this way the line address is set in the -ARY. That is, a row address line in the M-ARY is raised by a signal. high level below

i + 1
selected the '2 output signals of the RC-JDCR.

The data signals corresponding to the information “1” or “O”, which have been read out from the respective memory cells which are connected to the selected signal row address line in the M-ARY, are then transmitted by the sense amplifier, hereinafter referred to as “SÄ ¹ denotes reinforced). the operation of the amplifier SA is set after the generation of the signal _Φ ρΑ in motion.

At a suitable point in time, denoted by E in FIG. 6, the respective levels of the column address signals A. ₁ to A. are set to such levels that they select a column address of the desired memory cell. After the CAS signal has been set to the low level in order to supply a signal, ρ from the TGB, the column address signals A., to A. are then applied to the ADB and captured therein. The reason that the CAS signal is later than the column address signals A. .. to A-. is generated, is to reliably supply the ADB with the column address signals as the column address in the memory arrangement.

- After generating the signal Φ _Δ _, the ADB transmits the internal address signals ^a - ₊₁ / ^a - ₊ -i to a. _t ΈΤ corresponding to the column address signals to the · RC-DCR. The RC-DCR generates "2? ^ Decoded signals in one operation. Among the decoded signals, one corresponding to the combination of the internal address signals is brought to the high level. Thereafter, a signal Φ _γ delayed in consideration of the signal Φ__ After the generation of the signal Φ _γ , the decoded signals are supplied by the RC-DCR and transmitted to a column switch (hereinafter referred to as " ¹¹ C-SW" for short). In this way the column

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address set in M-ARY. That is, one of the bit lines in the M-ARY is selected by the C-SW.

A memory address in the M-ARY is created by setting the row address and the column address in this way set.

The read and write modes for the set address are now explained below.

A read mode is made by the high level of the WE signal specified. This WE signal is set high before the CAS signal is set low will. The read mode is prepared in that the WE signal is brought to the high level. After this the WE signal was brought to the high level in advance, the read operating state is made available accordingly, before an address of the M-ARY is set by bringing the CAS signal to the low level. As a result, the time to start the reading operation can be shortened.

After a signal $ _op r that is a CAS group signal,

was delivered by the TGB, a (not shown) output amplifier, which is in the data output buffer er '(data output buffer, hereinafter referred to as "DOB") is included, made effective. Information 'read out from the set address, namely Information supplied via the C-SW is amplified by the activated output amplifier. The reinforced Information is supplied to the data output connection via the DOB. In this way, the reading operation is effected. The reading operation ends when the CAS signal becomes high. A write mode is by the low level of the WE signal specified. A signal Φ is low by the WE signal and the CAS signal is low Level brought to the high level. The signal Φ "is sent to the data input buffer (hereinafter referred to as "DIB" for short. This DIB is made effective by the high level signal Φ

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and then transfers write data from the input data (D _1. terminal to the C-SW. The write data is transferred to the set address of the M-ARY via the C-SW. As a result, the write operation is carried out.

In write mode, the DOB is made ineffective, that it is supplied with the inverted signal of the signal namely the signal Φ "with a low level. In this way, the data is protected from being read out during write operation.

The respective clocks, Φ, Φ, _γ , etc. are established on the basis of the address strobe signals (ie, the RAS signal and the CAS signal) in the TGB which receives these address signals as stated above. The clock is formed on the basis of the WE signal and the output signal of the TGB in the read / write clock generator R / W-SG. Fig. 8 is a circuit diagram showing an essential portion of the D-RAM to which the present invention is applied.

The circuit shown in Figure 8 is made up of an N-channel IGFET (the abbreviation for "field effect transistor with insulated gate electrode") made up of an N-channel MOSFET is .. ■ '

The one-bit Speieherzelle (memory cell, hereinafter referred to as M-CEL) is built up from an information storage capacitor C _g and an address selecting MOSFET Q_ _M and stores the information "1" or ¹¹ O, "depending on whether the capacitor C "carries a charge or not.

The reading operation of the information is carried out as a result- = ■.

men that _he d MOSFET Q _m is turned on to charge the capacitor. C _c to connect to a common column data line DL, and in that it is then scanned how the potential of the data line DL has changed according to the size of the charge stored in the capacitor C ". If it is assumed that the potential stored in advance in a leakage capacitor C _Q is the voltage of the supply source V _cc , the potential (V _DL ) of the data line DL,

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which is determined during the operation to be assigned the address, _{leave it at the potential V_ c} if the information stored in the capacitor Cg is at "1" (ie the potential of the voltage V_, p). If the potential at the capacitor Cg is "0" (ie, 0 volts), the potential (V) "" at the data line DL can be given by the following equation

express: {C _A -V. "- C" (V _r7 - V.,)} / C_. Here υ i_c ο w tn υ denotes

V "the gate voltage of the MOSFET Q and V" the threshold voltage of the MOFET Q. In addition, the change in potential that is transmitted to the data line DL is that it corresponds to the logic "1" or "0", i.e., the signal quantity AV "to be detected in the following Expressed form:

^AV S ^{= iV} DL ^{) n} 1 "~ ^(V DL ^{) n} O"'(1)

= (V _W - V _th ) -C ₅ ZC ₀ ; (2)

If: V "= V _rr ,, the signal quantity Δν _{ς is expressed} by the following equation:""

^Av s. ^{= (V} cc- ^v th) - ^c s / ^c o · "■ ⁽³⁾

In the case of a memory matrix of high integration and capacity, in which the memory cells are small and connected to a common data line, an inequality applies: C _g «C _Q. That is, the ratio C _g / C ₀ takes an extremely small value. As a result, the signal quantity AV _g becomes a signal of a conspicuously fine level.

A dummy cell (hereinafter referred to as D-CEL) is used as an aid to to provide a reference when such a fine signal is to be detected. The D-CEL is under the same Manufacturing conditions and with the same design skon ^ · like the M-CEL, with the exception that a capacitor, C, has a capacitance that is roughly half

is as large as that of the capacitor C _c . The capacitor C i is charged to ground potential by the action of a MOSFFT Q ₂ prior to the access of the D-RAM (while the other electrode is fixed _{at V cc).} Therefore, the signal change AV _n transmitted to the column data line by the action of the D-CEL when the D-RAM is called up, as well as the (AV _C ) of the memory cell, is expressed by the following equation, where V _{w is} the gate - · voltage of a MOSFET 0_ .. and V ,, 'the threshold voltage of the MOSFET Q ₀ -, denotes:

If: V _w = V _cc , the signal change AV _{R is expressed} by the following equation:

^AV R ^{= (V} CC " ^V th ') - C _ds / C _0. ■ (5)

Because the capacitor C i is set to have about half the capacitance of the capacitor C _g , the signal change AV- becomes about half the signal size AV _g . As a result, the information "1" or "0" can be distinguished depending on whether the potential change to be transmitted from the memory cell to the data line DL is greater or less than the (AV _D ) of the dummy cell.

Ii

A sense amplifier SA ₁ extends such a difference in the potential changes, as occurs during the addressing operation, to the reading pulse which is determined by a clock signal (ie, the sense amplifier control signal). (This operating state is described further below.) The sense amplifier SA ₁ has input and output nodes which are connected to a pair of complementary data lines DL _1-1 and DL _1-1 which are arranged in parallel. The number of memory cells connected to the data lines DL _1-1 and DL _1-1 is identical in order to increase the accuracy of the data acquisition.

33H002

gladly; A dummy cell is connected to each of the data lines DL _1-1 and DL _1-1. Each memory cell is connected between a word line WL and one of the complementary data lines. If the memory cell connected to one of the complementary data lines DL _{1 Λ} and DL ₁ . shelled

I - I I - I

tet is selected, one of a pair of dummy word lines DWL ₁ _ .. and DWL ₁₂ is selected so that the dummy cell connected to the other data line can be selected.

An undesirable coupling capacitor, such as the parasitic capacitor not shown, occurs at the intersection between each word line and each data line. As a result, if the potential of a word line is changed, the potential change, which is interpreted as noise, is transmitted to each data line via the undesired coupling capacitor. In the case of a memory device of the double bit line type as shown in FIG. 1, each word line WL crosses any pair of the data lines. As a result, the noises become substantially the same level as the. Disturbances that are transmitted to one of the data lines due to the change in potential of the word line WL are also transmitted to the data line which is connected to the previous data line. Since the differential sense amplifier is essentially insensitive to general node disturbances, the fine signal which is given to the coupled data lines is amplified in a suitable manner regardless of the presence of disturbances. This sense amplifier SA ₁ is equipped with a pair of cross-coupled MOSFETs Q _s8 and Q _sg , so that it differentially amplifies the fine signal through the positive feedback (positive feedback) operation of these MOSFETs. These positive feedback effects are set in motion simultaneously with the start of conduction of a MOSFET Q _slo by a clock signal (ie, the sense amplifier control signal) Φ.

As a result of the effects of the reading amplifier SA. the data line potential (VVJ, which was set to the high level on the basis of the potential difference which was transmitted in advance to the paired data lines during the addressing operation, ■ 5 is lowered at a low rate of change, whereas the low data line potential (V _T ) with a high rate of change

Yy

is lowered. As a result, the potentials of the paired data lines are lowered while the difference between them increases. When the low data line potential V_ exceeds the threshold voltage V ₄ , the

Jj tn

Reached via cross-coupled MOSFETs, the positive feedback operation essentially ends. _{The high data line potential V n} is left at a potential that is lower than V rr and higher than V. The low data line potential eventually reaches _{V x}

Yy

0 volts. ·

After the addressing operation, the stored information of the memory cell, which has once been destroyed, is restored (or rewritten) as a result of the fact that it is written as it is in the memory cell in which the potential V n or V _x that at

• η yy

supplied to this scanning operation is selected.

If the high potential · V "falls by more than a predetermined level which reaches the level V-,", a malfunction occurs in which the potential Vjj is read out as the logic "0" after the repetitions of the read and rewrite operating states . There is an active regeneration circuit (active restore circuit) AR ₁ , which is made available to 'prevent this malfunction. This circuit AR ₁ has the task of only

to raise the high potential V "to the potential V_," without

ti Cv-

any influence on the low potential V _x

Yy

transfer. C _ß11 and C _{ßl2 denote variable capacitance elements of} the MIS type, whose electrostatic capacities according to the voltage applied to such a connection.

33H-002

will be changed as it is on the left side of the drawing. This variable capacitance elements should be interpreted such that they do not provide theoretically for a high voltage relative to the threshold voltage V. ,, ^a ^ ^it for a low voltage capacitors.

When the MOSFETs Q ₃₄ and Q ₃₅ are made conductive by a clock signal (ie, an active regeneration control signal) Φ, the variable capacitor component C _β belonging to the data line at the high potential V n is charged. When a clock signal (ie, an active regeneration control signal) Φ becomes high level, the gate potential of a MOSFET Q_ _g or Q _q7 / belonging to this data line becomes sufficiently higher than V_. As a result of the fact that the MOSFET Q ₅₆ or Q _{37 has} the sufficiently high conductivity, the potential V 'restores the level V .__. In order to reduce the power dissipation across the MOSFETs Qg and Q _s7 in this case, the respective threshold voltages V · i are designed to be lower than those of the un-asterisked MOSFETs, although there is no particular limitation thereto.

The following operations of the D-RAM transistor circuit as described so far will be explained with reference to the timing diagram of FIG.

When the signal Φ is generated at such a high level

.tr v—

is that it _{exceeds the level V cc} , the MOSFETs Q ₅₂ and Qj, ^ are made conductive accordingly, so that the stray capacitor C _{n of} the coupled complementary data lines DL ,, .. and DL-, is precharged to the level V _rc . Since a MOSFET Qq _{1 is} made conductive at the same time, the coupled complementary data lines DL _1-1

and DL _{1 Λ} short-circuited, even if during precharging by 1—1

the MOSFETs Q ₅₃ and Q ₅₃ "an imbalance occurs, so that they are under the condition of an equal potential

are set. The MOSFETs Q _g1 to Q ₅₃ are constructed to have lower threshold voltages than the MOSFET which is not marked with an asterisk, so that no voltage loss can be caused between their respective sources and drains.

The MOSFET Q _ in each dummy cell becomes this one Point in time made conductive by a clock signal (i.e., a discharge control signal) Φ. As a result, the Dummy cell D-CEL is similarly reset to a predetermined state.

The row address _{signals A n} to A., which after the clock of the clock signal (ie, the address buffer control signal) Φ. from the address buffer ADB are decoded by the decoder RC-DCR and output to the memory cell M-CEL T5 and the dummy cell D-CEL simultaneously with the rise of the control signal of the word line Φ.

_{As a result, a voltage difference of AV g} / 2 is built up between the coupled complementary data lines DL _1-1 and DL _1-1 , as described above, on the basis of the stored content of the memory cell.

When the MOSFET Q ₅₁₀ begins to conduct due to the clock signal (ie, the sense amplifier control signal) Φ ·, the sense amplifier SA ₁ begins to set the positive feedback operation in motion and the detected signal from AV / 2, which during the addressing operation the complementary data lines DL _1-1 and DL _1-1 , was added to reinforce. After the boost operation has essentially ended,> the clock signal (ie, the active regeneration control signal) Φ is generated. When this clock signal Φ is generated, the active regeneration

XT S

circuit AR ₁ operated synchronously, so that the logic level "1" of one of the complementary data lines DL and DL. 7 restores the level V _n .

The column address signals A. .. to A- from the address buffer ADB in common mode with the clock signal (i.e., the

4 f. Ψ,

33H002

- 31 -

Address buffer control signal) Φ--, are decoded by the decoder RC-DCR. Thereafter, the decoded signals of the RC-DCR are _{supplied to the column switch C-1} when the clock signal (ie, the column switch control signal) Φ _{γ is} generated. As a result, the stored information belonging to the selected column address in the memory cell M-CEL is transferred to the common data lines CDL ^ and CDL- _{by the column switch C-SW 1.}

_{Thereafter, a main amplifier / data output buffer OA & DOB operates in response to the} generation of the clock signal (ie, the data output buffer and main amplifier control signal) Φ ορ. As a result, the stored information read out from the selected memory cell is output to the output terminal D of the chip. The OA & DOB is put out of operation during the write operation by the clock signal (ie, the data output buffer control signal) Φ _w.
Typing ,

The precharge, addressing and scanning operating states are completely identical to those of the reading operation mentioned above. First of all, the stored information of the memory cell, which should be written in by itself, is ^{read out on the coupled complementary data lines DL} i_-i ^{un <} ^ ^DL i_i without taking into account the logical value of the input write information D.. The read information is ignored at this time by the write operation, which will be described below. It may therefore occur that the selection of the row address is made essentially by the operations described so far.

When the clock signal (ie, the column switch control signal) Φ is generated as well as in the read operation, the coupled data lines DL ₁ _, and DL _1-1 belonging to the column become synchronous with this generation.

was selected by the Spal tonum ;; eh.il tor C-SW ₁ an

33H002

the common data lines CDL ui.d CDL ₁ switched.

After the generation of the clock signal (ie the data input buffer f first control signal) Φ „ _w , the complementary write input signals d. and d. , which are supplied from the data input buffer DIB synchronously with this generation, are written into the memory cell M-CEL by the column switch C-SW ... At this point in time, the sense amplifier SA ₁ also operates, but the output impedance of the data input buffer DIB is low. As a result, the information to appear on the coupled column data lines DL _1-1 and DL., .. becomes through the information of the input
Refresh operation

mation of the input d. bestjjmmt.

in

This refresh operation is carried out in that the information which is stored in the memory cell M-CEL, but is about to be lost, is once read out to the common column data line DL and in that the read-out information is returned to the memory cell M- CEL is written after it has been set to such a level as was restored by the sense amplifier SA ₁ and the active regeneration circuit AR ₁ . Therefore, the refresh operation is similar to the operating condition during the column addressing and scanning period described in connection with the reading operation. In this case, however, the operation of the column switch C-SW- is not required. As a result, the refresh operation is performed simultaneously for all columns "and in the order of the respective rows / while the column changeover switch C-SW _{1 is kept} in its inoperative state.

In accordance with the present invention, the clocks having a structure as shown in Fig. 3 are used in the TGB as shown in Fig. 5 so that the clock signals Φ, ^, Φ _ν , Φ _Ο7ν , Φ _ν, etc. .. of the D-RAM can be generated.

33H002

For example, a clock generator not shown (hereinafter referred to as "Φ ^^ - ΘΕΝ" for short) which is put into operation to generate the clock signal 4> _R for controlling the address buffer ADB is designed to have a structure similar to that that of the circuit shown in FIG. The precharge pulse and the input pulse required by the Φ -, - GEN are generated by a suitable input buffer (not shown) which is located in the TGB and to which the RAS signal is to be applied via an external connection -GEN required precharge pulse is in phase with the RAS signal, whereas the input pulse has a phase position opposite to the RAS signal. As a result, the Φ _Α _-6ΕΝ is held in its precharge state if the RAS signal is not generated or is established at the high level, but is disabled when the RAS signal is established low, in which case the required delay time from the instant the RAS signal is generated until at the moment at which the clock signal Φ ^ _{κ is} generated, set to a suitable value by 'the Leitfahigkextscharistika of the MOSFET in Φ ^ -GEN, which is the MOSFET Q ₅ shown in Figure 3 ent speaks, accordingly, be established accordingly. In other words, the required delay time is set to the appropriate value by appropriately setting the dimension (ie, the channel width W / the channel length L) of the MOSFET corresponding to _{the MOSFET Q 5.}

Likewise, the clock generator, not shown ( ^{hereinafter referred to as 1} ^ _x -GEN "for short), which is operated to generate the clock signal Φ _χ for controlling the decoder RC-DCR, is designed so that it has a structure similar to that of the 3. The generator Φ ^ -GEN is to be supplied with the precharge pulse and the input pulse, which are identical to those with which the Φ "-GEN is supplied, although there is no pronounced restriction.

kung insists. The delay time to be determined by the Φ -GEN is determined by appropriately setting the conductivity characteristics of the MOSFET _{corresponding to the MOSFET Q 5 of} the circuit of FIG. 3, similar to the Φ "-GEN.

Incidentally, the clock signal Φ, _{ο can be used} as the input signal

AK

can be applied to the Φ "-GEN if a relatively long delay time can be set from the instant at which the clock signal Φ _{ΑΚ is} generated to the instant at which the clock signal Φν is generated, namely if the delay time which should be set is longer than the minimum delay time that can actually be set by the Φ -GEN.

Therefore, the multiple clock signals having different timing can be generated, by arranging several circuits in parallel to provide a structure similar to that of the The circuit shown in Figure 3 have and / or by having these circuits available in a serial arrangement be asked.

The value of the delay time of the clock shown in Fig. 3 can be easily set in accordance with 'the conductivity characteristics of the MOSFT Q ₅ and the voltage detection structure composed of the MOSFETs Q ₆ to Qq. One is able to get the value of the delay time. Suffice it to change by, for example, only changing the conductivity characteristics of the MOSFET Qc-. As a result, when the clock pulse generators shown in Fig. 3 are used, the design of the 'D-RAM is facilitated. In contrast to this, the delay time of the circuit shown in FIG. 1 is, as is clear from the preceding description, influenced not only by the MOSFET Q ₅ , but also by the MOSFETs Q ₁₂ 'Qi5 ^etc. This makes designing the MOSFETs for changing the delay time relatively difficult. As a result, when using the clock

_ ₃₅ _ 33U002

pulse generator, as shown in Figure 1 · the D-RAM design complex.

In the D-RAM, some clock signals must have particularly precise timing. Among these, the clock signal Φ must rise in precise temporal correspondence with the clock of the memory cell that terminates the selection. If the clock signal Φ is generated too early, in particular the sense amplifier SA- accordingly begins its amplification operation, regardless of the fact that the coupled data lines have not yet received the signal Δν_ at a sufficiently high level. As a result, the sense amplifier SA- is enabled to perform the malfunction. If the output time of the clock signal Φ_, _Λ to a sufficient

ir A.

On the other hand, the malfunction of the sense amplifier SA- can be prevented. In In this case, however, the access time of the D-RAM is restricted by the late start-up of the sense amplifier SA ^. In order to prevent the circuit from malfunctioning and to shorten the access time, it is therefore necessary to set the clock signal Φ-- precisely, as above

IrA.

has been described.

In addition, the appropriate output timing of the clock signal Φ- is also made by the fluctuations in the circuit characteristics influenced by the dispersion of the manufacturing conditions and by the fluctuations the operating temperature of the MOSIC.

_{For example, the word lines WL- and WL 1} "shown in the circuit diagram of FIG. 8 are made of a material layer with a high melting point, such as a conductive polysilicon layer or a molybdenum silicide layer, which is formed simultaneously with the gate of the switch MOSFET Q _M. Each of these word lines has a resistance that cannot be neglected.

In addition, each of the word lines is connected to a para-

33U002

Sited capacitor coupled, · the one from the gate capacitor of the switch MOSFET ζλ. is constructed. As a result from this, each of the word lines essentially constitutes a circuit with constant distribution (distribution constant circuit). In other words, each word line has a delay characteristic that cannot be neglected, Incidentally, of the two connections of each word line, which extend onto the semiconductor substrate, the connection to which the output of the decoder RC-DCR is to be applied, as the "nearby connection of the word line" whereas the connection remote from the decoder RC-DCR is referred to as the "remote connection of the word line" will.

The time from the moment the decoded signal is applied to the nearest terminal of the word line to be selected to the moment the potential at the distant terminal of that word line rises to a level higher than the . desired value is influenced by the delay characteristics of the same word line. If the clock signal Φ _{ΌΆ is generated} at a relatively early point in time, it becomes impossible to read the information of the memory cell, which is in the vicinity of the remote. Connection of the word line is arranged to be read in the normal way.

In order to enable normal data reading regardless of the delay characteristics of each word line caused by the scatter in IC manufacturing and fluctuations in the operating temperature, the delay characteristics of a corresponding line are detected. The timing of the generation of the clock signal Φ for controlling the sense amplifier SA ₁ is changed in accordance with the detected value.

An embodiment that enables these operations is constructed in the following manner.

Specifically, the signal is at the remote terminal of the paired dummy word lines to which how shown in Figure 8, the dummy cell is coupled, formed as the input pulse, which is not shown Pulse generator <i> -GEN is to be given that is designed to have a structure similar to that of the circuit in FIG. In this case, to to prevent the remote connections of the paired dummy word lines from being short-circuited, and to allow the pulse generator Φ -GEN on the

ir A.

To respond to a change in potential at the remote connection of each dummy word line, a suitable voltage composer is provided. This voltage composer (not shown) can be constructed from: A pair of input MOSFETs whose sources are connected in common to an output node, whose gates are connected to the remote connections of the respective dummy word lines and whose drains are connected to the connection connected to a source of supply; and a precharge MOSFET whose drain-source path is connected between the output node and a grounded point and whose gate is supplied with a precharge signal which is in phase with the RAS signal. The output of the voltage synthesizer thus constructed is given as an input pulse to the pulse generator Φ -GEN. The output of this pulse generator Φ _ρ -GEN is used as the clock signal Φ_-.

This structure makes use of the feature that the paired dummy word lines are made to have have the same structure as each word line of the memory arrangement M-ARY shown in FIG. 8, so that essentially their delay characteristics match those of each word line. As a result of that the work level of the input pulse from the pulse generator Φ -GEN

- 38 - 33H002

is suitably set, the clock signal Φ _ρΑ can be generated at the same time that the potentials at the remote terminals of the dummy word line are raised to a suitable value.

The simulation of the delay characteristics of each word line can be carried out by providing and using an additional dummy word line which is carried out independently of the paired dummy word lines. In this case, the additional word line is held at the selected potential even if, for example, one of the paired dummy word lines is selected in response to the signal aUS corresponding to _{the clock signal Φ ν.} If the additional dummy word line is made available, its remote connection can be switched directly to the input of the pulse generator Φ -GEN.

According to the structure described so far, the malfunction can be prevented because the clock signal Φ _{ρ can be} reliably generated in synchronism with the dip selection terminating clock of the memory cell located on the remote terminal side of the word line. In addition, the D-RAM can be made available at a high operating speed because · · there is no need to provide a time frame exceeding the necessary amount for the increase in the clock pulse Φ _ρ . Furthermore, this clock signal Φ _ρ 'can be generated in accordance with the fluctuations and dispersion of the modes selecting the word line. The present invention is not intended to. Embodiments described so far are limited.

The following MOSFETs can be added to the one shown in FIG Circuit to be added,

To shorten the access time of the D-RAM is e.g. sought that the clock pulse generators returned to their precharge states within a relatively short period of time are when the RAS and the CAS signal are not on the

33H002

D-RAM can be given. In the circuit shown in Figure 3, the period from the moment the precharge is started to the moment the node N-. assumes the sufficient precharge level (ie, the low level) is relatively elongated. In detail, the precharge of the node N., because it is _{carried out via the MOSFET Q 5} , is not started for as long _? How the MOSFET Qt- is kept in its non-conductive state even if the input pulse Φ is lowered to the low level simultaneously with the generation of the precharge pulse Φ. The time at which the MOSFET Q ₅ is switched on is shifted, taking into account the precharge pulse Φ, by such a delay time as is determined by the precharge MOSFET Qg and the interruption MOSFET Q ₁ . The precharge rate of node N ₁ when MOSFET Q _{5 is} on is limited by the conductivity characteristics of the same MOSFET Q ₁ -.

So that the MOSFET Q ₅ can be brought from its non-conductive to its conductive state within as short a period of time as possible after the precharge pulse has been generated, a first MOSFET can be made available whose drain-source path is between the connection of the supply source V and the gate of the MOSFET Q _{5 is} switched and the gate of the precharge pulse Φ is applied.

To the node N ₁ to. enable to restore its precharge state directly, a second MOSFET can also be made available, the drain-source path of which is connected between the node N ₁ and the ground point of the circuit and whose gate is applied with the precharge pulse Φ. If necessary, a third MOSFET can also be made available, the drain-source path of which between the node N ₁ and the drain terminal of the

_ _4O ._ 33H002

second MOSFET is switched and its gate with the Voltage of the supply source is applied.

Both the first and the second MOSFET or just one of the two can be provided will.

In order to enable the output pulse Φ to restore its precharge level in a more direct way, a fourth MOSFET can also be made available, the drain-source path of which is connected in parallel _{with the drain-source path of the output MOSFET Q 4} and the precharge pulse Φ is applied to its gate.

If the first, second and fourth MOSFETs are made available at the same time, the precharge rate will be of the clock pulse generator increased further.

On the other hand, the means for detecting the voltage can initiate the bootstrap mode of action can be modified in various forms, including means that use a voltage comparator make applying different! speed MOSFETs etc.

Claims (1)

iL * .; 33H002 WIDENMAYERSiTKÄSSE 17, D-8000 MUNICH 22 HITACHI, LTD. April 18, 1983 DEA-25 963 • Clock generator and dynamic memory that works with it PATENT CLAIMS 1. Clock pulse generator, characterized by (a) a first IGFET (Q _1. ) for applying an input pulse to a first circuit point (N-), (b) a bootstrap capacitor (^ _B ) _t between the said first node (N.) and a second node is switched, and (C) a driver (Q ₁ , Q ₀ , Q ^ -Q _1n ), which is designed so that it is ready to receive a voltage that occurs at said first node (N ..) as an input voltage and the therefore serves to generate an output voltage at said second node which is designed so that it then has a low level when said input voltage is lower than a value to be detected, and which then has a high level when said input voltage is higher than the stated value is j NAOHeEREtOHT where at said first circuit p ^ i.kt (N.) a signal is generated at an increased level. 2. clock pulse generator according to claim 1, characterized in that said driver includes: (a) a voltage detector (CL-Q _1n ) for generating the output voltage which occurs at said first node (N ^); and (b) a bootstrap capacitor control circuit (Qi / Q ^) / which is designed in such a way that it is ready to receive a _{signal that is generated by said voltage detector (Q fi} -Q 1o) for generating an output voltage which at. to be applied to said second node. , 3. clock pulse generator according to claim 2, characterized in that said voltage detector Q ₁₀ ) generates a signal which has a high level, * "** if its input voltage is lower than the one to be detected Is value and has a low level when said input voltage is higher than said value; and that the bootstrap capacitor drive circuit (Q, Q) is on Generates a signal whose phase position is opposite to that of the signal from the said voltage detector (19) is detected and fed by this. ORIGINAL INSPECTED .:!, ί * * .Γ '% 1 ~' ". ·. * '. *' j NACHQEREIOHTJ 4. clock pulse generator according to claim 3, characterized in that said IGFET (Q, -) (a) has a drain-source path extending between a node connected to said input pulse is acted upon, and said first node (N ^) is switched; and (b) has a gate to which the output of said voltage detector (Q ^ -Q ₁ ) is applied. 5. clock pulse generator according to claim 4, further characterized in that a second IGFET (Q) has a drain-source path between the output terminal of said voltage detector (Q ^ -Q ₁ ") and the gate of the D IU called first IGFET (Q ^) is connected, and a gate ■ has, which is applied with a reference voltage. 6. clock pulse generator according to claim 3, characterized in that said voltage detector (a) a third (Q ") and a fourth (Q) IGFET, whose Drains and gates are cross-connected with each other; · (b) a fifth IGFET (Q ^) whose drain-source path is connected between the connection of a supply source (V ^) and the drain connection of said third IGFET (Q_), and the gate of which is connected to said first node (N ₁ ); and (c) a load element (Q ₀ ) between the terminal of the \ Y \ J IT PAIRED] Supply source ^ qq} ^{and the} drain ¹ connection of said fourth IGFET (Q ₉ ) is connected. 7. clock pulse generator according to claim 6, characterized in that said load _{element includes a sixth IGFET (Q 0} ) whose drain Source path between the mentioned connection of the supply 5. source ( ^v _rr ) and the drain of said fourth IGFET (Qg) is connected, and des'sen gate with a pulse signal is to be applied, said voltage detector (Q ,, - Q ₁ _) is operated dynamically. ■ 0 IU 8. clock pulse generator according to claim 7, further characterized in that it has a seventh IGFET '(Q _1n ) whose drain-source path is connected in parallel with .dem' drain-source path of said third IGFET (Q ₇ ) and whose gate is to be "hit" with the said pulse signal. 9. clock pulse generator according to claim 3, characterized ge. indicates that said footstrap capacitor control circuit (Q ₁ , Q ₃ ) comprises: (a) a second IGFET (Q ₂ ) whose drain-source path is connected between said second circuit point and the ground point of said drive circuit ^ and whose gate is to be supplied with the output of said voltage detector (Qg ^- QI (O; and ORIQINAL INSPECTED 33H002 NACHQEREIOHTj (b) a load element (Q ₁ ) which is connected between the connection of the supply source ( ^v cc ^ and said second circuit point. 10. clock pulse generator according to claim 9, characterized in that said load element _{includes a third IGFET (Q 1} ) whose drain-source path is connected between the connection of the supply source (V ₀₀ ) and said second node, and its gate is switched to said first switching point (N ₁ ). • 11. The clock pulse generator of claim 3 further characterized characterized in that an output circuit '(Qo / Q4) includes: .. (a) a first output IGFET (Q ₄ ) having a gate terminal to which the output of said voltage detector _{(Q g -Q 1n} ) is to be applied, a drain terminal and a source terminal; and . (b) a second output IGFET (Q ₃ ) which has a gate connection connected to said first node (N ₁ ), a drain connection and a source connection. 12. Dynamic memory, labeled by (a) a memory array (M-ARY) containing a plurality of :: "ί? ' ::.: Inaohoereioht - ·, - or - i. · - I memory cells (M-CEL) arranged in a matrix form, a multitude of data lines (DL) to which the data input and output terminals of the corresponding memory cells are connected, and a plurality of word lines (WL) to which the selection terminals of the corresponding Memory cells are connected; (b) a plurality of dummy cells (D-CEL) which are each connected to said data lines (DL); (c) a dummy word line for selecting said dummy cells (D-CEL); (d) a plurality of sense amplifiers (SA), each are connected to said data lines (DL); and (e) a plurality of clock pulse generators for generating clock pulses, each of said clock pulse generators includes: · '■ (a) a first IGFET that has its drain-source. Path an input pulse to a first node creates; , (b) a bootstrap capacitor connected between the said ^ first node and a second node is switched; (c) a voltage detector designed to. ' that it is ready to receive a voltage appearing at said first node as an input voltage is and therefore produces an output voltage which is designed to be high when the said input voltage is lower than a voltage to be detected • * -B ST _ »-. ■ ₄ * * tr · ν «· # ' * t ft * fv , SUBMITTED Value, and which then has a low level when the input voltage is higher than the value is; (d) ·. a bootstrap capacitor drive circuit for generating a signal at said second node which is designed so that there is a phase position opposite to that of the output voltage fed by said voltage detector; and (e) a push-pull output circuit with first and second output ^ IGFETs, which are adapted so that they are both from an output voltage from the calledon Voltage detector is generated as well as by a. Voltage at said first node step, be controlled. 13.. Dynamic memory according to claim 12, characterized in that the operation of each of the said sense amplifier is controlled by one of said clock pulse generators, and in that the input pulses that are sent to the clock pulse generator for controlling the operation of said sense amplifiers are to be applied, are generated from the other terminal of the dummy word line, one terminal of which is acted upon by a control signal.