DE3026143C2 - Method and circuit arrangement for the transmission of information - Google Patents

Description

The present invention relates to a method for transmitting information according to the generic term of claim 1 and a Schaltur-fsanordnung to Implementation of this procedure.

From DE-OS 27 09 620 an arrangement for automatic contact-free detection of along a Location signs arranged in the lane become known. There is a moving vehicle there Transmitter / receiver arranged with a beam emitted by a directional antenna in passing Overwashes reflectors, the reflectors being connected to a characteristic modulation generating Control circuit are connected. An evaluation circuit is connected to the receiver in the vehicle, which are due to the coming back from the various reflectors and which are different in each case due to the reflectors modulated received radiation responds. The control circuit connected to the reflector causes a change in its terminating impedance in the rhythm of a pseudo-stochastic binary sequence characteristic of the respective reflector.

A pure information coding with pseudo-stochastic binary sequences PRBS (Pseudo Random Binary Sequences) are tight limits. If you use binary sequences of maximum length MLBS (Maximal Length Binary Sequences), the theory shows (see e.g. W. D. T. Davies "System Recognition for Adaptive Controls", published by R. Oldenbourg Verlag, Munich-Vienna. 1973. in particular section »Generation and Properties binary sequences of maximum length «on page 57 ff) that for the coding of, for example, 1800 ! information a shift register with a length of

15 bits and a shift register chain for a word length of 32 767 bits is required for decoding. Consider one, that with the known arrangement per bit in the shift register chain two evaluation resistors are provided, it is evident that serial bit sequences of this length can no longer be processed economically permit.

It is therefore the object of the present invention to specify a method for the transmission of information, in which a large number of information can be transmitted with little effort without affecting the known advantages of the pseudo-stochastic binary sequences, such as correlability, for example must become. This object is achieved according to the method characterized in claim 1. Further are advantageous embodiments of the method and an arrangement for performing the method can be found in the subclaims.

On the basis of an embodiment shown in the figures of the drawing, the invention is described below described in more detail. It shows

F i g. 1 shows a circuit arrangement for assigning different binary sequences of maximum length to one binary encrypted information;

F i g. 2 shows a first circuit arrangement for decoding the encrypted information; and

3 shows a second circuit arrangement for decoding of the encrypted information.

According to FIG. 1, a three-stage shift register 101-103 forms the basic component of the coding circuit. The theory reveals that at least one three-stage shift register is required to accommodate two binary sequences to generate maximum length. These binary sequences of maximum length are 7 bits in length. To the Generating the two different binary sequences of maximum length are different feedbacks of the shift register stages via exclusive OR gates 104,105 are required. To suppress the condition in which all shift register stages 101-103 output the value "0", which by definition is a Binary sequence of maximum length is excluded, the outputs of stages 101 and 102 are via a NOR gate 106 and an OR gate 107, to which the output signal of the exclusive OR gate 104 is also switched on is fed back to the input of the shift register chain.

The one formed by the exclusive OR gates 104, 105 Feedback is structured as follows. One input of the exclusive-OR gate 105 is connected to the Output of the last .Schieferegisterstufe 103 connected and the other input of this gate is over an electrical switch 108 can be connected to the output of the second shift register stage 102. The exit of the gate 105 is led to an input of the further exclusive-OR gate 104. The second entrance this gate 104 is connected to the output of the first shift register stage via a further electronic switch 109 connectable. The output of the gate 104 is - as already mentioned - the input of the OR gate 107 switched.

The electronic switches 108, 109 are controlled by a binary code which is stored in a memory UO, this memory being able to consist of a random access memory RAM or a programmable read-only memory PROM . The memory 110 is addressed by a counter 111. The respective addressed bit of the stored binary code controls the switch 108 directly and the switch 109 via an inverter 112. so that, depending on the binary state of the bit, only one of the two switches 108, 109 is actuated and the corresponding binary sequence of maximum length is generated.

A NOR gate 113 combines the output signals of the the last two shift register stages 102 and 103 and its output signal is used to determine the count de. Counter 111 to increase, since the bit combination 00 in the last two shift register stages the end

ίο signaled a binary sequence of maximum length. When the counter 111 has reached a count η corresponding to the word length of the memory 110, it is automatically reset to 0 and the coding process begins again. A central clock controls the bit shift through the shift register and the counting country increment of the counter. For the sake of simplicity, this clock control has not been shown

The mode of operation of the circuit arrangement according to FIG. 1 is explained using a practical example assumed that 5,000 pieces of information were to be transmitted along a certain route shtd. In this case 5000 of the circuit arrangements shown in FIG. 1 are required for generating location signs. The memory 110 must have a word length of 13 bits (2 "* .. 8192). The counter 111 must also have a Have a counting capacity of 13. With the three-stage feedback shift register 101-103 two binary strings of maximum length with one word length

jo generated by 7 bits, so that with the inventive Code nesting results in a total word length of 91 bits per information to be transmitted

When switching on the circuit arrangement according to FIG. 1 the counter 111 is at 0. The NOR gate

J5 ter 106 ensures that there is no "0" information chain in the shift register. When the count is 0, the information (“1” or “0”) stored in the memory 110 under address 0 is applied to the switch 108 directly and inverted via the inverter 112 to the switch 109. The first binary sequence of maximum length is then generated. As soon as the last two bits with the value "0" in the shift register signal the end of the binary sequence of maximum length, the count of the counter ί 11 is increased by one via the NOR gate 113 and the number at address I in the memory 110 is increased stored information is applied to the switches. This process of increasing the address and actuating the switch is repeated after each transmitted binary sequence of maximum length until the counter 111 has reached a count π corresponding to the word length of the stored binary word. If this is the case, then the counter 111 is reset to 0 and the coding process can begin again.

In order to recognize and decode the transmitted information, the system shown in FIG. 2 shown circuit arrangement are used, as shown and described in principle in DE-OS 27 09 620 :. This circuit arrangement is in a known manner

ω from a shift register with the shift register stages 201 to 207, in which the incoming pulse train is entered step by step. The length of this shift register is matched to the maximum length of the incoming binary sequence. The outputs of the individual

b5 ncn slide gate stages are via evaluation resistors, which are not numbered, connected to search filters 208 and 209 for the binary value "0" and "1". For more details, see the above

referenced published patent application. To the outputs of the group consisting of summing amplifiers filters 208.209 which the two possible binary sequences with a maximum length assign the binary values "0" and "I", a SSS memory flip-flop is connected, its j Q output according to the decoded result " 0 «or» 1 «is set.

The circuit arrangement according to FIG. 2 is in principle with the same clock frequency as the sound arrangement according to FIG. 1 operated. However, a slight frequency offset is beneficial, as is the case with the cited publication can be found.

A compared to the decoder circuit according to FIG. 2 more advantageous circuit is shown in FIG. Here there are no evaluation resistances and search filters. The outputs of the shift register stages 301 to 307 are connected to a memory with random access RAMMQ, which stores the pending binary sequence of maximum length under an address which is specified by a programmable read-only memory 309. A counter 308 counts - starting from the counter status 0 - again up to 13, whereby it is again incremented if the last two bits of the sequence which are fed to its input have the value "0". With each step of the counter 308, the next address of the memory RAM-3 \ 0 is selected via the read-only memory PR0M-3QQ and the pending binary sequence of maximum length is admitted. When all 13 binary sequences of maximum length with 7 bits each for the 13 bits of the binary encrypted information jo have been transmitted, the address counter 308 is reset and the decoding can start again, whereby the content of the memory RAM-3i0 can be corrected under certain circumstances. A memory counter 312 counts the decoding processes and, with a certain number of decoding processes, enables a processor 311 which evaluates the data according to a specific program.

The embodiment described above with a three-stage feedback shift register and an evaluation circuit with a 7-suifigen shift register chain represents the simplest implementation of the inventive concept. In principle, n-stage feedback shift registers can be used for coding and 2 " - 1-stage shift register chains for deco If you want to encode further information in addition to the binary values “0” and “1”, for example an initialization command, at least one further pseudo-stochastic binary sequence of maximum length MLBS is required for the coding and a three-stage feedback shift register is no longer sufficient.

For this purpose 3 sheets of drawings

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60

Claims (14)

Patent claims: 1. Method of transmitting a variety of information using pseudo-stochastic Binary sequences, characterized by a binary encryption of the information and assignment of different pseudostochastics Binary sequences for the binary states "0" and "1". 2. The method according to claim 1, characterized by the use of pseudo-stochastic Binary strings of maximum length. 3. The method according to claim 2, characterized by the use of pseudo-stochastic Binary sequences of maximum length with the smallest possible bit word length. 4. Circuit arrangement for performing the method according to claim 1 or one of the following with a; Multi-stage feedback shift register at the transmission end, characterized by the arrangement of switches (108, 109) in the feedback loops of the shift register (101-103 ) which are operated in opposite directions by the individual bits of the information to be transmitted. 5. Circuit arrangement according to claim 4, characterized by a first exclusive OR gate (104) which is connected with its output to the input of a three-stage shift register and which has an input to the output of a further exclusive ODEK gate (105) and a further input via a first switch (109) is connected to the output of a first shift register stage (101) , one input of the further exclusive-OR gate (105) being connected to the output of a second shift register stage (103) and the other input is connected to the output of a third shift register stage (102) via a second switch (108) . 6. Circuit arrangement according to claim 5, characterized by one of a counter (111) addressable memory (110) for receiving a coded binary word. 7. Circuit arrangement according to claim 6, characterized in that the bits of the memory (110) are fed in sequence to the second switch (108) directly and to the first switch (109) via an inverter (1 12) for their actuation. 8. Circuit arrangement according to Claim 7, characterized in that the outputs of the second and third shift register stages (102, 103) are fed to the incremental input of the counter (111) via a NOR gate (113) . 9. Circuit arrangement according to claim 8, characterized in that the outputs of the first and second Schiebercgisterslufe (t01,102) via a NOR gate (106) are fed to the input of the shift register (101-103 ). 10. Circuit arrangement according to claims, characterized in that the counter (111) is reset when t> o reaching a count corresponding to the number of bits of the binary word stored in the memory (110). 11. Circuit arrangement for carrying out the method according to one of claims 1 to 3 with a receiving end matched to the bit length of the binary sequence of maximum length, the outputs of which are connected to search filters via ßcwcrtungswidorstiindc, characterized in that the outputs of the search filter ( 208,209) an AS flip-flop (210) is connected, which serially outputs the decoded binary code. 12. Circuit arrangement for carrying out the method according to one of claims 1-3 with a receiving-side shift register graduated to the bit length of the binary sequence of maximum length, characterized in that a memory (i "AM- 310) is connected to the outputs of the shift register stages (301-307 ) is connected, in which the bit sequence present per binary sequence of maximum length is stored under specifiable addresses and that a processor (311) is also arranged for processing the information stored in the memory (RAM-31Q). 13. Circuit arrangement according to claim 12, characterized in that a first counter · - (308) is arranged. which addresses the memory (RAM- 310) via a programmable read-only memory (PROM-309) and that a further counter (312) is provided which enables the processor (311) after a predeterminable number of decoding processes. 14. Circuit arrangement according to claim 13, characterized in that the count of the first Counter (308) when the binary value "0" occurs at the outputs of the last two shift register stages (306,307) is increased by one and that this counter (308) for one of the number of bits of the encoded The counter value corresponding to the binary word is reset to 0.