DE2929060A1 - Integrated MOS semiconductor circuit prodn. - by double silicon gate technology using anisotropic etching to give stepped profile - Google Patents
Integrated MOS semiconductor circuit prodn. - by double silicon gate technology using anisotropic etching to give stepped profileInfo
- Publication number
- DE2929060A1 DE2929060A1 DE19792929060 DE2929060A DE2929060A1 DE 2929060 A1 DE2929060 A1 DE 2929060A1 DE 19792929060 DE19792929060 DE 19792929060 DE 2929060 A DE2929060 A DE 2929060A DE 2929060 A1 DE2929060 A1 DE 2929060A1
- Authority
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- Germany
- Prior art keywords
- etching
- poly
- silicon
- gate technology
- structuring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000005530 etching Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 9
- 229910052710 silicon Inorganic materials 0.000 title claims description 9
- 239000010703 silicon Substances 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000009413 insulation Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 7
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 4
- 150000008280 chlorinated hydrocarbons Chemical class 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- WMIYKQLTONQJES-UHFFFAOYSA-N hexafluoroethane Chemical compound FC(F)(F)C(F)(F)F WMIYKQLTONQJES-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 229910052736 halogen Inorganic materials 0.000 claims description 2
- 150000002367 halogens Chemical class 0.000 claims description 2
- 229930195733 hydrocarbon Natural products 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims 2
- 239000004926 polymethyl methacrylate Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- -1 hydrocarbons Methane series Chemical class 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 239000011521 glass Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical class C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Verfahren zum Herstellen von integrierten MOS-Halb-Method for producing integrated MOS half
leiterschaltungen nach der Doppel-Silizium-Gate-Technologie.conductor circuits based on double silicon gate technology.
Die Patentanmeldung setrif<t ein Verfahren zum Herstellen von integrierten MOs-Schaltungen nach der Doppel-Silizium-Gate-#echnologie, bei dem die beiden Poly-Silizium-Ebenen (Poly-Silizium-1 und Poly-Silizium-2) durch eine Isolationsschicht gegeneinander isoliert sind.The patent application describes a process for the production of integrated MOs circuits based on the double silicon gate technology, in which the two polysilicon levels (Poly-Silicon-1 and Poly-Silicon-2) against each other through an insulating layer are isolated.
Der Doppel-Silizium-Gate-Prozeß, wie er der vorliegenden Patentanmeldung zugrundeliegt, ist dem Digest of Technical Papers der im Februar 1976 stattgefundenen IEEE International Solid-State-Circuits Conference, Seite 128/129, zu entnehmen. 3ei diesem Verfahren wird über den kritischen Profilstufen der Poly-Silizium-1-Strukturen und dem darüberliegenden Isolationso@id eine zweite Poly-Silizium-Ebene abgeschieden. Aufgrund der Abscheidebedingungen fUllt das Poly-Siliziun-2 die beim isotropen Ätzen (d. h. Ätzrate in allen Richtungen gleich) der Poly-Silizium-1/Oxid-Doppelschicht entstandenen Hohlkehlen so gut aus, daß keine Einschnürungen bzw. Unterbrechungen der Poly-Silizium-2-Stnikturen an kritischen Poly-Silizium-1 -Profilstufen entstehen können. Zum Fertigstellsn der integrierten Halbleiterschaltung sind jedoch noch Metall-Leiterbahnen einer weiteren Verdrahtungsebene über den kritischen Poly-Silizium-1/Oxid-Profilstufen anzubringen, bei welchen Einschnürungen und Kantenabrisse durch die kritischen Poly-Silizium-1 /Oxid-Profilstufen verursacht werden können.The double silicon gate process as described in the present patent application is based on the Digest of Technical Papers that took place in February 1976 IEEE International Solid State Circuits Conference, pages 128/129. In this process, the critical profile levels of the polysilicon 1 structures and the overlying Isolationso @ id deposited a second polysilicon level. Due to the deposition conditions, the poly-silicon-2 fills the isotropic etching (i.e. etch rate in all directions same) the poly-silicon-1 / oxide double layer resulting fillets so well that no constrictions or interruptions of the poly-silicon-2 structures arise at critical poly-silicon-1 profile steps can. To finish the integrated semiconductor circuit, however, are still Metal conductor tracks of a further wiring level above the critical poly-silicon-1 / oxide profile levels to attach, in which constrictions and edge tears due to the critical polysilicon 1 / Oxide profile steps can be caused.
Aus der US-PS 3.825.442 ist ein Verfahren zur Herstellung integrierter MOS-Halbleiterschaltungen in Silizium-Gate-Technologie zu entnehmen, bei dem zur Vermeidung dieser Einschnürungen und Kantenabrisse vor dem Aufbringen der Metall-Leiterbahnebene eine Phosphorglasschicht (sogenanntes Flow-Glas) verwendet wird. Dieses Phosphorglas fließt bei einem nachfolgenden Temperprozeß über die Kanten und entschärft dadurch die kritischen Poly-Silizium-1 /Oxid-Stufen.From US-PS 3,825,442 a method for the production of integrated MOS semiconductor circuits in silicon gate technology can be found in the Avoidance of these constrictions and edge tears before applying the metal conductor track level a phosphor glass layer (so-called flow glass) is used. This phosphor glass flows over the edges during a subsequent tempering process, thereby defusing the critical poly-silicon-1 / oxide levels.
Die bekannten Verfahren haben folgende Nachteile: a) Das gute Ausfüllen von Hohlkehlen durch die zweite Poly-Silizium-Ebene erfordert beim Strukturieren dieser Schicht eine starke Zugabe in der Ätzzeit (bis zu Faktor 2 gegenüber normaler Ätzung). Dadurch sollen Kurzschlüsse zwischen den Strukturen der Poly-Silizium-2-Ebene durch unvollständiges Ätzen entlang der Hohlkehlen vermieden werden. Längere Ätzzeiten bedeuten größere Unterätzungen pro Kante. Damit verbunden ist ein größerer Platzbedarf bzw. eine Verminderung der Integrationsdichte der entsprechenden integrierten Schaltung. Zusätzlich kann unter Umständen die Reproduzierbarkeit des Ätzprozesses leiden.The known methods have the following disadvantages: a) Good filling out of fillets through the second poly-silicon level required when structuring This layer has a large addition in the etching time (up to a factor of 2 compared to normal Etching). This should short-circuits between the structures of the polysilicon-2 level can be avoided by incomplete etching along the fillets. Longer etching times mean larger undercuts per edge. Associated with this is a larger space requirement or a reduction in the integration density of the corresponding integrated circuit. In addition, the reproducibility of the etching process may suffer.
b) Der Flow-Glas-Schritt stellt einen zusätzlichen Prozeßschritt dar, das heißt, die Ausbeute sinkt und die Kosten pro Chip steigen. Da der Flow-Glas-Schritt bei 1000 bis 11000C ausgeführt wird, können Eindringtiefen von Diffusionen bzw. Profile von implantierten Bereichen ungünstig beeinflußt werden.b) The flow glass step represents an additional process step, that is, the yield decreases and the cost per chip increases. Because the flow glass step is carried out at 1000 to 11000C, penetration depths of diffusions or Profiles of implanted areas are adversely affected.
Die Aufgabe, die der vorliegenden Erfindung zugrundeliegt, besteht nun darin, die beim Doppel-Silizium-Gate-Prozeß auftretenden kritischen Profilstufen der Poly-Silizium-1-Ebene mit dem darüber liegenden Isolationsoxid durch ein einfaches, reproduzierbares Ätzverfahren so zu gestalten, daß ohne Durchführung einer zusätzlichen Phosphorglasabscheidung und ohne die Einhaltung kritischer atzzeiter Risse und Kantenabbrüche an den später aufzubringenden Leiterbahnen vermieden werden.The object on which the present invention is based exists now it is the critical profile steps that occur in the double silicon gate process the poly-silicon-1 level with the insulation oxide above it by means of a simple, to make reproducible etching process so that without performing an additional Phosphorus glass deposition and without adhering to critical etching time cracks and broken edges can be avoided on the conductor tracks to be applied later.
Diese Aufgabe wird durch die Erfindung dadurch gelöst, daß zur Ausbildung treppenförmiger Po ly-Silizium-1 -Isolationsschicht-Profilstufen unter Verwendung der bei der Strukturierung der Isolationsschicht durch eine isotrope Ätzung vorgesehenen Photolackmaske ein Ätzprozeß zur Strukturierung der Poly-Silizium-1-Schicht durchgeführt wird, bei dem überwiegend die vertikale Ätzkomponente in Bezug auf die Oberfläche der Anordnung wirksam wird.This object is achieved by the invention in that for training stair-shaped poly-silicon-1 insulation layer profile steps using which is provided during the structuring of the insulation layer by isotropic etching Photoresist mask carried out an etching process for structuring the poly-silicon-1 layer in which predominantly the vertical etching component in relation to the surface the order takes effect.
Dabei liegt es im Rahmen des Srfindungsgedankens, einen physikalischen Ätzprozeß wie Plasma-Atzen oder reaktives Ionenätzen dem zur Strukturierung des Isolationsoxids vorgesehenen isotropen Ätzprozeß anzuschließen.It is within the scope of the concept of the invention, a physical one Etching process such as plasma etching or reactive ion etching to structure the Isotropic etching process provided to connect insulation oxide.
Aufgrund der Ligenschaften des reaktiven lonenLÄtzens oder des Plasmaätzens fungieren nicht die Kanten der z. .Due to the properties of reactive ion etching or plasma etching do not act the edges of the z. .
naß chemisch erzeugten Isolationsoxidstrukturen als Ätzmaske, wie es beim Stand der Technik der Fall ist, sondern die Kanten der Photolackmaske. Da beim reaktiven Ionen- ätzen (nur die vertikale Ätzkomponente wird wirksam# sogenanntes anisotropes Ätzen) die Unterätzungen vernachlässigbar gering sind, entsprechen die Abmessungen der Poly-Silizium-1-Strukturen etwa denen der Photolackstrukturen.wet chemically generated isolation oxide structures as an etching mask, such as it is the case in the prior art, but rather the edges of the photoresist mask. There in reactive ion etch (only the vertical etch component will effective # so-called anisotropic etching) the undercuts are negligible are, the dimensions of the polysilicon-1 structures correspond approximately to those of Photoresist structures.
Man erhält eine Struktur, deren Querschnitt aus der Figur, welche einen Ausschnitt eines, einer REM (Rasterelektronenmikroskop)-Aufnahme nachgezeichneten Teiles einer erfindungsgemäßen Halbleiteranordnung darstellt, zu entnehmen ist. Dabei ist mit dem Bezugszeichen 1 das aus Silizium bestehende Halbleitersubstrat, mit 2 das darauf abgeschiedene Feldoxid, mit 3 die nach dem erfindungsgeinäßen Verfahren durch reaktives lonenätzen strukturierte Poly-Silizium-1-Schicht, mit 4 das auf isotropen Wege (z. B. naßchemisch) strukturierte Isolationsoxid und mit 5 die bei beiden Ätzprozessen als Maske wirkende Photolackschicht dargestellt. Der Pfeil 6 zeigt auf die beim isotropen Ätzen entstandene Unterätzung des Isolationsoxids 4.A structure is obtained, the cross-section of which can be seen in the figure a section of a SEM (scanning electron microscope) image traced Part of a semiconductor arrangement according to the invention is shown. In this case, the reference numeral 1 denotes the semiconductor substrate made of silicon, with 2 the field oxide deposited thereon, with 3 that according to the method according to the invention by reactive ion etching structured poly-silicon-1-layer, with 4 on it Isotropic ways (z. B. wet chemical) structured isolation oxide and with 5 the at photoresist layer acting as a mask for both etching processes. The arrow 6 shows the undercutting of the insulation oxide 4 that occurred during isotropic etching.
Als reaktive Gase beim physikalischen Ätzen werden insbesondere Fluor- und Chlorkohlenwasserstoffe wie Tetrafluorkohlenstoff (CF4), Tetrachlorkohlenstoff (CCl4), Trifluormethan (CHF3), Hexafluoräthan (C2F6), Octofluorpropan (C3F8) und/oder Mischungen verschiedener Fluor-und Chlorkohlenwasserstoffe und/oder gasförmige Halogene wie Chlor und Fluor und/oder Kohlenwasserstoffe der Methanreihe mit Sauerstoff oder Stickstoff gemischt, verwendet. Dabei wird zur Einstellung einer Ätzrate von 5 nm/min. bis 500 nm/min. in einem Druckbereich von 5 mTorr bis 500 mTorr mit einer Gasflußrate von 1 ml/min bis 500 ml/min gearbeitet.Fluorine in particular are used as reactive gases in physical etching. and chlorinated hydrocarbons such as carbon tetrafluoride (CF4), carbon tetrachloride (CCl4), trifluoromethane (CHF3), hexafluoroethane (C2F6), octofluoropropane (C3F8) and / or Mixtures of various fluorocarbons and chlorinated hydrocarbons and / or gaseous halogens such as chlorine and fluorine and / or hydrocarbons of the methane series with oxygen or Mixed nitrogen, used. To set an etching rate of 5 nm / min. up to 500 nm / min. in a pressure range of 5 mTorr to 500 mTorr with a gas flow rate worked from 1 ml / min to 500 ml / min.
Nach dem Entfernen der Photolackmaske erfolgen die üblichen Prozeßschritte der Doppel-Silizium-Gate-Technologie bis einschließlich der Reoxidation nach der Source- und Drain-Diffusion. Dann wird ein dotiertes oder undotiertes CVD-(chemical vapor deposition)-Oxid als Zwischenoxid abgeschieden und die integrierte Halbleiterschaltung nach bekannten Verfahrensschritten fertiggestellt (Kontaktlochätzung, Anbringung der Metallkontakte).After the photoresist mask has been removed, the usual process steps take place the double silicon gate technology up to and including reoxidation after source and drain diffusion. Then a doped or undoped CVD (chemical vapor deposition) oxide deposited as an intermediate oxide and the integrated semiconductor circuit Completed according to known process steps (contact hole etching, attachment the metal contacts).
Das Verfahren nach der Lehre der Erfindung hat die Vorteile, daß 1. durch die Übertragung der Maskenmaße im Verhältnis 1 : 1 auf die zu ätzende Poly-Silizium-1-Ebene eine zusätzliche Steigerung der Integrationsdichte erreicht wird, 2. die Poly-Silizium-1-Kanten selbstjustierend zu den Isolationsoxidkanten liegen, was ebenfalls eine Steigerung der Integrationsdichte bedeutet und 3. Risse und Kantenabbrüche an den aufzubringenden Leiterbahnen durch die treppenförmige Profilstruktur vermieden werden, wodurch die Ausbeute erhöht wird.The method according to the teaching of the invention has the advantages that 1. by transferring the mask dimensions in a ratio of 1: 1 to the poly-silicon-1 level to be etched an additional increase in the integration density is achieved, 2. the poly-silicon 1 edges self-adjusting to the insulation oxide edges, which is also an increase the integration density means and 3. cracks and broken edges on the to be applied Conductor tracks are avoided by the stepped profile structure, whereby the Yield is increased.
5 Patentansprüche 1 Figur Leer seite5 claims 1 figure Blank page
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19792929060 DE2929060A1 (en) | 1979-07-18 | 1979-07-18 | Integrated MOS semiconductor circuit prodn. - by double silicon gate technology using anisotropic etching to give stepped profile |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19792929060 DE2929060A1 (en) | 1979-07-18 | 1979-07-18 | Integrated MOS semiconductor circuit prodn. - by double silicon gate technology using anisotropic etching to give stepped profile |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2929060A1 true DE2929060A1 (en) | 1981-02-05 |
Family
ID=6076059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19792929060 Ceased DE2929060A1 (en) | 1979-07-18 | 1979-07-18 | Integrated MOS semiconductor circuit prodn. - by double silicon gate technology using anisotropic etching to give stepped profile |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE2929060A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405256A1 (en) * | 1989-06-27 | 1991-01-02 | STMicroelectronics S.r.l. | A method of hatching micrometric contacts in semiconductor electronic devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2845460A1 (en) * | 1977-10-21 | 1979-04-26 | Ncr Co | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE |
-
1979
- 1979-07-18 DE DE19792929060 patent/DE2929060A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2845460A1 (en) * | 1977-10-21 | 1979-04-26 | Ncr Co | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE |
Non-Patent Citations (1)
| Title |
|---|
| "J. Vac. Sci. Technol.", Bd. 16, Nr. 2, März/April 1970, S. 269-272 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405256A1 (en) * | 1989-06-27 | 1991-01-02 | STMicroelectronics S.r.l. | A method of hatching micrometric contacts in semiconductor electronic devices |
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| OAM | Search report available | ||
| OC | Search report available | ||
| 8110 | Request for examination paragraph 44 | ||
| 8131 | Rejection |