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DE2964037D1 - Method of making interlayer electrical connections in a multilayer electrical device - Google Patents

Method of making interlayer electrical connections in a multilayer electrical device

Info

Publication number
DE2964037D1
DE2964037D1 DE7979300315T DE2964037T DE2964037D1 DE 2964037 D1 DE2964037 D1 DE 2964037D1 DE 7979300315 T DE7979300315 T DE 7979300315T DE 2964037 T DE2964037 T DE 2964037T DE 2964037 D1 DE2964037 D1 DE 2964037D1
Authority
DE
Germany
Prior art keywords
multilayer
making interlayer
electrical connections
electrical device
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979300315T
Other languages
English (en)
Inventor
Don Warren Jillie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Sperry Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Corp filed Critical Sperry Corp
Application granted granted Critical
Publication of DE2964037D1 publication Critical patent/DE2964037D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/80—Material per se process of making same
    • Y10S505/815—Process of making per se
    • Y10S505/816—Sputtering, including coating, forming, or etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Drying Of Semiconductors (AREA)
DE7979300315T 1978-03-02 1979-03-01 Method of making interlayer electrical connections in a multilayer electrical device Expired DE2964037D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/882,826 US4176029A (en) 1978-03-02 1978-03-02 Subminiature bore and conductor formation

Publications (1)

Publication Number Publication Date
DE2964037D1 true DE2964037D1 (en) 1982-12-23

Family

ID=25381412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979300315T Expired DE2964037D1 (en) 1978-03-02 1979-03-01 Method of making interlayer electrical connections in a multilayer electrical device

Country Status (5)

Country Link
US (1) US4176029A (de)
EP (1) EP0004164B1 (de)
JP (1) JPS54125996A (de)
DE (1) DE2964037D1 (de)
IT (1) IT1202900B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
JPS56150883A (en) * 1979-12-25 1981-11-21 Nippon Telegr & Teleph Corp <Ntt> Josephson switching element
US4430790A (en) * 1980-05-20 1984-02-14 Rikagaku Kenkyusho Method of making a Josephson junction
US4370359A (en) * 1980-08-18 1983-01-25 Bell Telephone Laboratories, Incorporated Fabrication technique for junction devices
US4592132A (en) * 1984-12-07 1986-06-03 Hughes Aircraft Company Process for fabricating multi-level-metal integrated circuits at high yields
JPH08511659A (ja) * 1994-04-07 1996-12-03 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 半導体本体表面に多層配線構造が設けられた半導体装置の製造方法
US6331680B1 (en) 1996-08-07 2001-12-18 Visteon Global Technologies, Inc. Multilayer electrical interconnection device and method of making same
US7615385B2 (en) 2006-09-20 2009-11-10 Hypres, Inc Double-masking technique for increasing fabrication yield in superconducting electronics
JP6254032B2 (ja) * 2014-03-28 2017-12-27 住友重機械工業株式会社 Ｓｎｓ型ジョセフソン接合素子の製造方法及びｓｎｓ型ジョセフソン接合素子製造装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588777A (en) * 1968-07-15 1971-06-28 Texas Instruments Inc Superconducting tunneling barriers
US3599009A (en) * 1968-07-19 1971-08-10 Wisconsin Alumni Res Found Neuristor transmission line, learning junction, and artificial neuron
US3837907A (en) * 1972-03-22 1974-09-24 Bell Telephone Labor Inc Multiple-level metallization for integrated circuits
DE2459663C2 (de) * 1974-12-17 1977-01-13 Siemens Ag Verfahren zum herstellen von supraleitfaehigen mikrobruecken
US4096508A (en) * 1975-11-14 1978-06-20 Bell Telephone Laboratories, Incorporated Multiple junction supercurrent memory device utilizing flux vortices
JPS5277695A (en) * 1975-12-24 1977-06-30 Fujitsu Ltd Josephson device
JPS5929136B2 (ja) * 1976-03-30 1984-07-18 株式会社東芝 半導体装置の製造方法
US4060427A (en) * 1976-04-05 1977-11-29 Ibm Corporation Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
DE2629996A1 (de) * 1976-07-03 1978-01-05 Ibm Deutschland Verfahren zur passivierung und planarisierung eines metallisierungsmusters
US4055847A (en) * 1976-08-13 1977-10-25 Nasa Germanium coated microbridge and method
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
US4070501A (en) * 1976-10-28 1978-01-24 Ibm Corporation Forming self-aligned via holes in thin film interconnection systems

Also Published As

Publication number Publication date
JPS639391B2 (de) 1988-02-29
IT1202900B (it) 1989-02-15
EP0004164A1 (de) 1979-09-19
US4176029A (en) 1979-11-27
EP0004164B1 (de) 1982-11-17
JPS54125996A (en) 1979-09-29
IT7920675A0 (it) 1979-03-01

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: UNISYS CORP. (N.D.GES.D.STAATES DELAWARE), BLUE BE

8328 Change in the person/name/address of the agent

Free format text: EISENFUEHR, G., DIPL.-ING. SPEISER, D., DIPL.-ING. RABUS, W., DR.-ING. BRUEGGE, J., DIPL.-ING., 2800 BREMEN MAIWALD, W., DIPL.-CHEM.DR., PAT.-ANWAELTE, 8000 MUENCHEN

8339 Ceased/non-payment of the annual fee