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DE2944614A1 - Sealing system for two-section semiconductor device housing - uses hardening substance poured inside to joint level, followed by second layer - Google Patents

Sealing system for two-section semiconductor device housing - uses hardening substance poured inside to joint level, followed by second layer

Info

Publication number
DE2944614A1
DE2944614A1 DE19792944614 DE2944614A DE2944614A1 DE 2944614 A1 DE2944614 A1 DE 2944614A1 DE 19792944614 DE19792944614 DE 19792944614 DE 2944614 A DE2944614 A DE 2944614A DE 2944614 A1 DE2944614 A1 DE 2944614A1
Authority
DE
Germany
Prior art keywords
parting line
housing
semiconductor device
followed
potting compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19792944614
Other languages
German (de)
Other versions
DE2944614C2 (en
Inventor
Werner 8000 München Egerbacher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19792944614 priority Critical patent/DE2944614C2/en
Publication of DE2944614A1 publication Critical patent/DE2944614A1/en
Application granted granted Critical
Publication of DE2944614C2 publication Critical patent/DE2944614C2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Casings For Electric Apparatus (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The housing for a semiconductor device consists of an upper part (4) and a lower part (1). Both parts are cup shaped, and the upper part has a pouring hole for a sealing mass. The upper part has a groove (6) all round, forming a thin flange (5) which fits inside the wall of the lower part. To seal the two parts without using a sealing ring, the two parts are assembled, and sealing material poured in, until level with a plane (7) just below the external joint line (3). When this has set, a sand material can be poured inside until a second level (8) is reached.

Description

Halbleiterbauelement mit vergossenem Gehäuse undSemiconductor component with encapsulated housing and

Verfahren zum Vergießen Die Erfindung bezieht sich auf ein Halbleiterbauelement mit einem aus einem becherförmigen Unterteil und einem haubenförmigen Oberteil bestehenden Gehäuse, dessen Inneres mindestens bis zur Trennfuge zwischen Oberteil und Unterteil mit einer Vergußmasse vergossen ist.Potting method The invention relates to a semiconductor component with one consisting of a cup-shaped lower part and a hood-shaped upper part Housing, its interior at least up to the joint between the upper part and the lower part is potted with a potting compound.

Ein solches Halbleiterbauelement ist bereits beschrieben worden. Um die Trennfuge zwischen Oberteil und Unterteil gegen ein Austreten der Vergußmasse abzudichten, können bei einem solchen Halbleiterbauelement Oberteil und Unterteil vor dem Vergießen miteinander verklebt werden. Es ist auch denkbar, in die Trennfuge eine elastische Dichtung einzulegen. Die genannten Maßnahmen sind Jedoch nur mittels eines zusätzlichen Arbeitsganges durchzuführen.Such a semiconductor component has already been described. Around the parting line between the upper part and the lower part to prevent the potting compound from escaping To seal, the upper part and the lower part of such a semiconductor component can be used be glued together before potting. It is also conceivable in the parting line insert an elastic seal. However, the measures mentioned are only by means of carry out an additional work step.

Der Erfindung liegt die Aufgabe zugrunde, ein Halbleiterbauelement der oben beschriebenen Art so weiterzu- bilden, daß die Trennfuge auch ohne einen zusätzlichen Arbeitsgang gegen das Austreten der Vergußmasse abgedichtet ist. Außerdem soll ein Verfahren zum Vergießen dieses Gehäuses angegeben werden.The invention is based on the object of a semiconductor component continue in the manner described above form that the parting line sealed against leakage of the potting compound even without an additional operation is. In addition, a method for casting this housing is to be specified.

Die Erfindung ist dadurch gekennzeichnet, daß das Oberteil eine die Trennfuge im Inneren des Gehäuses überlappende Schürze aufweist und daß zwischen der Schürze und dem überlappten Bereich des Unterteils ein bis unterhalb der Trennfuge von der Vergußmasse ausgefüllter Spalt liegt.The invention is characterized in that the upper part is a Parting line in the interior of the housing having overlapping apron and that between the skirt and the overlapped area of the lower part one to below the parting line gap filled by the potting compound.

Beim Vergießen wird dazu zuerst so viel Vergußmasse in das Gehäuse eingegossen, daß der Zwischenraum zwischen Schürze und Unterteil bis unterhalb der Trennfuge gefüllt ist. Dann wird die Vergußmasse ausgehärtet und bis über die Trennfuge Vergußmasse eingegossen.When potting, so much potting compound is first put into the housing poured in that the space between the apron and the lower part to below the Parting line is filled. Then the potting compound is hardened and over the parting line Casting compound.

Die Erfindung wird an Hand eines Ausführungsbeispiels in Verbindung mit der Figur näher erläutert: In der Figur ist ein Gehäuse eines Halbleiterbauelements gemäß der Erfindung im Schnitt dargestellt. Es weist ein becherförmiges Unterteil 1 auf, das mit einer Wand 2 versehen ist. Auf der Wand 2 sitzt ein beispielsweise aus Kunststoff bestehendes haubenförmiges Oberteil 4 auf. Unterteil 1 und Oberteil 4 bilden eine Trennfuge 3.The invention is based on an exemplary embodiment in conjunction Explained in more detail with the figure: The figure shows a housing of a semiconductor component shown according to the invention in section. It has a cup-shaped lower part 1, which is provided with a wall 2. On the wall 2 there is a seat, for example made of plastic hood-shaped upper part 4. Lower part 1 and upper part 4 form a parting line 3.

Das haubenförmige Oberteil weist eine im Inneren des Gehäuses angeordnete Schürze 5 auf, die die Trennfuge 3 überlappt. Zwischen der Schürze 5 und dem von der Schürze 5 überlappten Teil der Wand 2 liegt ein Spalt 6. Dieser Spalt 6 ist bis unterhalb der Trennfuge 3 mit einer Vergußmasse gefüllt und dichtet so die Trennfuge 3 gegen ein Austreten der Vergußmasse ab, ohne daß ein Verkleben der beiden Gehäuseteile oder die Verwendung einer elastischen Dichtung in der Trennfuge notwendig ist.The hood-shaped upper part has one arranged in the interior of the housing Apron 5, which overlaps the parting line 3. Between the apron 5 and that of the skirt 5 overlapped part of the wall 2 is a gap 6. This gap 6 is Filled to below the parting line 3 with a potting compound and thus seals the parting line 3 against leakage of the casting compound without sticking the two housing parts or the use of an elastic seal in the parting line necessary is.

Zum Abdichten wird das Gehäuse zunächst so weit mit Vergußmasse gefüllt, daß sich das durch die gestrichelte Linie 7 angedeutete Niveau einstellt. Dieses Niveau liegt unterhalb der Trennfuge 3. Dann läßt man die Vergußmasse aushärten, so daß im Spalt 6 nunmehr eine aus ausgehärteter Vergußmasse liegende Dichtung vorhanden ist. Nach dem Aushärten wird das Gehäuse weiter bis zur gewünschten Höhe, die zum Beispiel durch die gestrichelte Linie 8 angedeutet ist, mit Vergußmasse gefüllt. Diese kann nun nicht mehr durch die Trennfuge 3 nach außen treten.For sealing, the housing is first filled with potting compound until that the level indicated by the dashed line 7 is established. This The level is below the parting line 3. Then the casting compound is allowed to harden, so that in the gap 6 there is now a seal made of hardened potting compound is. After hardening, the housing is further up to the desired height, which is used for the Example is indicated by the dashed line 8, filled with potting compound. This can no longer pass through the parting line 3 to the outside.

Wie dargestellt, hat die Wand 2 des Unterteils 1 im von der Schürze 5 überlappten Bereich geringere Wandstärke als außerhalb des überlappten Bereichs. Die Wandstärke des Oberteils 4 ist dagegen im wesentlichen überall gleich. Es ist Jedoch auch möglich, die Stärke der Wand 2 überall im wesentlichen gleich zu machen und die Schürze 5 in das Innere des Gehäuses vorspringen zu lassen.As shown, the wall 2 of the lower part 1 extends from the skirt 5 overlapped area has a smaller wall thickness than outside the overlapped area. The wall thickness of the upper part 4, however, is essentially the same everywhere. It is However, it is also possible to make the thickness of the wall 2 essentially the same everywhere and to project the skirt 5 into the interior of the housing.

3 Patentansprüche 1 Figur3 claims 1 figure

Claims (3)

PatentansntUche Ci. Halbleiterbauelement mit einem aus einem gen Unterteil und einem haubenförmigen Oberteil bestehenden Gehäuse, dessen Inneres mindestens bis zur Trennfuge zwischen Oberteil und Unterteil mit einer Vergußmasse vergossen ist, d a d u r c h g e k e n n -z e i c h n e t , daß das Oberteil (4) eine die Trennfuge (3) im Inneren des Gehäuses überlappende Schürze (5) aufweist und daß zwischen der Schürze (5) und dem überlappten Bereich des Unterteils (1) ein bis unterhalb der Trennfuge (3) von der Vergußmasse ausgeftillter Spalt (6) liegt. Patent applications Ci. Semiconductor component with one of a gene Lower part and a hood-shaped upper part existing housing, the interior of which At least up to the joint between the upper part and the lower part with a potting compound it is potted that the upper part (4) has an apron (5) overlapping the parting line (3) inside the housing and that between the skirt (5) and the overlapped area of the lower part (1) a gap (6) filled with the casting compound to below the parting line (3) lies. 2. Halbleiterbauelement nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß das Unterteil (1) im überlappten Bereich eine geringere Wandstärke als außerhalb des überlappten Bereichs hat und daß die Wandstärke des Oberteils (4) im wesentlichen überall gleich ist. 2. Semiconductor component according to claim 1, d a d u r c h g e k e n It should be noted that the lower part (1) has a smaller size in the overlapped area Wall thickness than outside of the overlapped area and that the wall thickness of the Upper part (4) is essentially the same everywhere. 3. Verfahren zum Vergießen eines Halbleiterbauelements nach Anspruch 1, d a d u r c h g e k e n n -z e i c h n e t , daß zuerst so viel Vergußmasse in das Gehäuse eingegossen wird, daß der Zwischenraum zwischen Schürze (5) und Unterteil (j) bis unterhalb der Trennfuge (3) gefüllt ist, daß dann die Vergußmasse ausgehärtet wird und daß dann weiter bis über die Trennfuge (3) Vergußmasse eingegossen wird. 3. A method for encapsulating a semiconductor component according to claim 1, d a d u r c h e k e n n -z e i c h n e t that so much potting compound in the housing is poured in that the space between the skirt (5) and the lower part (j) is filled to below the parting line (3) that the casting compound then cures and that further potting compound is poured over the parting line (3).
DE19792944614 1979-11-05 1979-11-05 Method for encapsulating a semiconductor component Expired DE2944614C2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19792944614 DE2944614C2 (en) 1979-11-05 1979-11-05 Method for encapsulating a semiconductor component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19792944614 DE2944614C2 (en) 1979-11-05 1979-11-05 Method for encapsulating a semiconductor component

Publications (2)

Publication Number Publication Date
DE2944614A1 true DE2944614A1 (en) 1981-05-14
DE2944614C2 DE2944614C2 (en) 1986-10-30

Family

ID=6085172

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792944614 Expired DE2944614C2 (en) 1979-11-05 1979-11-05 Method for encapsulating a semiconductor component

Country Status (1)

Country Link
DE (1) DE2944614C2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3521572A1 (en) * 1985-06-15 1986-12-18 Brown, Boveri & Cie Ag, 6800 Mannheim PERFORMANCE SEMICONDUCTOR MODULE WITH CERAMIC SUBSTRATE
DE3604882A1 (en) * 1986-02-15 1987-08-20 Bbc Brown Boveri & Cie PERFORMANCE SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE MODULE
CN1314107C (en) * 2002-02-10 2007-05-02 汪秉龙 Surface adhesive type prefocus cup structure for placing optical crystal chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2819287A1 (en) * 1977-05-05 1978-11-09 Fierkens Richardus METHOD FOR ENCAPSULATING MICROELECTRONIC ELEMENTS

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2819287A1 (en) * 1977-05-05 1978-11-09 Fierkens Richardus METHOD FOR ENCAPSULATING MICROELECTRONIC ELEMENTS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3521572A1 (en) * 1985-06-15 1986-12-18 Brown, Boveri & Cie Ag, 6800 Mannheim PERFORMANCE SEMICONDUCTOR MODULE WITH CERAMIC SUBSTRATE
DE3604882A1 (en) * 1986-02-15 1987-08-20 Bbc Brown Boveri & Cie PERFORMANCE SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE MODULE
CN1314107C (en) * 2002-02-10 2007-05-02 汪秉龙 Surface adhesive type prefocus cup structure for placing optical crystal chip

Also Published As

Publication number Publication date
DE2944614C2 (en) 1986-10-30

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Legal Events

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8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee