DE2835005A1 - Control circuitry for automatic focussing in still or cine cameras - has comparator for counters dealing with pulses representing actual and rated values - Google Patents

Abstract

The control circuitry is for continuous regulation of automatic focussing or lens system in still or cine cameras. It comprises actual and rated value generators and a comparator whose output is used as the control signal. The control is digited and is based on a pulse generator. Counters are provided to a deal with the pulses corresponding to the actual and rated values during a measuring phase. A rest time for the counters can be preselected. A comparator compares the counter results and a circuit evaluates them.

Description

Control device for controlling autofocus systems

or lens systems The invention relates to a control device for the continuous control of autofocus systems or

Lens systems in photographic and cinematographic equipment, with an actual value transmitter, a setpoint transmitter and a comparison device, their output variable is used for control.

Devices or circuit arrangements for automatic focusing and lens control in photographic and cinematographic devices are known.

Based on the known devices, the invention is the The object is based on a digital control device of the type described above create, with which a continuous motor run of the lens motor with direction-dependent Adjustment speed is possible.

According to the invention, this object is achieved in that the control is constructed as a digital control with a clock that a counter for each Counting of pulses according to the setpoint and the actual value during a measuring phase it is provided that a dead time range for the counter can be preselected, and that a Comparator for comparing the counting results and a circuit for evaluating the counting results are provided.

The comparator is advantageously connected to two shift registers, at their outputs control commands for different control directions and adjustment speeds can be tapped.

In addition, further counters can be provided, which depend on the actual value and setpoint pulses are applied and each via a further shift register and a further comparator are connected to the first shift register.

With the invention, practically any number can be digitally released preselectable thresholds for any number of adjustment speeds in both control directions preselect. A continuous running of the lens motor is ensured and the resolution can also be selected.

It is particularly advantageous that for the control device according to the Invention no external components are required.

The digitally preselectable dead time range is also essential for the invention, since it is precisely this dead time range that is essential for regulating the speed of the lens motor and whose accuracy is.

An embodiment of the invention is shown in the drawings and is described in more detail below. The drawings show: FIG. 1 a block diagram a digital continuous control device according to the invention, Fig. 2- 4 pulse diagrams for the three possible cases of states in the measuring phase, and 5 is a detailed illustration of the timing diagram of FIG. 2 in general illustrated switching position of components of the control device according to the invention according to FIG. 1.

As shown in FIG. 1, a selectable clock frequency is obtained from reaching a setpoint (setpoint switch on low potential IIoIr or low) via a NOR gate 1 to a setpoint counter 2. From this point in time, the Clock frequency counted in the setpoint counter 2. On the input side with the clock frequency and the actual value connected NAND gate 3 is on the output side with an actual value counter 4 connected in which the clock frequency from reaching the actual value is counted in via the NAND gate 3, the actual value switch high potential "1" or high. Since with autofocus systems from the setpoint switch the last Zero is required as the setpoint, there is still a link with the reset input R of counter 2 is required, which resets counter 2 for each setpoint = 1 and thus a measuring phase P1 only counts from the last zero level. This is done via an OR gate connected to the reset input R of the counter 5.

The counters 2 and 4 are on the inputs B and A of a comparator 11 switched.

Crucial for regulating the speed of the not shown The lens motor is the chronological order of the signals in the measurement phase P1. The regulation is ended when the actual value falls within the preselected dead time range T. the The dead time range Tt is specified by ignoring the lower value Bits of counters 2 and 4. The more low-order bits are not taken into account, the greater the dead time range Tt.

The actual value and the clock frequency are also sent to an AND gate 6 given, which is connected to a counter 7, the reset input R via Inverters 8 and 9 are connected to the measuring phase line. The counter 7 is about a Shift register 10 connected to a comparator, the clock input CL of the Shift register 10 is connected to the output of a NOR gate 14, the inputs of which with the setpoint or the measuring phase are applied.

The measuring phase is via an inverter 16 to one input of a AND gate 17, while the other input of AND gate 17 is the actual value is given. The output of the AND gate 17 is one with the clock input CL a comparator 13 connected shift register 15 connected, in addition is connected to a counter 18 whose clock input is connected to the output of the NOR gate 1 is connected, while at the reset input R of the counter 18 the setpoint is given via inverters 19 and 20. The comparators 12 and 13 each have an output A) B, the output of the comparator 12 to one input an AND gate 21 and the output of the comparator 13 to one input of a AND gate 22 is placed. The other input of AND gate 21 is with the output A> B of the comparator 11 connected, whose other output B) A to the other Input of the AND gate 22 is switched. The output of the AND gate 21 or 22 is connected to a shift register 23 or 24, with a further input of the shift register 23 with the output A-B of the comparator 11 and another input of the shift register 24 is connected to the output B> A of the comparator 11. The outputs of the comparator 11 are further via an AND gate 25 or 26 to a further input of the shift register 23 and 24, respectively, with the second input. this AND gate 25 and 26 with comparators 27 and 28 is connected.

The measuring phase is applied to the clock input CL of the shift register 23 or 24 placed, while the outputs of the shift registers 23 and 24 for the functions v11 ... vn or v1 ... vn according to different speed levels on the left and are provided on the right.

The three possible cases of the states in the measurement phase are as follows explained in more detail with reference to FIGS.

State 1 (Fig. 2): The actual value switch closes first, the setpoint lies outside the dead time Tt. For this state, the measurement phase P1 is shown in FIG and P2 as well as the pulse diagrams of the actual value, the dead time and the setpoint are shown.

After the actual value switch has closed, the clock pulses counted in counters 4 and 7. When the setpoint is reached, the count becomes of the counter 7 is transferred to the shift register 10, which is responsible for the control deviation important is. From this point in time, the setpoint counter 2 begins, the same clock frequency to count. At the end of the measurement phase P1, the counter readings of counters 2 and 4 are combined compared and the comparator 11 supplies a "1" at the output A> B to the AND gate 21 or 22, where further processing takes place.

The counter 4 (A) thus has a larger count than the counter 2 B). The direction of the regulation is thus decided. A deviation the setpoint is explained in more detail below: The shift register 10 takes over with each "O" of the setpoint switch, the difference between the actual value and the setpoint value (counter reading of the counter 7) and thus with the last 0 "O" the absolute difference between the actual and setpoint. This value already appears at the output of the shift register 10 the last "O" of the setpoint switch and is preselected in the comparator 12 or 27 with Values are compared, with any number of comparators being possible. The selected one Corresponding speeds are assigned to values (v1, v2 ... vn).

The outputs A> B of the comparators 12 and 13 are on the shift register 23 or 24 switched, which takes over the information at the end of the measuring phase P1 and maintains until the end of the measuring phase Pl. In addition, it is guaranteed that the Control deviation only then via the AND gate 21 or 22 to the shift register 23 or 24 arrives if the control really takes place in the appropriate direction target.

State 2 (Fig. 3): The setpoint switch closes first, the actual value lies outside the dead time Tt. For this state, the measurement phase P1 is shown in FIG and the measuring phase P2 and the pulse diagrams of the actual value, the dead time and the Setpoint shown.

After the setpoint switch has closed (= 0), the clock pulses counted into counter 2 via NOR gate 1 and at the same time given into the counter 18, which is important for the control deviation. At the later Closing the actual value switch is the count of the counter 18 in the shift register 18 taken over and appears at the inputs of the comparator 13 and 28, with also again several comparators are possible. The comparator 13 decides with which Speed is readjusted. After the actual value switch is closed, the counter 4 begins to count and at the end of the measuring phase P1 is the count smaller than in counter 2, so that a "1" appears at the output At B of the comparator 11. The direction of control is thus also determined. The control speed can obtained from the comparator 13, or from several comparators at several control speeds. As already described above, the output of the comparator 13 is via the AND gate 22 connected to one input of the shift register 24, at the end of the measurement phase P1 the information is passed on to the outputs. The information remains stored there until the end of the next measurement phase P1.

State 3 (Fig. 4): The actual value switch closes within the dead time For its state, FIG. 4 shows the measurement phases P1 and P2 and the pulse diagrams the actual value of the dead time and the setpoint.

The low-order Uits of the counter specified by the dead time Tt 2 and 4 are not connected to the comparator 11. Both counters 2 and 4 show the same meter reading. At the outputs AA B and AR B of the comparator 11 a 0 appears; the AND gates 21 and 22 are blocked.

The actuating devices or the lens motor are therefore not activated.

5 shows a detailed representation of the timing diagram according to FIG Fig. 2, i. H. for state 1. This contains the pulse diagrams for the clock generator, the actual value switch, the setpoint switch, the phase switch, the counter 7, the Comparator 12 and the output of the shift register 23 are shown.

Claims (3)

Claims S control device for the continuous control of Autofocus systems or lens systems in photographic or cinematographic Devices, with an actual value transmitter, a setpoint transmitter and a comparison device, whose output value is used for the control, characterized in that the control is constructed as a digital control with a clock that each one Counters (2, 4) for counting pulses according to the setpoint and the actual value during a measurement phase (P1) are provided that a dead time range (Tt) for the Counter (2, 4) can be preselected, and that a comparator (11) for comparing the counting results and a circuit for evaluating the counting results are provided. 2. Control device according to claim 1, characterized in that the comparator (11) is connected to two shift registers (23, 24) at their outputs Control commands for different control directions and speeds can be tapped. 3. Control device according to claim 2, characterized in that further counters (7, 18) are provided, which from the actual value and setpoint pulses are applied and each via a further shift register (10, 15) and one further comparator (12, 13) connected to the first shift register (23, 24) are.