DE2734726A1 - METHOD OF MANUFACTURING SILICON PHOTODIODES - Google Patents

Description

description

The invention relates to photodiodes, in particular to a method for producing η -p-ftt-p -silicon avalanche photodiodes or η -JT-p -silicon photodiodes of the pin type.

The advent of the laser and the prospect associated with it its use as a carrier source for optical communications has been of great interest in development Stimulates photodetectors that are highly sensitive to weak signals and to light intensity modulations show a quick response. An optical receiver, usually a photodetector and a Contains amplifier at its output should, according to H. Melchior, "Journal of Luminescence", Volume 7, pages 390-414 (1973) meet general operating criteria, namely:

1. Great response behavior (quantum efficiency) in the Wavelength of the incident optical signal;

2. Sufficient electrical bandwidth (i.e. speed of response) to match the information bandwidth, and

3. Minimal excess noise caused by the detection and reinforcement process is introduced.

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A common type of photodetector is a photodiode, the essential element is a depletion semiconductor zone with high electric field strength (high field zone) which is used to separate the electron / hole pairs which are photonically excited by band-to-band excitation serves. High speed photodiodes are usually associated with a very low impedance to enable the photonically excited charge carriers to induce a photocurrent in the load circuit, as they move through the high field zone. Photodiodes that are used to detect visible light and of radiation in the near infrared are usually used with comparatively high reverse voltages operated to reduce the carrier drift time and lower the diode capacitance without excessive introduce high dark currents (see Melchior, supra, page 397). For example, one penetrates in the reverse direction operated and exposed to radiation on the p-side p-i-n photodiode not on the surface reflected radiation to a certain depth into the photodiode material before it is absorbed and photocarriers are generated. Electrons and holes that are within the high field zone of the transition (i-layer) are generated, and the minority charge carriers from the p- and η-layers in front Recombination to diffuse transition will be in the

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Collected high field zone and contribute to the photocurrent.

The actual quantum efficiency and the speed of response of photodiodes depend heavily on the operating wavelength and on the structure and material of the Diode off. For example, silicon photodiodes are preferably used in the near ultraviolet and infrared used up to about 1um wavelength. Silicon photodiodes But because of the strongly changing light penetration depth for each wavelength of interest be optimally adapted (see Melchior, supra, page 400). The response speed will be at the larger wavelengths reduced as the width of the high field zone increases.

Dark currents in photodiodes limit the sensitivity to weak light signals and can either im Arise inside or on the surface. Surface leakage currents, which are a problem especially in the case of silicon photodiodes of high specific resistance, can be caused by special surface treatments and various guard ring arrangements can be reduced. On the other hand are out Internal leakage currents in silicon photodiodes are mainly the result of charge carrier generation within the space charge layer. For carefully

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worked silicon diodes are dark currents right down

-6 -8 3

10 to 10 A per mm of depletion volume has been achieved (see Melchior, supra, page 405).

A particularly useful type of photodiode is the Avanalcheghotodiode (APD), which provides optical detection Signals combined with internal photocurrent amplification. An internal current amplification takes place in an APD, if the charge carriers have enough energy by moving in a high field zone a strong reverse direction biased transition to create new electron / hole pairs by way of an impact ionization mechanism to release. The current gain of an APD varies because of the statistical nature of the carrier multiplication process. Even for spatially uniform avalanche zones, the statistical gain fluctuations give rise to excess noise over the multiplied "shot" noise and is common marked on the basis of an excess noise factor, which is given by

M>

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Here, <i "> means the mean square of the noise current at the exit of the APD divided by the middle one

Noise square <i. > the primary photocurrent times the square of the average gain M. For a silicon APD, the ionization rate Λ for electrons is much greater than the ionization rate ß for holes (ie ß / <*. is between 0.02 and 0.2); consequently, F (M) increases much more rapidly for hole injection than for electron injection (see Melchior, supra, p. 409). This consideration suggests that a η -p-lf-p silicon APD can be backlit (ie, the incident light on the p-layer remote from the junction is such that electrons are injected into the multiplication zone) rather than frontlit (ie that the incidence of light on the η -layer in the vicinity of the transition occurs in such a way that holes are also injected into the multiplication zone). The application of this principle in the design of a η -ρ-Jt-ρ -Silicon-APD is in the work "An Optimized Avalanche Photodiode" by HW Ruegg in "IEEE Transactions on Electron Devices", Volume ED-14, No. 5, pages 239-251 (1976). In this type of APD, which is particularly useful for high-speed detection at GaAs laser wavelengths, there is a multiplication of charge carriers

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the narrow n ⁺ -p zone is limited, and the wider JV zone acts mainly as a collector for photonically excited electrons generated by light incident on the ρ -layer. Ruegg states (supra on page 247, column 1) that "the optimized component requires that the illuminated surface (the ρ layer) must be opposite to the pn junction in order to ensure pure electron injection into the multiplication zone". Consequently, he demands that "in this case the total thickness of the component must be of the order of magnitude of the penetration depth of the light to be detected" (20 to 30 µm for GaAs laser wavelengths). He then goes on to say that "because wafers of this thickness cannot be handled, the only obvious solution was to etch local depressions (at the locations of the devices) in a much thicker silicon wafer". Unfortunately, the need to etch uniformly thick cavities or, equivalently, to reduce the substrate in thickness by lapping, significantly increases the cost of manufacturing this type of APD. An increase in cost also results from the fact that the flakes, which have been weakened in thickness, are difficult to handle, break easily, are prone to warping and make mask alignment as difficult as their eventual incorporation into the encapsulation.

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An alternative is therefore to produce the component on a thick ρ zone and to work with front-side lighting through the η layer so that the plate does not have to be weakened in terms of its thickness. As mentioned, however, a mixed hole and electron injection occurs here with an accompanying increase in noise. In known front-illuminated η-p-JT-p -silicon APDs (see US Pat. No. 3,886,579), the components were not yet optimized with regard to reducing excess noise, nor were they optimized with regard to low leakage currents and long-term stability. It is therefore questionable whether such devices are at all useful in an optical transmission system in which the receiver sensitivity is typically -55 dBm (e.g. at a wavelength of 0.825 µm and a data flow of 44.7 megabits / sec.) . Of course, one would then wish to reduce the noise performance and dark currents in a reliable APD without the need for an overly complex procedure, so that the generally lower cost and handling advantages of a front-lit APD can be exploited.

The object of the invention is therefore to produce silicon photodiodes such as η -ρ-ί * -ρ -APD's and η -ίϊ-ρ diodes of the p-i-n type, which can be illuminated from the front without

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in the case of excessive noise, especially excess noise at APD's is to be accepted, and at the same time precaution In particular, it is taken that at comparatively low manufacturing costs, the diode during the fabrication is easy to handle, high quantum efficiency, short response time, low dark currents and has good reliability and - in the case of a p-i-n photodiode - has low capacitance and at can be operated at low voltages.

The inventive solution to this problem is in the Claims specified.

In other words, a silicon photodiode which can be illuminated from the front is preferably produced according to this by: 1. Growing a tt epitaxial silicon layer high resistivity on a p-type silicon substrate with high conductivity and low dislocation density, 2. Creation of an n-protection ring in the Jt layer by phosphorus diffusion, 3. Creation of the protection ring surrounding p-channel stop zone in the it-layer Boron diffusion, 4. Introducing phosphorus into the back the substrate for gettering structural defects and / or impurities, 5. increasing and decreasing the furnace temperature in a ramp-shaped course (temperature ramping) during steps 2, 3 and 4 to reduce crystal structure

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fail, 6. Creation of an η -layer in the Jt-layer, 7. Creation of an anti-reflection / passivation coating on at least the η -layer and the zone between the guard ring and the channel stop zone and 8. generating electrical Contacts to the substrate, to the guard ring and to the channel stop zone such that the guard ring contact the Surface part of the metallurgical JV-n junction and the channel stop zone contact overlap the surface part of the metallurgical Jl-p junction.

One embodiment of the method according to the invention relates to the production of a front-illuminated n ⁺ -p-Jt-p ⁺ silicon APD with high quantum efficiency (better than 90% for GaAs-AlGaAs laser wavelengths of, for example, 0.80 up to 0.90 µm), short response times (e.g. one nanosecond), high gain (e.g. M = 100), low excess noise factor (e.g. F (M) = 4 to 6 at M = 100) , low dark current (10 ~ A) and good reliability. According to this embodiment, the method proceeds according to the following steps: 1. Growing an approximately 30 to 60 (in the thick epitaxial K-silicon layer high resistance (> 300 ohm.cm) on a ρ silicon substrate higher

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Conductivity (the use of epitaxial growth methods makes the present method special suitable for batch processing of large diameter plates (e.g. 76 rom diameter or about that) );

2. Creation of an n-protection ring in the η-layer by prior precipitation and diffusion of Phosphorus;

3. Creation of a p-channel stop zone surrounding the guard ring by prior precipitation and diffusion of boron;

4. Implant 30 to 150 keV boron ions into the J * layer

12 -2 at a dose of about 4 to 6 χ 10 cm;

To produce 5-driving of the implanted boron ions by 2 to hours heating at about 1150 to 1200 ⁰ C in a suitable atmosphere to a about 2 to 12 m thick p-layer;

6. masking the p-layer and introducing phosphorus into the back (p-substrate) by a POCl. source or the like. By 30 to 60 minutes long heating to 1100 ⁰ C to structural defects and / or impurities at about 1000 gettern;

7. Increase and decrease the furnace temperature in ramp

shape during steps 2 to 6 to eliminate crystal defects to reduce;

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8. Create a 0.1 to 1.0 micrometer thick n ⁺ thin layer in the p-layer;

9. Production of an anti-reflective and passivation coating from a thin SiO ₂ layer on the η layer and a quarter-wavelength thick Si ₃ N ₄ layer on the SiO ₂ layer;

10. After the SiO ^ layer has been produced, but before the SijN. Layer has been produced, heat treatment for 10 to 30 minutes at about 850 to 950 ° C. in an atmosphere containing 1 to 5% HCl in order to remove mobile ionic impurities in the SiO ₂ gettering or catching;

11. Creation of a p ⁺⁺ contact layer of high conductivity on the back of the ρ substrate; and

12. Create electrical contacts to the substrate, to the guard ring and to the channel stop zone in such a way that the guard ring contact the surface part of the metallurgical jr-n junction and the channel stop zone contact the surface part of the metallurgical ff-p transition overlap.

In addition, it is a feature of the present APD manufacturing method that the n ⁺ layer is made extremely thin in order to reduce the hole injection and thus excess noise caused by radiation incident on this layer. Although this layer

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is extremely thin, an edge breakthrough will occur even with Blocking voltages of 250 to 400 V are avoided by the specially used guard ring arrangement.

Another feature of the present APD manufacturing process is that the ion implantation step 4, the driving step 5 and the subsequent heating steps are mutually adapted to each other that the electric field profile in the multiplication zone (the p-layer) is substantially triangular. This Profile provides a balance between the opposing effects of field-dependent ionization rates and mixed injection of photocarriers into the high field zone to the extent that the low noise performance a pure electron injection in a wide diffusion depth range is approximated.

Another feature of the present process for making both n ⁺ -p-JV-p ⁺ APDs and n ⁺ -Jt-p ⁺ photodiodes is that the dark currents are two to three orders of magnitude lower than before, primarily because of the HCl gettering after process step 10 and because of the P gettering after step 6 in combination with the channel stop zone generated in step 3.

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The invention is explained in detail with reference to the drawing; show it:

Fig. 1 is an oblique view in section of a

n ⁺ -p-it-p ⁺ silicon APD, which is produced according to an embodiment of the method according to the invention,

2 shows a diagram to illustrate the electric field profile and the multiplication factor profile, how this is calculated for a theoretical APD of the type shown in FIG. 1, and

3 is a sectional view of a η -Λ-ρ silicon photodiode, corresponding to a further embodiment of the method according to the invention is made.

η -p-Jf-p -APD

The structure of the silicon APD shown in FIG. 1, which is produced according to an embodiment of the present method, will first be described, then the mode of operation and production.
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The APD shown has a ρ silicon substrate 10 on which a yt silicon layer 12 of high specific resistance is grown epitaxially. A p-layer 14, in which a thin n ⁺ -layer 16 is produced, is introduced on the upper side of the Λ-layer 12. This part of the array defines an elementary n ⁺ -p-JT-p -APD in which the p-layer is the multiplier region. In the case of the actual component, however, its structure still has to be adapted to the requirements of the system for which the APD is intended. In detail, an n-protection ring 18 is produced in the f> -layer 12, surrounding the p-layer and the n ⁺ -layer 16. The η -layer 16 extends laterally over the p-layer 14 in order to overlap the protective ring 18, which prevents the η-p-junction from breaking through the edge under normal operating conditions. The η layer also serves as a contact layer for an annular metal contact 20 (field plate) ζ. Β. made of PtSi-Ti-Pt-Au or Al. The positive pole of a bias voltage source (not shown) is connected to this.

In addition, there is a p-channel stop zone 22 in the rt layer generated. The channel stop zone surrounds the protective ring 18 at a distance and serves to prevent inversion layers the surface of the / t layer 12 of high resistivity. An annular metal contact or field plate (ζ. B. PtSi-Ti-Pt-Au or Al) is to the p-channel stop zone 22

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and thus produced to form the p ⁺ substrate 10. A contact / 3A / 2 to the substrate 10 is also made via a metal layer 26 (e.g. Ti-Au) on the underside of the substrate. Another metal layer 30 (e.g. gold) is produced on a ceramic assembly block 32. A conductive epoxy layer 28 or the like (e.g. a solder preform) is used to secure the APD to the block 32. The negative connection of the bias voltage source is to the metal layer 30 and, if desired and as shown, to the channel stop field plate 24 tied together.

To reduce ion accumulation on or on the surface of a dielectric layer 35 above surface portions 34 of the metallurgical p-jt junction, the channel stop field plate 24 overlaps the junction portion 34 and thereby reduces both noise and leakage current and improves operational reliability. For the same reason, the protective ring field plate 20 overlaps the surface part 36 of the metallurgical η-rc transition.

In order to reduce the reflection of the radiation 38 to be detected, the η layer 16 is covered with an antireflection coating made up of a thin SiO ₂ layer 40 and a Si ₃ N ₄ layer 42 that is a quarter wavelength thick. These layers also serve to passivate the surface. Note that a SiO ₀ - and a Si, N - layer,

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The latter is referred to as layer 35 and is also provided between the protective ring and the channel stop zone, but here the SiO ₂ layer is thicker because some SiO _{2 was} left behind from the previous process steps still to be described.

For operation, a sufficiently high reverse voltage (typically a few hundred volts) is applied to contacts 20 and 30 in order to completely depletion of JT-layer 12 and p-layer 14 with regard to free charge carriers (with the depletion laterally up to approximately the lines 13 and extends vertically down to the substrate 10), and the active area of the component, a circular zone 44 in the center of the protective ring, is exposed to the radiation 38 to be detected. The radiation generates photonically excited charge carriers mainly in the IT layer. These charge carriers are multiplied in the p-layer 14, which acts as a high field zone. Electrons are collected in the n ⁺ layer 16 and holes in the ρ substrate 10. The resulting photocurrent flows into a load (not shown) connected to contacts 20 and 30. Since the device is illuminated from the front, mixed charge carrier injection occurs. That is to say, the radiation incident on the η -layer 16 generates holes which are injected into the p-layer and multiplied there; and the same radiation that goes to the p-layer and 3t-layer

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penetrates, generates electrons that are injected into the multiplication zone. In order to obtain the low noise behavior of a pure electron injection (ie an APD illuminated from the back), the η layer is made very thin and the electric field profile (E) is shaped as shown in FIG. I. E. the field is almost zero in the η -layer, rises very steeply in the vicinity of the n ⁺ -p-junction and has an essentially triangular shape in the p-layer. The triangle profile produces an extremely low noise multiplication (M) for electrons _{entering near the p-JF interface (x 2} ) and also relatively low noise (compared to a rectangular field profile) for mixed hole and electron injection in the p-layer generated by the front lighting.

It should be noted that the thinness of the η -layer also reduces the optical absorption in this layer serves and thereby supports a high quantum efficiency. Otherwise, a significant number of the in The minority charge carriers generated in the η-layer recombine before they reach the high field zone of the p-layer.

Although the diagram of Fig. 2 shows only theoretical calculations, those were for the present invention named inventor will be able to identify the essential characteristics

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of this diagram in a η -p-jr-p -silicon APD to be implemented in accordance with an exemplary embodiment of the present method as follows.

1. On a p-silicon substrate 10 of low dislocation density, which was ^{doped with boron to about 5 10 17} - 1.2 χ 10 ¹⁸ cm " ³ , a 30 to 60 μm thick silicon layer 12 of high resistivity (> 300 The epitaxial layer is preferably thicker than 35 μm in order to collect at least 95% of the charge carriers photonically excited by radiation at a wavelength of about 0.825 μm. The epitaxial layers were made in a reactor using dichlorosilane (SiH ₃ Cl ₂₎ grown as the Siliciumguelle. the growth rate was, for example, 3.5 microns per minute at a deposition temperature of about 1100 to 1200 ⁰ C. diborane was used as a dopant source, and prior to growth of a one micron thick HCl Xtzung was situ in carried out at 1160 ⁰ C., since these high resistance layers are grown on heavily doped substrates, the auto doping from the substrate must be carefully k be controlled.

2. Then was on the eptiactic layer by oxidation of the silicon in a moist O ₂ environment, for example

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wisely for two hours at 1050 ⁰ C a SiC ^ layer is produced. Using conventional photolithographic methods, an opening was made in the oxide in order to enable the protective ring 18 to be formed.

3. Then, there was a phosphorus diffusion in the opening by 15 to 30 minutes long preliminarily depositing a phosphorus glass layer of POCl - source at 900 to 950 ⁰ C. The phosphor glass layer was removed and the phosphorus was diffused into the underlying parts of the epitaxial layer 12 by heating to 1100 to 1200 ^° C. for 30 to 60 minutes (not critical) in an atmosphere of N ₂ + 0.1% O _2. To reduce the crystal defects generated in the layers of the semiconductor devices were placed in an oven which was idling at approximately 900 ⁰ C. Then the temperature is gradually (z. B. 4 to 8 ° C / minute) to 1100 was increased to 1200 ⁰ C. For the same reason, the temperature was regulated ^{down to 900 °} C. after the diffusion had taken place over the prescribed time. This diffusion step provided the n-guard ring 18.

4. The oxidation and masking step 2 was then repeated in order to produce an opening for the channel stop zone.

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, 5. Boron diffusion into the opening then took place by previously depositing a boron glass layer from a BN source at 950 to 975 ° C. for 1 to 2 hours. The boron glass layer was removed and the boron then diffused into the underlying parts of the epitaxial layer by heating to 1100 to 1200 ^° C. for 30 to 60 minutes (not critical) in an atmosphere of essentially 100%. For the same reasons as in step 3, the furnace temperature between 900 ⁰ C and the boron recovery was increased in a ramp-ture curve and lowered. This diffusion step provided the p-channel stop zone 22.

6. The oxidation and masking step (2) was repeated again in order to create an opening close to the Protective ring 18 and this is located partially overlapping. Then boron ions were in the surface of the epitaxial Layer 12 with an energy of 30 to 150 keV

12-2 and a dose of 4-6 χ 10 cm. the Control the dose to within ^ 5% for a given Component design was particularly important. For example, if you set the dose too high, the whole would be Heating cycle (i.e. time and temperature of all subsequent Steps in which heating takes place) for longer times and / or higher temperatures, if possible, to be modified. If conversely the initial dose is 13/14

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were chosen to be too small, the device would have a very small gain and a high breakdown voltage.

7. After the implantation, the boron ions were driven into the epitaxial layer by two to eight hours heating at about 1150 to 1250 ⁰ C in an atmosphere of 0.1 to 1.0% O ₂ and nitrogen or argon. For example, this step provided an approximately 6 µm thick p-layer 14 (the multiplication zone) for four hours of heating at 1200 ° C. For the specified process conditions, however, the thickness range for this layer is from 2 to 12 μm, with a preferred thickness range of 5 to 7 μm for an APD with a multiplication factor M = 100 at 300 V. As in process steps 3 and 5, the Oven temperature ramps up and down between 900 ^° C. and the drive-in temperature.

8. The whole platelet was then ^{oxidized again at about 1050 °} C. for one hour. The oxide was then removed from the back of substrate 10 only.

9. A phosphor glass layer was then produced on the back of the substrate 10 using a POCl _{3 source.} Other sources of phosphorus, e.g. B. PBr ₃ , are for

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2734 ^ 26

just as suitable for this purpose as for the earlier previous phosphorus precipitations. The phosphorus was diffused into the rear side by heating for 30 to 60 minutes at about 1000 to 1100 ^° C. in an atmosphere of essentially N, + 0.1%. The elongation and / or misalignment dislocations caused by the phosphorus atoms were effective in gettingtering of contaminants (particularly fast diffusing metallic contaminants) and other defect formation sites. This step played a significant role in reducing the dark currents in the present APD ¹ s. As with the method steps 3 and 5, the Of en temper a door -between was increased 900 ⁰ C and the diffusion temperature in the course ramped and degraded.

10. Next, the phosphor glass layer on the back was removed and the plaque was. Oxidized again at about 900 ^{° C. for 10 minutes.} Using conventional photolithographic methods, the oxide was masked and an opening for the η layer 16 was produced.

11. The η layer 16 was formed ₍₃ -QUeIIe ie precipitation of a phosphorus glass layer from a POCl) by an antecedent phosphorus precipitation, followed by about 20 to 30 minute heating to about 920-930 ⁰ C in an atmosphere of essentially of N ₂ + 0.1% O ₂ . The glass layer was then removed.

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This step resulted in an approximately 0.3 μm thick η layer. Subsequent heating steps increased the thickness to about 0.4 µm - a preferred value - although a range of 0.1 to 1.0 µm is suitable. Alternatively, the η -layer can be generated by a previous arsenic deposition or by arsenic ion implantation, followed by drifting in. With this step, the previously implanted boron is compensated and thereby the depth of the pn ⁺ junction is determined. Time and temperature are critical because deeper diffusions reduce the overall charge in the p-layer and increase the breakdown voltage. In addition, this step, in conjunction with the implantation and drive-in steps 6 and 7, creates the desired triangular electric field profile.

12. At this intermediate stage of the process, the components were tested to determine their voltage characteristics and measure leakage currents. The diodes meeting the target values were subjected to the following processing. Those who did not reach the target data, but were overdoped in the critical p-layer, were in the Effort heated to bring them to the target data. Renewed testing and heating can be repeated, until the components reach the target data.

13. The components meeting the target data were coated with a thin (approximately 10 to 20 nm thick) SiO ₂ layer 40 in the generally known dry oxidation process.

14 was then subjected to the SiO ₂ layer of a 10 to 30 minute heat treatment at about 850 to 950 ⁰ C in an atmosphere of 1 to 5% HCl in N _2. This step is important to reduce the leakage current as it effectively gettered or trapped mobile ions such as Na ions in the oxide.

15. After gettering, a quarter wavelength thick Si ₃ N ₄ ~ layer 42 (about 100 nm for λ measured in the material) was deposited on the SiO. Layer 40 in the vapor reaction deposition method. The layers 40 and 42 served to passivate the component against external contamination and - in the active area enclosed by the protective ring 18 - as an anti-reflection coating.

16. Next, contact windows for the guard ring and channel stop field plates 20 were made in layers 40 and 42 introduced to 24.

17. The initially about 500 μm thick substrate was then etched or lapped on the back to remove about 75um of material and thus the phosphor layer that was covered by the

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earlier diffusion steps (ζ. B. the gettering step 9) was generated. To reduce the contact resistance were in the back boron ions with about 30 to 50 keV in one

1> -2
Implanted dose of (2-4) χ 10 ³ cm. The boron ions were activated by 30 to 60 minutes heating at about 750 to 800 ⁰ C in a nitrogen atmosphere.

18. Metal was deposited using a mask to form the guard ring and channel stop field plates 20 and 24, respectively, from a PtSi-Ti-Pt-Au metallization. In order to avoid ion accumulation on the surface portions 34 and 36 of the iV-p and JP-n junctions, these field plates were formed so that they overlap these metallurgical junctions. Since the oxide-nitride layers over these zones are thin and since high reverse voltages are applied, impulse noise due to surface croplasmas and / or leakage current would result without this overlap.

19. The component was then for about 16 to 24 hours at 300 to 320 ⁰ C in an atmosphere of N ₃ + 8 to 15%

H_ annealed to reduce the surface state density and annealing the gold in the contact areas to improve solderability.

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20. Finally, a Ti-Au alloy layer 26 was deposited on the substrate 10. Under use A conductive epoxy layer 28 attached the APD to the gold layer 30 of the ceramic mounting block 32.

Using the method described above, H ⁺ -P-Jf-P ⁺ -SiIiCiUm-APD ¹ S were produced with, for example, the following data: The ρ substrate 10 was 500 μm thick; the epitaxial tt layer 12 was 50 μm thick and had a specific resistance of more than 300 Ohm.cm; the ion-implanted p-layer 14 was about 6 μm thick and had an essentially triangular electrical field profile; and the η layer 16 was about 0.4 μm thick was about 100 μm, the inner and outer diameter of the protective ring 18 was 180 and 290 μm, while the corresponding values of the channel stop 22 were 350 and 460 μm, respectively.

The radiation of a GaAs-AlGaAs transition laser that emits in continuous wave operation at λ = 0.825 stimulates the radiation with double heterostructure was coupled to the active area of the APD via an optical fiber.

This APD was operated between full depletion of the p-layer and If-layer 12 at 100V and breakdown at 375V.

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In this voltage range, current gains of five to several hundred could be achieved. At a Boosting a hundred, the excess noise factor was only 4 to 6 above the shot noise limit. The total dark current was only about 10 A and the part that may be multiplied was about 10 ~ A. The quantum efficiency was above 95% and the response speed was about 1 ns. When built into an optical receiver the sensitivity was -55 dBm at λ = 825nm and at 44.7 megabits / sec. With regard to the operational reliability, it should be noted that the mean time until the failure of the

3 4

Component was determined to take about 10 to 10 hours, the measurements being based on mechanical and electrical preload aging tests at 200 ^° C.

The specific values for the more important parameters used to make this APD were as follows:

In step 3, the phosphorus was ^{diffused in at 1200 °} C. for one hour.

In step 5, boron was ^{diffused in at 1150 °} C. for one hour.

In step 6, boron ions were at an energy of 150 keV

12-2 and implanted at a dose of 5.5x10 cm ^ 5%.

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In step 7, the boron ions were driven in at 1200 ° C for four hours.

In step 9, the back phosphor glass layer was for one hour at 1100 ⁰ C ~ erhitzt.J In step 11, the phosphorus glass layer is heated on the p-layer for 30 minutes at 925 ° C.

In step 14, the SiOj layer was _{heated to 90 ° C. in N 2} + 5% HCl for 10 minutes.

η -jr-p photodiode

It has been found that the above APD manufacturing process, in addition to the ion implantation and drive-in steps, is also an effective way to produce η -ft-p silicon photodiodes with high quantum efficiency (better than 90% at wavelengths of a GaAs-AlGaAs laser), short response times (e.g. 1 ns at 10OV or 4ns at 5 V), low dark currents (e.g. 10 ~ A), low capacitance (e.g. 1.5 pf at 10V) and with good reliability (e.g. medium time until failure) ^ 10 hours). This type of detector is particularly useful in systems

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where amplification in the photodiode is not essential is, for example in optical LED systems for short distances and low data flow values.

In the photodiode shown in FIG. 3, the same reference numerals have been chosen for the sake of better comparability for components which correspond to those of the embodiment according to FIG. 1. The manufacturing process then comprises the following steps, for example: 1. epitaxially growing a p-type silicon layer with a thickness of about 30 to 60 μm with a high specific resistance (> 300 ohm.cm) on a p ⁺ -silicon substrate 10 of high conductivity; 2. Production of an n-protection ring 18 in the Tf layer 12 by prior precipitation and diffusion of phosphorus; 3. Creation of a p-channel stop zone 22 surrounding the protective ring 18 by previous precipitation and diffusion of boron; 4. introduction of phosphorus into the back of the ρ -Substrates 10 from a POCl - source or the like, by 30 to 60 minutes heating at about 1000 to 1100 ⁰ C, thereby to getter structural defects and / or impurities. 5. Increase and decrease the furnace temperature in a ramp-shaped manner during steps 2, 3 and 4 to reduce crystal defects; ^{6. Production of an n +} thin layer 16 approximately 100 to 1000 nm thick in the fr layer 12;

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7. Production of an anti-reflection and passivation coating 40-42 from an SiO thin layer on the η layer 16 and a quarter wavelength thick Si ₃ N ₄ layer on the layer; 8. After generating the ^ layer, but before the production of Si ₃ N-layer according to step 7, performing a 10 to 30 minute heat treatment at 850 to 950 ⁰ C in a 1 to 5% HCl-containing atmosphere to movable SiO gettering or trapping ionic impurities in the SiO _2; 9. Production of a ρ contact layer (not shown) on the rear side of the ρ substrate 10; and 10. Creating electrical contacts to the substrate 10, to the guard ring 18 and to the channel stop zone 22 such that the guard ring contact 20 overlaps the surface part of the metallurgical per-n transition, and the channel stop contact 24 overlaps the surface part of the metallurgical 7 * -p transition .

When carrying out each of the above process steps, the procedure is the same as for the corresponding step in the APD production, but with one exception. While the phosphor drive-in step for the production of the protective ring in the APD (step 3 of that production process) takes place for 30 to 60 minutes at 1100 to 1200 ⁰ C, the corresponding step (here step 2) for the pin photodiode takes place over a longer period of time (e.g. 120 minutes) preferably at a high end temperature

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that range (for example 1200 ⁰ C) carried out in order to generate the desired diffusion profile in the component. In particular, shorter heating times and lower temperatures can be used in the APD guard ring production because the APD production includes an additional heat treatment step, namely the ion implantation and driving-in step, which in turn causes a certain further diffusion of dopant atoms that were introduced earlier.

Finally, it should be noted that it depends on device behavior it is preferable to carry out all process steps that involve raising and lowering the furnace temperature in a ramp-shaped course, the phosphor gettering on the back, the HCl gettering, the channel stop and guard ring generation and contacting and the electrical field profiling (in the case of an APD) relate, however, to selected sub-combinations these steps still result in good, albeit suboptimal, components and operating properties to lead.

Numerous modifications are possible. For example, the method is also suitable for the production of silicon photodiodes for the detection of radiation at wavelengths in the range from 500 to 100 nm. At both borders this

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A certain impairment of the quantum efficiency and / or the excess noise factor can be present in the range. For example, it should be noted that in a clean oven which provides an essentially sodium-free environment, the HCl gettering step is not mandatory and can be omitted. Second, the sequence in which the channel stop zone and guard ring are generated can obviously also be interchanged. Thirdly, to the extent that the guard ring and field plate assemblies both serve to reduce the electric field at the surface of the epitaxial silicon layer, it is possible to build good components without guard rings. However, the provision of guard rings is preferable for two reasons: 1. Facilitating the metallization in both component types; ie because of the very thin formation of the η layer, the metal contact to the η -Jt transition could alloy or diffuse through and thereby worsen the operating behavior; and 2. avoidance of pressure on the APD reinforcement zone; that is, because of the pressure sensitivity of the gain / voltage characteristic of an APD, the arrangement of the metallization over the guard rings instead of on the n ⁺ layer means that processes such as bonding leads and placing test probes will not impair the APD characteristic.

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Claims (12)

BLUMBACH · WESER · BERGEN. KRAMER ZWIRNER · HIRSCH PATENT LAWYERS IN MUNICH AND WIESBADEN 2734726 Postal address Munich: Patenlconsult 8 Munich 60 Radedcestrafle 43 Telephone (089) 883603/883604 Telex 05-212313 Postal address Wiesbaden: Patentconsult 62 Wiesbaden Sonnenberger StraSe 43 Telephone (06121) 562943/561998 Telex 04-186237 Western Electric Company, Incorporated Hartman, 2 / 4-3 / 4-5 / 6-5 / 7 New York, N.Y. 10007, USA Process for manufacturing silicon photodiodes Claims V1 .) Method of manufacturing a silicon photodiode for front lighting,
characterized by the following process steps a) epitaxially growing a JT silicon layer high resistivity on a p-type silicon substrate of high conductivity and lower Dislocation density, b) Creation of an η-conductive protective ring in the ft-layer by phosphorus diffusion, c) creation of a p-channel stop zone in the jr-layer running around the guard ring by boron diffusion, g) increasing and decreasing the diffusion temperature in ramp-shaped course (temperature ramping) during Munich: Kremer ■ Dr. Weser · Hirsch - Wiesbaden: Blumbach · Or. Bergen · Zwirner 709886/0849 «r» μαι. inspect of steps b) and c) to reduce crystal defects, h) Creation of an η -layer in the jr ^ layer, i) Generating an anti-reflective coating on at least the η layer and a passivation coating on the Zone between the guard ring and the channel stop zone and j) producing electrical contacts to the substrate, to the guard ring and to the channel stop zone in such a way that the protective ring contact the surface part of the metallurgical f ^ n junction and the channel stop zone contact overlap the surface part of the metallurgical It-p junction. 2. The method according to claim, further characterized by the process step f) introducing phosphorus into the back of the substrate, in order to gettering of structural defects and / or impurities, and to carry out the temperature increase 9 and lowering step g) also during step f). 3. The method according to claim 1 or 2, characterized by performing the anti-reflective and Passivation layer generation after step i) as follows: 709886/0849 1. Creation of a thin SiC ^ layer, 2. Annealing of the SiO ^ layer at an elevated temperature in an atmosphere containing HCl and 3. Generation of a Si ₃ N ₄ layer about a quarter wavelength thick on the SiO ₂ layer. 4. The method according to any one of claims 1 to 3, characterized by inserting the following additional process steps into the process step sequence for the production of an η -p-it-p -silicon avalanche photodiode intended for front lighting: d) implanting boron ions into a surface part the JV layer within the guard ring, e) driving in the implanted boron ions by heating in order to obtain a p-layer, Carrying out step g), namely increasing and decreasing the diffusion temperature to reduce crystal structural defects, also during step e), and k) mutual adaptation of implantation step d), the driving-in step e) and the η -layer generation step h) in combination with the following Steps that include heating such that the resulting electric field profile in the p-layer is substantially triangular in shape and of the desired size. 709886/0849 5. The method according to any one of claims 1 to 4, characterized in that for the production of a diode suitable for the detection of radiation at a wavelength of approximately 800 to 900 nanometers in step a) the epitaxial layer at least 30 µm thick and with a specific resistance of at least 300 Ohm.cm is allowed to grow, in step e) the boron ions to obtain an approximately 2 up to 12 µm thick p-layer can be driven in and in step h) the η layer is generated in a thickness of about 0.1 to 1.0 μm. 6. The method according to claim 4 or 5, characterized in that in step d) the boron ions with 30-150 keV in one 12 -2 dose of approximately 4 to 6 χ 10 cm can be implanted the boron ions ₂ atmosphere composed to be driven in step e) by 2 to 8 hours heating at about 1150 to 1250 ⁰ C in a essentially of N ₂ + 0.1 to 1.0% O. 709886/0849 7. The method according to any one of claims 4 to 5, characterized by increasing and decreasing the Temperature ramped in step g) between the diffusion temperature and a lower, but increased temperature, Introducing phosphorus in step f) by depositing a phosphor glass layer and 30 to 60 Heating to about 1000 to 1100 ° C for minutes and 10 to 30 minutes long annealing of the SiOj layer in Step i) -2 at about 850 to 950 ° C in an atmosphere containing about 1 to 5% HCl. 8. The method according to any one of claims 2 to 7, characterized in that the phosphor glass layer is deposited in step f) from a POCl source . 9. The method according to any one of claims 4 to 8, characterized by Production of the protective ring in step b) by depositing a phosphor glass layer for 15 to 30 minutes at about 900 to 950 ° C, removing the glass layer, heating an oven to the lower raised Temperature of about 900 ° C, placing the component in the furnace in an atmosphere of substantially 709886/0849 of N ₂ + 0.1% O ₂ ι gradually increasing the temperature to about 1100 to 1200 ⁰ C, about 30 to 60 minutes long keeping constant the temperature for effecting the desired phosphorus diffusion, gradually decreasing the temperature back to about 900 ° C, removing the component out of the furnace; Creating the channel stop zone in step c) by depositing a boron glass layer for 1 to 2 hours at about 950 to 975 ° C, removing the glass layer, heating a furnace to the lower elevated temperature of about 900 ° C, placing the component in the furnace in a Atmosphere of essentially 100% O ₂ , gradually increasing the temperature to about 1100 to 1200 ° C, holding the temperature constant for about 30 to 60 minutes to achieve the desired boron diffusion, gradually reducing the temperature back to about 900 ° C, removal the component out of the furnace; Increase and decrease the furnace temperature in a ramp-shaped manner Course in step e) between about 900 ° C and the boron ion injection temperature as in the Procedure according to steps b) and / or c); and ramping up and down the temperature Course in step f) between about 900 ° C and the heating temperature for introducing phosphorus 703686/0849 as in the procedure after steps b) and / or c). 10. The method according to any one of claims 1 to 9, characterized in that the production of a electrical contact in step j) to the substrate happens as follows: 1. Remove enough material from the back of the substrate in order to remove the phosphorus-doped layer produced in previous steps, 2. Implanting boron ions into the backside an energy of about 30 to 50 keV with a 15 -2 dose of about 2 to 4 χ 10 cm, 3. Heating for 30 to 60 minutes at about 750 to 800 ° C in a nitrogen atmosphere. 11. The method according to any one of claims 1 to 10, characterized in that after step j) an additional tempering step is carried out at about 300 to 320 ° C for 16 to 24 hours in an atmosphere of essentially N- + 8-15% H ₂ . 12. Silicon photodiode for front lighting, characterized by their production in the process according to one or more of the preceding claims 700886/0849