DE2701875A1 - ANALOG-DIGITAL CONVERTER - Google Patents

Description

Applicant: ütuttyart, January 10, 1977

Hughea Aircraft Company P3310 S.

Centinela Avenue and

Teale Street

Culver City, Calif., V.üt.A.

Representative:

Kohler - Schwindling - Späth
Patent attorneys
Hohentwielstrasse 4-1
7000 Stuttgart 1

Analog-to-digital converter

The invention relates to an analog-digital converter. Such converters usually make use of an analog reference signal which is divided into a set of 2Γ reference voltage levels which are applied to appropriate comparators. The reference voltage levels are separated by a voltage Q, the quantization level.

709829/081 3

The comparators then compare the analogue input signal with the reference signal and generate a signal in the form of a logical 1 if the input signal overactivates the reference level; if the input signal is less than the reference level, the comparator supplies an output signal in form of a logiiichen O _u i-usgangij "Signalo the Vei" gle Icher weinleri a decoder zuf;; - leads, at its ik.us gang * 'ine digital number liej'ert "Daa letztstelligti LDS each \ <ν · ν. \ Auiifjanp.siii ^ nal formed number corresponds to the «ciuanLiaieiniti ^ Kijegel ^{ ι» iiei most analog-digital liiJiLie Lzern form the veri,; lier the üchlüaselelemente, which hiiut'ig <i ^a ; i! .irr .! -iici ·· - !! higher operating a ge achwind Lg I: egg to uihi / d (<m · a higher (.iexi-tuigkeit prevent _&

The comparisons ι · contain /, in order to make the comparison usually a bintabiley Uaue.ieinent _u D ~ .t; Conversion of an analog? .U a digital signal iut not complete until the iaiiigani ^ iingnal the biütahilen Baielementej bia zn a value r <igeneriert j.it that with which Hauuchwelle the following digital üchai tungfjanordnung compatible iat "This means daii the maximum speed of gating through the regiinera ^ ion ^ time b (-atimiiil; iat that the Auagangau signal of the Vurgleloch needs to reach a certain fraction of the tension band, which it nn-u The location of the model depends on the atochajitic properties of the scanned first of the input signal, the circuit properties of the predecessor belonging to the decoder and the desired unity for it that an unambiguous Au: igan {, üsignal is not generated,

709829/0813

ORIGINAL INSPECTED

If the comparator regeneration cycle fails is concluded, it is possible that in the to ambiguous Comparators delivering output signals connected digital circuit arrangements errors occur » Digital errors occur when more than one circuit is connected to the output of an ambiguous comparator? sen is different because different digital circuits on the non-digital (analog) ambiguous output signal respond and therefore the signal is interpreted differently in different signal paths * arise accordingly error in output code.

Therefore, the invention has the object of providing a To create analog-to-digital converters that require the shortest possible kegeneration time and the smallest possible Has transfer time, so that it is very high Conversion speeds locked.

This object is achieved according to the invention by that with the analog signal receiving input circuits

2 amplifiers are coupled, each having a threshold value and deliver an output signal when the signal supplied by the input circuits exceeds the threshold value that a switching network is coupled to the amplifiers, which supplies 2r + 1 output signals, each of which is from the exceeding of the threshold values the amplifier represents a dependent bit of a cyclic code, and that a logic is coupled to the switching network, which decodes the 2Γ + ι output signals of the switching network to N output signals, which form an N-digit binary number «

709829/0813

In a preferred embodiment of the invention an N-bit analog-to-digital converter has a voltage divider output network on, which is coupled to 2 differential amplifiers, which have individual reference voltages are fed. Each differential amplifier provides an output signal when given to it by the voltage divider network supplied KingBngssignal exceeds the reference voltage. ISin pretension compensation network is connected to the voltage divider network to determine the size of the differential amplifiers supplied total Vorapannstrom is, and approximately to generate the same and opposite current as the total bias current fed to the differential amplifiers essentially cancels. The differential amplifiers are selectively coupled to a number of switching networks, the depending on the output signals of the differential amplifiers generate a cyclic code. The switching networks are selective with a number of logical links for decoding the cyclic code into an N-bit binary code. the logical links are selective with one Number of networks to determine the output voltage level and connected for temporary signal storage to the various output signals to deliver logical standard levels «

The circuit arrangement according to the invention can in particular manufactured in units each forming a four-bit digital word. These units can then be used to generate words of more than four bits in parallel, series or series-parallel combinations be used·

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- JjT-

The inventive analog-to-digital converter draws apart from a maximum working speed, which can also be variable, a high input impedance and a low input capacitance and has a lower power requirement than analog-to-digital converters with comparable properties. Furthermore, the converter according to the invention is with a Bias compensation is provided to compensate for the non-linearity (bowing error) caused by the bias currents for the various input amplifiers.

The invention is described below with reference to the in the drawing illustrated embodiment described in more detail and explained. The features that can be derived from the description and the drawing can be used in other embodiments the invention can be used individually or collectively in any combination. Show it

1 shows the schematic block diagram of a preferred embodiment of an analog-digital converter according to the invention,

Fig. 2 is the equivalent circuit diagram of the generation of Voltage divider network of the converter according to FIG. 1, which is used for reference voltages,

3 shows the circuit diagram of a preload compensation network and an input amplifier of the converter according to FIG. 1,

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• 3.

4 shows the circuit diagram of a first type, a preload network of the converter »to Fi ^. 1,

Fig. 5 is a circuit diagram of a two-tone type of Vorr / J.ann network of the converter "according to Fig. 1,

6 shows the circuit diagram of a driver only with a new buffer dea Uinijetzerü according to Fig. 1,

7 shows the circuit diagram of a era th i * rt. of a switching network de »Converter :; n; i i''i; -. I ₁

Fig. 7 ^a the circuit diagram of a u üeeodierui-u of the harvest stage,

Fig. 6 the picture contains a second wt of a rapid

netzwerketj of the Uiusjetzers after i ¹ ' : u. I ₁

Fig. 9 is the diagram of a third and a «switching

netzwerketj des Umsetzrrb nncli Fi.% 1,

10 shows the circuit diagram of a fourth type of circuit

netzv / ErkOii des UiayetZfrs to Fi _t :. 1,

11 shows the circuit diagram of a delay logic of the converter according to Fig. 1,

Fig. 2 shows the circuit diagram of a UMU-GIitides,

Fig. 1 ^ the visual image of a Y-Giiedeu,

709829/081 3

ORIGINAL INSPECTED

Sf -

14 - the circuit diagram of an exclusive ODKK element, 15 shows the image of an output buffer network, Fig. 16 is the circuit diagram of an output driver network,

17 is a circuit diagram of a third type of preamble network;

18 is a circuit diagram of a fourth type of preamble network;

19 shows the block diagram of a 5-uit encoder and FIG Fig. 20 is a circuit diagram of a 6-bit encoder.

FIG _o 1 shows an analog-to-digital converter, which makes use of a 4-bit converter unit, which is hereinafter referred to as Quantisiernetzwerk 10, l ^ in lÜngangs network 11 receives analog i ^ ingangssignale from a signal source, such as a Radar receiver. The long-range network 11 contains sixteen identical amplifiers, which are described in detail below and which form an interface between the analogue king-input signals and the subsequent switching functions. The interface function of the input network 11 includes a voltage gain, an overload limiter, a level shift and a common mode rejection. The performance of the K gang network 11 determines the resolution and the response time of the analog-digital converter ο

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The output terminals of the input terminal 11 are connected to the input terminals of the first stage 1 ;? “Connected to a decoding network, which includes nine switching emergency units and a driver. The first stage 12 of the encoding network decodes the output signals of the input network into a cyclic 9-month code and holds the signals representing this code «Which the switching networks of the first stage Λ ?. of the deoodier-current effect forming circuit «-
arrangements have a minimum lie generation time constant, so that a «; Resolution of 8 lid L achieved when the analog signal is sampled with a frequency of $ 00 LUIz
will·

The output terminals of the first stage of the coding network are connected to the input terminals of a second
Stage 1) of the decoding network <; s connected to the one
A delay element, an AND element, an imaah 1 Y element and a number of exclusir-ODlili elements. The second stage 15 of the Üecodier-Hetzwerkea sets the 9-Wit-Zwinchencode, which is derived from the era th stage 1c? of the decoding network is generated into the desired ¹ \ -hit binary code.
In addition, the second stage 13 of the encoding network a generates an output signal which forms a position bit.

The output terminals of the second level 1.-5 of the
Network are connected to the Üingangsklemmen an output Netiiwerkes Λ ^ι ν , which of the second
Stage of the decoding network xu ^ jo-guided input signal holds and dadui-cli extends the time V (i, during the a
valid output signal for Vu-iüinji ^ r is

7 0 9 8 2 9/0813

ORIGINAL INSPECTED

The input network 11 comprises in detail input terminals 20a and 20b, which the analog input signals and they receive a voltage divider network 21 and a first differential amplifier 24a of the input amplifier network 24 feed. The tension divider-i network comprises a first network of series-connected, balanced resistors 22a to 22p and a second network from series-connected and balanced resistors 25a to 23p. The first differential input terminal 20a is connected to the first terminal of the resistor 22a and the first input of the first differential amplifier 24a.

The first electrode of the second resistor 22b of the first network 22 is connected to the first input of the second differential amplifier 24b connected. Correspondingly, the first terminals of the resistors 22c to 22p correspond to the first Connected inputs of the third to sixteenth differential amplifiers 24c to 24p.

The second differential input terminal 20b is connected to the first terminal of the resistor 23a and the second input of the first differential amplifier 24a connected · The first terminal of the second resistor 23b is connected to the second Input of the second differential amplifier 24b connected · Correspondingly, the first terminals of the third to sixteenth resistor 2? c to 23p each with the second input of the third to sixteenth differential amplifier 24c to 24p connected.

709829/0813

In order to achieve the high operating speed of 300 MHz, additional differential inputs must be used to set the setting time of the 3 input network 21 to reduce. Therefore, the amplifier network 24 has second and third pairs of differential input terminals. The first input terminal 20c dea the second Pair of differential input terminals is with the connection between the balanced resistors 22h and 22i and to the first input of the differential amplifier 24i connected. The second input cycle 20d of the second The pair is with the connection between the balanced resistors 23h and 23i and with the second input of the Differential amplifier 24i connected. The first input terminal 20e of the third pair of differential input terminals is connected to the second terminal of the resistor 22p, while the second input terminal 2Of this Pair is connected to the second terminal of the resistor 23p.

The second or negative input terminals 20b, 20d and 20f of the differential input terminal pairs are different Reference voltages supplied, whereas the first three or positive input terminals of the differential input terminal pairs the same analog signal is supplied. Applying different reference voltages to the different Pairs of input terminals and the application of the same analog input signal reduce the input inductance and the settling time of the resistor networks 22 and 23. In addition, the cumulative effect the tolerances in the values of the individual resistors within the first and the second resistor network 22 and 23 significantly reduced.

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The resistor networks 22 and 23 can be through the The equivalent circuit diagram of FIG. 2 is shown. The linearity error or arc error voltage (bow error-voltage), which are otherwise in the resistor networks 22 and 25 would exist by using balanced resistors in both networks 22 and eliminated «The use of balanced resistors in the two resistor networks 22 and 23 has one Compensation of the arc error by uniformly distributing the input bias currents to the differential amplifiers 24a to 24p result.

Analysis of the general equivalent circuit diagram of Fig. 2 shows that the arc fault voltage can be eliminated. The equivalent circuit diagram consists of N equal resistors which are connected between the voltages V _Q and V ^. A current I is supplied to each connection between two resistors. If M denotes the number of the tap, starting with M »O at Vq, then it can be shown that the voltage at each tap between the series-connected resistors has the following value:

(V -V) ₊ V ^v η ο ο

The two links at the right end of the printout are the terms of the linear voltage divider. The large expression in square brackets is the arc error term · Da

709829/0813

· 4Γ ·

the input terminals receive differential input signals, each amplifier is supplied with a differential voltage, which is the difference between the reference voltage supplied in each case and the input signal voltage supplied.The voltages V _n and V _Q are supplied to the N points of the reference resistance network that supplies the reference voltages to the respective input amplifiers 24a to 24p. The currents I fed to the input terminals of the differential amplifiers 24a to 24p are identical and it is V ₀ «V« «V., V _{n being} fed to the positive inputs of the Wideratanda network 22. Since the differential voltage from the corresponding resistors of the first and second resistor networks 22 and 23 is fed to each amplifier, the arc error is compensated, as shown by the following equations:

"^ WfV 'J - RI [Arc fault] ^{+ V} i η V ₁₁ C-) - RI [Arc error} (Y ₁₁ - V ₁₁ C ₊ ) -v _M (_) «Γ - w ( ; v _N - V <

V _Q

The compensation of the arc error is made by the adjustment tolerances all parameters of the resistors in the two resistor networks 22 and 23 are limited.

As can also be seen from FIG Input meshwork 11 furthermore a bias current compensation network, that from two transmission networks and 25b connected to bias scan terminals of

709829/0813

Differential amplifiers 24a to 24p are connected. The networks 25 »and 25b effect a bias compensation in such a way that the same bias currents are supplied to the input amplifiers 24a to 24p. The current mirror network 25a samples the positive Input bias current from and feeds amplifier 24a to 24p give a substantially equal but opposite current, creating the resulting bias current becomes zero, üaa current mirroring network 25b samples the negative input bias current and supplies the differential amplifier in the same V / eise an opposite current.

The iJtroraspiegelungü networks P. ^ a and 25b and the input amplifiers 24a to 24p will be explained in more detail later with reference to FIG.

A first type of header network 26a is related to the first bias terminals of amplifiers 24a to 24d connected. The network 26a determines the speed of operation of the quantizer, in that it selectively supplies different bias currents to the Vex «stronger. The smaller the current that is supplied from the network 26a, the slower the operating speed of the quantizera. Conversely, the greater the current, the greater the operating speed of the quantizer. The leader network 26a will be explained in more detail later with reference to FIG.

second bias network 26b, which is the same as network 26a, is the differential amplifier with the first bias terminals Connected 24e to 24h. A third leader network 26c, which is also the same as network 26a,

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is the differential amplifier with the first preload clamps 24i to 241 connected. Finally, there is a fourth leader network 26d, which also corresponds to the Network 26a is the same, connected to the first bias terminals of the differential amplifiers 24m to 24p.

A second type of header network 2? A is with connected to the »wide bias terminals of the differential amplifiers 24a to 24h. The network 27a carries the differential amplifiers 24a to 24h apply the bias voltages required to adjust the level of the output signal for a set logical zero. A second bias network 27b is the differential amplifier with the second small biases 24i to 24p connected. Look Pig. 5 becomes the leader network 27a. the second kind later in detail explained.

Generate in the first stage 12 of the decoding network the switching networks contained therein have a cyclic one 9-bit code depending on the output signals of the Differential amplifier 24a to 24p. The switching networks are essentially bistable circuits, the one have upper and lower power switching sections. As will be shown, some take these switching networks a first initial state if the assigned Amplify the threshold values are not exceeded. There is a first transition from the first initial state to a second output state when the threshold of the first amplifier is exceeded will. There is also a second transition from that

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- vf-

second initial state to the first initial state, when the threshold of the second amplifier is exceeded. Accordingly, a switching network combines the functions of two switching networks in known analog-digital converters ,, the switching networks 31a to 31c and 32a to 32d operate in the manner described above

The switching networks 30 and 3 ^ have only one transition depending on the input signals sent to you by be fed to the assigned differential amplifiers

The output terminals of the diffuse converter 24a aind with the input terminals of a switching network 30 first Kind connected. The switching network 30 generates a for a logical zero characteristic output signal, when the threshold of the differential amplifier 24a was not exceeded, and the state of a logical 1, if the threshold value of the differential amplifier 24a has been exceeded. The structure of the switching network a will be described in detail with reference to FIG

The output terminal of the second differential amplifier 24b is connected to the first input terminal of a switching network a 31a of a second type connected. The output terminal of the tenth differential amplifier 24j is connected to the second Input terminal of the switching network 31a connected The switching network 31a initially generates an output signal which is characteristic of a logic 0, if daa analog input signal does not exceed the thresholds of amplifiers 24b and 24j. If the threshold

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■ 4.

of the amplifier 24j is exceeded, the switching network 31a generates an output signal characteristic of a logic Λ. If the threshold value of the amplifier 24b is also exceeded, this switching network again generates an output signal which is characteristic of a logic 0. A more detailed description of the switching network 31a is given below with reference to FIG.

The third differential amplifier 24c is connected to the first Input of a switching network 32a connected. The eleventh differential amplifier 24k is connected to the second Input terminal of the switching network 32a connected. The mode of operation of the switching network 32a is the same as the mode of operation briefly described above of the switching network 31a. Accordingly, be dependent from the states of the differential amplifiers 24c and 24k, output signals having two different states delivered. The main operational difference between switching networks 31a and 32a lies in the levels of the output signals. Additional components are used to adjust the levels of the output signals move. The circuit diagram of the switching network 32a can be found in FIG. 8.

The fourth amplifier 24d is connected to the first input terminal of a second interlocking network 31b. The output terminal of the twelfth amplifier 24e is connected to the second input terminal of the switching network 31b. This switching network is also designed like the switching network 31a,

709829/0813

The ninth differential amplifier 24i is connected to the input terminal a fifth salary network 33 connected «The structure and function of the switching network 33 13t of the function and structure of the switching network same, juiine detailed representation of the £> chalt network 33 is also found in Fig. 6,

The fifth differential amplifier 24e is connected to the first input terminal of a sixth switching network 32b tied together. The thirteenth differential amplifier 24m is connected to the second input terminal of the maintenance network 32b connected, which is designed in the same way as the switching network 32a.

The sixth differential amplifier 24f is connected to the first input terminal of a seventh switching network 31c tied together. The fourteenth amplifier 24n i3t with the second input terminal of the üchalt network 31c connected. This network is designed in the same way as the üchalt network

The seventh differential amplifier 24g is connected to the first input terminal of an eighth output network 32b. The fifteenth amplifier 24o is connected to the second input terminal of the switching network 32b, the is the same as the üchalt network 32a «

The eighth amplifier 24h is connected to the first input terminal a ninth switching network 31d connected. The sixteenth amplifier 24p is connected to the second input circuit this üchalt network 31d connected, the is designed in the same way as the üchalt network 31a,

709829/0813

tSwitching signal buffer 3 !? Presses on and off signals from a switching signal source 34th Line first Output terminal de3! Differs 3 ^ is connected to the ^ ingangklemme a driver 37 connected. Line first, with LT designated output terminal of the üchaltaignal driver is connected to the control inputs of the fcichalt networks « The second output terminal, labeled LT, of the Lkihaltsignaldriver 37 is with the control clergy of the interlocking networks tied together.

The first i »-us input terminal U of iJchalt-iioozwerkes 30 is with the initial class of one member 40 and the first iiinput terminal of a UUD element 41 connected «" The second Output 3 terminal L of the L> (; iialt-N «.- network Jn int with the first inputs Y dej? three '/ limbs 4 ^ ü, 42b and' 4 ^ c tied together",

The output terminal U of the second ochalt network 31a is connected to the third input terminal U of the first Y element 42a connected «

The output terminal L of the third Schillt-Nwtzwurkes 32a is connected to the second input L of the third Ϊ-element 42c and the second input terminal L de3 first l ^ xclusiv-ÜDKR element 4Yes connected «The output U de3 fourth Switching network 31l> is connected to the first input terminal of the first lixclusiv-OüEH member 43a "

The first output terminal U of the fifth switching network is connected to the first input terminal U of the third Y element 42c connected «The second output terminal L of the switching network 33 is connected to the second terminal L of the

709829/0813

ORIGINAL INSPECTED

AND gate 41 blind. The second output terminal of the switching network 33 is also connected to the second Input terminals L of the Y-links 42a and 42b are connected. The first output terminal of the sixth switching network 32b is connected to the first input terminal U of the second Y-element 42b and the first input terminal U of the second Exclusive-OR gate 43b connected. The second output terminal L of the switching network 32b is connected to the second input terminal L of a third exclusive-OR gate 43c connected.

The output terminal of the seventh switching network 31c is connected to the first input terminal U of the exclusive-OR gate a 43c connected.

The output terminal of the eighth switching network 32c is connected to the second input terminals L of the second and fourth exclusive-OR gate 43b and 43d, respectively. The output terminal of the ninth switching network 31d is connected to the first input terminal U of the fourth exclusive-OR gate 43d.

The links 41, 42a to 42c, 43a and 43b are described in more detail below.

The output terminals of the first Y-member 42a, the first, of the third and fourth exclusive-OR gates 43a and 43c and 43d, respectively, are in the form of a wired OR operation connected to each other and deliver the last digit bit 2 ° of the output signal.

709829/0813

4 92
Κ * »

The output terminals of the third Y-member 42c and des second exclusive OD-bR member 43b are in the form of a wired OR link and form bit 2 of the penultimate position.

The output terminal of the second Y-element 42b supplies

bit 2 of the next higher position. The output terminal

■ χ of AND element 41 supplies the highest-digit bit 2.

The timer 40 causes a one-step delay for the output signal of the switching network 30 to to achieve an adaptation to the signal delay in the other logic elements »The timer 40 provides the position bit of the quantizer that is required is used when a combination of several quantizers is used and the capacity of the quantizer is exceeded will. The timer 40 then supplies an output signal in the state of a logical 1 · The use of the timer 40 is only required when required and can be omitted if a single quantizer is used as a four-bit analog-to-digital converter is used.

To the logic gates of the output signals of the second Level 13 dee decoding lietzvverkes to the required Adjust output level, for example for controlling ECL circuits in MEGL 1OK technology are required, 13 output stages 46a to 46e are connected to the logic elements of the stage. The output network formed by this causes the level shift, which is shown at an interface, see below Standard MECL 1OK type circuits required are. The logic levels of the output signals are determined by the internal driver circuits of the various output stages or networks determined. The network 14 effects

709829/0813 - /.

Vt.

also a storage of the output signals of the second Stage 13 of the decoding network, no that the Aufjgangssignale of the network 14 have a longer duration than its input signals. Furthermore, each output stage a plurality of identical Aungangükleiumen, which the Enable the use of independent, external connections in the manner of a wired OR link. An example of such a connection results from the use of two 4-bit quantizers for the formation a 5-bit analog-to-digital converter, as described above Fig. 19 is described «

The mode of operation of the quantizer or the analog-to-digital converter ^{circuit according to J 1} Xg ₁₁ 1 will now be described with reference to the circuit diagram shown in FIG. 1 and the table I given below. The numbers given in circles within the switching networks correspond to those given in the table Switching numbers. The three reference signal input terminals 20b, 20d and 20f are supplied with three different diffraction voltages, namely +1.5 V, OV and -1.5 V, which determine the reference levels for the individual differential amplifiers 24a to 24p. The smallest range of reference voltages that can be applied to the reference signal input terminals is limited by manufacturing technology and is currently 1) 0 mV. The input terminals 20a, 20c and 20e are connected to one another and receive a common analog input signal. The two series resistor networks 22 and 23 are used to correct the "arc error" described above with reference to FIG. The electricity mirroring networks 25a and 25b generate a bias compensation in that they determine the current requirement at the inputs of the amplifiers 24a to 24p and supply a current which approximately compensates for the entire input current.

709829/0813

For the purpose of explanation it is assumed that the analog input voltage is -1.5 V and with the Time increases steadily to +1.5 V. At the beginning, the Threshold values of the amplifiers 24a to 24p are not exceeded and the amplifiers do not provide any output signals to the switching networks in the first stage of the decoding network. The switching networks of the stage receive clock signals and deliver them to the logic gates in the second stage 13 of the decoding network Output signals that correspond to a logical O. The logic elements also deliver accordingly an output signal corresponding to a logic 0. Accordingly, the analog input signal of -1.5 V corresponds to the logic state O.

When the input voltage becomes more positive than the reference voltage, the amplifier 24p provides an output signal to the switching network 31d, the output of the switching network 31d assumes the state of a logical 1 and is supplied to the exclusive OR gate 43d. That Exclusive-OR gate 43d then also changes its State and provides an output signal in the state of logic 1. The output stage 46e then delivers depending on the output signal of the exclusive-OR gate a 43d and clock signals supplied by the driver 48 a time-extended output signal in the state of logic 1. Table I illustrates this output signal in the line with the threshold value number 2

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If the threshold value of the amplifier 24o is exceeded, the switching network 32c delivers in the same way the output signal characteristic of a logical 1 to the exclusive-OR gates 43b and 4 3d.

When the analog input signal continues to rise, the threshold of the second amplifier also becomes 24o exceeded and a signal fed to the switching network 32c. The switching network 3 ^ -C in turn leads Output signals with the state of logic 1 to the exclusive-OR gates 43b and 43d. The exclusive OR element 43d then supplies an output signal in the state of the logical O to the output stage 46e " The exclusive-OR gate 43b provides an output signal in the state of logic 1 to output stage 46d, Table I illustrates the result.

If the analog input voltage continues to rise, the threshold values of further differential amplifiers are exceeded and output signals characteristic of a logical 1 are generated. The switching networks respond to these output signals and feed the logic gates with output signals with the correct Λ and 0 states.

It should be noted that the switching networks as first step of decoding generate a cyclic code. The use of such a cyclic intermediate code simplifies the overall circuit because there is less Switching networks are required than with the known analog-to-digital converters. Most analog-to-digital converters require 16 switching networks for decoding

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an analog king input signal into a 4-bit digital output signal. In the system explained , on the other hand, only 9 switching networks are required to generate a 4-bit output signal «

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10
11
12th
13th
14th
15th
16
17th
18th
19th
20th
21
22nd
23

24 ρ

25 2

26 2

27 2
28

C. α>

r- i

1 ■ s

co

1
2
3
4th
5
6th
7th
8th
9

⁵ 10

11
12th
13th
14th
15th
16

TABLE I.

Output signals

the switching networks

907654J21

000000000

000000001

000000011

000000111

000001111

000011111

000111111

001111111

0 11111111

011111110

011111100

011111000

011110000

OlllOOüOO

011000000

010000000

110000000

¹ -

2 ° -

8 9

(4 0 8) * 9 ~

(2 0 4) + (6 0 8) x 9 "

(10 2) + (3 0 4) + (5 ©

i ' 2 ³ 2 ² 2 ¹ 2 ° 0 0 0 0 0 0 0 . 0 C. i 0 0 0 1 ü 0 0 0 1 i 0 0 1 0 ü 0 0 1 0 i U 0 1 1 0 U 0 1 I. 1 0 1 0 0 0 0 1 0 0 1 ü 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0

(7

6) 9

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ORIGINAL INSPECTED

-, 26. -

In fig. 3 are a differential amplifier 24-a and a Current mirroring network 25a shown in detail The current mirror network 25a comprises three transistors 50, 51 and 52, of which the first two transit gates 50 and 5t connected to each other at their bases are o In addition, the transistors 50 and 51 are at their Emitters connected to each other. The collector of the first Transietors 50 is connected to the base of the third transistor 52 connected. The collector of the second transistor 51 connected as a diode is connected to the emitter of the third Transistor 52 connected. The collector of the first transit stors 50 is connected to the cathode of a Schottky diode 55, the anode of which is connected to a frequency voltage is. The collector of the third transistor 52 is connected to an input terminal 5 ^.

The current mirroring network 25b is embodied in the same way as the current mirroring network 25a and therefore does not need to be described in detail. The differential amplifier 24a will now be described in detail. The analog differential signal is fed to the inputs 56a and 56b, which are labeled positive and negative, respectively. The positive input terminal 56a is connected to the base of a transistor 57 connected as an input emitter follower. The emitter of transistor 57 is connected to the base of a first transistor 58a of a pair of differential transistors. The emitter of the transistor 57 is also connected to the collector of a transistor 60 operating as a current source. The base of the transistor 60 is connected to the bias network 2? A. A resistor 61 connects the emitter of transistor 60 to ground or to a reference voltage of, for example -5 V _e

709829/0813 .

The collector of the transistor 57 is connected to the emitter of a transistor 62 serving for signal isolation. The base of transistor 62 receives a bias current from bias current compensation network 25a '. The collector of transistor 62 is connected to the emitter of a transistor 63 which is connected as an output emitter follower. The collector of transistor 62 is also connected to the output terminal 24b of a differential output terminal pair. The base of transistor 63 is connected to one end of a resistor 65 connected. The other end of the resistor 65 is connected to the Kuthode of a diode 66, the anode of which is connected to a bias voltage of for example +5 V _u The collector of the transistor 63 is connected to the positive bias voltage »

The second input terminal 56b is at the base of one Tranaistor also connected as an input emitter follower 67 connected «, the emitter of transistor 67 is connected to the base of the second transistor 59 of a pair Differtmztransistoren (transistors 5Ω and 59) connected. The emitter of transistor 67 is also connected to the collector of a transistor 68 operating as a current source. The base of transistor 68 is connected to bias network 26a. The emitter of transistor 68 is applied to a reference voltage through a resistor 69.

The collector of transistor 67 is one with the emitter for signal isolation serving transistor 72 connected « The base of transistor 72 is with the current mirror network 25b connected «the collector of the transistor

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- 28- -

is connected to the differential output terminal 64a. The base of transistor 73 is connected to the collector of transistor 58b and the first end of a resistor 74 connected «whose second end is connected to the cathode of diode 66 ·

The emitters of the balanced pair of differential transistors 58a and 58b are with each other and with the collector of a transistor 70 operating as a current source. The emitter of transistor 70 is connected via a Resistor 71 connected to a reference voltage · The The base of the transistor 70 is connected to the Vorapann network 27a tied together"

The differential amplifiers 24b to 24p are constructed in the same way like the differential amplifier 24a and therefore need not be described in detail. How the Differential amplifier 24a and the current mirroring networks 25a and 25b will now be explained in more detail with reference to FIG.

A bias voltage is applied to the bases of transistors 60 and 68 by bias network 26a. Transistors 60 and 68 together with resistors form 61 and 69 a constant current source. The constant current flows from the emitter of transistor 57 to the collector of the Transistor 60 and, to a small extent, transistor 58a. The constant current flowing through transistor 60 and the small current flowing to transistor 58a is from Transietor 62 delivered. The base of transistor 62 is connected to the summing node of current mirror network 25a connected that provides a reference voltage and also the

.A 709829/0813

Current flowing in the base of transistor 62 is detected by the emitter current of transistor 62 compared to the current flowing into the base of transistor 62 is large, then flows into the collector of transistor 62 » This collector current is drawn from the emitter of transistor 63, which is essentially from the collector of the transistor 63 and ultimately supplied by the reference voltage source will",

The series connection in the right part of the differential amplifier is the mirror image of the series circuit just described and therefore does not need the to be described individually.

The positive and negative Kjngangnaignale be supplied to the bases of the control transistors 57 una 67 »The transistors 57 and 67 reduce the Kingangsimpedanz for the bases of the differential Tranaistorenpaares .58a and 5üb _o from the emitter electrodes of the differential pair of transistors 58a and 58b by means of the transistor 70 formed constant current source o a constant current drawn The constant current is passed through the transistors 58a and 58b. The portion of the current that flows through each of the two transistors is proportional to the voltage difference across the terminals of transistors 58a and 58b. The constant current is drawn from the collectors of the transistors 58a and 58b to the resistors 65 and 74. The currents flowing through the resistors 65 and 7 ^ produce a differential voltage which is fed to the bases of the transistors 63 and 73 in proportion to the input voltage. The transistors 63 and 73 effect one

709829/0813
OOPY

-HögelverHchiubung and a liapedar: · /, '/ *; ria.i nderuiigo Uk.s iwui3gangii supplied by the transistors bp and Vi:; igna; i becomes the iJohalt-lJe tawerken dt; r t.-rüten Ji-ur.'e 1 ,. ' cie.s Uecodier-iit.'tzwerkcs fed * The opannungiibisreioh ei ti u output signal cheating about +5.5 biue +> _t 0 V _u

The bases of Tranwiiitv -an υ \. 'Er: it; iji ^ r,'. ¹ ^ ;. Lu; <>i;

get their iJti'oiii ■■ '. dor « _;: , iij ..; ijitl '! irii.ie'>. ·>do; j oirotis]) iegelungL> -i ^ itzwurkt; ^ .- ^ a _- ^ unaotuit uii-u der Jtrci ;: .lurch the i ^ asia deü TriiiiiiiJ toj-y % ' pulled, wa.s dua i''Ii'-; .. t; ii von KollektoTHtroci through the 'i'ranyiii tor'? -. ' in. *: aiiüciil it-üeria dan Tranaistür ^[ ; 1 i ^ .vvkte; "Ιλι die Baijis des '^ vuniiL.iUovu%'. with the Kollektoi 'd «y Ti-anai :; tors ^£ jü verbu / iden i: i L, at the Transiatoi · [> 0 a juiche iiaaiH- ^ iait ter-LJjjerung builds up, daii the Kollt.'Rtorsti'iime the "l'rariüiijtoren ^v ^> and ^v / \ Dna ν \, · ι · ηϋ1 tnia dei ¹ Uirforcüiz der LJLrörae to the amount deü L>trum> -iü iut then Λ /, ' ¹ " urul results in a filer of less alu 1> ao Der an dor hleiurue yi au : The current flow is added to the 'j'r;in:;. i: j i ~ .ui-en \>'<of all iJiLTert.-n · / -veratärker _u * uu; α ei. bt;: j .-; hrt - ibunf; the '»• ii'lcungijweise der Dii? i." ereni: vt: r: ji; ürker g: in ^ out, daii the Ütrome, v / «ilcln; the collector of the'i'r:.n:;i; itors 6'J and 57 fly through, almost _f ; lejch üind, no daiJ au:; L die üasisstrüiüe annähci'na |.. Ii .sinu.: nl'olgedti.suen becomes the ^ 'ingangüütrom dur \>. -rtia /,ve.i ., tai "i.er kouiperi.'jiert by adding one of the J ti ^ Gin.sj.iti ^ c .. ·] ungü-iio tzvvei-k ge-i'ter otroin wjivu iYes. ^f > υ troti.'ipiege iuin ^ ii.et ^ wurk - ;; b works in glei-acr Wuiso ^ i-: <iuu Li, ronüpi.v; t; lung ;; - network ^ n una brauclit therefore hi ^ r never!.;, ii: i individual treated;: u vvt; i-cen _o

BAD OBIG »* '· ¹

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As can be seen in Figure 4-, the bias network 26a includes a transistor 80 whose collector is connected to Hasse. The base of the transistor 80 is connected to the collector via resistor branches 81a, 81b and 81c containing switches, which make it possible to change the current flowing through the transistor 80 in order to adjust the operating speed the higher the currents flowing through the transistor 80 in order to achieve a high operating speed. The control network 5 ^ - is used to select the switch sections a, b and c _e

The emitter of the transistor 80 13t is connected to the collector of a diode-connected transistor 85 and the base of a transistor 86 which is connected to the junction between the resistors 81a, 81b and 81c. The emitter of transistor 86 is connected to the first end of a resistor 8? tied together. The second end of resistor 87 is connected to the collector of a transistor 88. The emitter of the transistor 85 is directly connected to the collector of the diode-connected transistor 88 via a resistor 89 and to an output terminal. The emitter of transistor 88 is connected to a bias voltage of -5 _f 2 V, for example.

The mode of operation of the prestressing network 26a will now be explained in more detail with reference to FIG.

709829/0813

IT

The bias network 26a generates a voltage at its output which determines the strength of the current at the input of the differential amplifiers 24a to 24p. Accordingly, this bias network controls the output voltage of the amplifiers. Transistor 88 compensates for changes in base-emitter voltage that occur across current source transistors 60 and 68 of the network of FIG. 3 as a function of temperature and manufacturing tolerances. The transistors 86 and 80 are connected in such a way that they form a voltage source which is negatively fed back with a low amplification factor. The output signal of the negative feedback voltage source is supplied by the emitter of transistor 80, which leads to a low output impedance. The transistor 86 forms an inverting amplifier in the generated emitter circuit which controls the output voltage and provides negative feedback from the emitter of the transistor to further reduce the output impedance. The output voltage of the source is determined by the ratio of resistor 81 to resistor 87, the voltage drop across the three base-Kmitter diodes of transistors 88, 86 and 80 and by the negative bias of, for example, -5.2 volts . The output voltage is shifted by the diode-connected transistor 85 "which is biased by a current determined by the resistor 89". The output voltage of the network is set so that it is about 1.35 V more positive than the bias voltage of -5 * 2 V, i.e. about -3 * 85 V.

709829/0813

Referring now to FIG. 5, the preamble network 27a briefly described. The circuit construction of the bias networks 26a and 27a is identical, except that that the network 27a has only one resistor 81. As a result, the components of the network according to FIG. 5 have been given the same reference numerals as those in Fig. 4. The difference between the two networks 26a and 27a lies in the voltage level of the Output signal.

The mode of operation of the prestressing network 27a according to Fig. 5 is identical to the operation of the prestressing network 26a of FIG. 5, so that in this respect the Description of FIG. 4 can be used.

Referring now to Fig. 6, the switching signal buffer and the switching signal driver 37 will be described. In the buffer 35 is the bases of two differential transistors 10Oa and 100b supplied the switching signals from the switching signal source. The emitters of the transistors 100a and 100b are with each other and the collocator of a transistor 101 connected. The base of transistor 101 is connected to a bias network 47. The emitter of the transistor 101 is connected via a resistor 102 to a bias voltage of -5 $ 2 V, for example.

In the Schaltsifjnal driver are the emitters of two input transistors 103a and 103b with the collectors of one of the two transistors 100a and 100b of the buffer

709829/081 3

tied together. The bases of the transistors 103a and 103b are grounded. The collectors of transistors 103a and 103b are connected to the cathode of a Schottky diode 106 via a respective resistor 104 or 105 connected to the anode of the diode 106 eniine D ₀ is connected to the emitter of a transistor 107 and an off transition ski connected to a bias voltage of about 3 »4 V. Collector and base de3 transistor 10? connected to each other and the emitter of a transistor 108. The emitter of the transistor 108 is also connected to a disconnect terminal D, which supplies a bias voltage of about 4.2 V "The collector and the base of the transistor 108 are connected to one another and applied to a bias voltage of, for example, +5 V ",

The collector of the transistor 103a is connected to the base of a two emitter Ti'ansistor 109. Of the The collector of transistor 109 is at a voltage of +5 V. The two emitters of transistor 109 are connected to ground via a resistor 110 or 111. In addition, the two emitters have output terminals connected to the Sohalt networks Apply switch-off signal ,,

The collector of transistor 103b is connected to the base of a two-emitter transistor 112. Of the The collector of transistor 112 is applied to a voltage of +5V. The two emitters of the transistor 112 are connected to ground via a V / resistor 113 or 114 · The two emitters of transistor 112 are connected

709829/0813

also connected to a second set of output terminals, which the switching-agitation the switch-off Tnktsignale respectively,,

The operation of the buffer 35 and the Switching signal driver 37 described with reference to Fig. 6 »

The transistor 101 generates a switched current, which flows through one of the transistors 100a or 100b, depending on which input signals these transistors are supplied from a signal source 36 »i ^ in the Causes the base of the transistor 100a supplied signal, that the switching current flows through this transistor « If a signal is fed to the transistor 100b, then the holding current flows through the ;; on 'i'rariiii

The puncture of the switch signal switch 3 ¹ ? and the switching signal driver 37 consists in receiving ULC signals from an external source 36 with the usual values for iX / L circuits, namely -0.82 to -1.7 V and bringing these signals to those levels and to offer the impedances that are required for the switching meters of the first stage of the Deco Ler network.

'when the switching current between transistors 100a and 100b is switched, the current between transistors 103a and 103b is also switched. £ lin current flow through the transistor 103a causes a voltage drop across the resistor 104, which the output signal LT of the transistor 109 controls, therefore, when the switching current flows through the transistor 103a, the output level of the transistor is 109 below the output level of transistor 112.

709829/0813

ORIGINAL INSPECTED

On the other hand, when the switching current flows through the transistor 103b, transistor 112 generates output signals LT 1 and LT 2 which are lower than the output signal of the Tranaistors 109. The transistors 109 and 112 are emitter followers, which produce the circuit isolation, which is required to achieve a high working speed while using the switching networks which is a capacitive load.

The Tranaistor 108 provides a bias voltage around the The voltage drop across a diode is below +5 V. Of the Transistor 107 provides a bias voltage equal to the voltage drop across two diodes under the bias voltage of +5 V.

The voltage level of the output signals LT 1, LT 2, LT 1 and LT 2 is about 2.1 V for the high state and about 1.8 V for the low state «

It can therefore be seen that a transistor 100a The input signal supplied in the state of a logical 1 results in an output signal at transistor 112 which is also characteristic of a logic 1, but its level in relation to the voltage level of the signal ULC is postponed. In the same way, a signal fed to the transistor 10Ob which indicates a logical 0 is characteristic, results in an output signal characteristic of a logic 0 at transistor 109, the level of which is also shifted with respect to the level of the signal tJLC.

709829/0813

As I ^<n ic * 7 shows, a switching network 33 has a cascode isolation stage 120 with two transistors 120a and 120b, the bases of which are jointly applied to a bias voltage D. of approximately 4.2 volts. The collectors of the transistors 120a and 120b are each connected to a voltage of +5 V via a resistor 121 or 122. The emitters of the transistors 120a and 120b are connected to the collectors of the transistors 123a and 123b of a differential current switching stage 123. The emitters of the two transistors 123a and 123b of this differential circuit stage 123 are connected to one another and to the first collector of a differential circuit switch 124. The base of the transistor 123b is connected to a first input terminal A and the base of the second transistor 123a to a second input terminal B. tied together.

The differential current switch 124 includes two transistors 124a and 124b, which are connected to one another at their emitters. The emitters are still on connected to a current source, shown here as transistor 125. The emitter of the transistor 125 is biased through a resistor 126 of for example -2 V connected. The basis of the Transistor 125 is connected to ground potential. The bases the switching clock signals from the switching signal driver are supplied to the transistors 124a and 124b. Of the Transistor 124b receives signal LT while transistor 124a receives signal LT. The differential current switch 124 switches the current between transistors 124a and 124b depending on the Switching cycle signals »

709829/0813

The "Johalt-iietüwerk ^v jj also includes a differential generator current switch 127" which consists of two Tirana ist ore η 127a and 127b, the emitters of which are connected to one another and to the collector of the transistor 124b. The collector of transistor 127a is biased at +5 volts through resistor 122. Correspondingly, the collector of the transistor 127b is connected to the resistor 121 at + SV o m ', υ. The base of the transistor 127 is connected to the emitter eii, o: i output imitter follower 12h, the ba.ii.j des' PransisLors 1 <? 7b is connected to the emitter of a second t.-n i-uii, success <.- rs i; ^x j * «

ijasi3 and Kollcktoi 'des' Di-c-vni istors 12ii .iiü! through the resistor 121 vei-luinden and os the collector is directly connected to the voltage of + ■> \ f »i ^ benso are -base and collector of the .-. mitterffekturs 1 ^{/ (} j connected through the resistor 122 and it ijU der Collector connected to the voltage of + ^l j> V.

The base of the transistor 127ίι is mio the collector connected as a diode connected transistor 1 ^ 0, which causes a level shift «The emitter of the Transistor 1 ^ 0 is tlasaepotential through a resistor 1, o1 created. The collector of transistor 1 ^ ü is also one of the first with the first exit cloiaiao A Over-level output terminal pair U connected. The emitter of the transistor 1.50 connected as a diode is connected to the first terminal A via an insulating resistor 1j $ 7a Sub-level output terminal pair L connected »The emitter of the transistor 1pü is außonuim via a resistor

709829/0813

ORIGINAL INSPECTED

connected to ground potential. The collector of a second connected as a diode for level shifting Serving transistor 130 is connected to the base of the transistor 127b connected., The collector of the transistor is also connected to a second output terminal B of the Upper level output. Terminal pair U connected via a resistor 135 »The emitter of transistor 133 is connected to ground via a resistor 134 " The emitter of transistor 133 is also connected to a second output terminal B of the sub-level output terminal pair L connected through a resistor 137b.

In operation, the transistor 125 Resistor 126 formed current source supplied current to the emitters of the differential current switch, the formed by transistors 124a and 124b. If the LT signal is 1 or high, the Transistor 124a carries the current to the emitters of the differential input amplifier to that of the transistors 123a and 123b is formed ,, This is the differential amplifier activated «, The differential output current of transistors 123a and 123b is the difference between the input voltages at input terminals A and B. proportional. The differential output voltage becomes the The emitters of the cascode isolating transistors 120a and 120b are fed to positions X and Z, respectively. It should be noted that the digits X and Z are the differential current input nodes for all basic switching arrangements »The Differential input current passes through transistors 120a and 120b and is fed to resistors 121 and 122,

709829/0813

at which a corresponding differential voltage then occurs. In this operating mode, the üchalt network generates an output signal that corresponds to the differential state of the input signal. The output signal is provided by the output IC follower transistors 128 and 129. The transistors 128 and 129 cause an impedance transformation from a high to a low value and a level shift, hs output signals corresponding to one another are simultaneously supplied at different potentials. The first output signal is supplied directly from the emitters of transistors 128 and 129 via insulation resistors 132 and 135. The level of the second output signal is shifted by the voltage drop at diode-connected transistors 1JO and 133 and is available via insulation resistors 137 and 137b .

The retention function is achieved by changing the polarity of the signals LT and LT is reversed so that LTD in goes high or 1 under this condition, the current supplied by transistor 125 will be the transmitters of the differential amplifier formed by transistors 127a and 127b. The input and Output signals of the differential amplifier 127 are fed to the transistors 128 and 129 and effect positive feedback. The output signals are bistable, i.e. only stable for logic states 1 or the output signal of the differential amplifier. 127 stable,

709829/0813

when the current is switched through one or the other transistor. When an input signal is supplied, which is in the area of the middle or the reversal point of the transfer function dea differential amplifier an exponential regeneration takes place until the signal finally reaches the 1- or Has reached the O-state. The time constant of the expons— tial regeneration characteristic is called the regeneration time constant »regeneration is the Process by which the analog input signals become active be quantized into discrete digital output characteristics " The regeneration differential current school transistors 127a and 127b control the same overall control as the output stage and accordingly the same output levels appear in the switching state.

In the switching networks according to FIGS. 7 », 8, 9 and 10 are the components which have the same function as the components of the switching network according to FIG the same reference numerals as in FIG. 7 are provided. Of these switching networks, the one shown in FIG. 8 is first shown Switching network 31a explained in detail. A cascode isolation level 120 comprises two transistors 12Oa and 120b, whose ^ phases are connected to one another and with a bias voltage D. of about 4.2V are connected. The collectors of the transistors 120a and 120b are biased at about +5 volts connected via load resistors 121 and 122, respectively. The emitters of transistors 120a and 120b are with the collectors connected by transistors 123b and 123a, respectively, which have a differential current switching function. The emitters of the

709829/0813

Transistors 12Ua and 12Ub are also connected to the collectors of two transistors 140a and 140b, which have a second differential current öci. .iltfunktion have connected "The bases of the Tranaistoren 14Ca and 140b are connected to the Eingarigsklemmen A or" B connected to which a first control signal I _-. is supplied »

The emitter of transistor 120a is also connected to the Collector of a used to compensate for the signal transit time Transistor 141 connected ,, the base of the transistor 141 is applied to a bias voltage Dp during the Emitter is connected to the collector of a transistor 142a, at deta it is the harvested transistor of the differential current switch 142 acts. The emitter the differential current switching transistors 12 ^ a and 12Jb are connected to each other and to the collector of a second differential current switching transistor 142b « The emitters of the second differential current holding transistors 140a and 140b are also connected to each other and to the collector of a third transistor 142c of the third differential current switch 142 connected »

The bases of differential transistors 12 ^ a and 123b are each with one of the input terminals A or v /. B connected, which has a second input signal I,> receive.

The bases of the transistors 142a, 142b and 142c are connected to one another and to a control input LT. The emitter of the transistor 142a is connected to the first emitter of a three-emitter Tranais sector 142d. The emitters of transistors 142b and 142c are connected to the second and third emitters of transistor 142d

709829/0813

ORIGINAL INSPECTED

tied together. The first emitter of transistor 142d is connected to the collector of a transistor 125a serving as a current source. The second and the third Emitter of transistor 142d is with the collector a second or a third transistor 125b or, 125c connected, which is also used as a power source serves. The emitters of the transistors 125a to 125c serving as a current source are connected via resistors 126a to 126c each connected to a bias voltage of -2 V «The bases of the transistors 12Sa to 125c are at ground potential placed.

The Kegenerations-DifferenzH (, romschalters 127 consists of transistors 127a and 127b having their emitters connected together and to the collector of transistor 142d. The collectors of transistors 127a collar 127b are respectively connected through the Lnafcwiderstand 122 or 121 _o with the voltage of +5 V tied together"

The collector of one switched as an output emitter follower ^ Transistor 128 is connected to the voltage +5 V, while the base is connected to the voltage +5 V via the load resistor 121 is applied o The emitter of the transistor 128 is with the base of transistor 127a and above A resistor connected to ground potential. The emitter of transistor 128 is also connected via a VJiderstand 132 with a first output terminal A one Output terminal pair connected. The collector of a second transistor forming an output emitter follower 129 is also applied to +5 V while his Base is connected to +5 V via resistor 122 *

709829/0813

ORIGINAL INSPECTED

The emitter of transistor 129 is connected to the base of transistor 127b and to ground potential a resistor 134 is connected. In addition, the emitter of transistor 129 is connected to a second output terminal B connected.

The base of the transistor 142d is with the base and the emitter one for capacitance Konipensation serving transistor 143 connected. Din base of Transistor 142d is also connected to a second input terminal LT. The collector of the transistor 14 5 is dom emitter of the transistor 141 connected, the additional compensation of the signal transit time serves

The mode of operation of the switching network according to FIG. 8 will now be described with the aid of FIG. 8 also to Pig x 7a described the kind referred to in Fig. 7 ^a with a surrounded 1 power source supplies the Eingangssx ^ oltage for the transistors 140a and 123a, transistors 140a and 140b form a first and Tranaistoren 123a and 123b a second differential amplifier, Transistor 12 ^ c supplies current to the emitters of the differential amplifier formed by transistors 140a and 140b. The transistor 12 ^> b supplies the bias current to the emitters of the transistors 123a and 123b. The voltage source indicated by a ringed 3, which supplies a reference voltage, is connected between ground potential and the base of the transistor 123b.

709829/0813

ORtGlNAL INSPECTED

* Ht-

The voltage source marked with a 2 represents the second input voltage positive and negative terminals between the base of transistor 140b and the base of transistor 123b The third current source 125a is connected between the collector of transistor 123b and the collector of transistor 140a and node X are switched dead. The node Z is connected to the collector of the transistor 14 (Jb and the collector of transistor 123a connected *

FIG _o 7a also includes a table of values which the current in the node X and Z as a function of • voltage 1 to voltage 3 unn voltage 2 indicates "iienn the current sources 125c, 125b and 125a to a iJennstrom I, .. are set, switches the output current differentially from an originally 0-state when the voltage 1 changes from a value which is * less than the voltage 3 to a value which is greater than the sum of the voltages 2 and 3 »as it is the table of values shows. In the initial state, the output current X is equal to I _Q and the output current Z is equal to 2 l ^ _o In the 1 state, the output current X is equal to 2 Iq and the current in node Z is equal to I _QO. The first change in status occurs when the threshold value is exceeded where voltage 1 is equal to voltage 3. A second threshold value is exceeded when voltage 1 is equal to the sum of voltages 2 and 3 * Here the output differential current switches back to the original Q state and the current in Ki .., th X is equal to I, , and the current in the node Z is equal to 2 I., "This üifftii-enzstrom-iincteruiig takes place with a common current strength, which is 3 ^ r / 2 "

709829/08 13

i'COPY

at diener ocha tt, uii _: '; iiani) i \ inun _f , dj.e i-aucode-Iaolier tjviuii:.; toj'eii -1.ua and · |. ^; υί>, the.-ideratlinde Ί · ~ 'Ί and 1 «\ /, which form a Ίΐΐίϊ ^; ιυμ; ϋ - << ^: Ϊ11, i; · t'ol ^ er forming V.raiu; itj U ,. 'tMi 1 .-' 8 mi .. L: ') unu die den iie ^ -euerat, ion £ il) iff erenzvej ·.,;, ;; rkwr t> l],! ends Vruns i: i lio / eu 1. · ■ _ '', '·' ι and 'h-7b in tSenau. ::; r fjleit ;; u; i! wines like like corresponding components in iei .. J ^ hai; .- !. <;;,;; werk όό with an ijirif ^ an ^ * Jer i-mi tter doü '!' far · :! lj t, n <· α '\. C.'a can also alti i.no!, E: i X uua der- ί-πη. t, t.er: ii ;; i '.'raniiiu tc; · :; '1-Ob alrj knot IJ ready; inei, turn ,, i) in i,;., Dt,!, E iviii.'ic:> il ii:;:. ■>; of transistors 1, '7 ^a "ni-.i I' ⁷ Ij ₁ dit; iü ii, (* ι ικ ■ ?: i ^ r verirun ι ·.: η: iind, ^ iinnen old; node .. \>t-;t; i chnel, be _o Pie> ...: [:. · ι Lur.f ': i ~ ajiurdnun ^ cn' ULeüer lci.len o>: i; .- i ι u-iie ι. ¹ /:'./·;ri-e,; j dit below the ».note :: a, 2- nnu w arifUroi ^ iri tt ¹ : · i.> -: iial tui;>':; - tt: ile, sine! auuL ^ aii ^ iiiia: '. 1 / · ;: ^ Jwh ^ lt-iiu!.;.'.; » ^{;; i} k i.:it ο: _; _λ (·! η ijirifjan ^ can be converted into a Ji-.::a ι I.-Je ;;., v; erK tiit:; * ■■: Ί. - · τ i. _f , "n, ^f ·: i v \ ejMen, iniera di (. ^v ait;!. · i: .im:;,:! i! ^, ila de:> ociial t — l'iet ^ V / e! 'KfLi;'. la uar ^ e :; te i ! J. tc; Jo ia.LlA.ii, ';;: u H);''ii i i ^{^;;} liurch the unte.riial L, a <ji · Knute ,, A _t:.!'. and .. ia der ^ :: r.:!~ tuiu "(hjü Liclial L-» ie ü / .wt.'i'icfiü; ■ '>u; ^j . i'r; e :; te ι ι t ,. n! .Awiiiltiit - '. ■ --Share erüt; t :: t wt ^' den, - ^ in '.ve ι Lerer bnte i - :, ctiied ü.viiicuei: den ochal t-Iie tziverlien ~ ö '\ and i;> bt :: ii; uhi durin, that only rin single Au: i _{ r: ijn, "uses \ ,; i ril and ii'-iin e i.; üf · ;! iclik -it: 'ur one i'e ^: elver:; i; niebun ^ · before ^ eiint-eii i:; t ^ the ünter-; ic.-nit.: do: '.'. '. den ochai t-ü «. · ι. /.,. Erl; en be / .ii ^ lioh der v '>; : - :;>: hiebuiii ^f ; de: j ii.iuifj'an ^ i.ipe ^ jej.; liatien no aui die ^ ruiidlef'j-enMi-i »rii'Kun ^ riJi '.-' iiijti der Jena j üronuny, from ^ e ^ on, daii different Λικϊ ^ ϋϋ; · ::; - peyeL zui" VtJrTiU ¹ JUIu; ^ e'ijtellt v.erdfn, \. <■■ they; "iir dit: füliijenden ijO ^ ik-.jc.iiaJ tunken iiiiiuiLi _r ; i; \ m ■ r ■■ ·; [,,: ii: \ -. n Λ \ ν. *. \ α ii.Uij ₍ ; -inge ajii ^ :. ^: jcUJ oü: jen β i rui _o

709829/0813

CXDPY BAD ORIOINAt

• Λ *

As i * ¹ ± t; - β further shows, the translators 12 ^ a ₁ 125b and 12 ^ c with their resistors 126a, 126b ui \ ; 126c three identical, balanced current sources, the output current of which is set to -2 V on Iq due to the bias voltage Tranaistors 127a and 127b is connected. When the signal LT is in the high or 1 state, the transistors 142a, 142b and 14: 'c are conductive and it leads, juder of them, an otroin I _{() to} the limit of the preceding circuit Transistor 142d is completely blocked and there is no otroia fed to the generation differential amplifier. The transistor 14p serves to suppress overcoupling of the ochaltsj-Miuiungspulses or zxx reduce, which as a result of the collector-base Ka When the input signal LT rises and the input signal LT falls, the resulting current through the two capacitor iiasis capacitances of the transistors 142a and 14 ^ is essentially the same and increases due to the equality of the delays in the rise time at the emitter of transistor 141. This will elimüniert a reason for Üpannungoverschiebungen that may of Üchalt-IJetzwtvrkeg otherwise occur in this structure, "operates as a switching power source in the same manner as the üchaltstromquelle 125c in FIG _o 7" ^ ie upper and lower differential amplifier of Fig The transistor 141st 7 and 8 work in the same way * The switching network 3'ia generates a differential current output signal whose Ui f reference current change I ,, carries around a common mean value of 3 - ^ r / '''° ^e «

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ORIGINAL INSPECTED

The switching network 32a shown in Fig. 9 is designed in the same way as the switching network 31 & i has however, additional means for level shifting the ivu output signal '. Therefore only need here treated additional components for the leech displacement zti become «The basis of the residual current switch 127 »is one with the collector as a diode switched transistor 130 connected. The emitter of transistor 130 is connected to Ilassepotential via a resistor 131. The emitter of the Transistor 130 is also connected to a first output terminal A of a differential output terminal pair. The transistor 130 connected as a diode causes a Level shift, for the logic circuits is required, which is connected to the üchalt network 132a are connected "

The base of the transistor 127b is with the collector of a diode-connected transistor «133. The emitter of transistor 133 is through a resistor 154 with ground potential and a resistor 137 connected to a second output terminal B.

The mode of operation of the circuit arrangement according to FIG. 9 is identical to that of the circuit arrangement according to FIG. identical and therefore need not be described in detail.

The switch network 30 shown in FIG. 10 is correct with the switching network 33, except for a few additional circuit parts, which are detailed below to be discribed.

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The emitter of a transistor connected as a diode is connected to the collector of a third air; Diode switched transistor 145 connected to produce a level shift. The emitter of transistor 145 is connected to the collector of a transistor 146, which forms a current source. The emitter of transistor 146 is connected to a bias voltage of -? Via a resistor 147. V applied ο The base of the transistor 146 is connected to ground potential. The emitter of the transistor 145 is connected to a first output terminal A of a differential output terminal pair L »

The emitter of a second, air. Diode-knulteten -ramnstors 1 ^ 3 is with the collector of a fourth as a diode switched transistor 14H vürbunden. The emitter of the Transistor 148 is connected to the Kojlektor of a transistor 149, which forms a second power source o the The emitter of transistor 149 is connected to a bias voltage of -2 V through a resistor. The base of the Transistor 149 int! »Laseepotential applied. The collector this transistor 149 is connected via a resistor to a second output Ii of the differential output terminal »· pair L connected

The Wirlaingsweise of the ochalt Uetzwerkea according to Fig. 10 is the same as that of the ochalt networks according to the Fig. 7, 7a and 8 and therefore does not need to be detailed more to be explained.

The delay element or delay element shown in FIG Contains two differential current switching transistors 155 »and 155b» their emitter with each other and with deia collector of an ala

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ORIGINAL INSPECTED

Current source acting transistor 156 are connected «The emitter of transistor 156 is connected via a resistor 157 ^with a bias voltage of, for example -2 V · The base electrode is connected to ground potential. The collectors of the transistors 155a and 155b are each connected to a voltage of +5 V via a resistor 158 and 159, respectively. The resistor 150 is a balanced resistor to compensate for the power losses in the transistors 155 and 155b. The bases of the transistors 155 & 155b are each connected to an input terminal A and B, respectively. * The collector of the transistor 155b is connected to the base of a transistor 160 connected as an emitter follower. The collector of transistor 160 is connected to +5 V, while the emitter is connected to an output terminal.

In operation, the timer 40 has no logical function, but only introduces a signal delay, which is the runtime of the signal in the logic elements corresponds to the second stage 13 of the logic network. The differential input signal is fed to the two differential transistors 155a and 155b. if the input of transistor 155a is more positive than the input of transistor 155b, flows there is no current through transistor 155b and there is no voltage drop across resistor 159. Consequently In this state, the transistor 160 supplies an output signal which is characteristic of a logic 1. is on the other hand, the input signal of the transistor 155b is more positive, the resistor 159 is traversed by current, so that a voltage drop occurs at this resistor © The transistor 160 then supplies an output signal logical 0.

709829/0813 ./.

The AND gate 4-1 shown in detail in FIG has an upper level differential atromachometer 65, the two transistors 165a and 165t), whose Emitters are connected to each other. The bases of transistors 165 & and 165b are positive or negative input cycle of an over-level input terminal pair U connected. The collectors of transistors 165 & 165b are each via a resistor 166 or 16? applied to a voltage of +5 V.

A sub-level differential current switch 168 comprises two transistors 168a and 168b, the emitters of which are connected to one another. The bases of transistors 168a and 168b are connected to the negative and positive input terminal of a sub-level output terminal pair L, respectively. The collector of trannistor 168a is connected to +5 volts through resistor 166. The collector of the second transistor 168b is connected to the emitters of the transistors 165a and 165b. The emitters of transistors 168a and 168b are 'connected to the collectors of a current source transistor constituting 16'), the emitter of the transistor 169 is applied through a resistor 170 to a voltage of -2 V, while the base is connected to ground potential _u

The base of a transistor 171, which is an output emitter follower is applied to the voltage of +5 V through resistor 166. The collector of this The transistor is directly connected to this voltage. The emitter of transistor 1? 1 i;> t with a Output terminal connected.

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* sr *

During operation, the AND element 41 then generates MI> B output bit (2) the four-bit quantizer according to the invention, by using the output signals of the switching networks 30 and 33 linked according to the logical relationship 33Le30U » The transistor 169 generates the switching current that is passed through the transistor 168a, 168b, 165a and 165b existing logical cascode tree. A true signal that is fed to the positive input terminal causes transistor 168b to conduct current and transistor 168a to turn off. Likewise flows depending on the input signals supplied Current through either transistor 165a or transistor 165b. -line applied to the transit author 165b logic 1 and one applied to transistor 165a logic 0 causes transistor 165b Stroia through the resistor 16? pulls. As a result, will the transistor 165 'blocked, with the result that the output of transistor 171 is a logical is equivalent to. However, when a signal corresponding to a logic 1 is fed to the transistor 165a and a A signal corresponding to logic 0 is fed to transistor 165b, current flows through transistor 165a and creates a voltage drop at Vüderstand 166, which has an output on transistor 171 in the form of a results in a logical 0.

for a logic 1 characteristic signal at transistor 168a and one characteristic for a logic 0 Signal on transistor 168b cause transistor 168a to draw current through resistor 166, which results in a logical 0 as the output signal «

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Therefore, the transistor 17I always provides an output signal in the logic 0 state when current flows through transistor 165a or 168a.

As shown in FIG. 13, the illustrated therein Y-member 42a comprises a first upper level differential current switch 175 on, the two transistors 175 ^a and 175b includes whose emitters are connected together. A second upper level differential current switch 176 also comprises two transistors 176a and 176b, the emitters of which are connected to one another. The collectors of transistors 175a and 176a are connected to +5 V through a resistor 177. The collector electrodes of transistors I75b and 176b are connected to +5 V through a resistor.

A transistor 179 forms an output emitter follower. Its base is connected to the collectors of the transistors I75 ^a and 176a. The collector of transistor 179 is connected to +5 V while the emitter is connected to an output terminal.

The liaeen of transistors 175b and 176a that go to the two upper level differential current switches 175 and 176 are connected to one another and to the positive Input terminal of an upper level difference input terminal pair U connected. The bases of transistors 175a and 176b are also connected together and to the negative input terminal of the pair of upper level input terminals connected.

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• SV-

Under level differential current switch 180 comprises two

Transistors 180a and 180b, the emitters of which are connected to each other. The collector of transistor 180a iet with the emitters of transistors 175a and 1? 5 "b connected «The collector of transistor 180b is connected to the emitters of transistors 176a and 176b. The base of transistor 180b is connected to the positive input terminal of a pair of sub-level input terminals tied together. The Bn sis de3 transistor 180a is connected to the negative terminal of the lower level input terminal pair L tied together.

A Y-level Üifferenzstromschalter 181 comprises two transistors 181a and 181b, whose emitters are connected with each other _e The collector of transistor 181a is connected to the base of the emitter follower Transi3tors 179 · The collector of transistor 181b is connected to the emitters of the transistors of Unterpegel- Differential current switch 180 connected. The base of transistor 181a is connected to the positive terminal of a T-level ^ input terminal pair. The base of the transistor 181b is connected to the negative input terminal of the Y-level input terminal pair. The emitters of the transistors 181a and 181b are connected to the collector of a transistor 182 serving as a current source. The emitter of transistor 182 is connected to a voltage of -2 V via a series resistor 183, while the base is connected to Maaaepotential.

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The Y element 42a is a three-level cascode circuit, that of current switching emitter followers comprehensive family of logic circuits. The Y element 42a performs the logical function (U + L) .Y off. When transistor 181a turns on for a logic 1 characteristic signal and the transistor 181b a characteristic of a logic 0 signal Signal is supplied, the current supplied by the transistor 182 forming a current source flows through the resistor 177. The voltage drop across the resistor causes transistor 179 to provide an output signal characteristic of a logic.

When the signal for a logical 0 is fed to the transistor 181b and the signal for a logical 0 is fed to the transistor 181a, the current supplied by the transistor 182 as a current source flows through the transistor 181b _t while the transistor 181a is blocked. The current then flows either through transistor 180a or transistor 180b, depending on which input signals are present at these transistors. A signal for a logic Λ at transistor 180b and a signal for a logic 0 at transistor 180a cause transistor 180b to Current flows to transistors 176a and 176b. When a signal for a logic 1 is applied to transistor 176b, this transistor conducts current through resistor 178, which means that transistor 179 provides an output signal which is characteristic of a logic 1. However, when the signal for a logic 0 is fed to the transistor 176b, the current flows through the transistor 176a and produces a voltage drop across the resistor 177 »so that the output signal corresponds to a logic 0.

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The operation of the upper level differential current switch and the medium level differential current switch correspond that of a classic lixclusiv-ODliU limb and therefore does not need to be described in detail.

How from ^ ig. 14, a Kxclusiv-ODüR element has a first over-level differential current switch which comprises two transistors 185a and 185b, the Kmitter of which are connected to one another. The second over-level differential current switch 186 also includes two transistors 186a and 186b, the emitters of which are connected to one another. The collectors of transistors 185a and 186a are connected through a resistor 18? connected to +5 ^v . The collectors of transistors 185b and 186b are connected to +5 volts through resistor 188.

The base of an emitter follower transistor 189 is across the resistor 188 connected to +5 ^. The collector de3 transistor 189 is directly connected to +5 V, while the emitter is connected to an output terminal is.

The bases of transistors 185b and 186a are with each other and with the positive Kingangiiklemiae of an upper level Kingangsklemiaenpaare U connected. The bases of transistors 185a and 186b are connected to the negative Ising terminal of the upper level input terminal pair.

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A sub-level differential current switch 190 includes two Transistors 190a and 190b, the emitters of which are connected to each other are connected. The collector of transistor 190a is connected to the emitters of the first upper level differential current switch 185 connected. The collector of the transistor 190b is connected to the emitters of the second upper level differential current switch 186 connected. The base of transistor 190a is connected to the positive input terminal of a pair of sub-level input terminals L connected. The base of the transistor 190b is connected to the negative input terminal of the lower level input terminal pair.

A current source comprises a transistor 191 »whose collector with the emitters of the Unterpogel differential current switch 190 is connected. The emitter of the transistor 191 is connected through a resistor 192 a bias voltage of -2 V, while the base is connected to ground potential.

The exclusive-OR gate 4 $ a is one Two-itegel cascode circuit of the Stromscholt emitter follower comprehensive family of logic circuits. The first level is a differential current switch in the form of dee off the transistors 190a and 190b existing emitter follower. An input signal applied to transistor 190a, which is characteristic of a logical 1, switches this transistor through and switches the Transistor 190b. Current source 191 then causes current to flow through transistor 190a and through one of the two upper level transistors 18 ^ a or 185b,

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Depending on which input signals are fed to these transistors, an input signal which is characteristic of a logic 1 and which is fed to transistor 185a “switches this transistor on and switches off transistor 185b”. Therefore the current then flows through resistor 18? and the output emitter follower 189 generates a signal which is characteristic of a logic 1. If, however, a signal for a logical Λ is fed to transistor 185h, this transistor is switched on and transistor 185a is blocked. The current then flows through resistor 188 and causes a voltage drop, with the result that transistor 189 provides the output signal for a logic 0. Accordingly, the output signal is a logic 0 when input signals characteristic of a logic 1 are supplied to both the transistor 190a and the transistor 185b.

If the translator 190b receives the signal for a logical 1 and throw the signal for a logic 0 fed to the transistor 190a, the transistor 190a is blocked and The transistor 190b carries the current supplied by the transistor 191. The transistor 186a receives the signal for a logical 1 and the transistor 186b the signal

for a logic 0, the transistor 186a conducts current through the resistor 18? and it delivers Emitter follower 189 has an output signal in the 1 state. if however, the logic 1 signal to transistor 186b and the logic 0 signal to transistor 186a is supplied, transistor 186b conducts current

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2701Θ75

the resistor 188 and it supplies the emitter follower 189 the output signal for a logical 0. Here too is again it can be seen that the output signal corresponds to a logic 0 if the U and L terminal pairs the same signals are supplied.

Referring now to Figure 15, the latch and level shifting network 46a will now be discussed in greater detail. The cathode of a Zener diode 200 used for level shifting is connected to an I input terminal I, while the anode is connected to the collector of a level shifting current source, which is illustrated here as transit port 201. The base of transistor 201 is connected to a biasing network 49, while the emitter is' ⁵ is connected via a resistor 2O ₁ -5.2 V.

The base of a Kmitterfolder transistor 205 is with connected to the anode of the zener diode 200. The collector of transistor 203 is connected to ground potential, while the emitter is -5 »2 V through a resistor 204 connected is. Kin second central follower transistor 205 also has a collector connected to ground potential, while its base is connected to a bias network connected. The emitter of transistor 205 is Connected via a resistor 206 bit -5.2 V.

A differential current switch 207 comprises two transistors 207a and 207b. The bases of transistors 207a and 20b are each connected to the emitter of transistor 205 and. The collectors of transistors 207a and 207b are each connected to the Ground potential connected.

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second differential current switch 210 comprises two transistor transistors 210a and 210b, the emitters of which are connected to one another connected aind. The collector of the tranaiatora 210a iat connected to the collector dea Tranaiatora 207a. The collector of the transformer 210b is connected to the collector of the transformer 207b. The differential current switch 210 provides the positive feedback for the memory portion of the present circuitry.

A differentially switchable current source 21 $ includes two transistors 213a and 213b whose emitters are connected to each other and connected to -5 »2 V through a resistor 214. The collector of transistor 213a iat connected to the emitters of the differential current switch 207. The collector dea Transiatora 213b is with the emitter electrodes of the differential atom switch 210 are connected. The base of transistor 213b is with a first control signal terminal LT connected. The base of transistor 213a is connected to a second Control signal source LT? tied together.

The base of the transistor 210a is through a resistor 211 connected to -5f2 V. The emitter of the transistor 21Ob is -5.2 V across a resistor 212 tied together.

A first output emitter follower is used here by a Transistor 215 is formed with a triple emitter. The collector of this transistor 215 is immediate connected to ground and the base via a resistor 209 to ground potential. The first emitter of the

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Transistor 215 is connected to an output terminal OUT 1. The second emitter is with a second Output OUT 2 connected. The third emitter of transistor 215 is connected to the base of transistor 210a tied together. Ea becomes a transistor with a triple emitter here used so that the individual output terminals OUT 1 and OUT 2 can be individually combined with other output terminals can be connected in the form of a wired OR link to connect several Simplify quantifiers.

A second output emitter follower is formed here by a translator 216, which is also a triple emitter having. The collector of this Transiatora is directly and the base connected to ground potential via resistor 208. The first emitter of the transformer 216 is connected to the first terminal OUT 1 of a second output terminal pair. The second emitter of the Transistor 216 is connected to the second output terminal OUT of the second output terminal pair. The third Emitter is connected to the base of the transistor 210b

In operation, the latch shown in FIG. and level shift network 46a in level shifted output signal by using a reference voltage which is the middle of the difference between those characteristic of a logical 1 and a logical 0 Forms output signals of the logical network. The zener diode 200 shifts the level dea arriving logical signal. The emitter follower transistor 203 buffers

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the signal between diode 200 and the base of transistor 207b. The reference level of the transistor 207a is set by a reference voltage H across the transistor 1 is applied, the base of transistor 203 is about 200 mV more positive than the base of transistor 205. Therefore, the base of transistor 207b will conduct a switching current through transistor 213a when the signal for logic 1 is applied to the base of transistor 213a will. The emitter follower transistor 216 then in turn supplies the output signal characteristic of a logical 1,

When the state for a logic 0 is applied to the Zener diode, the transistor 2O ^r7 a conducts current through the resistor 208 and the transistor 213 &, if the signal for a logic 1 is applied to the base of this transistor. The emitter follower 215 therefore generates the signal for a logical 1.

The input signals LT and LT, which are provided by the driver 48 are supplied, generate a temperature-compensated Voltage on resistor 214 to maintain a bias current, which is largely independent of the tempex ^ ature. When the signal LT is greater than the signal LT, causes the transistor 213b of the differential current switch one positive feedback through transistor 210a, emitter follower 216, transistor 210b, emitter follower 215 and back to transistor 210a. This positive

709829/0813

ORIGINAL INSPECTED

Feedback causes a bistable switching process that allows the output stage to be used as a data storage register to use"

Accordingly, the diode 200 and the transistor 213a supplied signals which are each characteristic of a logic 1, the result that the emitter follower 216 provides an output signal characteristic of a logic 1 and the emitter follower ? AJ> an output signal characteristic of a logic 0 . If the diode 200 is supplied with an input signal characteristic of a logic 0 and the transistor 213 is supplied with an input signal characteristic of a logic 1, the transistors 215 and 216 supply output signals characteristic of a logic 1 or "0" 213b, which is characteristic of a logical 1, brings the output memory network into the switching state in which it stores the output states that were previously entered. If the control signal applied to transistor 213a rises above the signal applied to transistor 213b, the output memory network is returned to the state in which signal reception is possible until the next switchover to the memory state occurs.

As shown in FIG. 16, the header network 47 has a Reference current source, which is shown here as transistor 220, its base at ground potential and its

709829/0813

Emitter is connected to -2 V through a resistor 221. The collector is on via a resistor 222 +5 V connected. One used for level shifting The current source is formed here by a transistor 223, the emitter of which is connected to -5.2 V via a resistor 224 is. The base is connected to an input terminal and receives a bias from the bias network 49. The collector of transistor 223 is connected to the anode of a Zener diode which is used for level shifting 225 and connected to an output terminal

The collector-basia route of one as an output-emitter follower Serving transistor 226 is connected in parallel with resistor 222. The colector is on +5 V connected. The emitter of resistor 226 is connected to the cathode of diode 225.

In operation, the bias network 47 generates one logic level which lies in the middle between the logic levels of all logic elements 40, 41, 42 and 43. This mean reference level is then set in the same way as by the level shifters in the output stages shifted and forms a common bias that is used to compensate for fluctuations that caused by changes in the power supply and temperature fluctuations. This compensation takes place through the use of precisely matched components such as zener diodes and transistors. The logic reference voltage is generated by drawing a current from the Transistor 220 and resistor 221 existing current source

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is generated, is passed through a resistor 222, which is half as large as the load resistance in the logic elements. Hence, the resistance creates a voltage that is half the size of the voltage change, which normally occurs in the logic gates · The transistor 226 then serves to control this Shifting and isolating reference levels, as was also the case in each of the logic elements. The Zener diode 225 is used to control the voltage at the emitter of transistor 226 to a fourth that is midway between the level shifted Output signals of the logic.

The driver 48 for the clock signals to be fed to the output stages will now be explained in more detail with reference to FIG. In this driver, a resistor 2) is 0 connected between +5 V and the collector and base of a first transistor 231 connected as a diode. The emitter of this transistor 231 has a collector and the base of a second transistor 232, also connected as a diode. The emitter of the Transitsors 232 is connected to the cathode for bias compensation serving Zener diode 233 connected. The anode of the Zener diode 233 is connected to the collector and base of a third one, connected as a diode Transistor 234 connected. The Kmitter dea Transietors 234 is connected to -5.2 volts through resistor 235 connected.

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A Kmitterfolger voltage generator, here as Transistor 236 shown has one at +5 connected collector and a basin connected to the base and collector of transistor 231

Differential truce switch 237 exists; aua two 'i'ransistoren 237a and 237b having their emitters connected to each other sindο The collectors of transistors 237 ^a and 237b are connected to the emitter of the Tranaistors 236 connected via a resistor R 2 and $ 239 "The base of transistor 237 is connected to a -input terminal, which it: iiuiigangs-iichalttaktsignal OLC receives from an external clock iJetzwerk 50 (* 'ig · 1). The base of the transistor 237b is connected to an input terminal which receives the clock signal OLC from the clock network.

The emitters of transistors 237a and 237b are connected to the Collector of a power source connected, shown here as transistor 24-0 13t. The emitter of the transistor 24-0 is connected to -5 »2 V via a resistor 241, whereas the base is connected to the collector and base of transistor 234 int.

ώϊη serving as the first output transistor The base of 242 is connected to the collector of the transistor 237, and the collector is connected to +5 V connected «The emitter of transistor 242 is connected to the cathode one for shifting the output level The anode of the diode 243 is connected to -5 »2 V via a resistor 244.

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ORIGINAL INSPECTED

The anode is also connected to a failure cycle, which the control signal LT to the output networks 46a to 46e supplies.

A transistor 245 serving as a second output emitter follower has its base connected to the collector of transistor 237b and its collector connected to +5 ^v . The emitter is connected to the cathode of a second Zener diode 246, which is also used for level shifting. "The anode of the diode 246 is connected to -5.2 V via a resistor 247." The anode of the diode 246 is also connected to an output terminal which provides the output a -Networks that supply clock signals LT «

The driver shown in Fig. 17 has the puncture, the logic level of the input signals fed to it,

as they are supplied by a common emitter-coupled logic and which, for example, at -0.9 and -1.7 V are to be converted into the logic level, which is at the LT and LT input terminals of the output stages are needed »so that they are also used for level shifting and at the same time used for signal storage output stages even under the most unfavorable conditions temperature and power supply are in the same range, this driver must provide very accurate voltage levels to bias the current in the output stages to the correct value and thereby determine the final output voltages. Of the The driver therefore supplies voltage levels which essentially temper the changes in current in the output stages. make it independent of the course.

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• Η

The output clock signals OLC and OLG are fed from the external source at the logic levels as they are supplied by an emitter-coupled standard logic to the bases of the transistors 237u and 237b. Therefore, if the OLC signal is more positive than the OLG signal is in the 1-state, the transistor 237 ^a conductive and the ütrom supplied by the Tranaistor 240 and the resistor 241 flow through the Viiiderstand 236, so that at the isaais of the transistor 242 a U or a low level arises. Correspondingly, if the signal OLC is in the state of logic 1, that is to say more positive than the signal OLC, the transistor 237b becomes conductive and causes a current to flow through the resistor 239, whereby the base of the transistor 24 | comes to a lower level · The active preamble level in the misgangn stages is set to whom the LT signals are in the 1 state or at the highest level «Accordingly, the LT output signals are in the correspondingly high state«

Output signals LT and LT are generated by diodes 243 and 246, transistors 236, 242 and ? A $, and resistors 238 and 239. The voltage at the base of transistor 236 is the final check of the voltage of the output signals LT and LT when they are in the 1 state. The base voltage is set by an interconnection of transistors 231, 232, 234, the Zener diode 233 and the resistors 231 and 235. Therefore, the voltage of signal LT is substantially equal to the voltage across resistor 235 plus

709829/0813

ORIGINAL INSPECTED

the voltage at transistor 234, which is connected as a diode « When the output signal LT that the output stage (Fig. 15) is supplied, is in the high state, there is another voltage drop across the base ^ middle junction of the transistor 213b is present, and as a result, the voltage across resistor 214 in the output stage is dem The voltage drop across the resistor 235 is equivalent to «Is on the other hand the signal OLC in the 1 state, then the output signal LT is in the high state and the transistor turns it on 213a the voltage across resistor 214 to the same Value that is present at resistor 235 of the driver stage. The clock signal driver thus controls the current flowing through the output stage and thus the logic Level of the output signals of the quantizer. By applying signal tracking and properties Adjusted energy diodes and transistors the temperature sensitivity of the logic level of the output signals is reduced to a minimum. The resistances 247 and 244 represent the transistors 245 and 246 bias currents flowing therethrough. It should also be noted that the transistor 240 flowing through Current that controls the change in voltages LT and EF, also from the voltage drop across resistor 235 and the Voltage drop across the resistor 234 connected as a diode is determined.

The bias network 49 shown in Fig. 18 has a first transistor 250 whose collector is on Maasepotential is connected. The base is with that one end of a resistor 251 connected, the second

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-bilde is also connected to ground potential. The collector of a second transistor 252 is connected to the first end of the resistor 251 »The base of this transistor is connected to the emitter of the transistor 250» The emitter of the transistor 252 is connected via a resistor 253 to the collector of a transistor connected as a diode. The emitter of the transistor <^; 54 is connected to -5f2 V «

The collector of a transistor 255 connected as a diode is connected to the base of transistor 252 « The emitter is connected to the collector of the transistor through a resistor 256 »The emitter of the Transistor 255 is also provided with a tied together"

The operation of the leader network 49 is the same as that of the leader network according to ϊϊβ. 16 and therefore does not need to be explained in more detail here to become «The difference between the two header networks is that the output of the Network 49 is shifted in level compared to the output of the network «

19 illustrates an analog-to-digital converter, which has a five-digit binary output signal (5 bits) and consists of two quantizers 10a and 10b. An input reference network consists of serially connected Resistors 305 to 509 that are positive between and negative reference voltages are applied. Input amplifier 500 to 304 connect the connection points of the

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ORIGINAL fNSPECTED

Resistors with the negative ^ input terminals of the Quantizers 10a and 10b. The input terminals of the quantizers 10a and 10b for the analog signal are connected to each other and receive the same input signal. The output terminals of the quantinator 10a, apart from the output terminal for the position bit, there are also the corresponding output terminals of the quantizer 10b connected. The position bit output terminal of the quantizer 10b provides the output signal for the most significant bit. So it becomes a five-bit output signal formed by two quantizers "

Fig. 20 illustrates the construction of a six-bit converter. In this case six quantizers A, B, C and D are connected together in parallel and received a common analog input signal. The four last digit bits of the four quantizers are closed wired with an OR link and form the output signal characteristic of the last-digit bit (LSB) of the converter. The two most significant bits are supplied by the position bit output terminals of quantizers A, B, and G. To this end, the true output terminal of the position bit of quantizer A with one input and the false output terminal of the position bit of the quantizer B with the second input connected by an AND element. The signal A.B is connected to the true output terminal of the position bit of the quantizer C. wired to an OR link and then forms bit 2 of the second highest position. The true output terminal of the position bit of the quantizer B provides the most significant bit. Timers lead a single-stage

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Delay a, d ^ ait the signals for the six Output table of a subsequent circuit to the same Time to be offered.

The following table 2 illustrates several analog-to-digital converters, which is realized using several v ^ uant is at ores and a suitable decoding logic can be.

Table 2

Converter with quantizers connected in parallel

Number Number of decoding of the OR wiring of the bits of the highest digit of the last digit tisatoren Bits Bits

4th 1 no university in binary there 5 2 no university in binary there 6th 2 bit university in binary there 7th 8th 3 bit there 8th 16 4 bit there

It can be seen from the above that the invention creates a high-speed quantizer which, as an analog-to-digital converter, supplies a four-bit output signal and can be interconnected with other such quantizers if output signals with more than four bits are required . The quantizer uses 2 ^ differential amplifiers, which are coupled with 2 ^ """+ 1 switching networks and 2Γ + Λ logic elements

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Analog-digital converters require έ comparative switching networks and logic elements in order to achieve the same resolution at the same speed. Here, N is the number of bits in the output signal.

Although the invention has been described and explained with reference to a specific embodiment, understand it is clear that the invention is not limited to the illustrated embodiment, but can be modified in many respects in a manner which is obvious to the person skilled in the art.

709829/0813

Claims (7)

-74 - Claims / iJ analog-digital converter, characterized in that the analog signal receiving input circuits (21) 2 amplifiers (24) are coupled, each having a threshold value and deliver an output signal when the signal supplied by the ■ input circuits exceeds the threshold value , Dali with the verse turner (24) a switching network (.12) is coupled, which supplies ΊΤ + 1 output signals, each of which represents a bit of a cyclic code that is dependent on the threshold values of the amplifier (24) being exceeded, and that with a logic (i; j) is coupled to the switching network (12) which decodes the 2 +1 output signals of the switching network into N output signals which form an N-digit binary number. 2. Analog-digital converter according to claim 1, characterized in that the logic (13) one with the Switching Hetzwerk (12) coupled device (40) for forming a position bit. 3 «analog-digital converter according to claim 1 or 2, characterized in that the input circuits (20, 21) 2 first and second series resistors (22a to 22p and 23a to 23p) comprise which the analog input signal or a reference signal received and connected to each of the 2 amplifiers (24-). 709829/0813 ORIGINAL INSPECTED -ρ- 'K- 4 _β analog-to-digital converter according to one of the preceding claims, characterized in that current compensators (25) are coupled to the amplifiers (24), which respond to the input currents fed to the amplifiers (24) and supply an oppositely equal üfcrom, whereby they cancel the input currents and enable the use of signal sources with high internal resistance. 5 · Analog-digital converter according to one of the preceding Claims, characterized in that the switching network (12) cascode circuits (31, 32) iait comprises an upper and a lower section which are responsive to two different input signals and provide a first output signal when the first of the two input signals the upper and the lower Section or the second input signal to the upper one Section is fed, and a second output signal when the second input signal is the lower Section is fed » 6 · Analog-digital converter according to one of the preceding Claims, characterized in that the logic (13) has three cascode links, each with three stages (42) includes those with the üchalt network (12) are coupled and one of which a supplies a first output bit that with the switch network (12) and the three-stage cascode logic elements (42) four exclusive-OR elements (43) coupled which provide a second and a third output bit and that with the switching network (12) AND gate (41) is coupled, which supplies a fourth output bit. 709829/0813 _Jm 7. Analog-digital converter according to one of the preceding claims, characterized in that output circuits (14-) are coupled to the logic (15) which supply the N output signals for the duration of a certain time 7 09829/0813