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DE2661099C2 - - Google Patents

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Publication number
DE2661099C2
DE2661099C2 DE2661099A DE2661099A DE2661099C2 DE 2661099 C2 DE2661099 C2 DE 2661099C2 DE 2661099 A DE2661099 A DE 2661099A DE 2661099 A DE2661099 A DE 2661099A DE 2661099 C2 DE2661099 C2 DE 2661099C2
Authority
DE
Germany
Prior art keywords
conductivity type
layer
silicon nitride
source
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2661099A
Other languages
English (en)
Inventor
Gregorio Saratoga Calif. Us Spadea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE2661099C2 publication Critical patent/DE2661099C2/de
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

Die Erfindung betrifft ein Verfahren zu Herstellung einer CMOS-Halbleitervorrichtung, bei dem die Ver­ fahrensschritte a) bis e) und g) bis k) des Patentan­ spruches durchgeführt werden. Ein solches Verfahren mit im Prinzip ähnlichen Verfahrensschritten ist aus "IBM Technical Disclosure Bulletin", Band 16, Nr. 9, Februar 1974, Seien 2876 und 2877, bekannt.
Aus "IBM Technical Disclosure Bulletin", Band 14, Nr. 5, Oktober 1971, Seiten 1568 und 1569, ist es weiter be­ kannt, bei der Herstellung von MOS-Transistoren das Gate-Oxid in einem frühen Verfahrensschritt aufzu­ bringen und anschließend unverändert zu lassen. Ferner sind aus dieser Literaturstelle auch die Verfahrensschritte i) bis m) bekannt.
Der Erfindung liegt die Aufgabe zugrunde, ein Herstel­ lungsverfahren für CMOS-Schaltungsbausteine mit sich selbst ausrichtenden Gate-Elektroden und mit vermin­ dertem Flächenbedarf zu schaffen, wobei gleichzeitig gegenüber herkömmlichen Herstellungsverfahren Einspa­ rungen erzielt werden.
Diese Aufgabe wird durch die im Patentanspruch gekenn­ zeichneten Merkmale gelöst.
Im folgenden wird die Erfindung beispielsweise und anhand der Zeichnungen ausführlich er­ läutert.
Die Fig. 1-4 zeigen Schnittansichten zur Darstellung der aufeinanderfolgenden Schritte bei der Herstel­ lung einer CMOS-Halbleitervorrichtung mit selbstaus­ richtenden Gate-Elektroden.
Fig. 1 zeigt den ersten Schritt, der in der Ausbil­ dung einer dünnen Gate-Elektroden-Oxidschicht 15 be­ steht, der die Aufbringung einer Siliziumnitridschicht 16 folgt. Mittels der ersten Maskierung werden die Siliziumnitridschicht 16 und die Oxidschicht 15 in allen denjenigen Gebieten entfernt, wo keine Diffu­ sion bis zum Ende des Herstellungsverfahrens ge­ wünscht wird, und daher bleiben diese Schichten dort vorhanden, wo Gebiete von Source-, Drain- und Gate- Elektroden, sowie Sperr- oder Isolationsringe ge­ wünscht werden (siehe Fig. 1).
Während des zweiten Maskierungsschrittes wird eine Negativ-Photoresistschicht 51 aufgebracht und derart belichtet, daß nach ihrer Entwicklung die Photore­ sistschicht 51 nur außerhalb derjenigen Gebiete zu­ rückbleibt, wo ein n-Kanal-Feldeffekttransistor ge­ bildet werden soll. Durch das bekannte Ionen-Implan­ tationsverfahren wird eine festgelegte Menge von Bor-Atomen 52 in das Silizium im Gebiet des n-Kanal- Feldeffekttransistors eingebracht, um eine flache p--Schicht 14′ (siehe Fig. 1) zu bilden. Soweit sie vor­ handen ist, hindert die Photoresistschicht 51 die Bor-Atome daran, das Siliziumsubstrat 13 zu erreichen.
Die implantierten Bor-Atome werden sodann tiefer hineingetrieben, um das p-Gebiet 14 zu bilden, und am Ende dieses Diffusionsschrittes wird unter Wärmeeinwirkung eine dicke Oxidschicht 53 selek­ tiv in denjenigen Gebieten ausgebildet, die nicht durch die Siliziumnitridschicht 16 (siehe Fig. 2) geschützt sind.
Beim dritten Maskierungs- und Ätzschritt werden das Siliziumnitrid 16 und das Gate-Elektroden- Oxid 15 von den Drain- und Source-Elektrodengebie­ ten 17, 17′ und dem Sperrgebiet 18 entfernt, und die p⁺-Diffusion ausgeführt. Der vierte Maskierungs­ schritt öffnet die Source- und Drain-Elektrodenge­ biete 21, 21′ und das Sperrgebiet 22 des n-Kanal- Feldeffekttransistors, wonach die n⁺-Diffusion ausgeführt wird (siehe Fig. 3). Durch eine selektive Ätzung mit Phosphorsäure wird das Siliziumnitrid 16 sodann in den Gate-Elektrodengebieten entfernt. Der fünfte Maskierungsvorgang wird darauf verwendet, Kontaktierungsöffnungen zu den Source- und Drain- Elektrodengebieten auszubilden, und nach der Metalli­ sierung legt die sechste Maskierung das metallische Verbindungsleitermuster 25, 26 fest (siehe Fig. 4).
Beim Einsatz dieses Verfahrens wird die selbstaus­ richtende Art der Ausbildung der Gate-Elektrodenge­ biete beibehalten, und die Kontaktierungsöffnungen zu den Source- und Drain-Elektrodengebieten werden an den Rändern dieser Gebiete begrenzt, weil die an­ fänglich außerhalb der Diffusionsgebiete ausgebildete Oxidschicht mühelos zumindest zweimal stärker als die während der n⁺- und p⁺-Diffundierung ausgebil­ dete Oxidschicht gemacht werden kann.

Claims (1)

  1. Verfahren zur Herstellung einer CMOS-Halbleiter­ vorrichtung, bei dem
    • a) zunächst eine erste Oxidschicht (15) auf der Oberseite eines Halbleitersubstrats (13) vom ersten Leitfähgkeitstyp (n) hergestellt und eine Siliziumnitridschicht (16) auf dieser ersten Oxidschicht (15) ausgebildet wird,
    • b) diese beiden Schichten mit einer Maskierung versehen und darauf Öffnungen durch die Schichten hindurchgestellt werden, so daß die Siliziumnitridschicht (16) und die Oxid­ schicht (15) an solchen Bereichen verbleiben, wo Drain-, Source- und Gatezonen ausgebildet werden sollen,
    • c) alle diejenigen Bereiche, in denen Transistoren mit einem Kanal vom ersten Leifähigkeitstyp (n) nicht ausgebildet werden sollen, mit einer Mas­ kierung (51) versehen werden,
    • d) durch Ionenimplantation eine dünne Schicht (14′) vom zweiten Leitfähigkeitstyp (p) erzeugt wird in den Bereichen, wo Transistoren mit einem Kanal vom ersten Leitfähigkeitstyp (n) in dem Substrat (13) erzeugt werden sollen,
    • e) die letztgenannte Maskierung entfernt und die dünne Schicht (14′) in das Substrat (13) hinein vertieft wird (Schicht 14),
    • f) eine thermische Oxidschicht (53) über den nicht durch eine Siliziumnitridschicht (16) geschützten Bereichen ausgebildet wird,
    • g) die Siliziumnitridschicht (16) und die erste Oxid­ schicht (15) zur Ausbildung von Öffnungen für die Herstellung der Source- und Drainzonen (17, 17′) der Transistoren vom zweiten Leifähigkeits­ typ (p) maskiert und geätzt werden,
    • h) ein Dotierungsmittel zur Ausbildung von Source- und Drainzonen (17, 17′) vom zweiten Leitfähig­ keitstyp (p) in das Substrat eindiffundiert wird,
    • i) die Siliziumnitridschicht (16) und die erste Oxidschicht (15) zur Ausbildung von Öffnungen für die Herstellung der Source- und Drainzonen (21, 21′) der Transistoren mit Kanal vom ersten Leitfähigkeitstyp (n) maskiert und geätzt werden,
    • k) ein Dotierungsmittel zur Ausbildung von Source- und Drainzonen (21, 21′) vom ersten Leifähigkeits­ typ (n) in das Substrat eindiffundiert wird,
    • l) die Siliziumnitridschicht (16) an den Gatezonen fortgeätzt wird,
    • m) eine Metallisierungsschicht auf dem Halbleiterbau­ stein aufgebracht und zur Festlegung des Leitungs­ musters für die Metallanschlüsse für die Gate­ elektroden (26), die Source- und Drainanschlüs­ se (25) sowie die Leitungsverbindungen maskiert und fortgeätzt wird.
DE2661099A 1975-05-08 1976-05-07 Expired DE2661099C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/575,655 US3983620A (en) 1975-05-08 1975-05-08 Self-aligned CMOS process for bulk silicon and insulating substrate device

Publications (1)

Publication Number Publication Date
DE2661099C2 true DE2661099C2 (de) 1988-10-20

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ID=24301188

Family Applications (4)

Application Number Title Priority Date Filing Date
DE2661099A Expired DE2661099C2 (de) 1975-05-08 1976-05-07
DE19762620155 Granted DE2620155A1 (de) 1975-05-08 1976-05-07 Verfahren zur herstellung eines silizium-halbleiterbausteins in cmos- technik
DE2661097A Expired DE2661097C2 (de) 1975-05-08 1976-05-07
DE2661098A Expired DE2661098C2 (de) 1975-05-08 1976-05-07

Family Applications After (3)

Application Number Title Priority Date Filing Date
DE19762620155 Granted DE2620155A1 (de) 1975-05-08 1976-05-07 Verfahren zur herstellung eines silizium-halbleiterbausteins in cmos- technik
DE2661097A Expired DE2661097C2 (de) 1975-05-08 1976-05-07
DE2661098A Expired DE2661098C2 (de) 1975-05-08 1976-05-07

Country Status (6)

Country Link
US (1) US3983620A (de)
JP (2) JPS51138174A (de)
CA (1) CA1057862A (de)
DE (4) DE2661099C2 (de)
FR (1) FR2310635A1 (de)
GB (4) GB1529023A (de)

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Also Published As

Publication number Publication date
DE2661097C2 (de) 1988-05-26
FR2310635B1 (de) 1980-02-15
GB1529023A (en) 1978-10-18
JPS61253U (ja) 1986-01-06
CA1057862A (en) 1979-07-03
GB1529297A (en) 1978-10-18
DE2620155A1 (de) 1976-11-18
US3983620A (en) 1976-10-05
JPS51138174A (en) 1976-11-29
GB1529296A (en) 1978-10-18
DE2620155C2 (de) 1988-05-19
GB1529298A (en) 1978-10-18
FR2310635A1 (fr) 1976-12-03
DE2661098C2 (de) 1989-07-06

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