DE2516681C2 - Telecontrol device - Google Patents

Description

The invention relates to a telecontrol device according to the preamble of the patent claim 1.

Such a remote control device is already from DE-PS 11 69 009. Column 1. Lines 17 to 30 and column 2. Lines 20 to 35 are known.

A telecontrol system in which several substations work together with a control center and the substations are called up cyclically by the headquarters, is also from "Landis & Gyr-Mitteilungen" 1969. Issue 8 Pages 2 to 13 known. After a message has been called, the called station sets measured values in a cyclical sequence away. In this telecontrol system, different values are used for a counter value, a command and a message group Pulse telegrams used.

Furthermore, a digitally operating telecontrol device is already known ("Brown Boveri Mitteilungen", Oct./Nov. 1960, No. 10/11. Pages 723 to 740), at the a cyclical transmission of measured values is provided.

With this telecontrol device, monitoring of seven transmission attempts is provided.

The object of the invention, on the other hand, is to provide a telecontrol device of the type specified above in such a way that the failure of stations be it due to a malfunction in the relevant station itself or due to an interruption in the 'Signal transmission network in at least one evaluating Station can be determined and saved safely.

According to the invention, the telecontrol device to solve this problem is according to the characterizing Part of claim 1 formed. The stations provided with an evaluation circuit can be central stations or with evaluating stations that facilitate the exchange of information between

of the central station and the other stations.

Through these measures, there is the advantage that the message Station failure in the remote control device by simply realizable supplement existing ~~> Dener building blocks of the remote control device is possible.

In a further embodiment of the invention, the telecontrol device is designed such that the memory and the buffer store clock-controlled circulation ι » Fende memories are, in which in the Rückkopplungs2zweig a multiplexer is arranged and that to the Evaluation circuit and a comparator is connected to a clock controllable address counter, and that the multiple r> xer connected upstream of the intermediate storage unit is connected to the comparator Control circuit is controllable from the beginning of the equality following a release between the Circular address and the respective station address emits a control signal until the end of equality, and that the Λ » the memory upstream multiplexer by a further aas the signal at the first Au. '^ ang the Evaluation circuit derived control signal is controllable. In particular, they serve as a circulating memory feedback shift register. Controllable switches can serve as multiplexers, which connect the input of the downstream memory depending on the state of the control signal either with the memory output or connects with a registered path.

Further advantageous embodiments of the invention- J '> result from the subclaims.

The invention is based on the circuit arrangement of a telecontrol device shown in the figure explained in more detail.

The circuit arrangement shown in the figure is J ' Part of a central station or an evaluating or listening station of a telecontrol device. This telecontrol device is designed so that it works continuously or temporarily in call mode.

The Figui shows a telecontrol device with ⁴ "self-monitoring of the stations of a telecontrol network.

In the telecontrol system not shown in detail in the figure, a central station cyclically calls its stations and expects a response telegram. Stations and substations can apply for training ^4> dung as A ^ attractive system spontaneously in the waiting time gaps to step in if they are to signal a message Change.

In addition to collecting all messages from the telecontrol network, the query cycle of the central station also has the task of monitoring the stations and indicating their failure or return. In addition to the active central station, there are also passive central stations that only listen in and evaluate are switched on everywhere in the network and should ^{also indicate 5} > station failure or return of a station. Part of a central station is shown in more detail in the figure.

If a central station sends a request telegram, it expects a response telegram from the called ^b0 station. If the station does not answer, the central station calls the next station after a waiting period. One criterion that indicates that a station has failed is that the central station transmits twice without receiving the called station in between. For central stations that only listen passively, a station failure criterion is that they receive a central station telegram twice in succession.

The status of each station is recorded in the central stations in memories and in lamp fields displayed. Changes in status trigger an acoustic alarm. You can see the state of the stations too first save it in registers and then display it in lamp fields via external individual memories or enter in logging facilities.

Each central station, whether it is active or just listening in, has an evaluation circuit 11 which determines whether a call telegram is on the line with the address of the called station or a station steiegram with the address of the sending station. A line a leads from the evaluation circuit, which has the logic state "1" when a request telegram is sent and a line b, which assumes the logic state "1" when a station program is transmitted. The coded address or the bitmu.v: r of the address of the sending or requested station is on the address lines c \ ... cn, which also come from the evaluation circuit

The address lines c 1 ... cn and the address of the address counter 15 which is incremented by the clock generator 14 are fed to the Vergieicher 12 gives at each address equality a pulse to the from the flip-flop circuits 1 and 2 and consisting of the inverter 16 control circuit .

The delay element 13 is connected to the output a of the evaluation circuit 11. The OR element 9 has one input at the output of the delay element 13 and its other input at the output b of the evaluation circuit 11. The AND element 10 has a non-inverting input at the output a and an inverting input at the output of the OR element 9 connected.

The intermediate memory 3 is the multiplexer 6, the new memory 4 is the multiplexer 7 and the old memory 5 the multiplexer 8 is connected upstream. The multiplexer 6, 7, 8 is used in each case to the input of the downstream Memory 3, 4, 5 depending on the state of a control signal emv eder with the output of the downstream To connect memory 3, 4, 5 or a recording line.

The control input of the multiplexer 6 is at the output of the AND element 18 of a control circuit containing the flip-flops J and 2. In this control circuit, the clock input of flip-flop 1 and the clock input of flip-flop 2 are connected to the output of comparator 12 via the upstream inverter 16. The D input of flip-flop 1 has the logic state »1« or »H«. The D input of flip-flop 2 is connected to the Q-Au ^ flip-flop 1. The (J> output of the flip-flop 1 and the inverting ζ) output of the flip-flop 2 are connected to the inputs of the And-Güedes 18, the output of which is routed to the control input of the multiplexer 6. The Clear inputs elder flip-flops 1 and 2 are at the output of the OR gate. 9

The two flip-flops 1 and 2 can be kept in a defined position by a signal applied to their clear inputs el with the logic state "0". : The clock generator 14 drives in addition to the address ^; senzähler 15 designed as shift registers memories 3, 4 and 5, lire are fed back via the multiplexers 6, 7 and 8, and the delay element 13, which is also designed as a shift register in the embodiment shown.

The multiplexer 7 is connected to its sleeve input Exit of the Uncl-Gliecles 10.

The power input of the multiplexer 8 is connected to the information bus 17 of the station together with the address outputs of the address counter 15, the clock generator 14 and the outputs of the new memory 4 and the old memory 5. The control signal is formed in the at Meldungsvcrarbeiturig with saving an old and a new alarm status and acquisition of new Mcldezustandes in the w Altspeicher in acknowledgment of the message in the usual way.

If a central station sends, the line a resounds over the link 10 to the multiplexer 7. and the new memory 4 is loaded with the contents of the d buffer 3. At the same time, the logic state of the line α is transmitted to the delay element 13. The delay time of the delayed gliCuCS i3 iSi fTiiriuCSiCnS giCiCh UcT duücf ciflcS address counter circulation. After this delay time - ">". The gate 10 is blocked, the multiplexer 7 is reset and the two flip-flops 1 and 2 are enabled.

With the beginning of the address equality established by the comparator 12, the flip-flop 1 is set. The i> output of the AND element 18 assumes the logic state "1". The multiplexer 6 is switched over and the state of the line a is stored in the memory location in the buffer 3, which belongs to the pending address. This memory status means: "The called station has failed".

With the end of the address equality, the flip-flop 2 is set, the AND element 18 is blocked and the Multiplexer 6 switched back. The flip-flops 1 and 2 are reset as soon as the signal) ί "Central station is sending" on line a disappears.

Armrests! the called station, flip-flops 1 and 2 are released via line b and OR gate 9. If the addresses are the same, the logical state of line a is again stored in the memory location of the buffer 3, which is the logical state "0" in this case and means "station has answered".

With the next telegram from the central station again the content of the buffer 3 is given into the new memory 4 and then the next one The storage space of the buffer 3 is set to the status “station failed”, which is immediately possible is done when the station responds. The following structural publication arises:

The central station sends:

The buffer 3 gives its information to the new memory during the delay time of the delay element 13,
After the end of the delay time, the buffer store 3 and the new store 4 are separated. In addition, Kippstufcii I and 2 are released.

If the address is identical between the telegram address and that of the address counter, the information “station failed” is stored in the corresponding memory location of the buffer 3.
End of the central station tclegram.

2.

The station replies:
The tilting stage !! I and 2 are released.
If there is a match, the written information “station failed” is corrected in the corresponding storage space of the buffer 3.
End of the station cycle.

Case 2:

Station does not answer. The flip-flops 1 and 2 are not released. The information »S'ation failed «is not corrected in buffer 3. With the next telegram from the central station this information is given in the new memory 4 and triggers alarming and processing of the state of the station.

The telegrams transmitted in the telecontrol system expediently contain criteria for whether the Telegram was sent from a central station or another station. These criteria are used in the evaluation circuit 11 processed. The central station has the address of in its telegram called station. The called station has its own address in its telegram. These addresses are also processed in the evaluation circuit 11.

1 sheet of drawings

Claims (7)

Patent claims: 1. Telecontrol device with at least one central station and with further stations, the stations each provided with a coded address being connected to one another by a common signal transmission network, the central station sending out call information to the stations in chronological order and, in normal operation, always calling information from the central station Response information of the called station triggers, with a failure test circuit in at least one of the stations, characterized in that the failure test circuit contains an: i evaluation circuit (11) which, in addition to the coded address (lines el ... cn) of the transmitting central station called station or responding station emits a signal at a first output (s) when a central station is in use and at a second output (b) when a station replies, and that a buffer (3) outputs the signal from the first output (a) of the evaluation circuit (11) delivered signal cached to the coded address and this signal either -H which deletes with the subsequent signal assigned to the same address at the second output (b) or retains it with the subsequent signal at the first output (a) and sends it as a message about the failure of the assigned station to one of the Intermediate store (3) pach-connected memory (4) passes on. which saves the message assigned to the coded address. 2. Telecontrol device according to claim 1. characterized in that the; memory (4) and the K intermediate memory (3) are clock-controlled circulating memories, in which a multiplexer (6, 7) is arranged in the feedback branch and that a comparator (12) is connected to the evaluation circuit (11) and to a clock-controllable address counter (15) ) -to is connected. and that the multiplexer (6) connected upstream of the buffer store (3) can be controlled by a control circuit connected to the comparator (12). the run from the beginning of the following on a release equality between the environmental ⁴ ^ and the respective station address to the end of equality emits a control signal, and in that the said memory (4) upstream multiplexer (7) through a further, from the signal at the first output of the evaluation circuit (11) derived; > o control signal is controllable. 3. Telecontrol device according to claim 1 or 2, characterized in that the arrangement for deriving the further control signal from the signal at the first output (a) of the evaluation circuit (11) contains an AND element (10) which has an input directly and with a further, negated input is connected to the first output (a) of the evaluation circuit (11) via a delay element (13). and that the delay time of the delay element (13) is at least as great; like the overturning time of the dressing counter (1.5). ψ. % 4. Telecontrol device according to one of the preceding claims, characterized in that the control circuit contains two clock-controllable bistable flip-flops: | stages (1, 2) which are fed into their by means of a pulse applied to the Splear inputs (el) (Basic position can be transferred and that the clock input (T) of the first flip-flop (1) can be acted upon with the output signal and the clock input (T) of the second flip-flop (2) with the inverted output signal of the comparator (12) and that the (^ - Output (Q) of the first (1) and the φ output of the second flip-flop (2) are fed to the inputs of an AND element (11), the output of which controls the multiplexer (6) connected upstream of the buffer (3) 5. Telecontrol device according to claim 3 or 4, characterized in that the negated input of the AND element (10) is preceded by an OR element (9), in which an input on the delay element (13) u: id a further input on the second output (b) of the evaluation circuit (11) is located. 6. Telecontrol device according to Anspps.-h 5, characterized in that the clear inputs (ei) of the trigger stages (1, 2) are connected to the output of the OR element (9). 7. Telecontrol device according to one of the preceding claims, characterized in that the memory is a new memory (4) in a circuit arrangement for old-new comparison in which in each case the content of a memory location of the new memory (4) in the case of an acknowledgment of the relevant message is transferred to the old memory (5).