DE2552498A1 - Adjustment of clock frequency of data transmission - resets clock phase of outgoing data when intermediate store for incoming data overflows or empties and during transmission pauses - Google Patents

Abstract

Incoming data are stored at their own frequency in an intermediate store, and read out at a different, independent frequency. If the store overflows or empties the clock phase of outgoing data is reset. Depending of frequency and phase of incoming data, at least n-2 storage locations out of n existing storage locations in the intermediate store, are made available during continuous frequency drift until another overflow or emptying. Phases of outgoing data are so reset, during transmission pauses that the same storage capacity is available until overfill or emptying.

Description

Circuit arrangement for controlling a device for

Clock adaptation The invention relates to a circuit arrangement for Control of a device for clock adjustment at interfaces in data transmission systems. At such interfaces, transmission links often have to be separately synchronized Systems are interconnected. That means that those with a certain Frequency and phase of incoming data at the interface in terms of frequency and phase must be adapted to the cycle of the outgoing transmission link.

For this purpose, such clock adjustment devices are usually included Provide caching. In these buffers, their individual storage locations e.g. consist of flip-flops, the incoming with a certain clock frequency Data is stored and restored at the rate of the outgoing transmission link read out. Because of the limited storage capacity the buffer is used at uninterrupted data transmission after a certain time, which depends on the memory size and the frequency difference between incoming and outgoing Data, the memory is filled or emptied, which usually leads to errors in the Data transfer leads.

For reasons of cost and space, these buffers cannot be used arbitrarily to be made big. The invention is therefore based on the object of a relatively specify simple circuit arrangement that has a clock adjustment device with a buffer controls so that the available storage capacity is used optimally and as far as possible few transmission errors occur.

This task is based on a device for clock matching, in which the incoming data with their own clock into a buffer stored and read out again with the given rigid cycle, thereby solved that immediately with a memory overflow or with a memory underflow during a data transmission, the phase of the clock of the outgoing data is set anew that, depending on the frequency and phase of the clock of the incoming data, at least n-2 storage locations of the existing n storage locations of the intermediate storage to are available for a new memory overflow or memory underflow. and that in transmission pauses the phase of the clock of the outgoing data is set anew becomes that when data transfer starts up to a memory overflow or up to The same amount of storage capacity is available to a memory idle.

An advantageous embodiment of the circuit arrangement according to the invention consists of a retriggerable timer that detects transmission pauses, only from logical combination circuits.

In the following, the circuit arrangement according to the invention is based on an embodiment with an 8-bit buffer is described in more detail and explained.

FIG. 1 shows a basic circuit diagram, FIG. 2 shows a timing diagram, FIG. 3 shows a Detailed circuit diagram of this exemplary embodiment and FIG. 4 a table.

The arrangement shown in Figure 1 consists of a buffer ZS with eight memory locations (preferably flip-flops), a BCD decimal decoder D, an 8-to-1 multiplexer M, the two binary counters Z7 (decoder counter) and Z2 (Multiplexer counter), the testing device LO, which Transmission pauses recognizes, and the logic circuits L2, L4, L6, LS and LZ. The incoming With the aid of the decoder D, whose addresses DO to D7 are cyclically transferred from the Decoder counter Z7 are controlled with the clock T1 of the incoming data, in the Read in memory flip-flops of the intermediate memory ZS. With that independent of Ti Clock T2 is the data by means of the multiplexer M, whose inputs MO to M7 accordingly the addresses generated by the counter Z2 are cyclically switched through to the output are read from the buffer ZS.

The link LO that detects transmission pauses can be, for example, a retriggerable Be a timing element that is triggered again and again during data transmission and in data transfer pauses, e.g. if the character "L" (LOW) or "H" (HIGH) is sent, drops out and the multiplexer counter Z2 on the jump for the address MO preprogrammed (PO). If the address DO is now controlled by the decoder counter Zi, the multiplexer counter Z2 is set to "0", that is to say, via the link LS Multiplexer address MO, set (S). It does not matter whether the frequency of the clock is now Ti of the incoming data is greater or less than T2, half the capacity is available of the intermediate memory ZS is available as a buffer. The input address DO and the Output address MO is "in opposition" at the beginning of a data transmission. because the direction of the frequency drift is not known in advance. There the phase relationship between the two clocks T1 and T2 is arbitrary, is also this middle position of the two addresses DO and MO to one another within two outer ones Arbitrary limits (see Fig. 2c).

Is the 'frequency of the clock T2 of the outgoing (to be read out) Data greater than clock T? of the incoming (to be read in) data, the Time interval between reading in and reading out a specific memory location always smaller. If the distance between the read-in address (decoder address) and read-out address (Multiplexer address) is only one memory location, the counter Z2 is on preprogrammed a jump forward by two multiplexer addresses. In this embodiment here this means that SZ is preprogrammed to P6 through L6, i.e. if at the Decoder address Di is read in and the counter Z2 controls the multiplexer address M4 (at the output of the counter "4" is present (L4)) the counter Z2 is on the jump after "6" preprogrammed with L6 (P6). Now the distance between the controlled Decoder addresses and multiplexer addresses so small that reading and reading out start to overlap at the upper memory location (DO and M4), the counter becomes Z2 set to "6" by means of LS and LZ (S).

This is shown schematically in a time diagram in FIG. 2a. The arrow at T2 shows the frequency drift of the clock T2 compared to the clock Ti. D are the decoder addresses, M shows the position of the multiplexer addresses shortly before the jump and Mn the multiplexer addresses shortly after the jump. With persistent The same frequency drift of the incoming data transmission characters are now six of the eight memory locations are available as buffers until another "memory empty run" occurs.

In the other case, the frequency of the clock T2 is less than the frequency of the clock Ti, the currently controlled multiplexer address is approximated to the currently activated decoder address now "from the other direction" (cf. Fig. 2b). If in this case, too, the distance is only one memory location, the counter Z2 is preprogrammed to jump back two multiplexer addresses.

In this embodiment, this means that LZ by 1.2 P2 is preprogrammed, i.e. when reading in at the decoder address D7 and the counter Z2 controls the multiplexer address M4 (L4), Z2 is on the jump-to "2" preprogrammed using L2 (P2). Now start again Reading in and reading out at the upper memory location (DO and M4), the Counter Z2 is set to "2" (S) by means of LS and LZ (see FIG. 2b). In this case, too There are now six of the eight memory locations with the same frequency drift remaining available as a buffer until another "memory overflow" occurs.

In Figure 3 is a detailed circuit diagram of a simple embodiment of the invention Circuit arrangement shown in Figure 1. It contains the multiplex counter (binary counter) Z2, consisting of three D flip-flops ABC, the retriggerable timing element (mono-flop) I, O and the logic circuits L6, L2, LS, LZ, L4. The D flip flops of Z2 have the significance A = 2 °, B = 21 and C = 22. So if at the exits QA, QB, QC the signals LLH (L = LOW, H = HIGH) are present, the counter is in the "4" state, thus controls the multiplexer address M4. At the inverted outputs QA 'QB, QC is correspondingly the opposite signal.

The NAND gate L4 then emits an L signal 74 when M4 applies = M4 = T2.QA.QB.QC The decoder outputs also enter here when they are activated L signal off. Then with the rules of Boolean algebra P6 = D1.M4 = D1 + applies M4 (I, 6) P2 = D7-M4 = D7 + 714 (L2) S = DO.PO + DO.M4 or s = (DO + PO) (DO + M4) (LS) The functionality of the D-Flip-Flops ABC of Z2 as a binary counter may be known as are assumed. An L signal at the "Preset" inputs (PA, P3, P) or on the "Clear" - Inputs (CA, CB, CC) causes a change of state, such that e.g. with PB = L the output QB = H or with CB = L the output QB = Ti will. Which signals then at these inputs for a jump of the counter Z2 must be applied to the multiplexer addresses MO, M2 and M6, Fig. 4 shows.

The NOR flip-flop FF is toggled with an H signal. For R = H (P6 '.) Q = H and for S = H (P2 ') Q = t.

If R = S = L (P6 and P2 not) the previous state of FF remains obtain. At the output of the mono-flop LO there is an L signal in transmission pauses (PO '). So the counter Z2 is on a jump to M6 (P6 '), M2 (P2!) Or MO (PO!) preprogrammed accordingly ". If the setting pulse S is now given by LS, the counter Z2 set to the corresponding 'preprogrammed value, as from the logical Links can be found in Fig.3.

Claims (2)

Circuit arrangement for controlling a device for clock adjustment at interfaces in a data transmission system, the incoming data is stored in a buffer with the irlxen own clock and can be read out again with an independent, rigid clock and the incoming and outgoing data stream is monitored, in that immediately at a memory overflow or a memory underflow during a data transfer the phase of the clock of the outgoing data is reset so that, dependent of the frequency and phase of the clock of the incoming data, at least n-2 storage locations of the existing n storage locations of the intermediate memory with persistent frequency drift are available until a new memory overflow or memory underflow and that in transmission pauses the phase of the clock of the outgoing data is set anew becomes that when data transfer starts up to a memory overflow or up to The same amount of storage capacity is available to a memory idle. 2. Circuit arrangement according to claim 1, characterized in that the counter (Z2) that controls the multiplexer (M) for outputting the data from the buffer (ZS) controls, can be set in one of three preprogrammed positions, the Criteria for preprogramming (PO, P2, P6) and setting (S) the multiplex counter (Z2) by means of logic gating circuits (L2, L6, L4, LS) from the state of the Decoder (D), the multiplexer counter (Z2) and the transmission pauses indicating Link (LO) can be derived.