DE2435420C3 - Control device for a vending machine - Google Patents

Description

a) the comparator (16) is connected to a disbursement device (28) for the remaining money;

b) the payout device (28) controls the clock generator (12);

c) the clock generator (12) supplies the second accumulator (20) with coin value pulses corresponding to the coins dispensed to be added to the purchase price while the remaining money is being paid out; and

d) the comparator (16) generates if the values stored in the two accumulators (14, 20) are identical Sizes a blocking signal for the payout device (28).

2. Control device according to claim 1, characterized by a blocking circuit (18) between the second accumulator (20) and the comparator (16).

3. Control device according to one of claims 1 or 2, characterized by one with the Comparator (16) connected differential decoder (24) with outputs showing the difference between the sizes stored in the two accumulators (14, 20).

4. Control device according to claim 3, characterized in that the two accumulators (14, 20), the comparator (16) and the differential decoder (24) by a single integrated circuit are formed.

5. Control device according to one of claims 1 to 4, characterized in that the two Accumulators (14, 20) are formed by several bistable flip-flops connected in series.

6. Control device according to one of claims 1 to 5, characterized in that the payout device (28) as a function of the difference the sizes of coins with different sizes stored in the two accumulators (14, 20) Outputs values.

7. Control device according to one of claims 1 to 6, characterized in that the clock generator is formed by an oscillator circuit.

8. Control device according to one of claims 5 to 7, characterized in that the comparator (16) contains several Sunvnierschaltungen, each with the corresponding bistable flip-flops of the two accumulators (14, 20) are connected.

The invention relates to a control device for a vending machine in the preamble of Claim 1 specified genus.

From DE-OS 20 60 642 a coin operated goods sales device is known in which a bidirectional counter for storing the amount of money inserted and correlating it Amount is used with the sales price. The amount thrown in beyond the purchase price can can be reissued.

From DE-AS 17 74 138 a control device for a vending machine is known in which also a bidirectional counter is used. This takes place

ίο no review of the beyond the purchase price thrown in, to be disbursed again, but when such a difference occurs Payout pulses are generated until the count reaches zero.

From GB-PS 10 70 005 there is a change machine known, which can also be used in a vending machine. A comparator is used for used to compare different amounts of money

Furthermore, from US-PS 33 44 898 a control device known for a vending machine in which a bidirectional counter is also used. Of the Any amount of money thrown in above the purchase price is lost and will not be refunded.

Finally, from US-PS 33 65 045 a control device for a vending machine is the specified type known that a clock, the coin value pulses according to the inserted coins Sir created a first accumulator, one second accumulator for the purchase price of the goods, one stored in the two accumulators Comparator sizes comparing and one connected to the comparator, the output of the goods only after entering a certain amount has enabling locking device. This vending machine can only dispense a certain product, namely, for example, gasoline at a gas station, with each a certain amount of petrol to be dispensed is assigned to a certain amount of money thrown in. The output of the amount of money that exceeds the value of the amount of gasoline consumed, such as for example would be desirable when the tank is full is not possible.

The invention is therefore based on the object of a control device for a vending machine to create the specified type, with the issue of different goods with different Prizes and amounts thrown in beyond the purchase price are repaid and the issue these amounts can be precisely controlled.

This object is achieved according to the invention by what is stated in the characterizing part of the new claim 1 Features solved.

Appropriate embodiments are compiled in the subclaims.

The advantages achieved by the invention are based in particular on the fact that with the locking device connected comparator not only output the goods after entering a sufficient amount of money, but also monitors the payment of the remaining money; this results in a very exact one Control of the issue of each individual coin, which ensures that only the remaining money and a higher amount is not spent again. In addition, this monitoring of the remaining money the clock generator present in the coin unit for the inserted coins for the generation of the coin value pulses used, so that despite this precise control of the coins dispensed, no high

additional design effort is required, because the existing components can largely be used. And finally, requires even when changing the coin system or a Change in the purchase price this payout facility does not require extensive maintenance work, as this Maintenance work must already be carried out in the coin unit and at the same time also the Adjustment of the associated components of the payout device takes place, namely the! Comparator and the Clock.

The invention is illustrated below on the basis of exemplary embodiments with reference to Schematic drawings explained in more detail It shows

F i g. 1 is a block diagram of the essential components and connections for one embodiment of a controller for a vending machine according to the present invention,

F i g. 2 shows a detailed circuit diagram of the programmable clock generator of the control device according to FIG. 1,

Fig.3 is a detailed circuit diagram of the parts of the Embodiment according to FIG. 1, which is outlined in the by the dashed line and with the reference number 10 provided part of FIG. 1 are located,

4 shows a detailed circuit diagram of the reimbursement facility, the payout device and the sales control of the control device according to FIG. 1, and

F i g. 5 a diagram of FIG. 4 corresponding Circuit diagram for a vending machine in which two or more different sales prices are used can be.

In the figures, the part of the control device is with provided with the reference numeral 10, which is completely integrated, that is to say present on a single chip is That part of the control device which is located in area 10 outlined with dashed lines identical for the two described embodiments of the present invention, that is to say for the embodiment according to the F i g. 1 to 4, where only a single fixed sales price is used, as well as the Embodiment according to FIG. 5, in which two or more different purchase prices can be used.

The essential, in the following described in detail components of the control device for a Vending machines according to the present invention are: a programmable clock 12, also known as "Clock circuit" is to be designated; an adder and storage circuit 14, hereinafter also referred to as Accumulator and sometimes also as a -4 counter referred to as; a comparator 16, that is, a comparator circuit; a locking device 18; one second adding and storage circuit 20, also referred to below as an accumulator or B counter is designated; a price coding circuit 22; an output decoding circuit 24; a refund circuit 26; a payout device 28, also referred to as a "payout control circuit" will; and a sales control circuit 30.

In the case of the in FIG. 1, the circuits 14, 16, 18, 20 and 24 are a single control device integrated circuit summarized, for example, located on a single chip; this Circuit part is provided with the reference number 10.

Programmable clock circuit

The programmable clock circuit 12 provides a corresponding number of pulses for the credit or Credit input signals that are sent by a coin unit or other similar input device, such as B. a coin validator, are received; these facilities also include input units, who are able to accept coins, tokens, paper money, credit cards and other similar ones to include means of payment representing a certain monetary value. The credit or credit entry device is only indicated generally by the number 32

ίο and has a large number of output connections, which are connected to corresponding inputs to the programmable clock circuit 12. In the figures are the inputs to the clock unit with 34,36,38, 40, 42 and 44. In practice, the input connections between the credit unit 32 and the programmable clock circuit 12 through various types of links, where z. B. electrical connections, magnetic connections, optical couplings, etc. are used can be.

If an input signal is received at the input terminal 34, the programmable clock circuit delivers an output pulse appearing on an output line 46 which is the Λ output line This The output signal can be a dime, a five-cent, or any other basic unit for that Represent the credit of a buyer, including basic units in foreign currencies. As soon as an input signal is received on the input connection 36 are on the output line 46 of the clock circuit 2 output pulses are generated which represent the basic unit twice. In a similar way a Input signal on input line 38 three output signals on output line 46 of the clock circuit, an input signal on input connection 40 produces four output signals on the output line 46 of the clock circuit, an input signal on input line 42 produces five output signals, and an input signal on input line 44 of the clock circuit produces ten output pulses on the Output line 46. Of course, a greater or lesser number of combinations can be used if necessary are supplied by input and output pulses of the clock circuit. The one on line 46 at The output pulses of the clock generator that occur in the circuit shown are always available if another input to the programmable clock circuit 12, namely an input on the line 48 (this input can therefore cause an output signal to be issued), a specific state, such as B. has a low voltage state. If the input on line 48 has a "high." State «or a high voltage state, the clock steps or clock pulses from the programmable clock circuit 12 output via a further output line 50, which is used as a 5-output line is designated.

The programmable clock circuit 12 has further input lines which act as payout inputs 52, 54 and 56 are indicated; these inputs can be used to send one, two or five pulses generate, which then each control the payment of change. In the case shown, the Numbers 1, 2 and 5 each pay out one-cent pieces, five-cent pieces and 25-cent pieces These inputs are connected to other locations in the circuit which will be described later will. The programmable clock circuit 12 is used

as a controllable pulse generator that receives input pulses when coins or other forms of Cash is dropped or otherwise entered into the vending machine; the Pulses correspond to the value of the entered tender; the clock circuit also includes 12 an order that responds to other institutions, which control the amount of money by determining the value of the coin, which is returned for each amount entered is to be repaid, which exceeds the price of a selected item, can continue to the entire amount entered will be refunded or refunded if a buyer after the Entering a certain amount for any reason decides not to proceed with the purchase. This can e.g. B. happens when the customer after entering part of the amount to be paid his Changes mind when he finds that he does not have enough money with him to make the purchase he is looking for perform when he has to determine that the stock of the product he wants to purchase is in the Vending machine is used up, or if for any other reason he decides that the deposited amount is to be repaid.

In addition to the above-mentioned connections to the programmable clock circuit, the Clock circuit has a further input 58 which serves as its reset input. Is available at this entrance high signal, so if it is held high, it prevents any clock pulses programmed and / or generated. A control circuit such as B. a control circuit for a Vending machines with a programmable clock circuit such as the clock generator 12 are extremely beneficial Versatile, adaptable and flexible arrangement for the amounts deposited and refunded to control and always keep track of them; the parts of this control circuit can dem Use with any known existing coin system, such as e ·. currently used in the world will be adjusted.

Counter and comparison circuits

The y4 counter circuit 14 receives as above mentioned, inputs from the programmable clock circuit 12 on line 46. These pulses from the clock circuit are given to one connection of a UN D logic element 60, the output of which is connected by a line 62 to the input or the counting connection of the counter 14. The counter 14 has a further output terminal, which bears the reference numeral 64 and through a further line 66 is connected to the other input of the UN D logic element 60 at the output terminal 64 a signal is generated whenever the count in the counter 14 has any before certain, maximum count, such as B. 31 in the shown FaIL reached. A count of 31 is the maximum possible count for a five-level binary counter and is achieved by the possible counter readings for levels from 1, Z 4.8 and 16 can be added. If a count of 31 is reached, thus a signal is generated on output terminal 64 and on line 66 to prevent the AND gate 60 by the clock circuit 12 generated output signals to the / 4 counter 14 can give. This will add another summation beyond the limit imposed by the binary Arithmetic technology results, which would otherwise result in a loss of 31 counting units or in steps Credit increases would result.

Price coding circuit 22 is used to determine whether the credit amount is sufficient for a specific purchase determined, which is so constructed and connected that via its input lines 68, 70, 72, 74 and 76 of the Amount of a selected purchase price directly into selected binary levels of the β-counter circuit 20 implemented or transferred. The lines 68 to 76 code in the respective stages of the counter 20 one, two, four, eight and sixteen increments or any combination from these values. Furthermore, the respective stages of the counter circuit 20 are connected to the blocking circuit 18 and from there connected to corresponding inputs of the comparator circuit 16. In addition, has the counter 20 has an input that connects to the output of the programmable clock circuit 12 on the output line 50 of the clock is connected.

The comparator circuit 16 should be the binary complement (inverted or reversed amount entered) from the counter circuit 14 to the binary amount in the corresponding, at the output connections of the Counter circuit 20 present stages add up, so that there is a binary summation of these two amounts This summation appears at output terminals 78, 80, 82, 84 and 86 of the comparator circuit 16. The output signals appearing on these lines are fed to the decoding circuit 24 and therein as the difference in increase between those stored in counters 14 and 20, respectively Amounts shown

The blocking circuit 18 is a logic circuit

J5 device and is used to store data in the memory or counter 14 to decode stored amounts regardless of the state of the counter circuit 20. The blocking effect occurs whenever the input to interlock circuit 18 is high. the The input line to the blocking circuit 18 is denoted by 88, as is another line 90 shown grounded which is connected to a further control input of the comparator circuit 16 of these two or both connections may contain additional arrangements so that their Input signals under certain conditions large and further requirements (not shown) on the Design of the vending machine are met. The comparator circuit 16 also has a carry output line 92 on, which is at all times with the exception of the times at a low Level is when the amount stored in the counter 20 is greater than that in the counter 14 stored amount is. In the present circuit, according to a preferred embodiment, the Counters 14 and 20, the comparator circuit 16, the blocking circuit 18 consisting of logic elements, the decoder circuit 24 as well as the internal associated connections all in a single, relatively small one

μ and compact, formed by integrated circuits Part or element included. The details of these circuits are shown in the figures and are intended in detail in connection with FIG. 3 to be described.

- decoding circuit

The decoding circuit 24 is at the output of the comparator circuit 16 and generates output signals,

which control the operation of certain other circuit parts and arrangements including devices on the vending machine. As discussed above, decoder circuit 24 has a plurality of input connections, some of which are connected to output lines 78 to 86 of comparator circuit 16; The decoder circuit also has an input connection to the carry output line 92 from the comparator circuit and a plurality of output lines 94, 96, 98, 100 and 102. These lines go to a low level (potential) when they are active. The output line 94 always goes over to a low level (potential) when the Λ counter 14 has stored an amount that is exactly the same as the amount that is stored in the B counter 20. This is illustrated in the figure by the term AB near line 94. Similarly, the voltage on decode output line 96 goes to a low level (potential) whenever the amount stored in counter 14 is one or more increments greater than the amount stored in counter 20; the voltage on output line 98 goes low whenever the amount entered into counter 14 is two or more increments greater than the amount in counter 20; the voltage on output line 100 goes low whenever the amount entered into counter 14 is three or more increments greater than the amount in counter 20 and the voltage on line 102 goes low whenever the counter 14 contains five or more increments than entered into the counter 20. Only one of the decode output lines 94, 96, 98, 100 or 102 may be at a low level at any given time, with the highest detected difference in increase between the amounts entered into the counters becoming predominant and determinative. Therefore, the following applies: If the condition is such that the output signal on line 102 has a low level, this will prevail and take precedence over possible low levels which may also be present on the other three output lines 96, 98 and 100; this selection applies in a similar way to the other lines.

The decoder circuit 24 has two further connections for blocking input signals, one of which is described as a "two or more inputs" blocking signal, which is on a line 104, while the other is described as "five or more ρίη €" £ ησς "S ⁿ enrs ! ^<r ns! is described, which is on a line 106 is one of the lines 104 or 106 due to the closure of a respective empty coin switch 108 or 110 to a low level, so they come into action to prevent the output lines 98 and 102 of the decoder circuit in Be put into operation; they also control another output line of the decoder with the next highest increase difference, so that this takes over control. In the circuit shown, the output line 100 of the decoder, which is the output line of the decoder for three or more increments, is independent of the other output lines of the decoder, so that this line is not connected in the present circuit Circuit is configured primarily for use with a monetary system such as that of the United States of America in which one increment or one increment is a five cent, two increments are a ten and five increments represent a quarter of a dollar, or a 25 cent piece. In a currency system that uses different combinations of incremental values, it may be necessary to also use line 100 and provide another associated blocking input connection. In such a case it may also be necessary to install an additional coin switch that corresponds to the different values of the coins.

Sales control

The circuit 30 for the sales control is controlled by signals which it receives on a line 120 which serves as the output line of an AND logic element 122. The AND gate 122 has two input connections, one of which is connected to the carry output 92 of the comparator circuit 16 and the other to the input of the B counter 20, which receives a signal each time the counter 20 has stored an amount that is greater than zero. The counter input signal to the AND gate 122 is on a line 124 and is an indication of the presence of a coded price. A carry output from comparator circuit 14 on carry output line 22 indicates that Λ counter 14 has stored an amount at least equal to the amount stored in counter 20. If these two conditions are present at the same point in time, the AND logic element 122 generates an output signal which activates the sales controller 30. The sales control 30 supplies output signals which characterize the product selection and are given by a further AND logic element 126 to an output line 128 (see FIGS. 1 and 4) of the logic element. The AND gate 126 has three inputs, one of which is the same as that which is connected to the input of the AND gate 122 via the line 124; the second input is on a line 130, which is an output line of the circuit 30 for sales control, while the third input is on the line 94, which is the output line of the decoder circuit 24 when the counters are equal Λ = B. The AND logic element 126 emits a signal whenever the B counter 20 has not formed a total so that a signal is on line 124 and if at the same time the Λ counter 14 contains an amount that is not equal to the count display in the B-counter 20 is as indicated by the signal on the line 94.If the sales control circuit 30 is triggered by receiving an input signal on the line 120, it triggers a delivery function for the purchased item and continues to cause that the refund control 26 is disabled. The reimbursement is blocked in that an output signal is generated in the sales controller 30, which output signal is sent to the reimbursement controller 26 via a line 132. In this way, the control circuit 28 for the payout is also controlled by a circuit which contains an OR logic element 134 that has two input connections

having; one of these receives output signals from sales control circuit 30 on line 136 while the other input from refund control circuit 26 is received on line 138. If one of the two input signals for the OR logic element 134 is present on the lines 136 or 138, the OR logic element 134 generates an output signal on its output line 140 which is sent to the control circuit 28 for the payout and controls it. The refund control circuit 26 and the payout control circuit 28 both have reset inputs which are connected to the output line 94 of the decoder circuit 24 for resetting when A = B equals. In addition, the refund control circuit 26 has a switch-operated control input 142 which is connected so that it is put into operation by actuation of a refund switch 144. The refund control circuit 26 also has a blocking output line 146 which is connected to a blocking input of the sales control circuit 30. This connection such. B. the inhibit input signal provided by signals on line 132 prevents the vend control circuit 30 from operating and making a vend when the refund control 26 is actuated. The same applies in reverse when the sales control circuit 30 is first put into operation. The details of the refund circuit 26 are shown in Figures 4 and 5 and will be discussed later.

The circuit 28 for controlling the payout has input connections which are connected to the output lines 96, 98 and 102 of the decoder circuit 24, respectively. In addition, a further, additional input connection from the sales control circuit 30 on the line 148 is provided. This last connection is used to reset the payout control circuit 28 when the vend control circuit 30 receives identical inputs from the counter circuits 14 and 20 indicating equality. This is indicated in the drawings by adding Rab. The sales control circuit 30 has a second output connection to the circuit 22 for the price coding. This is an optional special connection which, as shown, contains a line ISO and an AND logic element 152 (see FIG. 1). This connection is always put into operation when additional arrangements for price coding are required, such as B. is the case when the vending machine is to deliver items with more than one retail price.

Payout control

55

The circuit 28 for the payment control monitors the payment of coins to the customer, wherein the coins are dispensed in amounts determined by the total or the stored value in the counter 14, which goes beyond the set sales price; the amounts are in the The number of coins to be paid out is coded by signals transmitted to the circuit on lines 96,98 and 102 receives from the output of decoder circuit 24 For example, a signal on line 96 causes it Payment of a coin with the value of one increment, a signal on line 98 causes the Paying out a coin with a value of two increments and a signal on line 102 has the Paying out a coin that has a value of five increments. When every coin paid off is, the programmable clock circuit 12 is actuated to a corresponding number of pulses to lead to the counter 20. The connections between the payout controller 28 and the clock 12 take place via lines 160, 162 and 164, each of which connects to input lines 52, 54 and 56 of the clock generator are connected. The line 160 serves as a line in the event of an increase by one step, that is to say with one Increment, line 162 as a line for two increments, and line 164 as a line for five Increments, whereby in the circuit shown 1, 2 and 5 each five-cent pieces, ten-cent pieces and represent a quarter of a dollar. If output signals occur on one of these lines, the clock circuit is 12 energized to produce a corresponding number of output signals on the clock circuit output line 50, which establishes the connection to the counter 20. At this point it is possible to do the Counter 20 via this connection to feed pulses because the input line 48 on which the control input signal for the ß-counter to the clock 12 is below Control of the connection from the output control connection 166 to the payout control circuit 28 is brought to a high level.

While the payout process is being carried out, the clock pulses are fed to the β-counter 20 and not to the A-counter 14; This operating sequence is continued until an amount is added up and stored in the counter 20 which is equal to the amount stored in the counter 14. These two amounts are represented in binary form as mentioned above. If this occurs, an output signal indicating equality appears on the output line 94 of the decoder circuit, with the result that the voltage on the line 94 assumes a low level. It is then possible to reset the payout control circuit 28. This also sets up circuitry to reset counters 14 and 20. The provision of / - counter 14 is carried through the line 168, which is connected to an output of the payout controller 28 is carried out, the resetting of the Ä counter 20 through a further line 170, the output signals either receives from the reimbursement circuit 26 or from the payout control circuit 28 A line 170 is connected to the input for the reset control of the B- counter 20. At the same time, the output line 94 of the decoding circuit indicating the same thing gives a further reset signal to the reset input of the circuit 30 for the sales control. This reset signal is input via a further line 171 when the purchase time has elapsed. If the circuit 30 for the sales control is reset, the signal on its output line 148 assumes a low level; thereby resetting the counter 14 and 20 blocking on the payment controller 28 ^ until the time of purchase by As will be explained, the displaying on the equal (A = B) line also serves to reset the refund controller 26 serves 94 reset output signal generated.

Refund Control

The refund controller 26 is shown in detail in FIG. 4 shown and is used in the inventive

Control circuitry for providing a customer or buyer with any inserted amount or storage amount that is present in the counter 14 repay, as long as their inhibit input signal on line 132 from the vending control circuit 30 is present to prevent a refund. So that the reimbursement facility can take action, should be on the equality-indicating output line 94 of the decoder circuit 24 no signal that the Equals equality. If these conditions are met, the buyer can request a refund at any time can be initiated by operating the refund switch 144. If the refund counter 144 triggered, the refund control circuit 26 blocks the operation of the sales control circuit 30 a signal generated on inhibitor output line 146; at the same time, the refund control circuit produces an output on line 138 which to one of the inputs of the OR gate 134 and to the input of the payout control circuit 28 is given. The energization of the refund controller 26 also produces another output signal on line 174, being that output signal to an OR gate 172 and from there to the reset input of the counter 20 is given, as has already been described. If these conditions have been established by the operation of the refund controller 26, the payout control circuit 28 is set to initiate the payout of coins control until the B counter 20, which is now starting an operation in its reset direction, to one Counter reading is brought, which is equal to the counter reading which is stored in the counter 14. Will this one When the state is reached, an output signal indicating a low level occurs on the output line 94 of the decoding circuit 24, which indicates the equality, thereby to the refund controller 26, the To reset the payout controller 28 and, in turn, the counters 14 and 20 in sequence as mentioned above.

So far, the structural and operational details of the circuitry of the invention shown only in broad outline, with a detailed description should now follow. Of course, many of the circuits and components, including the counter, the comparator circuit, the blocking device and the decoding circuit, as integrated circuits in miniaturized form Assemblies are combined; this can be done by having all of these and other circuit elements in the same block or chip or in various blocks or chips of integrated circuits can be arranged. This allows the Same basic building blocks are used to make control circuits with different capabilities and establish connection options; this includes circuits that work with one or more Purchase prices can be operated, circuits in which repayments in one or more, different coin values can be carried out, including the repayment with the smallest possible Number of coins, circuits continue to be used to make a full refund can, and circuits with which based on the Price for a selected purchase item is the coverage amount of each entered amount for Repayment purposes is determined. As far as is known, none of the conventional control circuits have these diverse possibilities, so that this circuit and its structure represent a new generation of control circuits for the specified purposes. The now The following parts of the description explain in detail nen the structure of the circuit and the company's own shafts of the more essential components of the switching arrangement. This includes a description of a switching arrangement for a device with a fixed, specific one Price (Fig. 4), as well as a switching arrangement for a device

ίο with two or more prizes (Fig. 5).

Details of the programmable clock circuit

The details of the programmable clock circuit 12 are shown in FIG. 2 of the drawings. Of the The clock generator 12 shown contains a four-stage binary counter 179 which consists of four flip-flop circuits 180, 182, 184 and 186 is constructed of the D-type. These flip-flops are controlled by an oscillator circuit 188 clock-controlled, which a NOR logic element 190, an inverter 192, a resistor 194, and a Contains capacitor 1%, which are interconnected in the manner shown. The oscillator circuit performs timing control each time the input signal on its input line 198 has a has a low level. The input line 198 of the oscillator is the output line of an OR gate 200 and then takes one each time low level when the OR gate 200 on one of its two inputs 202 and 204 has a low level. An input line 204 to the logic element then always has a signal with a high level when the binary counter 179 of the clock circuit is reset and a signal with low level on each input of the OR-Ver link 206 causes the inputs to the OR gate 206 are each connected to the (p-output connections of the binary stages 180, 182, 184 and 186 connected. This in turn places a low level signal on the corresponding one Input to a further NOR gate 208 generated on its input line 210.

If a signal is low on input line 34 of the clock, it will be a one of the two input signals to an AND link fungs member 212 given, the output of which with a a plurality of inputs 214 of a further UN D logic element 215 is connected. These Conditions have the consequence that the output signal of the AND logic element 215 on the line 216

so assumes a high level because the line 216 is one of the two inputs of the OR gate 200 is when the signal on line 216 is high ho * h you

Fo! "" * That the operation of the

Clock is blocked While the input signal on line 214 is low, this is same signal with a low level at the same time also as an input signal on further input lines 218, 220, 222 and 224 given by individual NAND gates 226, 228, 230 and 232, their outputs ω each with a respective SET input (set input) of one of the clock rip-flops 180, 182, 184 and 186 tied together. If these conditions are present, this has the consequence that the logic elements 206 and 208 a Apply the signal with a low level to the NGR logic element 200 via the input line 204.

If then the signal on the clock input line 34, which is the clock input line, which programmed a clock pulse to its high

Level returns, cause the input signals to the logic element 200 on the input lines 202 and 204 that a signal with a low level on the input line 198 of the logic element 190 occurs, so that due to this state of the input line, the clock circuit 12 can oscillate. A Another NOR gate 242 is connected to the oscillator circuit, two of its three Input connections 244 and 246 to input lines 202 and 204 of the logic link, respectively 200 are connected. If signals with a low level are present on these input lines, then clock the output connection 248 of the logic element and continue doing so until all Inputs to the OR gate 206 have a low level signal. This is in the The case shown occur in which an input signal on the input line 34 of the clock according to a clock pulse, because in this state it is the next binary state after the set state of binary circuits 180 to 186.

Similarly, if a pulse train of ten pulses is required, a signal is temporarily generated with low level occur at the clock input 14 instead of at the clock input 34; this will be the Start the clock circuit with a pre-set count display of 6 as indicated by the signals the input lines 250 and 252 of the NAND gates 228 and 230 is set. For this State, the oscillator circuit must clock control ten pulses until the output line 204 of the logic element 2Ü8 changes its state. During this timing control, the first binary stage 180 receives des Counter 179 of the clock input signals on line 254 between the output of the logic element 242 and the D input of the first flip-flop stage 180 is switched. At this time are on output line 46, which is the line connecting clock circuit 12 to counter 14, Clock pulses when on control input connection 48 from payout control circuit output line 166 28 is a low level signal. Is a high level signal instead of low level on of the B control output line 48, the output signals of the clock generator 12 become the instead B-counter 20 passed via line 50.

If the binary clock stages 180, 182, 184 and 186 are set to a count reading below 16 which is the reset count reading, the clock will provide an output equal to the number of pulses that exist between those two states. For example, setting a count display of 11 will require five clock pulses to reach the sixteenth or reset pulse state. As soon as a high level signal is applied to the reset line 58 for the clock, the result is that the four binary stages 180, 182, 184 and 186 of the clock circuit 179 are reset even if the clock has not completely completed its normal operation . This is to prevent any output signal on output connection 256 of NAND gate 258 from being generated in the output of clock 12 (FIG. 2). This is because the NAN D gate 258 receives a low signal at its other input 260 which is connected to the reset circuit. This connection contains an inverter 262, the input side of which is connected to the input connection 58 for resetting the clock. The line 58 for resetting the clock is also connected directly to all of the reset inputs of the binary stages 180, 182, 184 and 186 of the clock. The AND logic element 212, which is connected to the input 34 of the clock generator, as well as other, similar inputs of the UN D logic elements 264 and 266 in the circuits for the credit entry of the clock generator 12 are connected to one, two or five incremental or Incremental inputs of the clock circuit 12 connected; these logic elements are provided in order to provide isolation for the respective credit input signals and also for the associated input signals to the clock generator from the payout circuit 28, which are received on lines 52, 54 and 56.
A preferred embodiment of the input circuit 32 for the credit is shown in FIG. As shown in Fig. 2, the credit entry circuit 32 includes a coin operated switch 270 which is convertible from engaging a normally closed switch contact 272 to engaging a normally open contact 274; If this happens, a capacitor 276 can be charged relatively slowly through a circuit which contains a resistor 278 with a relatively high resistance value. Due to the action of the switch 270, another capacitor 280 can change its state of charge so that its charge equals the charge of capacitor 276 becomes. Subsequently, when switch 270 returns to its quiescent state engaging normally closed contact 272, capacitor 276 rapidly discharges through another resistor 282 of relatively low resistance to keep the current within the limits of coin switch 270 . The rapid discharge of the capacitor 276 results in a signal having a low level at the output connection 284 intermittently. The duration of this temporary low level signal is controlled by the resistance of another resistor 286 and also by the action of capacitor 280. The specific shape and particular construction of the credit input circuit 32 as shown in the figure has been chosen for purposes of illustration only, since many different types of credit input circuits can be used to operate the programmable clock circuit 12 in a pulsed manner.

Details of the counters, the comparator
and the decoder

F i g. 3 shows in detail the circuit of the counter 14, the comparator 16, the blocking circuit 18, the counter 20 and the decoding circuit 24. According to the illustration, the counter 14 is a five-stage binary counter consisting of five flip-flops 300, 302, 304, 306 and 308 is constructed of D-type. The first flip-flop stage 300 receives the input signals to the circuit 14

bo the line 62, which is the output line of the UN D logic element 60; all flip-flops have reset inputs connected to reset line 168 from an output of payout control circuit 28. Each of the flip-flop circuits, with the exception of the first flip-flop stage 30O, furthermore has a clock input 310, 312, 314 and 316, which is each connected to the previous stage of the counter. For example, the clock input becomes the second

Stage 302 controlled by ζϊ output signals from of the first stage 300, and the same applies to the other stages in a similar manner. That means the following: If input signals are received, they are converted to the ones customary for such meters Added and stored manner. The accumulator circuit 14 also has an output OR gate 318, which has a plurality of inputs, each with each Q output of the counter stages 300 to 308 are connected; the logic element 318 has an output 64, on which only then a signal low level when all five levels of the binary counter are in the state of their maximum count display are; this only occurs when the counter has totaled 31 and stored it

Each stage 300_ to 308 of the accumulator 14 has a respective (? -Output connection 320,322,324,326 and 328 on; the combined signals present at these connections represent the binary complement the summation in the counter 14. The Q outputs are connected, as explained above; in addition, they are each provided with a full adder or summing circuit 330, 332, 334, 336 and 338 which are parts of the comparator circuit 16. The following truth table shows how the Comparator circuit 16 the binary numbers it receives from the five stages of the counter 20, from the Subtracts input signals it receives from the five stages of counter 14 by taking the complements of the Counter 14 (sum of the ^ output signals) to the Q output signals of the counter 20 are added. That The complement of the result 5 is the binary difference.

Allocation table 1 2 4th 8th 16 = 1 1 1 0 0 = 7 A. = 0 0 0 1 1 = 24 A. = 0 1 0 0 0 = 2 + B = 0 1 0 1 1 = 26 S. = 1 0 1 0 0 = 5 S.

The counter 20 has five stages 340,342,344,346 and 348, so that the number of Steps is the same as for counter 14. The individual stages of the counter 20 can be accessed directly by input signals which are received on input lines 68, 70, 72, 74 and 76, respectively; these Stages are clock-controlled by input signal ^, which are received on the ß-counter input line 50, and are reset by input signals either from the refund control circuit 26 or received by the payout controller 28. The reset pulses are from the OR gate 172 supplied at its output 170. Each stage of the counter 20 also has one Q output, where the individual outputs are identified by the reference numerals 350, 352, 354, 356 and 358 are identified. Signals occurring at these outputs are processed by respective NOR logic elements 360, 362, 364, 366 and 368 reversed and inverted, respectively; therefore, the NOR gates deliver non-inverted, binary output signals from the counter 20. These output signals are each to the Adding circuits 330, 332, 334, 336 and 338 in the comparator circuit 16 are given in a similar manner, how the input signals are given to the adding circuits from the / 4 counter 14.

The blocking input line 88 to the blocking circuit 18 is as shown in Figure 3 with a second Input of each of the NOR gates 360-368 connected. there is a signal on this input with a high level, this has the consequence that a signal with a low level at the respective outputs 370, 372, 374, 376 and 378 of the logic links; this creates a locking function between the B counter 20 and the comparator circuit 16 triggered.

ι ο This would prevent the comparator circuit 16 Signals from the B counter 20 can receive.

The comparator circuit 16 contains a parallel carry circuit part 380, which provides "carry-out" control signals on the "carry-out" line 92

If the signal on the "carry-out" line 92 is low, this means that the binary The counter reading in the B counter 20 is not greater than the binary counter reading in the A counter 14. The "carry-out" line 92 will carry a signal with a low level as long as the counters are in the same state or in are a state in which the A counter 14 has stored a larger sum value than the B counter 20. The comparator circuit 16 also has a "carry-on" line 382; is on this line usually a low level signal; this line is used as an additional control parameter for others, possible use cases foreseen in the future; she can z. B. in devices with another Basic structure can be used, the additional operational possibilities Offer.

The circuit of the B counter 20 contains a further AND logic element 384; this link has a variety of input connections, each with the ^ outputs of stages 340 to 348 are connected. A signal is then always present at an output 124 of the logic element 284 low level if there is any count in the B counter 20. In other words, delivers the output of the AND gate 384 an indication that the B counter 20 a Has a count that is greater than zero; this output signal is sent to the price coding circuit 22 and applied to the vending control circuit 30 as mentioned above.

The decoding circuit 24 (see Fig. 3) should do that Provide the complement of the sum of the output signals of the counters 14 and 20; this is done in the decoding circuit with the help of inverters 286, 288 and 290 as well as NAND gates 392 and 394 achieved the are interconnected in the manner shown. The output signals of the decoder circuit 24 are present on output lines 94,96,98,100 and 102; these Output signals indicate the various relationships that exist between the values contained in the A and β counters 14 and 20 are totaled or stored. These conditions are indicated by a Signal with a low level is on the respective output lines. For example is the one in that A counter 14 stored amount equal to the amount that

bo is stored in the B counter 20, it becomes Output signal on the output line 94 of the decoder have a low level, and the Output signals on the other output lines of the decoder will be high. Under the same

b5 point of view applies in a similar way: Is that in that Counter 14 stored amount is greater than the amount stored in the β counter 20, so the output signal on output line 96 is low

to have. If the amount in the A counter 14 is two, three and four increments greater than the amount in the β counter, the output signal on the output line 98 have a low level. If a coin tube switch such. B. the coin tube switch 108 s closed for the dime, this indicates that the tube is empty; then a signal with generated low on line 104 connected to line 396; this causes the Output on line 98 is blocked. If the counter 14 has a carry of three or more Increments compared to the counter 20, the output signal on line 100 will be a low Accept level to indicate this state. This condition is one of the possible, 5 Available states, but is not used in the circuit shown; however, she could be used in particular if the circuit would be adapted to other coin systems. Has the A counter 14 is five or more increments more than the B counter 20, the output is on the Line 102 assume a low level, if not at this time the switch UO for the empty The tube with the quarter dollar pieces is activated, causing a low level signal to be sent to the connected lines 106 and 398 and at the input to the logic element that is generated to the> 5 line 102 belongs to

The decoding circuit 24 has further connection and switching options which are intended to prevent certain output signals from occurring. For example, if the signal on output line 98 is low, this prevents the signal on line 96 from going low. This is achieved in the circuit by the line 400, which couples the output of the logic element belonging to the line 96, as will be explained later. Correspondingly, the following applies: as soon as the output signal on line 102 is low, it prevents the output signals on lines 96 and 98 from assuming a low level due to signals on line 402, line 402 being the output of the to output line 102 Associated logic element connects to the inputs of the logic elements which are assigned to the outputs 96 and 98. The result of this is: If there is a low level signal on the blocking> 5 line 398, the> 2 output signal on line 98 will assume a low level for each count in the A counter that is two or more ( 5, 6, etc.) is greater than the amount stored in the B counter 20. Similarly, if both inhibit input lines 396 and 398 are low at the same time, the signal on the> 1 output line% will go low for every count in the A counter 14 that is one or more increments greater than the amount in that B counter 20 is. As soon as a coin corresponding to five increments, e.g. B. a quarter of a dollar is not available for repayment or refund, the circuit indicates, as shown, that instead a two-increment coin such. B. a ten-cent piece should be paid back; if ten-cent pieces are also not available, the circuit indicates that repayments should only be made in coins corresponding to an hs increment, namely in five-cent pieces. It thus follows that the present circuit can be used with any known coin system regardless of the relative incremental values of the coins used, although some minor changes in the connections may be required.

The decoding circuit 24 has a further inverter 404 which is connected between the output output line 92 of the comparator circuit 16 and the various output logic elements of the decoding circuit 24. E.g. is stored. The output signals on line 406 are applied to the inputs of a multiplicity of decoder-output gates which contain a NAND gate 408; This logic element is the gate which generates the output signals on the line 94 to indicate the state in which there is equality between the amounts stored in the counters 14 and 20. The state of equality is, as indicated above, by a signal with a low level displayed on line 94; this always occurs when the signal on the output line 410 of the NOR gate 412 has a high level due to a signal with a low level on its input line 414. This is the case when the inverted or inverted output signal Si on the line 416 from the first stage of the adding circuit 330 indicates a zero state and when the other input signal to the logic element 412 on the line 418 as a function of the inverted output signals of the other adding circuit 332, 334, 336 and 338, which occur as input signals for a further NAND logic element 419 , has a low level. The output signal of the NAND logic element 419 is on the line 418 and on the connected line 420, a zero state being indicated by the state of the NAN D logic element 419. Under these conditions, a further NAND logic element 424 will indicate this state and generate a> 1 function on its output line 96 in that a signal with a low level occurs when this is on a line 426 (which is connected to the output line 94 of the logic element 408 is) the output signal fed to it has a high level, which indicates that there is no equality state A = B. The line 426 is connected between the decoder output line 94 of the NAN D gate 408 and one of the input lines to the NAN D gate 424, which is the> 1 gate. The conditions just described also require that a further input signal to the logic element 424 on the line 428 has a high level, which indicates that the amount in the A counter 14 is not less than the amount in the counter 20, that the Signal on the input 430 to the logic element 424 has a high level, which indicates that no

> 5 state is present, and that the signal on the other input line 432 of the logic element 424 is also high, indicating that it is not a> 2 condition.

Another NAND gate 434 is provided at the output of the decoding circuit and the

> 2 output line 98 assigned; this linking

The circuit provides a low level output when (1) the signal on input line 436 is high, indicating that counter 14 has an amount not less than the amount in counter 20, (2) the blocking input signal on the line 396 has a high level so that the logic element is not blocked, (3) the signal on the input line 420 from the output of the NAND logic element 419 has a high level, and (4) the input signal that it receives on line 402 (output line 102) is also high, indicating that there is no> 5 condition

Another NAND gate 440 assigned to the> 3 output line 100 of the decoder supplies a signal with a low level to represent the> 3 state. Although this state is not used in the circuit shown, it is available and occurs when the logic element input signal on line 406 has a high level at a time when there is also a high signal on the other input line 442 of the logic element Level, this line being connected to the output of the NAND logic element 392. A signal with a high level is present on this line when the input signal of the logic element is on line 444 due to the operation of another NAND logic element 446, which has an output signal with a high level level produced has a low level, the inputs of the NAND gate 446 are respectively connected to the outputs of the inverter circuits 386 and 388 generate the inverse of the output signals of the adder circuits 330 and 332nd The NAND logic element 392 also depends on input signals which it receives from the output of a further NAND logic element 448, in particular when signals with a low level are present on these inputs. The NAND gate 448 has direct input connections to the outputs of the adder circuits 334, 336 and 338 which are the adders associated with the third, fourth and fifth stages of counters 14 and 20, respectively.

Another NAND logic element 450 of the decoder is provided in connection with the> 5 output line 102 . NAND gate 430 then produces a low output on line 102 when (1) its input on line 406 is high, indicating that counter 14 has stored an amount no less than that amount is stored in counter 20, (2) inhibit input line 398 has a high signal so that it is not inhibited, and (3) its other input lead 452 also has a high signal. The line 452 is connected to the output of the NAND logic element 394 and always supplies a signal with a high level when the input signals to the logic element 394 from the adding circuits 336 and 338 in the comparator circuit 16 have a low level or when its other input signal is on line 454 is low. Line 454 is connected to the output of a further NAND gate 456 , which has two inputs, one of which is connected to the output of inverter circuit 390 on line 458 and the other on line 460 to the output of a further NAND gate 462 The NAND gate 456 will always provide a signal with a low level at the output 454 when the output signal from the adder circuit 334, which is inverted by the inverter 390 on the line 458 or vice versa, has a high level and its other input signal on the line 460 from the NAND gate 462 also has a high level. The NAND gate 462 provides a high output signal when

ίο either the output of the adder circuit 330 serving as the first stage or the output signal of the adder circuit 332 serving as the second stage is low.
The in F i g. Control circuits shown in Figure 3 provide a high degree of adaptability and choice in their construction and operation; furthermore, as illustrated, they can be used in a variety of different operating circumstances; these include B. several different purchase prices, different coin values, and a variety of choices with respect to the outputs generated. These possibilities are shown in the circuit shown in that the control for the sales control device, the payment control device, the reimbursement control device and the other associated circuits and switching elements are created.

Sales control details
at a purchase price

F i g. Figure 4 shows details of the circuit which is particularly designed to control a vending machine in which only one price is provided. In contrast to this, FIG. 5 shows a circuit which is intended to serve as a control circuit for a vending machine with two prices and which will be described later. The circuits according to FIGS. 4 and 5 also contain the details of the associated devices for the refund control and the payout control. The sales control 30 is controlled by the presence of a signal on its control input line 120 , which is connected to the output of the AND logic element 122. As already described, the AND element receives

Gating element 122 is input signals from the carry output of the comparator circuit 16, which are on line 92, and is used in the case of a carry output signal with a low level to indicate that the value stored in the counter 14 is equal to or

so is greater than the value stored in counter 20; Furthermore, the AND gate 122 receives signals from the ZJ counter 20 on the B> O line 124, which indicates. is that the B counter 20 has stored an amount which is greater than zero, so that a signal is generated on line 124 with a low level.

The purchase price entered in the β counter 20 is introduced by the price coding circuit 22 via the AND logic element 126 ; A high level signal is always present on its output connection 128 when the value stored in counter 20 is greater than zero. This condition is met when a signal rr> t is high on the decoder output line 94, which indicates that the values stored in counters 14 and 20 are equal, and when a signal with a high level is at another level Input line 470 to the logic element 126 is located. On line 470

a high signal occurs in response to a condition occurring at an inverter circuit 472 the point in time when a selection is made at the vending machine (not shown). These The change causes a current to flow from an input control terminal 474 (the one with the vending machine connected is) flows to activate an electro-optical device, which acts as an optical coupling device 476 is shown. The coupling device 476 works through an operating mode switch 478, whereby be ίο will cause the signals on input line 480 of inverter 472 to go low at the time Have level when the output signal on line 128 of logic element 126 is at a high level goes, thereby setting up circuitry to input the price into the S-counter 20. The real one Input is made by placing high level signals on designated lines 68-76; these Lines are connected between the price coding circuit 22 and the stages of the β-counter 20. This The sequence depends on the setting of a large number of switches connected to lines 128. These switches are indicated generally by the reference numeral 481 with their composite Adjustment states result in the sales price.

As in the pending American patent application Serial Number 3 31 380, the elements of the circuit associated with the optical coupling device 476 include resistors 482 and 484, a capacitor 486 and a diode 488 which are connected together in the manner shown. These elements and their interconnections enable the coupler 476 to vibrate or pulsate when a selection is made in the vending machine. The operating mode toggle switch 478 is shown in the drawing in a position in which stored amounts are paid back until a product is selected. If the operating mode switch 478 is moved to its opposite position, the result is that the set sales price is transferred to the counter 20 in the manner described as soon as a y-fc flip-flop circuit 490, also in the sales control circuit 30, is reset. If the j-Jt flip-flop 490 is clock-controlled or brought to a low state by a signal on its control input 120 from the logic element 122, the signal on its Q output terminal 492 goes to a low level, whereby its ./ -input 494 and its Jt input 496 also go low to prevent possible further clock controls of the flip-flop and to disable (keep its reset state low) the refund controller 26 by a signal appearing on the refund disable line 132. The time of sale is the time at which a vending relay 498 is energized and its contacts 500, which are in engagement with a stationary contact associated with a line 502, are toggled and come into engagement with a stationary contact associated with a line 504; This "> time of sale" is controlled by input signals or responses that are given by the y-it-rip-open circuit 490 via lines 508 and 510 to and through a NAND gate 506. The input line 508 is connected to the ζί output terminal t, 5 512 of the flip-flop 490 and has a high level signal as soon as the j-Jc-FWp- flop 490 itself goes high was high until the input to logic circuit 506 on line 510 was high and stayed_high until the low signal at the (^ output 492 allows a Capacitor 514 discharges through resistor 516; capacitor 514 and resistor 516 are connected in parallel and between the base of a transistor 518 and ground. The resistor 516 and the Capacitors 514 serve to drive transistor 518 forward and cause that the input signal to logic circuit 506 on line 510 goes low

Another AND gate 520 is provided to the / -Jt flip-flop 490 by signals which is received at its input port 522 whenever the refund control 26 is set, or by signals which are received on its other input line 524 if there is one on an output line 528 OR gate 526 a signal with a low level occurs This state is then when the signal at the input 530 to the logic element 526 after the time of Sell has a low level and if the signal at its other input 532 also has a is low, indicating that the same count reading in the two counters 14 and 20 This occurs either when the stored amount is equal to the sales price or when the change is paid out, as added to the sales price entered in the ß-counter causes the amount stored in the counter 20 to be equal to that stored in the counter 14 Amount is. If the amount stored in counter 14 is not equal to the amount stored in counter 20, after the time of sale is up, as indicated on line 510, it goes Output signal of a further inverter 534 connected to line 510 on line 536 to a high level. This signal with a high level is given as a control input signal to the OR gate 134 in the control circuit to the disbursement control 28 and causes a signal with high occurs on line 140 which is the control input line to the payout controller 28 is

If payment is to be made on the basis of a signal with a high level on the control input line 140, then a payout motor 540 is energized. This occurs because there is then also a high level signal on the Input line 542 of a further NAN D logic element 544 will be in order to represent the state when the amount stored in the counter 14 Therefore, the NAND gate 544 is closed at this point it has high level signals on its two inputs 542 and 140 at its Output 548 a signal with a low level appear, so that a transistor 550 through a Zener diode 552 in Is operated in the forward direction. Zener diode 552 is in series with the base circuit of transistor 550 a current limiting resistor 554 and with other series resistors 556 and 558 connected the are interconnected in the manner shown. The zener diode 552 is used for isolation between the Motor feed and the logic circuit. Another resistor 560 and a capacitor 562 are to a circuit in parallel with the payout motor

540 is connected to suppress the motor noise. Resistor 558 then turns off the Transistor 550 safe when not forwarding through NAN D gate 544 is operated. When the payout motor 540 is energized, it will operate some means to increment Withdraw coins. However, if the motor 540 is operated in conjunction with the relay 564, as later will be explained, it will pay out two increments of coins; the motor 540 is connected operated with a further relay 566, it becomes coins with a value corresponding to 5 increments pay off. The relay 564, which is used with 2 increments, is energized when on the two input lines 570 and 572 of a NAND gate 568 signals with a high level occur. On the entrance line 572 is a high signal when the input to an inverter circuit 474 is at Line 576 goes low. This occurs when there is a signal on the> 2 line: 98 low level.

The five increment relay 566 is energized when the NAND gate 578 hits the Lines 580 and 582 has high level inputs. The input signal on line 580 goes during a payout due to a high level signal appearing on the payout input control line 140 is high; the signal on input line 582 goes high, when a low level signal is present on an input line 586 of an inverter circuit 584. Line 586 is connected to the> 5 output line 102 from decoder circuit 24.

The payout control circuit 28 has output connections 160, 162 and 164 which are connected to the respective Input lines 52, 54 and 56 of clock 12 are connected as shown in FIGS. 1 and 2 shown is. The outputs from the payout control circuit 28 provide intermittent low level pulses, the program the clock circuit 12 so that the clock circuit each time one, two or five clock pulses will generate. Lines 160, 162 and 164 of payout control circuit 28 are each as outputs switched by OR gates 588, 590 and 592, which always deliver pulses when the Voltages on line 594 under control of the operation of payout motor 540 Assume level, the payout motor 540 a motor pulse switch 596 via a mechanical Connection actuated The temporary closing of switch 596 is effected by an I: pulse shaper circuit, which is formed by resistors 598, 600 and 602 and capacitors 604 and 606 that the Output pulses are generated which appear on line 594. The pulse shaper circuit is similar to that Pulse shaper circuit used in credit entry circuit 32 and used in conjunction with FIG. 2 is described. If the signal on line 594 is clocked low, it will OR gate 588 for edn increment the clock-controlled output signal] with a low level of the line 160 if at the same time the> 1 output signal on line 96 is also low. Similarly, the OR gate 590 provide an output pulse on line 162 when the > 2 output on line 98 is low; if that > 5 output on line 102 is low at a time when a signal is low on line 594, a pulse occurs on line 164. Closes the Motor switch 596, the capacitor 606 in the pulse shaper circuit discharges when each coin is paid out; this causes a high level signal through an inverter circuit 608 to appear an output line 610 which is the Bour control line shown in FIG. 1 also the reference

chen 48 wears. This signal causes the clock generator 12 to send signals to the B counter 20 instead of the / t counter 14. Thus, a signal on the line 48 has the effect that the clock pulses are directed to the counter 20 during the payout operation. If then the value stored in the B counter 20 is reduced to the amount which, during the payout, is equal to the value stored in the / 4 counter 14, a signal on the line 94 which represents this equality becomes a low Assume level, so that there is a signal with a low level at the output 528 of the logic element circuit 526, which is located in the sales control circuit 30. This low-level signal is connected to an input 612 of a further logic element 614 in the disbursement control circuit 28. If the signal at the other input 616 of the logic element 614 goes to a low level due to the state on the output line 140 of the logic element 134, the output signal of the logic element 614 on the line 618 will go to a low level, so that the counters 14 and 20 are reset by signals which are on the reset output lines 168 and 170, which are controlled by an inverter 620 and a logic gate circuit 622, respectively. These two circuits are temporarily clock-controlled by a circuit that includes a capacitor 624 and a resistor 626.

Refund Control Details

In Fig. 4 are details of the refund control circuit 26, which is provided, an inserted and added or stored To return the amount if no purchase or sale is achieved. The refunds take place under the control of the reimbursement switch which can be operated by an operator or a customer 144 when the movable switch contact moves from its normal to its repositioned position is moved. If the switch 144 is put into operation,

thus, a control input signal is thereby put on an input line 630 of the jk flip-flop 632, and the signal at that input goes high and then low. As a result, flip-flop 632 has a low level signal at its Q output 634. This also keeps the signals at j and k inputs 636 and 638 low so that further changes in state of the flip-flop can be prevented, although additional changes to the input line 630

eo could occur. The lockout output line 146 delivers Inhibit output signals from the refund controller 26 to the sales control circuit 30 in order to prevent the sales control circuit 30 from operating during the refund. this

b5 is caused by the y-it flip-flop 490 is held in its reset state by the low signal on the line 146 is fed to the reset input 640. A

Capacitor 642 and resistor 644 are also connected to the output circuit of refund flip-flop 632 to provide a low level signal to one of the inputs of logic gate circuit 622. The logic element 622 was described above in connection with the payout controller 28; its output line 170 is connected to the reset input Rb of the β counter 20. As already indicated, the payout controller 28 is controlled by a signal with a high level on the control input line 140, which is connected to the Q output line 646 of the refund flip-flop 632 through the logic element 134. If the payout controller 28 causes the counter 20 to store an amount equal to the amount stored in the counter 14, as stated above, an output signal will appear on line 94, this output signal being the signal for A = B ; this output signal is low and causes the refund control circuit 26 to be reset by a reset input signal which is provided on the reset input line 648 of the flip-flop 632. This signal is fed via a logic element circuit 650, one input of which is connected to line 94 and the other to line 132. It is then caused that the input signals on the two input lines 542 and 140 of the NAND gate 544 in the repayment control circuit 28 go to a low level; as soon as this happens, the repayment will be terminated.

Sales control details (more than a price)

Fig.5 shows an alternative embodiment of the Sales control circuit 30 according to the invention in which more than one sales price can be used. Sales control lines 660 and 662 on the right-hand side of Fig.5 yeast input signals to the To monitor selection in the vending machine and to create a control potential that is based on a further line 664 is available for two different purchase prices Switches 666, 668, 670, 672 and 674 are determined and set in the device; these switches are in a price coding circuit shown in the lower left corner of FIG. 5 is shown; the other purchase price is controlled by setting another set of switches 676,678,680,682 and 684, which are also located in the price coding circuit 22 are set and determined in the circuit. If a selection is made in the sales control circuit 30, the result is one way either from VerkauisSieuericiiüng 660 or from the vending control line 662 so that current flows from the line 686 through an optical coupling device 688 or 690. The current flows through the associated coupling devices is limited by associated resistors 692 and 694 and through associated diodes 696 and 698 rectified. The current flowing through these circuits causes the corresponding optical coupling device 688 or 690, each with a light-emitting diode 700 or 702, an associated phototransistor 704 or 706 irradiated. In the drawing, the light emitting diodes 700 and 702 separated from the associated transistor sections 704 and 706 of FIG the same arrangements shown. However, this is only intended to improve the clarity and clarity of the drawing increase; in actual construction, each diode will be in the same package with its associated Phototransistor arranged. A price selection has been carried out and the respective phototransistor 704 (or 706) is saturated (i.e. a good conductive current path between its collector and its emitter), clock pulses are applied to the clock input terminals 708 (or 710) of the respective y-jt flip-flops 712 and 714 given. this will happened as long as the payout control line 140 is not activated or a signal with a low If this happens, one of the flip-flops 712 or 714 is put into operation and the others not; the one of them who has a signal

has a low level at its ^ output 716 or 718, will cause the other, opposite flip-flop to be held in the reset state. This is achieved with the help of a circuit, the cross-coupled logic links 720 or 722 contains. These links are supposed to ensure that only one of the vend relays 724 or 726 can be energized at any one time. Transistors 728 and 730 are in the output circuits of the y-jt flip-flops 712 and 714, respectively provided to establish the connection between the sales relays 724 and 726 and the associated (^ -connections 732 and 734 of the flip-flops 712 and 714.

The reset inputs 736 and 738 of the flip-flops 712 and 714 are activated by the logic elements 722 and 720 controlled, which ensure the necessary low reset states as soon as the other, opposite flip-flop 714 or 712 is switched on by input signals that are sent to the respective Input terminals 744 or 746 of the linkage limbs occur at the times when at a Output line 748 of another UN D logic element 750 has a signal with a low level

The logic element 750 should always exert a reset effect in the reset circuit when a further optical coupling device, namely the optical coupling device 756 serving for resetting, is activated; this occurs during the Output of the item on when the carry output line 92 from the decoder circuit 24 is on Receives high level signal. Again, this happens when the Λ counter 14 stores an amount which is smaller than the price stored in the counter 20 as well as when due to a signal a line, such as on line 758 in Fig. 4, Total reset or total reset takes place

The vending control circuit 760 in Figure 5 (lower right corner) is switched in such a way that current flows through the optical coupling device 756 and through a light emitting diode (LED) 762 can flow. A Resistor 764 and a diode 766 are connected in series with light emitting diode 762 around the Control the size and direction of the current flow.

The light emitting diode 762 of the optical coupler 756 is located in the same Housing or jacket with a phototransistor 768. Once the selection of a special item is carried out and the clock control of one of the j-Jt flip-flops 712 or 714 is effected on a Line 770 with the help of an OR logic element 772 given a signal with a high level, the inputs 774 and 776 of the OR gate

772 are connected to the Q output terminals 732 and 734 of the flip-flops 712 and 714, respectively. The same signals with a high level also appear at the respective input connections 782 and 784 of further AND gates 786 and 788 and cause a signal with a high level to appear at the gate output 790 or 792 of the gates 786 and 788. The other input signals on lines 794 and 796 to the same logic gates are also high because they are connected to an output terminal 798 of an inverter circuit 800. The high level signal appearing on line 770, discussed above, is delayed somewhat by the influence of a capacitor 802, which causes the output signal of inverter circuit 800 on line 798 to go low at a somewhat later point in time, so that the The high-level signal that is fed to the price coding circuit 22 is temporarily clock-controlled in order to prevent any coding taking place during a payout

If the purchase price is determined by the coding circuit 22 on the basis of a signal on one of the lines 790 or 792 is encoded, an output signal will appear on the encoding output lines 68 to 76 which denote the ω Connect the encoder to the B counter 20. The entered, stored or totaled in the ß-counter The value is then in the comparator circuit 16 with the stored or summed value in the Λ counter 14 compared; as a result, a clock output signal is generated on the control line 120 of the sales controller 30 if the amount stored in the counter 14 is equal to or greater than that in the counter 20 Counter 14 does not have enough stored credit to make a sale, then this will cause Carry out on line 92 that another line 808 (FIG. 5) has a low Level is to reset the binary flip-flops 712 or 714 that triggered this process however, sufficient credit is available to control the timing of another y-Jt flip-flop circuit 810 in the vending control circuit 30 has the low level signal at its (J output terminal 812 has the effect that a Capacitor 814 discharges through resistor 816, causing delayed conduction through a associated transistor 818 results in the transistor Yefen then a signal with a high level a line 820 connected to the output side of an inverter 822. This state is for the ss Payout necessary, and the low level signal that appears on the output side of transistor 818 is also applied to an input port 824 another OR logic element 826. The logic element 826 in the circuit according to FIG is similar in structure and operation to logic gate 526 in the circuit of FIG. 4. It also has similar ones Connections and connections. The circuits belonging to the logic element 826, including the flip-flop circuit 810 and its connections and the associated circuit parts the elements described above with reference to FIG. 4th have been described.

If a signal rr.it is low on the input terminal 824 of the logic element 826 given, a signal with a low level is generated at the logic element output on line 828. This happens as soon as the other logic element input line 830 to the logic element 826 has a low signal indicating that either the one in the two counters 14 and 20 stored value is the same or that the value stored in the counter 14 is the purchase price exceeds. The signal generated on output line 828 of logic element 826 is low Level is given to an input connection 832 of a further logic element 834 and in addition used to reset the / - jt-FIip-Flop 810. Of the Flip-flop 810 can also be reset by a signal supplied on line 808 when on the output terminal 92 of the comparator circuit 16 has a high level signal. The same can also occurs when the refund output line 146 has a low signal appears.

A further logic element 836 is provided in the circuit assigned to the flip-flop 810 in order to control the blocking operation of the reimbursement control circuit 26 on the basis of a signal which is fed to it on the line 132 from the output of the logic element 836. This circuit is available when a signal with a low level is on the Q output line 812 of the flip-flop 810, while a signal with a high level is on the line 770, which is connected to the input of a further inverter 838.

So that purchases or sales can be carried out with even higher purchase prices, only additional switches for price coding and associated circuit components for isolation Serving link elements and the sales control are added, with all of these elements can be interconnected in a manner similar to that described above. Although the present invention using D-type flip-flops for counters 14 and 20 Moreover, using j-it flip-flops for these elements as well as other bistable elements can be achieved. The summing or storage device can also ring counters, shift registers, switching memories, counters that can count in both directions, and contain other binary storage arrangements. Furthermore, the facilities required for use in the comparator or decoder circuit, as described, were selected by exclusive-OR gates, symbolic or half adders and other conventional arrangements and techniques can be substituted. The device for generating pulses may be similar to that described in pending American patent application, Serial Number 2 67 558 (Levasseur) which is assigned to the assignee of the present application became. Other suitable pulse generating arrangements are also already known and can be used. Furthermore, the types and combinations of logic links and others Elements and their interconnections in some cases compared with those described here, specific embodiments can be changed significantly, without thereby changing the basic idea and dip

To leave the basic effects and operational processes as they are compiled and described here. Furthermore, for operational or cost reasons, some elements Ui.d features of the described Circuit can be omitted. For example, the refund control can be the feature that the payout in several coin denominations, and the use of photodiodes by other, similar ones Arrangements are replaced to which electrical and

include magnetic devices that can perform similar functions. In certain areas the circuit described, however, the use of photodiodes is preferred because of the Type of signals they generate as well as the type of Signals that the circuit can process and respond to. These elements are also relative small, reliable and relatively maintenance-free.

In addition 5 sheets of drawings

Claims (1)

Patent claims: 1. Control device for a vending machine with a clock that corresponds to the inserted coins generated coin value pulses for a first accumulator, with a second Accumulator for the purchase price of the goods, with one stored in the two accumulators Comparator comparing quantities and with one connected to the comparator, the output of the Goods marked only after entering a certain amount enabling blocking device through the following features: