DE2423456C3 - Circuit arrangement for error detection when evaluating signals which are derived from changes in status of a recording that take effect one after the other at periodic intervals - Google Patents

Description

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An exemplary embodiment of the invention is explained in more detail below with reference to the drawings.

F i g. 1 shows a circuit arrangement according to this exemplary embodiment;

F i g. 2 shows voltage diagrams for

According F i g. 1, a binary quantized read signal A obtained from a directional clock script is fed to the preparation input of a D flip-flop 51 and the preparation input of a D flip-flop 52. The reader signal A is also fed to an edge detector FD which outputs a short positive pulse B when a signal edge occurs, regardless of the direction. The pulses B are fed to an input of an AND element UX .

The output of the AND element U1 is connected to a clock generator TG , the frequency of which can be regulated and is equipped in a known manner with a flywheel effect, that is to say ignores short-term changes in the rule pulse intervals. For this purpose, the clock generator TG contains an oscillator OS which can be controlled in frequency and which is followed by a frequency divider flip-flop Π. The one output of this Fiipflops Tl is a further frequency divider FIipflop T2, and the other output (weleher the base position 1 is output) of the Fiipflops 71 is also a frequency divider flip-flop T3 nacheeschaltet. One output of the frequency divider flip-flop T2 is connected to a phase comparator PH for the purpose of supplying its signal D , to which, on the other hand, the output signals of the AND element C / l are also supplied. The phase comparator PH is followed by an integration stage IN , which in turn controls the oscillator OS and thereby ensures the flywheel effect. An output of the frequency divider flip-flop 7 "3 is connected to a second input of the AND element Ul for the purpose of supplying the signal C, which is periodically positive for half a period, thereby forming a time window during which the AND element 1/1 is permeable to pulses B and is so positioned that a regular change of state, which determines a data bit, occurs in the middle of this time window.

Each positive edge of the signal C becomes effective in the trigger input of the D flip-flop 51 and switches the D flip-flop to the value that the Sicnal A has at this point in time. The other output of the frequency divider flip-flop Γ3, which is the basic position I output, supplies the signal C, which is positive a quarter period after a regular data bit pulse, becomes effective in the trigger output of the D flip-flop 52 and sets it to the value which the reading signal A has at this point in time.

The basic position of the 1-output D-Flipfiops 51 provides a \ u ^c output signal E to an input of a Antivalcnzschaltung AV, the other input of the signal F of the non-basic position l Outbox of the D-flip-flop 52 receives. The output original G of the antivalence circuit AV is fed to the preparation input of a jk-skew flip-flop 53, the trigger input of which is fed with the output signal Ό of the base 1 output of the frequency divider flip-flop 7 "2. Home position 1 output emits a positive H signal.

The sienal C is also fed to an AND element i / 2, to which the signal E is fed to a second input. The output of the AND element U 2 supplies clocked data signals CE

On the basis of the stress diagrams in FIG. 2, in which the signal voltages with the same letters are designated as in Fig. 1, let the mode of operation of the circuit arrangement according to FIG. 1 continue explained.

According to line A , read signal A should represent information 01100100. The signal edges, which indicate the bit value, should follow one another with the uniform period P. In the case of the edge marking the fourth "0" to be displayed, which is indicated by the vertical arrow, however, the case should have occurred that this edge was read too early, more than a quarter period before the regular point in time. (The signal course, as it would be regular, is shown in dashed lines.)

In line B , there is one flank of the signal. 4 corresponding positive pulses are shown, which are output by the edge detector FD.

Lines Q and £ 3 show the output signals of the two outputs of the frequency divider flip-flop Tl. Which is switched back and forth by the oscillator OS with the frequency P 4. Each negative edge of the Q switches to Frequcnzteiler-FIipflop Tl, the signal D is then positive, respectively, at the same time when a pulse of the periodic ß Daienbits appears. Such pulses are output in the form of the signal BC from the AND gate t / l. This is because the output signal C of the frequency divider flip-flop 7 "3. Which is switched over by the negative edges of the signal ζ?" Becomes positive at time 3/4 P and negative again at time P / 4 of the following period intervening time is the AND gate Ul permeable to the pulses B. the originating from non-relevant state change pulses B will not be passed by the AND gate Ul. In the phase comparator PH pulses BC with the positive edges of the signal D are compared so to control the frequency of the oscillator OS via the integration stage // V and therefore to regulate the clock generator TG in accordance with the data bit frequency.

Line E shows the values to which the D flip-flop 51 is set by a positive edge of the signal C, i.e. at time 3/4 P. Since the value is tapped from the initial position 1 output, it is in each case the value ~ Ä. Line F shows the set values of the D flip-flop 52 set by the positive edges of the signal u, that is, at the time P / 4 of a subsequent period: Since "the value F is tapped from the non-Gundposition-I output , it is the value tapped at this point in time / 1. The antivalence glicd AV supplies a signal G 1 at its output if E and F are different and a signal G- 0 if the signals E and F are the same. The flip-flop 53 takes over the value of the signal G when 75 becomes positive, i.e. at time P / 2, and passes this value on with the negative edge of the signal Ό. At this time, the signal G must have the value 0, which means that the value FA

is equal to the value E = Ά set at the previous time 3/4 P, in other words that the value A at time / 74 of the period in which the measurement is made is different from the value A at time 3/4 P of the previous one Period. This is not the case with the test or "window" period between the times mentioned, which is represented by the positive phase of signal C immediately following the vertical arrow in line A , because the negative edge identified by the arrow of signal A has already been read before this "window cr" phase. The signal H therefore jumps at the point in time P / 2 of the last period P shown in line A , at which the

Failure to change "0" is detected at the regular time, to the value "1" and reports thereby the error.

The last line of FIG. 2 shows the signal CE E? Which appears at the output of the AND element U2. These are the values of the signal form E already containing the information read, which are present during those time phases in which the signal C is positive, in other words, to data to be read out in a clocked manner. The last positive phase of the drawn signal CE , which simulates the value “L” instead of the required “0”, is faulty, as indicated by the “!” Value of the signal H output immediately afterwards.

For this purpose 2 sheets of drawings

Claims (7)

'f ι 2 basic position O output of the other D-flip claims: Hops (52) to inputs of an antivalence element (A V) and its output to an i-enlersignal- 1. Circuit arrangement for error detection encoder (53) is connected. in the expansion of signals from in peri- 5 8. Circuit arrangement according to claim 7, daodic intervals are effective one after the other, characterized in that the Fehler.gnalgeber the change of state of a recording is a flip-flop (53) with a preparation such. B. the magnetic direction clock writing device input, which is derived from the output of the anti-derived, characterized by valence element (AV) is controlled, and a storage io triggering input clocked according to the periods, which is provided via one of the oscillator devices (51, 52), in which the values of a downstream frequency divider '/ 2-penode according to the read signal generated by the state change, a regularly expected state change which is activated during the second half of a period,
ode and the first half of a subsequent one Period occur, are saved, and a 15 comparison circuit (AV) connected to this memory, the inequality or equality The invention relates to a circuit on the periodic points in time of the status arrangement for error detection when evaluating alternately synchronized clock generator (TG) 20 of signals that are generated at periodic intervals with a flywheel effect, which the memory clocks one after the other evolving changes of state. a recording such as B. the magnetic direction 2. Circuit arrangement according to claim 1, data clock script can be derived. characterized in that the clock generator 3ei the directional clock script, which is part of the (7G) synchronizing pulses via an AND gate 25 technique of recording binary values on a (U 1), to which the signals of a read signal - magnetizable surface is generally known, are edge detector (FD) and from the clock generator Output derived signals are fed, testifies whose respective direction the desired which activate the AND gate, while a value of the bit indicates that this flow change is made when Time in which a periodic change of status, 30 uninterrupted reading at periodic intervals but no one that occurs outside of this period is effective in relation to one another. For recording on each other Change of state is regular? U expected. the following constant bit values must also be 3. Circuit arrangement according to claim 2, da- lent flux changes are interposed, which are characterized in that the clock generator consequently when reading only from case to case and therefore (7G) an oscillator 35 controllable in frequency did not occur periodically. Of these flux changes gate (OS) , the frequency of which is a multiple generated read signals must be distinguished from the relevant signals (data bits) of the period of the periodic state change and then subtracted, furthermore an oscillator must be connected after the oscillator, for which accompanying signals are used, frequency divider ( 71, 72, 73) as well as a phase comparator 40 will hold a phase comparator 40 for the control of the oscillator in synchronism with the relevant flux changes. (PH), the clock edges of the frequency tuMers and it is known, with the help of the flux change the output signals of the AND element (t / l) to signals of synchronized circuits the lack of be guided. ben of flow change reading signals to determine and 4. Circuit arrangement according to claim 3, to take suitable measures for this case, characterized in that an integrating stage 45, for example, the German Auslegeschrift 20 64 255th (IN) between the phase comparator (PH) and the present invention makes this possible Oscillator (OS) is switched. if, but also pursues the task, too 5. A circuit arrangement according to claim 4, da- such errors to be recognized, which are characterized by reading that the AND element (Ul) signals can result which, for. B. by read signals of the oscillator (OS) downstream 50 peak shift ("peak shift"), considerably wider frequency divider (73) are supplied in such a way that their set times occur accordingly. that the AND gate for half a period. To solve this problem is according to the invention odendauer is activated, which a quarter periodi: a circuit arrangement of the aforementioned before the normally expected change of state Type characterized by according to the peri- begins. 55 barren clocked storage devices in which the 6. Circuit arrangement according to claim 1, da- values of a generated by the change of state characterized in that the quantisierfe read-read signal, each during the second half signal the preparation inputs of two of a period and the first half of an after-D flip-flops (51, 52) and the period following the trigger input are stored, of the one D flip-flop (51) has a switching edge 60 and a Ver - '/ 4 period connected to this memory in front of a regularly expected co-ordination, the inequality or equality Change of state and the trigger input of these values determines in connection with an on other D-flip-flops (52) a switching edge the periodic points in time of the state change to -'Λ-period after this change of state, train-synchronized clock generator with flywheel leads will. 65 effect, which supplies the memory clocks. 7. A circuit arrangement according to claim 6, there being further designs according to the invention characterized in that the basic position of such a Schahungsanordnung go out of the sub-1 output of the one D flip-flop (51) and the claims.