DE2335989C3 - - Google Patents

Description

The invention is concerned with a problem that occurs with bucket chain circuits, such as those for example from "IEEE Journal of Solid-State Circuits", June 1969, Pages 131 to 136, are known occurs. Such bucket chain circuits have a variety of similar stages, each consisting of a transistor and one between its control terminal and whose collector terminal are located capacitor and are connected in series in such a way that the collector connection of one is connected to the emitter connection of the next following transistor, wherein the control terminals of the even-numbered transistors from a first square-wave clock signal and the control terminals of the odd-numbered transistors of a second rectangular and equal frequency clock signal are controlled, the effective pulses in the gaps between the effective pulses of the first clock signal lie. Such bucket chain circuits are in the Literature also referred to as shift register or delay line for analog signals.

The problem with such bucket chain circuits is that the DC voltage level migrates to higher or lower values in the course of the bucket chain circuit, this DC voltage level from the DC voltage applied at the input of a bucket chain circuit, the the signal to be delayed is superimposed, and the

Composed equal part of the signal to be delayed. This drift of the DC voltage level is, for example, in isolated field effect transistors built up bucket chain holdings due to the fact that at low clock frequencies a drift of the direct potential in the direction of the substrate potential caused by the reverse current of the diffused zones is, while on the other hand at high clock frequencies the DC voltage level in the opposite direction, due to surface conditions, emigrates. With bucket-chain circuits made up of bipolar transistors the base current of the transistors causes an effect corresponding to the latter the DC voltage level.

In bucket-chain circuits constructed from bipolar transistors, this problem is encountered according to the above-mentioned reference by so-called level regeneration circuits tried to solve, but in these circuits also the one to be delayed Signa! reinforced An application of this well-known principle in bucket chain circuits made of isolated Field effect transistors also only allow compensation for that caused by surface conditions Effect, while the DC voltage level drifts towards the substrate potential with the known Circuit cannot be prevented.

It is the object of the main patent to provide an improved DC voltage compensation circuit for bucket chain circuits specify, in particular in the case of bucket-chain circuits constructed from isolated field-effect transistors allowed to restore the drifted DC voltage level Level correction circuit automatically adjusts the original DC voltage level, i.e. in a self-regulating manner Way, restore. This problem is solved by the main patent in that the one input of a differential amplifier, the direct component of the potential at the collector connection of a bucket chain input Transistor and the other input the direct component of the potential at the collector terminal of a bucket chain input remote transistor is supplied, which two transistors are controlled by the same clock signal, and that one of the two output signals of the differential amplifier capacitive to the collector connection of one of the transistor remote from the bucket chain input preceding transistors is supplied

In further investigations made by the inventor, it was surprisingly found that in addition to the im Main patent specified solution still another possible solution to the problem of the main patent gives. It is therefore the task of the present additional application, within the scope of the task of the main patent to specify this further solution. This solution specified in claim 1 is based on the knowledge of the inventor that it is not absolutely necessary to capacitively apply the correction signal to the bucket chain circuit but that it is possible to convert the correction signal of the differential amplifier into a proportional To derive a current pulse that can be fed galvanically to the bucket chain circuit.

Further developments and preferred exemplary embodiments of the invention are set out in the subclaims and are now identified together with the invention with reference to the one shown in the drawing Figures explained in more detail.

Fig. 1 shows the Pititzip of the invention Solution;

Fig.2 shows a level correction circuit for a consisting of p-channel insulating layer field effect transistors Bucket chain switch;

Fig, 3 shows a level correction circuit for a consisting of n-channel insulating layer field effect transistors Bucket chain control, and

4 shows the principle of a two-stage self-regulating level correction circuit using the principle according to the invention.
In the upper half of Fig. 1 are scheme.tisch

ίο some stages of a conventional bucket chain circuit EK shown from the course of the bucket chain circuit, which, as is well known, can have a number of stages in the order of a few hundred, the number of stages depending on the intended delay time and the maximum signal frequency to be transmitted in Fig. 1 the stages itj, π— 1, η and π + 1 shown The stages m and π are controlled by the first clock signal Φ \ and the stages λ — 1 and n + l by the second clock signal Φ ₂ Each clock signal consists of a square-wave voltage of the same frequency, which is related to the circuit zero point, wherein the amplitude of the one clock signal lies in the gap between the effective pulses of the other clock signal and vice versa. Here, the duty cycle of the clock signals can be 0.5; However, it is of course also possible to choose a pulse duty factor that deviates from this pulse duty factor in such a way that gaps occur between the effective pulses of the two clock signals, during which both clock signals are zero.

The mode of operation of such a bucket chain circuit is known to be that at the end of a Clock pulse every second stage, i.e. every odd-numbered or every even-numbered stage, a piece of signal information in the form of an amount of charge stored in the capacitor belonging to each stage, while the capacitors of the intermediate stages are discharged and therefore no information contain.

<O.as the invention underlying principle of DC voltage level regeneration or maintenance of the input DC voltage level now exists therein, the potentials of a bucket chain entrance near and a bucket chain entrance distant stage according to the corresponding Suppression of the signal component fed to the two inputs of a differential amplifier and a current pulse proportional to its output signal to one of the transistor remote from the bucket chain input to supply the preceding transistors galvanically in the correct phase.

In the schematic diagram according to FIG. 1 is this stage dfe preceding stage η remote from the bucket chain entrance, stage n-1 directly preceding stage. The first delaying stage of the bucket chain circuit is preferably chosen as the input-close stage m , at the collector connection of whose transistor the DC potential still has its full setpoint value, which ensures optimal control of the bucket chain circuit. The signals picked up at the collector connections of the two transistors of the stages m and π are each fed to the two inputs E \ and Ei of the differential amplifier DK1 via the high-value resistors Rg ι.

The high-ohmic resistors in the main patent specified transistors are used.

Furthermore, the two inputs of the differential amplifier are each connected to the Schaltungsiiullpunkt via the capacitor Cg ι, the resistor

value of Ray and the capacitance of the capacitor are chosen such that this RC combination acts as a low-pass filter for the signal frequencies of the bucket chain circuit to be delayed. If the bucket chain circuit is implemented in an integrated form, the filter capacitors will usually not be able to be integrated because of their large area requirement, but will be connected from the outside to the integrated circuit. The low-pass filter associated with the bucket chain input can also be replaced by an adjustable DC bias of the differential amplifier input E \ , so that the DC potential at the beginning of the bucket chain circuit is simulated.

The two stages m and n. At which the input signals for the differential amplifier DVX are picked up, are both even-numbered stages, the stage numbers now correspond to the transistors

7m Tmn, Tm, 2 · T _n \, T _n and 7 " _nt ι.

These transistors are linked to the associated capacitors Cin of the type described above and connected in series. The potential U _n at the collector connection of the transistor T _n is fed to one input E \ and the potential LZ _n at the collector connection of the transistor T _{n is} fed to the other input E _{2 of} the difference in amplifier DVX. The difference nm does not necessarily have to be an even number. If it is an odd number, it must be ensured with clocked transistors as high-ohmic resistors Rc \ that these are controlled by the same clock signal as r> the transistor to which the resistor Rc \ is connected. This differential amplifier consists

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it is guaranteed that the two stages are always in the same state. Of course you can two odd-numbered stages are also used to decrease the input signals of the differential amplifier DVI which are then connected to the clock signal <f »2 would be.

| c depending on how the control electrodes of the additional transistors serving as high-ohmic resistors are activated, the mean constant potential averaged over all time intervals or the constant potential averaged only over the collector connection clock periods of the transistors of the stages m, η can be generated at the inputs of the differential amplifier. The last-mentioned mean DC voltage potential is naturally higher than the DC voltage potential averaged over all times and is therefore, under certain circumstances, better suited for turning on the amplifier transistors of the differential amplifier DVX.

In the schematic diagram according to FIG. 1, the output signal of the differential amplifier DVX is now fed to the controllable constant current source RSQ , the output current pulse i _r of which carries the stuff π-1 7ii £ = galvanically directly preceding the stage η. The output of the controllable constant current source is galvanically connected via the emitter-collector path of the additional transistor T * ₅ to the stage n- 1 of the bucket chain circuit EK , the control connection of the additional transistor 7 "being controlled by the second clock signal Φι, that is, by the same clock signal, which also controls the stage to which the current pulse from the constant current source is fed galvanically.

The current pulse supplied by the controllable constant current source; _r is to a good approximation a linear function of the control potential Ur- Furthermore, the current pulse / _r for a certain control potential t / _r o is zero, this control potential U _r o is defined by the fact that it occurs when at the inputs of the differential amplifier no difference signal is applied, ie when the two input potentials are equal to one another. Finally, the polarity of the current pulse /, - is reversed when the control potential U _{r runs} through U _r o , so that the following applies as a good approximation:

ir = g <(Ur-U _r0 ),

where go essentially corresponds to the steepness of the transistor T _r

In Figure 2, an embodiment of the invention is shown, which is constructed from p-channel insulating layer field effect transistors, which are preferably designed as an integrated circuit. The above-mentioned from /.wci τ cräiafKcriräfiSiSim 6Π ümu / two 5i5 LuSi'wiucr states connected transistors, which are connected together with the operating voltage Uo \ . The emitter

2 »connections of the two amplifier transistors are connected together via a constant current transistor to the circuit zero point , while the control connection of the constant current transistor is connected to the constant voltage U01. The construction of the differential amplifier DV 1 is therefore of the usual type.

Dz :. with respect to the collector potential difference U _n - U _m between the transistors T _n and T _{m not} inverted. The output signal of the differential amplifier DVX is now used as a control potential i / _{r of} the control electrode of the

thus operated in the emitter circuit transistor T _r supplied, which is complementary to the other transistors of the overall circuit, that is, this transistor is an n-channel insulating layer field effect transistor. Its emitter is at the negative potential Up, while its

Ji collector via the additional transistor Ts, which is in turn a p-channel insulating layer field effect transistor, is connected to the collector of the transistor T "- \ of the bucket-chain circuit EK. The control electrode of the additional transistor T ₅ is connected to the second clock signal Φ-> via the capacitor Cc ₅ and also reads via the high-resistance Res at the potential Ucs.

At the collector connection of the transistor T _n -; A further p-channel insulating layer field effect transistor Tk is also connected, the control terminal of which is connected to the clock signal Φ2 via the capacitor Cck, to the circuit zero point via the capacitor C _m and to the constant potential Uck via the high-value resistor Rck.

Thus, the transistors 7 "" _ i, 7 " _s and Tk are always turned on or blocked at the same times. The DC potentials Ucs and ί / c * are dimensioned so that the transistors T _s and Tk are fully conductive during the corresponding half-periods of the clock signals are or are fully blocked. If necessary, the transistor T _r can be blocked directly by the control potential U _r during the corresponding half-periods. If this is guaranteed, the additional transistor T _{5 can be} dispensed with.

The clock pulse amplitude effective at the control connection of the additional transistor Tk is thus

U _rB =

• (U _1. = Full clock amplitude)

The DC potential Uck and the clock pulse amplitude UcG can be selected, for example by

suitable dimensioning of the capacitances C _Gk and C _{m so} that the current h flowing through the transistor T _k just compensates the current flowing in the transistor 7 " _r in the case of U _r = U _r0 , so that the control current pulse / V becomes zero.

(The sign of the current pulse i _r can be reversed by swapping the differential amplifier output.

The circuit of the controllable constant current source shown in Fig. 2 remains completely equivalent in its function if the transistor 7> instead of as η-channel as p-channel insulating layer field effect transistor and the additional transistor 7 * instead of p-channel as n -Channel insulating layer field effect transistor and the potential U ₁ at the respective emitters is interchanged with the reference potential and vice versa. At the same time, the control of the transistor T _k must also take place from the other clock signal, that is to say the clock signal Φ \, and the DC potential U _G k must be adapted accordingly. If the control is changed accordingly, the additional transistor 7 ″ can also be replaced by an n-channel insulating layer field effect transistor.

Of course, the differential amplifier DV1 can also be constructed differently; for example, the constant current transistor of the differential amplifier DVX can be replaced by a complementary, that is to say n-channel, transistor which, however, then has to be between the two load transistors and the direct potential Ud t . Furthermore, the two parallel inverters of the differential amplifier halves can also be replaced by two inverters (CMOS inverters) implemented using complementary insulating layer field effect transistor technology. On the other hand, however, all transistors of the differential amplifier can also be replaced by complementary ones and the potentials exchanged.

FIG. 3 shows an exemplary embodiment of the invention with n-channel insulating-layer field effect transistors which, with regard to the choice of transistors, is thus completely complementary to the exemplary embodiment according to FIG. In particular, the transistor T _r in FIG. 3 is a p-channel insulating layer field effect transistor. Furthermore, at all those circuit points at which in FIG. 2 is the potential of the circuit zero point (with the exception of the connection of the capacitor C _n , at the circuit zero point), in FIG. 3 the potential U _{p is} connected, while at all points at which the potential U _D \ or U _p is in FIG , in Fig. 3 is the potential of the circuit zero point. What was said in the explanation of FIG. 2 with regard to the possible modifications also applies in a corresponding manner to the exemplary embodiment according to FIG. 3, so that reference can be made to the relevant details set out above.

In Fig. 4 finally shows the principle of repeated equal-level regeneration. For this purpose, the control current pulse i _{r is} fed again galvanically at the required level χ above level nl. Both control current pulses originate from the same controllable constant current source RSQ, which must only be provided once. In this case, the constant current source can be connected to the corresponding stages of the bucket chain circuit EK via decoupling resistors R.

For this purpose 4 sheets of drawings

Claims (9)

Claims; 1. Bucket chain circuit with a large number of similar stages, each consisting of a transistor and a capacitor lying between its control terminal and its collector terminal and connected in series in such a way that the collector terminal of one is connected to the emitter terminal of the next transistor, the control terminals of the even-numbered The transistors are controlled by a first square-wave clock signal and the control connections of the odd-numbered transistors are controlled by a second square-wave and constant frequency clock signal, the effective pulses of which are in the gaps between the effective pulses of the first clock signal, whereby according to patent 23 1/252 one input of a differential amplifier is the The direct component of the potential at the collector connection of a transistor near the bucket chain input and the other input is supplied with the direct component of the potential at the collector connection of a transistor remote from the bucket chain input, which two transistors are controlled by the same clock signal, and one of the two output signals of the differential amplifier is capacitively fed to the collector connection of one of the transistors preceding the transistor remote from the bucket chain input, characterized in that instead of one of the two output signals of the differential amplifier (DVl) a current pulse proportional to it (i _r ) one of the transistors preceding the transistor (T _n ) remote from the bucket chain input is fed to the collector connection not capacitively but galvanically 2. Bucket chain circuit according to claim 1, characterized in that the current pulse (i _r ) is generated by a constant current source (RSQ) controlled as a function of the output signal (U _r ) of the differential amplifier (DVL) 3. bucket chain circuit according to claim 1 or 2, characterized in that the collector connection of the bucket chain input near transistor (T _n ,) and the collector connection of the bucket chain input remote transistor (T _n ) each via a high-resistance resistor (RaOmH the corresponding input of the differential amplifier (DVi) and via One filter capacitor (Cat) each is connected to the circuit zero point such that the resistor and filter capacitor act as a low-pass filter for the signal frequencies of the bucket-chain circuit to be delayed. 4. bucket chain circuit according to one of claims 1 to 3, characterized in that the output signal of the differential amplifier (DVl) proportional current pulse ß) to the collector of the bucket chain input remote transistor (T _n ) directly preceding transistor (7 " _B _i) is fed galvanically. 5. bucket chain circuit according to claim 4, characterized in that with respect to the collector potential difference (U _n - U _m ) between the bucket chain input remote (T _n ) and the bucket chain input near (T _m ) transistor non-inverting μ output of the differential amplifier (DVi) with the input of the Controlled constant current source (RSQ) is connected, that its output is connected via the Emitter'KoIlektor path of an additional transistor (TJ to the collector terminal of the directly preceding transistor (77 >> -1) and that the control terminal of the additional transistor from the clock signal (Φ2) of this transistor is controlled. 6. bucket chain circuit according to one of claims 1 to 5, characterized in that the current pulse (i _r ) is equal to zero when the two input signals of the differential amplifier (DVl) are equal to each other. 7. bucket chain circuit according to claims 5 and 6, characterized in that the collector connection of the immediately preceding transistor (Γ ,, - ι) in addition to the current pulse one of a Additional constant current source generated, constant and so adjustable additional current pulse supplied is that when the input signals of the differential amplifier (DVL) are the same, the total current pulse equals zero 8. Bucket chain circuit according to claim 7, characterized in that the constant current source consists of a transistor (T _r ) of conduction type complementary to the other transistors of the overall circuit and the additional constant current source consists of a transistor (Tk) of the same conduction type as the other transistors of the overall circuit and that the transistor of the additional constant current source is controlled _{by the clock signal (Φ 2} ) of the immediately preceding transistor (T _a - \) 9. bucket chain circuit according to one of claims 1 to 8, characterized in that as Transistors integrated insulated gate field effect transistors of the enhancement or depletion type and integrated as capacitors Serving capacities.