DE2326798B2 - CONTROL DEVICE FOR A SERIES PRINTER - Google Patents

Description

The invention relates to a control device for controlling a serial printer, which has a print logic has a data input, a constant drive mechanism, an anvil and a Print head, which is optionally driven by actuating a clutch that is parallel to the anvil and is automatically returned to the rest position when the clutch is released, the Control device is inserted between the data input and the print logic, and a register with an output connected to the print logic and with an input for the momentary storage of a single character, through a buffer register with a

The input for the serial input of digitally coded characters and an output for serial output of the digitally encoded characters to the register.

Such serial printers have a simply constructed drive mechanism and a high pressure

speed. However, they are only suitable for synchronous operation, i. H. for simultaneous data entry at the entrance of the printer. When used in conjunction with an input memory, they are also fed with input data that is faster than the printing speed can be entered as long as the capacity of the input memory is not exceeded. You read z. B. not feed with a typewriter-like data entry, the data flow is much lower than the printing speed, namely only a few characters per second in the Compared to a printing speed of 180 characters per second, for example.

In the case of data input with a lower data flow than the printing speed, up to now only increment printer used, d. H. Printer with a stepper motor. Such printers are however, it is costly because it has a complex control circuit for the motor and an expensive motor demand.

The invention is based on the object of providing a control device of the type mentioned at the beginning create, which an asynchronous output of alphanumeric characters regardless of the rhythm Entering the same allows between zero and a maximum, through the properties of the printer using an automatic mail merge printer.

When the rhythm of entering characters is equal to or faster than the printing speed of the Printer, the latter works continuously. However, if the rhythm of data entry is slower, the printer works step by step.

The solution to this problem is given by an addressing device for the buffer register input, which indicates the address of the last character given to the buffer register input by a Adiessierereinrichiung for the buffer register output,

each the address of the first to the buffer register output to be forwarded indicates by a logical comparator, which the buffer register input address constantly compares with the highest address and with the buffer register output address, by an operation control device which, depending on your comparison result of the comparator the input of a character to the input of the register or the transmission of a Character at the output of the same releases, and by a marker device to mark the through the printhead assumed position when the addresses coincide and to control the return of the printhead to the rest position in the event of coincidence and to control the speed of the printhead along the anvil until the assumed position is exceeded, if after one Coincidence new characters are entered.

Further developments are characterized in the subclaims.

The invention is illustrated below with the aid of schematic drawings of an exemplary embodiment described in addition.

FIG. 1 is a schematic view of a known printer for use in conjunction with "5" with the invention;

F i g. 2 is a block diagram of a printer according to FIG the invention;

Fig. 3 is a block diagram of the control device of the invention;

Figs. 4 and 5 are diagrams for illustrative purposes the mode of action, and

Fi g. 6 and 7 are flowcharts of operation control for the input and output of the controller, respectively according to Fig. 3.

Fig. 1 shows in detail an example of a printer for use in the present invention.

The printer uses a print head 1 which rests movably on two guideways (not shown) which run parallel to an anvil or plate 2 which does not move axially. The head is moved evenly from left to right by means of a drive belt 3 which is looped through two disks 4 a, 4 b. The disk 4 a is driven by a motor at constant speed, for example a drive device 11 in the form of a synchronous single-phase motor, which rotates at constant speed in the direction of the arrow, by an electromagnetically connectable belt and a S ° disk clutch 10 the electrical supply device for the motor, the clutch and the control device for the clutch are not shown since they are conventional and known. ; i5

If the electromagnetic clutch 10 is released, the print head automatically returns to its Rest position at the far left end back. This is done by a spring 6, which is normally with connected to a buffer which is not shown. One end of the spring is connected to the head 1, the other end with the frame of the device, which is symbolically marked with 13. the Spring 6 can of course be replaced by any other preloading system (for example electromagnetic).

Actuation of clutch 10 causes the head to begin moving to the right from its rest position. In order to ensure that the printing process is only carried out when the head is moved uniformly, the beginning of the printed line is shifted from the rest position. For this purpose, a photo-coupling arrangement 7 consisting of a light source and a transducer detects the passage of the head, and the latter actuates a cover plate 5 which normally covers the light source. As soon as the cover plate is actuated, a line start signal DL is generated.

A regularly slotted disk 9 connected to the photocoupling device 8 (light source and a transducer) generates a signal DC which synchronizes the start of printing of a letter. The signals DL and DC are applied to a conventional print logic 12, which receives coded input data at the input end 14 from an external control device (not shown) and controls the operation of the head.

For this purpose, the printing logic 12 controls under the control of the data applied to the input 14 and the signals DL and DC

- (i) the paper crack, via a to the

Plate applied line feed signal LF;

- (ii) the printing process, via a Si

gnal CI, which is applied to the head in order to control the pressure elements of the head (actuation of selected electromagnets in the case of a head of the type mentioned above), and to the coupling 10 for energizing the same,

- (iii) the continuous movement of the head,

if no printing is performed, by means of a signal HT (tabulation signal) to insert a space or a space bar either at the beginning of a line or during a line.

When placed in coded form data recorded to the input 14, it is decoded in the print logic and, if there are letters signals in synchronism with the signal DC to the inputs you head control set, while the logic at the same time the excitation of the clutch ( Signal C /) controls. In order to achieve correct operation, the letter data must be applied to input 14 at printing speed; they can also be applied to the input at greater speed if the printing logic has a memory.

When the print head reaches the rightmost print position, a known one, not shown, controls Detector (a photocell array or any other device that indicates the end of the line) the de-excitation of the clutch 10.

With this type of printer, the speed of data entry cannot be slower than the print head. Either the clutch is not energized if no data appear for printing and irregular spaces would appear between each letter, and depending on the work of the print head between the recording of successive data,

5 or the clutch is entregi (what rucisiciis the Case is) and the head is moved back to its rest position: In the latter case, the successive Data either printed on top of each other

or at the beginning of consecutive lines, when the paper is moved further by de-energizing the clutch.

Printers of the type described above can be made into pseudo-incremental printers. by the control device according to the invention between the data input 14 and the printing logic is installed, the block diagram of which is shown in FIG is.

The basic idea of the invention that an incremental operation of a synchronous printer is the following: If in a certain If there are no more letters to be printed, the position of the After the last letter has been printed, while the head is in its rest position far left is moved back, the return of the printhead not from a paper crack is accompanied.

As soon as new letters arrive, the printing process starts all over again, in the same place Line as before return of the head to the rest position, starting with that on the last one printed Letter following position.

For this purpose, the control device consists essentially of a buffer register 101 of the RAM (Random Access Memory) type, the output of which is connected to the print logic 12 via an output register 314, of devices 17 and 18 for the respective display of the input address AE and the output address AS to the register , from a logical comparator 304, which compares these addresses with one another and with the maximum capacity of the register, from a sequence control device 20, which enables the input of a character into the register or the output of a character from the register, depending on the results of the comparison in the logical comparator 304, as well as a device 21 for noting the position of the print head when the printing process is interrupted and for controlling the return of the print head to its rest position and then to the position following the last print position as soon as a letter character arrives at the input 14 is placed.

Fig. 2 is a general block diagram illustrating the logical functions of the various α basic elements of the control unit 15. The enable signals from the sequence controller 20 to the register 101 through the pipes 20 and 20 b is fed. The signal OKE on the line 20 a connects the input 14 to the buffer register 101 and controls the transmission of an input character to the register at the address AE, while the signal OKS on the line 20 b the transmission of the character in the buffer register at the address AS to output register 314. When a signal TJKS (the complementary signal to OKS ) is supplied, the sequence control device 21 notes the position of the print head and sends an instruction character to the output register via the line 21 α , which is not fed by the buffer register 101 at this point in time Head to be returned to its rest position, signal CRF which, in the case of the printer shown in FIG. 1, increases the cost of de-energizing the clutch 10). When the sequence controller 21 provides another OCS-S'ignal, 101 triggers the coupling there buffer register to the register 314 via the line 21 h, the means 21 controls the now CJI <return of the print head in the following on the lelzti Druckposilion position.

F i g. 4, 5 a and 5 b illustrate the effect of data recording and printing of the individual Letters.

The buffer register 101 comprises, for example, 25f memory units, each of which is a group of cS bit and forms an octet that

ίο through the corresponding address a, b, c, d, e. . . (Sub-units 101 «-101 e. Fig. 4) is specified. In the figure it is assumed that each memory position in the row of data acquisition has received the characters A, B, C and D , whereby the individual successive characters can of course be separated from one another by any time interval.

Two addressing devices are assigned to the buffer register 101, namely an input addressing device 17 and an output addressing device 18, which determine the address of the character entered last, that is, in the special embodiment according to FIG. 4, the addresses d and α of the characters D and A. that each time a new character is entered into the buffer register, the input addressing device 17 is indexed one step to the right, and that each time a new character is output, the output addressing device 18 is indexed one step to the right independently of the input addressing device. If the characters A, B, C and D have been successively entered into the buffer register 101, which form the word ABCD , the input

addressing device 17 successively the addresses a, b, c and d .

Assuming that the print head has a proper position, the Ausgangsadressicreinrichtung 18 denotes the initial position 101 α in the buffer register 101 and outputs the output of the character A free. Then the process continues character by character as a function of the step speed of the print head, the positions 101 b, 101 c and 101 d of the buffer register 101 being designated and the output of the characters B, C and D respectively being enabled. Once the position 101 d iereinrichtung by the Eingangsadres & 17 is referred to, the word / 4BCD is output. At this moment, the control device 21 controls the return of the print head to its rest position, under the action of the spring 6 (Fig. 1). Since there is no paper jump (or line feed), this position is just before the beginning of the line that has just been printed and which is referred to in the following as the "print line". Due to the inertia of the print head, a small space is provided between the rest position and the beginning of the print line to regulate the distance between the individual letters. The address of the most recently output character D is stored in an auxiliary memory so that the printhead can resume forwarding immediately after a new character has come to the position where it is to be output. This is done by generating

a number of spaces equal to the content of the auxiliary memory (MerkeinTichtung).

The addresses contained in the two addressing devices are, as will be explained below

is determined, and the comparison of the contents from the auxiliary memories gives the acquisition or the output free of characters in or from memory.

The different positions of the buffer register 101 are of course not always manned. They become free every time a new character is output will. Special facilities are provided to block the output of characters when the buffer register is empty and to block the detection of characters when the buffer register is occupied is, which is equivalent to limiting the displacement of the two addressing devices 17 and 18 in Fig. 2.

FIG. 5 shows another possibility in which the output of a word or a character takes place after a number of spaces. As shown in FIG. 5, before the output of the character Z η = 19 spaces are inserted, starting from the beginning of the line. First the code "tabulate" is introduced into the successive positions of the buffer register 101, as shown in FIG Corresponds to spaces. This number is converted to binary code and finally the code of the character, such as Z, is output. The successive analysis of the contents of the successive positions of the buffer register 101 by the output addressing device results, according to FIG.

This feature of the controller gives the advantage of having a number of locations in the memory that would otherwise be saved for the consecutive 2 Generation of several tab codes would be required, ur.d that the digit acquisition speed at the same time is incremented for the following characters.

Theoretically: The OKS signal appears as long as there is at least one character in the buffer register 101. The OKE signal appears as long as the buffer register is not filled, ie as long as AE <256 in the present example. In practice, input and output to and from the buffer register are not completely simultaneous. And, therefore, means are provided to synchronize input and output, as described below in relation to a FIG. 3, namely a master clock generator 504, which supplies release signals, will be explained in more detail.

The buffer register 101 according to FIG. 2 is formed here from a RAM (Random Access Memory) which has a capacity of 256 groups of eight. Input and output lines of device 101 are shown here as single lines, but in reality there are eight parallel lines for input and eight parallel lines for output. Eight lines are also provided for inputting and outputting data.

Each time a character arrives at input 14, a counter 302 is incremented; this counter designates the address where this character must be registered in the register. Likewise, a counter 303 is incremented whenever a character is removed from register 101 and designates the address where this character can be found.

Thus, the operating address AD is optionally indicated by the counters 302 and 303, which each have 8 bits and can therefore address the 256 memory positions of the buffer register. The content of these counters is decoded in the decoder 309. The arrangement 302-309 corresponds to the device 17, the arrangement 303-309 of the device

ίο 18 of F i g. 2.

The conditions under which a signal is entered into the memory register 101 are: Register not full and output address AS φ input address AE; a signal OKE is then generated.

The requirements for the output of a signal are: register not empty, output address AS φ input adires.se AE (namely AS <iAE, since AS> AE impossible); an OKS signal is then generated.

For this purpose, a flip-flop 400 is brought to "1" via the carry pulse from counter 302 (state R) and back to zero (state H) via the carry pulse from counter 303. Since the logic circuits 401 each have two inputs which are connected to the outputs of the comparator 19 or the flip-flop 400, they generate the signals

OKE = Ή. (AE φ AS), OKS = R. (AE φ AS).

The sequence control unit 20 according to FIG. 2 becomes from the two devices 316 (input sequence control unit) and 317 (output sequence control unit).

The OKE signal is applied to device 316, while the OKS signal is applied to device 317. These two devices are also driven by the master clock 504 so that the output signals do not appear at the same time. Although the master clock 504 is shown in the figure as part of the control unit 15, it is understood that the output signals of the master clock, which is normally part of the conventional print logic 12, are used. can also be applied as signals to the sequence control devices 317 and 318.

Each seven-bit character to be entered into the buffer register includes a signal SE which is applied to the input sequence controller 316. As long as the signal SE is present.

the tensions must be absolutely stable. While the data signal is formed from eight logical levels which are applied to eight feed lines in parallel, the signal SE is applied to the unit 316 via a separate line. For the sake of clarity, however, all external control signals are drawn in such a way that they lead to a single end point 14.

The input unit 316 consists of two bistable! Devices HE _V 316 a, 316 b, HE ". It can be triggered in four different states, as the table below shows, where HE ₁ and HE are the bistable states of 316 a and 316 b

HE ₁

HE ₁

State

0 0 1 1 0 2 1 3 609 527/2

t ίο

State 0 is the idle state, the buffer register is waiting for a character to be entered.

When the OKE signal is present, the SE signal causes the unit 316 to cycle:

State 1: The one indicated by the counter 302 Address becomes stable;

has been registered), this character is supplied to register 314.

If it is not a function character, the contents of the counter 312 are read.

If the character is other than zero, the print logic receives a number of spacing commands equal to the MCC contents of counter 312 before the print control signal is applied to the print logic.

This arrangement enables tabulation

State 3: the input signal is written into the buffer register when the signal E - HE ₁ .

Sign al HE ₁ means state 1 of 316a, and io at each desired address in one line. The TTET _x means state 0 of the same. Σ is pres- Tabuliercode HT, which is stored before the next book-end, wherein L indicates that the output sequence bars (this is a feature which is located on the control unit in the state 1 or 2, the general input 14 down signals) enabled what the latter is explained further below, and it is clear that the distances that should be tabulated, which correspond to the reading of a ^ letter or a 15 from the beginning of the line to the next printed ^ -i - .. ijjr, ... rr,. Letters to be stored in unit 312.

When a signal appears at the output of the buffer register 101, it triggers the "minus" input of the Device 312 and thereby causes a downward counting the device down to zero, the counting 3 d

Corresponds to the tab address from the buffer register;

State 2: Acknowledgment signal ACK from the buffer register to the external control unit controls the deletion of the signal SE, and, if the latter is off,
Return to state 0.

g,

Counting device 312 sends to register 314 distance signals ESP which are applied to the printing logic, thereby causing the displacement of the head along the anvil and no printing

6 shows the flow diagram of the unit 316.

When the OKS signal is present (which means that

at least one character takes place in the buffer register 101 25. For this purpose, a flip-flop 3 * i9 "is registered), controls the output sequence control unit 318 is set to the state" 1 "if that means the transmission of characters that is recognized by the code HT. Flop 319, address AS are registered in 101, when an 8-bit off is in the "1" state, it triggers the sequential setup register 314., "Ng 317, which then increments the counter 303.

As already mentioned, these characters are either 30 tated, so that the address AD of the tabulation in the "print codes", ie codes that skip the printing of buffer register 101 and effect the flip-flop on letters (it is essentially zero is postponed

loaned by letter codes) or "function codes", the output sequence control device consists of

such as tabulator, line feed, where all three bistable devices -HL ₁ IiL and HL _x function codes the forced return of the head in 35 It can be carried out according to the table below in eight different states cause the rest position.

The data at the output of the register 314 are decoded in the decoder 318. If a letter code is recognized by the ~~ decoder, it increments a letter counter 310, the content of which CC must not exceed 133 letters per line. If a function code is recognized, the counter 310 is reset to zero.

If at a given point in time the buffer register is empty ((JKS) and the last code read from the buffer register was not a function code, the content CC of the letter counter 310, which is not equal to 0, is stored in a further counter 312, its "plus""Input to the counter 310 and whose" MINUS input is connected to the output of the buffer register 101; MCC means the value stored in the counter 312. At the same time, the counter 310 is reset to zero again, and the

Code FCR (forced return of the printhead) becomes

Via a signal generator 402 to the register 314 55 with the information data'spe'isL 'to the input 14, from where it is fed to the printing logic. is placed; the signal SE is fed together with ai (the codes CA and FR are the same, the letter F is data information and lasts until there is only used here to indicate that the acknowledgment signal ACK from the buffer register ar not controlling the return of the head by a the external control device is generated by the latter registered input characters, but is generated by the control 60,
unit is generated.) The first clock pulse after the start of de;

The signal CR is then also generated by the generator signal SE triggers the unit 316 from the Zu 402 (an encoder that generates an 8-bit signal code 0 in the state (1) the state (1) duration), if the content CC of the counter is equal to until the signal I triggers it in the state (3) JV + 1, where N is the maximum number of books 65 It should be mentioned again that the signal L is on bars in a line , about JV = 133. shows that no reading is taking place at this time

When the signal OKS reappears (ie when det. The state (3) corresponds to the writing time ii at least one more character in the buffer register the buffer register. When writing end

HL ₃ HL ₂ HL ₁ State η 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4th 1 0 1 5 1 1 0 6th 1 1 1 7th

Only seven states are used (0, 1, 2, 3, 4, 6 and 7).

It should be mentioned once again that the signal SB is controlled by an external control device which controls the prints!

is, the ACK signal triggers the unit 316 into state 2.

The time span (W) required for writing is the sum of the time for the state (1) in which the address is stabilized and the time for the state (3) in which the actual writing process takes place. When the writing process is finished, the OKS signal can appear. Then triggers the next Uhrimpuls the Sequenzsleuereinrichtung from state 0 to state (1) or (2), depending on whether a Tabulierzeichen has been detected (condition 2) or not (state 1). The next clock pulse triggers the device into state (3) in which various functions are performed, as indicated above and as in the flow chart of FIG. 7 is shown.

When a signal Cl is present (i.e. when a letter character has been decoded), the next clock pulse triggers the unit 317 in state 7. The confirmation signal PEC from the printing logic triggers the unit 317 in state 5. The next clock pulse starts the state (4th ), in which the signal CRF is recognized if it is present.

To enable the function of the complete Sleuc purely direction To understand, three selected operating cases are discussed below.

1. Operational case

At the moment when the printing is finished, the next * characters of the text should all be stored in the buffer register 101 (i.e. OKS ^ 1 during the entire output process, whereby only the last character corresponds to a function as determined by a decoder 318 is detected, which is connected to the output of the output register 314 ).

When the output sequence control 317 passes through state 1, the output register 314 is loaded with the character to be printed.

In state 3, when MCC = 0, only the increment formation of the output addressing device 303 alone is carried out. In state 7, the print control signal C1 is sent to the printer via the output sequence control 317 , and the character counter 310 is incremented. This state ends when the PEC signal from the output sequence controller 317 has been received. The sequence control moves from state 4 to state 0, whereby no signal CRF reaches the sequence control (which is the case if either the content of the character counter 31O = CC = O or if the presence of OKS CC is different from the number of characters, in the lines.

The sequence control cycle is synchronized with the printer and enables the characters * - 1 to be displayed.

Since the last character is a function, the 10th cycle of the sequence control in state 7 causes the character counter 310 to be reset to 0 by the output sequence control 317. As soon as the function has been carried out, the sequence control returns to 0 and waits for the next output enable signal OKS.

2. Operational case

Assume that if χ characters have been printed, OKS = O , although the line contains x + y characters, and that only the character x + y represents a function.

If the printer has 132 characters per line,

the character counter 310 outputs a signal CRF , which indicates the accelerated return of the print head, either if the counter content is CC- 132 or if in the absence of OKS, CC is different from 0. The functional sequence for the * —1 characters is identical to that for the first

ίο case described process.

If for the x. If the sequence control is running through state 4, the CRF signal is present. The output sequence control 317 is designed such that a transition from state 4 to state 6 is achieved under these conditions.

In state 6, the code CR (carriage return) is entered in the output register 314, and the content CC is stored in the auxiliary counter 312.

The rapid return of the print head is achieved in the printer during the status 7 and 5 subsequent runs.

In state 4, the signal CRF is no longer present, since CC = 0 now, and consequently the output sequence controller 317 moves to state 0.

After the printhead has come to rest again, the value OKS becomes effective when new characters are entered in the memory register 101 , so that spaces are generated by a .v-times transition in state 3 under the condition MCC ψ 0. If these .v spaces are generated, printing of y characters is carried out as in the first case.

3. Operation case

If one now considers the case of tabulation, with the OKS signal being present during the entire operation, which is usually the case, then the memory register 101 contains the text A to be output and the tab code HT and then the tab address AD and a text B.

The output of the text A takes place by continuing the output sequence control 31 7 according to the cycle 0, 1,3, 7, 5, 4,0.

When the code HT arrives in register 314 , the signal CR is transferred to this register and a tabulator flip-flop 319 is switched. This flip-flop thus stores the code HT and allows the transition of the output sequence control 317 from state 0 to state 2. The exit sequen; Control 317 is set up in such a way that it memorizes the tabulator address at this time (RAM z ± MCC) and that the output addressing device 303 advances so that the address AD in da:

Buffer register 301 and the flip-flop after (

is postponed. Once that's done, give the sequence control the passages through the Zu 0.1 and 3 would be free.

When passing through state 3, de counts

Counter 312, since the code stored in register 314 is not a function code and since the MCC count is not 0, goes down, so that blanks are carried out until MCC becomes 0. This is done by forwarding the output sequence control 317 after cycle 0, 1, 3, 7, 5, 4, C If MCC = 0, the output of the text i from the address AD + 1 is carried out.

When using the control device according to de

Invention can come in handy when the input speed the digit is below the maximum speed of the printer, the pressure one Execute the line of characters by moving the printhead in the same translatioiis from each other by a return

rows row gelrenni binu. «^. - -.—- · - —-

especially with mosaic printers, s.ch e.ne ß width

Execute STSTSd ^ by placing the print head * £££ using several consecutive tiandatious movements 5 senrgru »

In addition 5 sheets of drawings

Claims (4)

Patent claims: 1. Control device for controlling a serial printer, which has a printing logic with a data input, a constant drive mechanism, an anvil and a print head, which is optionally driven by actuating a clutch that is parallel to the anvil and is automatically brought back to rest position when the clutch is released , wherein the control device is inserted between the data input and the print logic and a register (314) with an output connected to the print logic and with an input for the momentary storage of a single character, digitally coded by a buffer register (101) with an input for the serial input Characters and an output for the serial output of the digitally coded characters to the register, characterized by an addressing device (17, 302, 309) for the buffer register input, which in each case indicates the address of the last character given to the buffer register input, by an addressing device (18, 303 , 309 ) for the buffer register output, which indicates the address of the first character to be forwarded to the buffer register output, by a logical comparator (304, 19, 400, 401), which constantly compares the buffer register input address with the highest address and with the buffer register output address, by an operation control device ( 20, 316, 317), which, depending on the comparison result of the comparator, enables the input of a character to the input of the register or the transmission of a character to the output thereof, and by a memory device (21) for flagging the value generated by the print head in the event of coincidence the address position and for controlling the return of the printhead to the rest position in the event of coincidence and for controlling the rapid advance of the printhead along the anvil until the assumed position is exceeded when new characters are entered after such a coincidence. 2. Control device according to claim 1, characterized in that the input and output addressing device comprises a first and second counter (302, 303) , which are each incremented when a character is given or outputted to the input. 3. Control device according to claim 1 or 2, characterized in that the memory device comprises a third counter (310) which is advanced by one unit with each character step of the print head, and a fourth counter (312) into which the content of the third counter is given when an address match occurs, the content of the fourth counter being reduced by one with each step of a new printhead advance, and that furthermore an enabling device is provided for outputting the first character stored in the buffer register when the content of the fourth memory has become zero . 4. Control device according to claim 1 to 3, characterized by means (318) for determining a tab code, by means (319, 310, 312) for incrementing the count value of the second counter (303) and for preventing the output of a character until that counter exceeds the tab address.