DE2233556A1 - ARRANGEMENT FOR THE FORMATION OF THE CONTROL IMPULSES FOR THE ELECTROMECHANICAL DRIVE OF AN ELECTRONIC WATCH - Google Patents

Description

Our reference: S 2715

SESCOSEM - Societe Europeenne de Semiconducteurs et de Microelectronique
101, vol. Murat
75! Paris I6e, France

Arrangement for generating the control pulses for the electromechanical drive of an electronic clock

The invention relates to an arrangement for the formation of Pulses necessary for controlling the drive of the electromechanical Part of an electronic clock are determined, the arrangement in particular a pilot oscillator, an electronic frequency divider »a DC power source and a display system, for example from one Includes stepper motor driven pointer.

For this purpose, pulses of precisely defined duration, for example in the order of one millisecond, are used required, which drives a stepper motor with a repetition frequency of the order of 1/2 Hz to 2 Hz steer. Furthermore, in the case of so-called "bipolar" Motors require two control pulse trains of the same duration and the same repetition frequency, with the pulses of one Sequence are offset from the pulses of the other sequence by a time interval that is equal to half a time

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Subsequent period is. The two pulse trains are therefore interleaved in time.

It is "known to generate such control pulse sequences by a logical function Decoding of signals is carried out at appropriately selected points of the frequency divider stages a frequency divider to which the signal of a pilot oscillator is fed. However, this method has some disadvantages, namely:

- a large number of connection points between

the frequency divider stages and the decoding circuit

- the need to use two separate decoding circuits in the case of bipolar motors, that need two nested pulse trains}

- There must be considerable changes to the decoding circuitry and made on the connections to change the characteristics of the pulses.

The aim of the invention is to eliminate these drawbacks.

In the arrangement according to the invention, at the outputs of predetermined stages of a frequency divider circuit the following two pulse trains were taken:

1. Synchronization pulses, the duration of which is equal to the duration of the desired control pulses;

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2. Follow-up period pulses, the duration of which is equal to half the follow-up period of the desired control pulses.

These two pulse trains are fed to certain inputs of a logic circuit, the two synchronizable Contains flip-flops that are connected as a "mother-daughter flip-flop". The synchronization pulses are fed to a clock input (or synchronization input) of the first flip-flop, while the complementary Synchronization pulses are fed to a clock input of the second flip-flop. The operation of the trigger circuits controlling subsequent period pulses are fed to another input of the first flip-flop.

The control pulse trains are decoded by decoding the output signals at predetermined outputs of the two Receive flip-flops; this decoding takes place in two logic gating circuits, for example AND gates, the first of which is a control pulse train and the other supply the offset control pulse train. "

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The invention is described by way of example with reference to the drawing. Show in it:

1 shows a basic diagram of the arrangement according to the invention,

2 shows the scheme of a possible embodiment of the bistable multivibrators in the arrangement of Figure 1,.

3 shows a diagram to explain the mode of operation,

4 shows a further diagram to explain the mode of operation and

5 shows the diagram of an arrangement according to the invention with an additional adjusting device.

In Fig.1 a part of the electronic circuits of a clock is shown. On the one hand, this includes in conventional V / eise a frequency divider whose divider stages N, N-1 ... n, n-1 ... 2.1 in cascade between the Output 0 of a pilot oscillator (not shown) that sends a high frequency signal, for example 32 kHz supplies, and a consumer terminal S for signals with a reduced frequency of, for example 1 Hz are connected. Each stage divides the frequency that it emits from the output of the previous stage (or in the Case of level N from the output of the oscillator. ) receives by a constant factor, for example the Has value '2. On the other hand, these electronic circuits include an arrangement for generating control pulses

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and Mg. This arrangement contains two synchronizable bistable flip-flops B ^ and Bg, and two AND gates 21 and 22-.

The circuit is structured as follows: The output of the stage η of the frequency divider is connected to an input T. the bistable trigger circuit B ^ and via an inverter connected to an input T of the bistable multivibrator Bg. The input Ϊ is complementary to the input T. This means that the flip-flop Bg its state then changes when its input signal is complementary to the input signal of the flip-flop B ^.

The output of a frequency divider stage of low frequency, for example stage 1, is connected to an input J of the multivibrator Bj. The trigger circuit Β * has two mutually complementary outputs X and X, and the trigger circuit Bg has two mutually complementary outputs Y and Y.

The inputs of the AND gate 21, which supplies the pulses M ^ at its output, are connected to the output X or the Output Y connected; the inputs of the AND gate 22, which supplies the pulses Mg at its output, are with connected to output X or to output Y.

Before the mode of operation of the arrangement of Fig.1 closer is described, an embodiment of the two bistable flip-flops B ^ and Bg in more detail Details are described; these flip-flops are in Figure 2 inside the dashed rectangles shown. The flip-flops contain combinations

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of logic gates and inverters, where the gates are opened and closed by the synchronization signals coming from the output of stage η and are denoted by H in FIGS. The AND gates and 32 control the accesses to NAND gates, respectively are formed by an AND gate 33 or 34 with a downstream inverter circuit 35 or 36, respectively. The circuits 33, 34, 35 and 36 form as a result of the connections between the output of the inverter 35 and an input of the NAND gate 34 and between the output of the Negators 36 and one input of the NAND gate 33 a Toggle switch. The same measures are also associated with the trigger circuit Bg, in which the logical Circuits 41 to 46 correspond to circuits 31 to 36. The synchronization signals H are via the Terminal T is fed to the synchronization inputs 311 and 321 of AND gates 31 and 32, respectively. The complementary Signals T * are applied to the corresponding inputs 411 and 421 of AND gates 41 and 42, respectively. Every Flip-flop, which has two possible stable states, forms a memory flip-flop that contains binary information can save. The inputs T and T * allow a new binary information value to be entered into one or the other memory.

The JFolgeperiöd-Bnsignale coming from the output S with the lowest frequency on the frequency divider of FIG R are fed to the flip-flop circuit B ^ via the input J, which is connected to an input 312 of the AND gate is connected directly and to an input 322 of the AND gate 32 via an inverter 24. The output of the negator 35 is connected to an input 412 of the AND gate 41, and the output of the inverter 36 is connected to an input

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of the AND gate 42 connected. The terminals X, It, Y, Y shown in Figure 1 are connected to the outputs of the inverters 35 and 36 of the flip-flop B ^ and the inverters 45 and 46 of the flip-flop B ₂ .

The operation of the system is based on the response of the trigger circuits B ₁ and Bg to the input pulses. The type of response of the trigger circuits is in! Pig '. 3 is shown for the general case that the LOlgeiodenixnpulse R arriving at the input J and the one at the inputs T and Ü? incoming synchronizing pulses H are not synchronous (ie that the leading edges begin to rise at different points in time) and that the waveform of the pulses is not exactly rectangular. As far as the pulses H are concerned, these must exceed the threshold values for opening the Uhd circuits, which are not arbitrary. These threshold values are shown in Fig. 3 and correspond to the changes in state listed below:

- threshold X ,. : Closing the AND gates 41 and 42 through

the effect of the complementary momentum T,

Threshold V ₂ : opening of the AND gates 31 and 32 by the action of the pulses H (at the terminal T);

Threshold V ^: Closing the AND gates 31 and 32 by the Effect of the impulses H;

- threshold

.: The AND gates 41 and 42 are opened by the action of the pulses T.

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-B-

There is therefore the following double condition, which is nothing more than the condition of a "mother-daughter" Operating "is:

v ₂

It is now known to construct AND gates with a predetermined threshold value, for example in the case of AND gates with diodes and resistors in that a corresponding: value for the respective resistance of the AND gate is determined. If the so-called "threshold condition" is not met, the state changes of the control signals sufficiently fast compared to the settling time of the signals inside each flip-flop.

The complete investigation of the voltage states of the components of the flip-flop circuits B ₁ and B ₂ gives the results shown in the diagram of FIG.

This diagram shows the high potential (state 1) at W ^ and the low potential (state 0) _{at W Q.} At each point E, the potentials are plotted on the ordinate (EW axis) and the time on the abscissa (Et axis). The lines a, b, c, d parallel to the axis EW represent characteristic times of the state changes of the AND gates.

With regard to the output voltage X and Y, the diagram can be interpreted as follows:

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1. The pulse R at terminal J becomes output X first transmitted at time b, i.e. with a delay of at least (b-a).

2. The impulse. R becomes output Y only at time d transmitted, i.e. at least with a delay (d-a).

3. Thus the leading edges of the pulses are X and Y offset from one another by a time interval (d-b) which is of the order of magnitude of the duration of the synchronizing pulse H lies.

For this reason, the trigger circuit system (the can be implemented in a different form than the form described) also type "V" flip-flop (for delay) called.

4 shows a diagram to that of FIG. 3 is analogous _t but recognize the full period of the signals R 'can be. If this period is denoted by D and I is the duration of the pulses R, if one works with divider stages of the division factor 2 and with square-wave signals, then i applies

D = 2 I ".

The output pulses of the synchronizable toggle circuits have the same duration I and the same period D. However, the pulses X and Y are against each other by an interval i offset, which is substantially equal to the half cycle of the H pulses.

The performed by the AND gates 21 and 22 (Fig.1) Decoding corresponds to the following logical products:

M ₁ = X: * Y - M ₂ = 1 * Y

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It should be noted that for the implementation of the deco, dation logic circuits of the type "And", "Or", "Not-And (NAND)", "Not-Or (NOR)" are used can be. Depending on the type of circuit used / ended, the output signals M- ,, Mp are then negated and / or with each other · permuted.

The diagrams of the pulses M and Mp are shown in FIG. It is to be noted:

1. That their duration is essentially equal to the duration i j

2. that its subsequent period D ^ is equal to period D;

3. that their leading edges are offset from one another by a time interval of duration I.

The invention., Of course, is not related to the one described and examples shown. In particular, it is possible:

- to change the duration i by using synchronization signals which are at the output of another Stage of the frequency divider can be removed. . \

- To change the period D by using pulses R which are at a different stage than at the Stage 1 can be removed. In certain cases the frequency divider can be equipped with an additional frequency divider stage which is connected to the output S of stage 1, and then the signal R at the output this additional stage decreases.

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- To increase the number of flip-flops IL and B 2 in order to obtain pulses whose duration % is multiplied by _{2, 3, 4, and so on.}

Another advantage of the arrangement described arises from the possibility of adding a simple control system for the operation of the flip-flops so that the display can be changed, ie the time can be set. For example, the parts 51 to 57 shown in FIG. 5 serve this purpose. Two AND gates 51 and 52 are connected between stages 1 and 3 in the manner shown in FIG. Gate 51 and the input 522 of the AND gate 52 is connected, while the input 511 of the AND gate 51 is connected to the output of stage 3 and the input 521 of the AND gate 52 is connected to the output of stage 1. The input 512 is either connected to a potential W,. or applied to the ground potential W _Q. The outputs of the AND gates 51 and 52 are connected to the two inputs of an OR gate 53, to whose output one input of an AND gate 54 is connected. A second input of the AND gate 54 is connected through a changeover switch 57 either to the potential ¥ ^ or to the ground potential W _Q , and the output of the AND gate 54 is connected to the input terminal J of the first flip-flop B ^.

Based on these additional measures, the Set the time by changing the operation of the multivibrators. This process works as follows away:

a) Shutting down the motor, which as a result of the blocking of the AND gate 54 (changeover switch 57 at ground potential W _Q ) does not

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Receives more control impulses;

b) the motor continues to run rapidly by opening the AND gate 51 (changeover switch 56 at potential W ₁ ) and the AND gate 54 (changeover switch 57 at potential W ₁ );

c) normal further running of the motor by blocking the AND gate 51 and opening the AND gate 52 (changeover switch at ground potential W _Q ), while the AND gate 54 remains open (changeover switch 57 at potential W ₁ ).

In Fig.5 is; a wiring rail 50 is shown, which makes it possible, by making a solder connection, to switch the synchronizing input of the flip-flops B ₁ and Br to the output of the desired level n + 1, η or n-1 and thereby affect the duration of the pulses.

All of the circuits described and illustrated above can be implemented as integrated circuits. Ever according to the different models of electronic clocks that differ from each other by the electromechanical Partly differentiate, the various possible wirings can be carried out in that only the metallization masks be changed slightly, which is an additional advantage of the arrangement described.

The arrangement described is also suitable for an electronic clock that replaces a stepping motor or, in addition to this, contains a pulse counter which, by delivering currents at predetermined time intervals luminescent elements, such as electroluminescent diodes excited.

Claims

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Claims (9)

Claims (iy arrangement for the formation of the control pulses for the electromechanical drive of an electronic clock with a pilot oscillator, a frequency divider circuit with several stages of higher rank, of middle rank and of lower rank, an electric stepping motor, the operation of which is controlled by the control pulses of predetermined duration and frequency, and with a direct current source, characterized in that at least two logic arrangements (B ^, B ₂ ; Pig.1 and 2) are provided which can store binary information that the first logic arrangement (B ..) has a first input (J ), which is connected to the output of a _{frequency divider stage of low rank which determines the frequency of the control pulses (ML f} M ₂ ), a second input (T) which is connected to the output of one which determines the duration of the control pulses (M ^, M ₂ ) Frequency divider stage of middle rank is connected and two mutually complementary outputs (X, ΪΓ) for a direct logi cal signal or a complementary logic signal that the second logic arrangement (B ₂ ) is the same as the first and has at least one first input which is connected to an output (X, X) of the first logic arrangement (B ₁ ), a second input (T ") which is connected directly or via an inverter (23) to the second input (T) of the first logic arrangement (B ..), and two outputs (Y, T) for a direct logic signal or respectively . A complementary logic signal, and that at least one logic AND gate (21, 22) is provided for the decoding, which has two inputs connected to the direct output (X) of the first logic arrangement (B ..) and the complementary Output (T) of the second logical arrangement (B ₂ ) 209884/0968 or to the complementary output (3c) of the first logic arrangement (B ^) and · the direct output (Y) of the second logic arrangement (B ₂ ) are connected, and at the output of which the control pulses (M,., M ₂ ) are emitted will. 2. Arrangement according to claim 1, characterized in that two AND gates (21, 22) are provided for decoding for the delivery of two sequences of control pulses of the same duration and the same subsequent period, which are temporally shifted from one another, one of which is and Gate (21) is connected to the direct output (X) of the first logic arrangement (B *) and to the complementary output (Y) of the second logic arrangement (B ₂ ), while the second AND gate (22) is connected to the complementary Output (Y) of the first logic arrangement (B ^) and the direct output (Y) of the second logic arrangement (Bp) is connected. 3. Arrangement according to claim 1, characterized in that the decoding effecting logic circuit depending on the use of the control signals (Mi, M ₂ ) by at least one gate of the type "NAND", "Or", "NOR", • Antivalence ""Equivalence" is formed. 4. Arrangement according to one of claims 1 to 3, characterized in that the storing logical input Orders (B ₁ , B ₂ ) are formed by flip-flops of the type "V" or equivalent, which are connected as a "mother-daughter flip-flop". 5. Arrangement according to one of the preceding claims, characterized in that it is in the form of integrated Circuits is formed. 209884/0968 6. Arrangement according to one of the preceding claims, characterized characterized in that the connection between the output of the frequency divider stage of middle rank and the second Input (T) of the first logic arrangement (B-j) a wiring arrangement (50) to change the rank of the frequency divider stage which determines the duration of the control pulses is inserted. 7. Arrangement according to claim 6, characterized in that the wiring arrangement is a rail (50) which optionally connected to the output of one of several frequency divider stages (n + 1, n, n-1) by soldering can be. 8. Arrangement according to one of the preceding claims, characterized in that the first input (J) of the first logic arrangement (B,.) to the output of a Operating control circuit is connected, which contains a gate circuit (54) for blocking the control pulses, depending on a hand switch (57) and a by a further manual switch (56) dependent system of AND gates (51 »" 52) and OR gates (53) controllable in this way is that the output of the frequency divider stage (1) of low rank through the output of a frequency divider stage (3) replaced by a higher rank and thereby the repetition frequency of the control pulses can be changed. 9. Arrangement according to one of the preceding claims, characterized in that the control pulses for the Actuation of a non-mechanical display device can be used. 209884/0968