DE2201856B2 - PROCEDURE FOR INFORMATION TRANSFER IN A PCM SWITCHING SYSTEM - Google Patents

Description

40

The invention relates to a method for transmitting various types of information in a PCM switching system, in which the PCM words arriving in a first cycle of channel intervals over a synchronizer is written into a data register in a second cycle of channel intervals channel numbers are assigned to the channel intervals and the position of the channel numbers of the incoming channel intervals in the second cycle of the channel intervals as a function of the phase difference between these channel intervals and the channel intervals of the first cycle of channel intervals is changed, and the number of time slots in reading the various types of information from the Data register is greater than the number of time channels in the second cycle of time channels.

The data register permanently assigned to the first time channel determines the position of the first time channel in space. By reading this register in the Time intervals of the second time channel is a connection (switched in time) between the first and the second time slot maintained. In such a connection information can be lost, if the data register is written in a faster sequence than it is read out. The consequence of the Registration depends on the sequence in which the iformation of the first time channel is received,

60 while the sequence of reading is determined by the transmission of the telecommunication switching system.The two sequences are nominally the same, but can achieve an unrestricted phase difference in non-synchronized telecommunications networks, which makes it possible for information to be written in twice in succession every now and then without Information is read out in the meantime. The information written first is lost in the event

The object of the invention is to provide a method that prevents information loss in such Prevents connections switched in time, which is particularly important if the first Time channel is a so-called common signaling channel. This object is achieved by the invention the features specified in the characterizing part of the main claim.

From the multiple information obtained in this way, the original information can pass through Elimination of the information excess can be derived. This will absolutely ensure that too if there are large phase differences between writing in and reading out the data register, none Information is lost because the frequencies of the channel intervals in both time channels are only small can be different.

Embodiments of the invention are explained in more detail with reference to the drawings. It shows

1 shows a block diagram of a part a telecommunications switching system with pulse code modulation and time division multiplex,

Fig. 2 shows some timing diagrams the mode of operation of the in F i g. 1 part of the telecommunications switching system shown,

3 corresponding timing diagrams for illustration of the method according to the invention,

F i g. 4 shows an example of a logic diagram of an arrangement for eliminating the excess of information;

Fig. 5 and 6 tables to illustrate the Operation of the arrangement according to FIG. 4th

The problem of the lossless transmission of information over connections, which are established by switching in time, using independent clocks i>. "The different parts of the connections are explained in more detail with reference to FIG. 1. This shows a TdI of a telecommunications switching system in which connections are established by switching in the time between receiving channels and transmitting channels of PCM time-division multiplex transmission systems. Each PCM system contains one Receive multiplex line and a transmit multiplex line each comprising π channels in one direction, each channel using a different time interval (channel interval) of one cycle of time intervals. In the present case, it is assumed that π = -32. 1, 100-1 and 100-8 denote the first and the eighth receive multiplex lines of a group of eight PCM systems.

The information is transmitted via a PCM multiplex line transmitted in grids which are each divided into 32 character positions and in which each character position is subdivided into, for example, 8 bit positions. The time in a PCM multiplex line is accordingly in Divided into time rasters, each containing 32 channel intervals and in which each channel interval is divided into 8 bit intervals is divided.

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The telecommunications switching system described here Jiat a cycle which comprises more time intervals than the cycle of a PCM multi-duplex line. The number of channels of an internal PCM multiplex line of the telephone exchange is correspondingly larger. In particular, the telecommunications switching system described here has a cycle of 16 × 32 = 512 time intervals, ie the number of time intervals of a cycle is twice as large as the number of channels in a group of eight external to PCM multiplex lines. In the control center, the 8-bit characters are transmitted in parallel using parallel serial converters on the receiving side and parallel serial converters on the transmitting side of the control center, which converters are responsible for the adaptation between the serial transmission method on the external PCM multiplex lines and the parallel transmission method the internal PCM multiplex lines of the control center. Each of the 512 time intervals of a cycle of the telecommunication switching system defines a channel interval on each of the internal PCM multiplex lines. The telecommunications switching system also determines the channel intervals on the transmission multiplex lines of the connected PCM transmission systems, for which the cycle of the control center is divided into 32 main time intervals, each comprising 16 of the aforementioned 512 time intervals, the latter being referred to below as sub-time intervals. Therefore, each sub-time interval defines an (internal ^{) channel 1 of} each internal PCM multiplex line and each main time interval defines an (external) channel of each external transmission multiplex line.

The receive multiplex lines 100-1 and 100-8 terminate in the synchronizers 101-1 and 101-8, respectively, which the convert received information signs on the time scale of the telecommunications switching system. At the same time with When converting the series into the parallel form, the channel number is determined for each character.

The synchronizers used here are known arrangements in terms of their design and effect. The mode of operation of these arrangements is therefore only described insofar as it is important for understanding the invention. Each 8-bit character received by the reception multiplex line is stored in a character register of a reception buffer which contains, for example, four character registers. The received characters are distributed cyclically via the character register by a first distributor under the control of a receive clock generator which supplies clock signals which are synchronized with the bits, the characters and the grids of the receive multiplex line. The reading of the characters from the receive buffer takes place under the control of the clock generator of the control center in main time intervals. Here, the character registers are read out cyclically by a second distributor and in the same order as when writing. The bits of a character are read out at the same time, so that each read-out cell has the parallel form. The characters read out are fed to an input multiplex line of the telecommunications switching system, which line is shown in FIG. 1 is designated by 102-1 and 102-8 .

The channel numbers are determined by counting the read characters modulo 32. Of the Receive clock provides an indication of the beginning of each receive cycle, which indication in a flip-flop and stored therefrom by the master clock with the same relative time delay which is caused by the receive buffer in the transmission of the characters from the Flip-flop read indicator is used to display a Modulo 32 counter to the beginning of the cycle of the To synchronize receiving multiplex line. Every time a character is read out, the The content of the count is increased by one, so that the associated channel number is excited for each character read out Channel numbers are fed to a number multiplex line, denoted in FIG. 1 by 103-1 or 103-8 is designated.

In asynchronous telecommunications networks, each control center has a clock that is derived from the clocks of the other Central is independent. As a result there aren't any upper limit in the phase difference between the clocks. In the present telecommunications exchange the phase difference between the master clock and a receive clock can be any Achieve value. The receive buffer of a synchronizer can only have a limited phase difference take up.

In the synchronizer, the phase of the first distributor is compared with that of the second distributor. The first distributor has a cycle of four channel intervals of the receive clock while the second distributor has a cycle of four main time intervals of the main clock. As a result of speed differences between the receive clock and the master clock, there are differences between the rotational speeds of the Distributor aui By measuring the phase difference between the two distributors, it is determined whether the Phase difference tends to drop below a critical value. This critical value is that Value at which the same channel register is written and read at the same time. Before the mentioned If a critical value is reached, an alarm is given and the phase of the second distributor is corrected. if If the first distributor catches up with the second, the second distributor becomes an additional one after the alarm Step forward corresponding to a one-time shortening of the cycle by a main time interval. This causes a character to be skipped when reading. However, if the second distributor catches up with the first, so the second distributor is held after the alarm so that he takes a step on the spot corresponding to a one-time extension of the cycle by a main time interval. During the step the character of the character register to which the second distributor is set is immediately displayed again read out.

The channel number counter is synchronized by having it at the same time as the second distributor an additional step or a step on the Position. The characters are then sent to the input multiplex line and the number multiplex line always supplied with the correct channel number.

In the following it is assumed that the times at which the phase of the second distributor is corrected are chosen in such a way, the only sign of the synchronizing channel, which can be the channel with the number 32, can be skipped over. That way gcher no variable characters lost.

The input multiplex lines 102-1 and 102-8 and the number multiplex lines 103-1 and 103-J end in a multiplexer 104, the one cycle before

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has a main interval. The output of the multiplexer 104 is formed by an internal multiplex line 105 and an internal number multiplex line 106 , which end in a data memory 107 . The multiplexer 104 connects the input multiplex line 102-1 to the internal multiplex line 105 in the first sub time interval of each main time interval and at the same time connects the number multiplex line 103-1 to the internal number multiplex line 106. In the second sub time interval of each main time interval, the multiplexer makes the corresponding connections for the second reception multiplex line of the group of eight, and so on, in the third through eighth sub-time intervals of each main time interval. In this way, eight of the sixteen sub-time intervals of each main time interval are used to supply the data memory 107 with the characters received from the receive multiplex lines 100-1 to 100-8. The remaining eight sub-time intervals of each main time interval can be used for other purposes or remain unused.

The data memory 107 has 256 data registers, that is to say one register for each channel of a group of eight receive multiplex lines. These registers can each store one character and can each be addressed by a channel number. The data memory 107 stores each character received from the internal multiplex line 105 in the register addressed by the channel number received from the internal number multiplex line 106 . The output of the data memory 107 is formed by the internal multiplex line 108 .

The data memory 107 is controlled by a cyclic memory 109 with 512 memory locations, ie with one memory location for each channel of the internal multiplex line 108. By storing a channel number in a selected memory location of the memory 109 , the data memory register corresponding to this channel number is saved in each cycle read out once and the character read out is fed to the internal multiplex line 108 in the subtime interval or channel interval corresponding to the selected memory location. In this way, a connection (switched in time) between each channel of the group of eight receive multiplex lines and each channel of the internal multiplex line 108 can be maintained.

The characters originating from a specific receiving channel normally have a repetition period on the input multiplex line 102-1 or 102-8 which is equal to one cycle of the central clock. If, however, a correction is carried out in the synchronizer , the repetition period for all channels is shortened or lengthened by a main time interval, depending on whether the second distributor takes an additional step or a step on the spot. irenden character is always equal to a cycle of the master clock. As a result of the differences between the repetition periods in the internal multiplex lines 105 and 108, characters are occasionally skipped over or characters are read twice in the data memory. To make this clear, a simplified system with a group of three receive multiplex lines with four channels each and a cycle of 24 sub-time intervals is described. It is assumed that a character is written into the data register in the first half of a sub time interval and read out therefrom in the second half of a sub time interval. A sequence of characters A, B, C. D, ... which originate from the same receiving channel is considered. F i g. 2a shows the times at which the characters are written into the data memory 107 . The character A is written in the first sub-time interval of the first main time interval of the cycle of the main clock generator. This sub-time interval is denoted by 1.1 ίο in FIG. 2a. In general, Lj. Means the / th sub time interval of the / th main time interval. It is assumed that the register of the data memory corresponding to the present receiving channel is read out in sub-time interval 1.5. In the sub-time interval 1.5, which follows the sub-line interval 1.1 in which the character A is written, the character A is therefore read out, as in FIG. 2b is shown. The character ß is normally written in the sub-time interval 1.1 of the following cycle. It is assumed, however, that the repetition period is lengthened by a main time interval. so that the character B is only written in the sub-time interval 2.1 . In the preceding sub-time interval 1.5 , the character A is read out again, on the assumption that the characters are read from the data memory in a non-erasing manner. Character B is read out in sub-time interval 1.5 of the following cycle. In the sub-time interval 1.5 of the following cycle, the character C etc.

In Fig. 3, the case is shown that a character is skipped by shortening the repetition period. A sequence of characters A, B, C, D ... which originate from the same receiving channel is considered again. Fig. 3a indicates the times at which the characters are written into the data memory. The character A is written in the sub-time interval 1.1 . It is assumed that the register of the present receiving channel is read in subline interval 3.5. In the subze «! Interval 3.5. that follows the sub-time interval 1.1 in which the character A is written, the character A is read out, as shown in Figure 3b. The character S is normally written in the sub-time interval 1.1 of the following cycle. It is assumed, however, that the repetition period is shortened by a main time interval, so that the character B is already written in the sub time interval 4.1 of the same cycle. The character B is read out in the sub-time interval 3 5 of the following cycle. The character C is written in the sub-time interval 4.1 of this cycle. The character D is normally written in the subline interval of the following cycle. It is assumed, however, that the repetition period is again shortened by a main time interval so that the character D in the sub time interval 3.1 of this cycle! In the following sub-time interval 3J: the character D is read out. The character C win has not been read and is therefore lost.

At the moment when a phase correction is carried out in a synchronizer, there may be a number 60 of connections between the channels of the relevant receive multiplex line and the channels of the internal multiplex line 108. Whether a connection is influenced by a phase correction depends on the relative positions of the sub- cells in which the data memory is written and read for the connection. For example, it can be seen from FIG. 3 that the connection under consideration does not go through the first phaser

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Correction is influenced, which causes the shift of the sub-time interval for writing the character B. A character is only lost after the second phase correction, which causes the sub-time interval for writing the character D to be shifted. In the simplified system with only four channels per receive multiplex line, a character is skipped over in each connection after four phase correctors in the same direction or transmitted twice. In the practical system, each connection is influenced in the same direction after 32 phase corrections, corresponding to a phase shift between the cycle of the receiving multiplex line and the cycle of the central clock of 360 ° or a time grid. If stable clocks are used in the switching systems, the frequency with which a disturbance occurs, which consists in the loss of a character or the additional occurrence of a character, is very low. In the transmission of telephone signals, these disorders are hardly noticeable. A problem occurs when data is being transferred over a connection.

In modern telephone systems, a so-called common signaling channel is used for the transmission of signaling information, via which the signaling information is transmitted in the form of coded reports. A specific time channel is used for this in PCM systems. For this signaling channel it is desirable that the information is transmitted without loss. In Fig. 1, 110 denotes a signaling information memory which is connected to the internal multiplex line 108 and acts as a receiver and buffer for the signaling information which is fed through the signaling channels to the group of receiving multiplex lines 100-1 ... 100-8. The connections between the signaling channels on the one hand and the memory 110 on the other hand run via the data memory 107 in the same way as the telephone connections.

In order to prevent that as a result of phase corrections lost signaling characters erfindu is proposed igsgemäß, three times to read each register of the data memory 107, which corresponds to a signaling channel in each cycle of the master clock with breaks of at least one main time interval and to transfer each character read out to the memory 1 10 degrees. Normally, each signaling character is transmitted three times to the memory 110 , and every now and then this number is increased by one or decreased by one as a result of phase corrections , so that, for example, a series of signaling characters R, S, T, U,. .. in the modified row R, R, R, S, S, S, S, T, T, T, U. U U. ... or in the row R, R. R, SS T, T, T . U, UU .. skips These latter rows can be brought back to the first mentioned row by a simple logic manipulation.

The foregoing is illustrated in FIGS. 2c and 3c for the series of characters A, B. QD, ... already described. It is assumed that the relevant register of the data memory is read out in the sub-time intervals 1.5, 2-5 and 3.5 of each cycle of the master clock. First, F i g. 2 described. In the sub-time interval 1.5. which follows the sub-time interval 1.1 in which the character A is written into the data memory, the character A is read out, as in FIG. 2c is shown. The character A is also read out in the following sub-time intervals 2.5 and 3.5. Because of the shift in which the character B is written the timing, in Subzeitintervall 1.5 of the following cycle is again read out the mark A, so that the character A is read out four times in total. In the sub time intervals. 2.5 and 3.5 of this cycle and in the sub-interval 1.5 of the following cycle, the character Z? read out, etc. In this way the row A, A, A, A, B. B, B, C, C,

ίο C- - ■ Now F i g. 3 described. In the sub-time interval 1.5, which follows the sub-time interval 1.1 , in which the character A is written into the data memory, the character A is read out, as shown in FIG. 3c. The character A is also read out in the following sub-time intervals 2.5 and 3.5. The character B is read out in the sub-time intervals 1.5, 2.5 and 3.5 of the following cycle. The character C is read out in sub-time intervals 1.5 and 2.5 of the following cycle. Because of the shift in the point in time at which the character D is written in, the character D is read out in the sub-time interval 3.5, so that the character C is read out a total of two times instead of three times. In the sub-time intervals 1.5 and 2.5 of the following cycle, the character D is read out again, etc. This creates the series A, A, A, B, B, B, C, C. D, D, D ....

In Fig. 4 shows the logic diagram of a logic arrangement for converting the modified row read from the data memory into the original row. It should be noted that this logic scheme can be implemented in various ways, for example by suitable programming of the control processor of the telecommunications switching system. The logic scheme is similar to the simplified system and examples of FIG. 2 and 3 adapted.

The characters originating from the data memory are fed to the three-stage shift register 401 via the input terminal 400 . The shift pulses for the shift register are derived from the output of the AND gate 402 , which has a first input to which the clock pulses are fed and which has a second input which is connected to the output of the OR gate 403 . This OR gate has a first input to which the clock signal S1.5 is fed, a second input to which the clock signal S25 is fed, and a third input to which the clock signal 535 is fed. A clock pulse is a clock pulse that occurs in a sub-time interval. A clock pulse Si ₅ is a 2-state signal which has the state "1" in every subtime interval 1.5, and in general a clock signal S _{v is} a 2-state signal which has the state "1" in every subtime interval /. / has where / and y are arbitrary integers. The result of the action of the AND gate 402 and the OR gate 403 is that shift pulses are fed to the shift register 401 only in the sub-time intervals 13, 23 and 33. As a result, only the characters that occur in the sub-time intervals 1.5, 23 and 33 at the input terminal 400 are recorded in the shift register. Each shift pulse shifts the characters by one place in the shift register, so that each character is shifted out of the shift register after three shift pulses. The three stages of the shift register 401 have separate outputs. The output of the first and the output of the second stage are connected to different inputs of a first comparator 404. The output of the second and the output of the third

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Stages are connected to different inputs of a second comparator 405 . The output signal of each comparator is a 2-state signal, which only has the state "1" if the two characters fed to the comparator are the same.

A pair of flip-flops 406 and 407 are used to store the states of the output signals of the comparators 404 and 405. A pair of UMD gates 408 and 409 are connected between the outputs of the comparators and the inputs of the flip-flops. The AND gate 408 has a first input connected to the output of the comparator 404 , a second input connected to the output of the AND gate 412 and an output connected to the input of the flip-flop 406. The AND gate 408 has a first input connected to the output of the comparator 405 , a second input connected to the output of the AND gate 412 and an output connected to the input of the flip-flop 407. The flip-flops 406 and 407 are controlled by the clock pulses derived from the output of the AND gate 410 , under the control of which the state of the output signals of the AND gates 408 and 409 is stored in the flip-flops. The AND gate 410 has a first input which is connected to the output of the OR gate 411 , and a second input to which the clock pulses are fed. The OR gate 411 has a first input for the clock signal S \ _b , a second input for the clock signal 5 ₂ .h and a third input for the clock signal S _ib . The result of the action of the AND gates 408, 409 and 410 and of the OR gate 411 is that the states of the output signals of the comparators 404 and 405 are stored in the sub-times of all 1.6, 2.6 and 3.6 in the flip-flops 406 and 407 , with the condition that the output signal of the AND gate 412 has the state "1" in these sub-time intervals. If the output signal of the AND gate 412 has the state “0” in these sub-time intervals, the flip-flops 406 and 407 are reset to the state “0”. The latter depends on the result of the previous comparisons, as will be explained in more detail below.

Each of the flip-flops 406 and 407 has two outputs, which are labeled 1 and 0 in the figure. These outputs provide opposing 2-state signals. The 1 output supplies a 2-state signal which has the state "1" if the state "1" is stored in the flip-flop. In this case, the O output supplies a signal that has Zuüland »0«. The 1-outputs of the flip-flops 406 and 407 are connected to different inputs of the AND gate 413 and the 0-output of the flip-flop 406 and the 1-output of the flip-flop 407 are connected to different inputs of the AND gate 414.

The output of the AND gate 413 is connected to the input of the flip-flop 415, the 1 output of which is connected to the input of the flip-flop 416. The output of the AND gate 414 is connected to the input of the flip-flop 417. The clock pulses for controlling flip-flops 415, 416 and 417 are derived from the output of AND gate 418. This AND gate has a first input, to which the clock pulses are fed, and a second input which is connected to the output of the OR gate 419. This OR gate has three different inputs, each of which the clock signals Sz i, Sn and & ι are supplied. The result of the AND gate 418 and the OR gate 419 is that the flip-flops 415, 416 and 417 are supplied with clock pulses in the sub-time intervals 2.1, 3.1 and 4.1. The 0 outputs of the flip-flops 415, 416 and 417 are connected to different inputs of the AND gate 412 . The result of this is that the ucz output signal of the OR gate 412 only has the state "1" when all flip-flops 415, 416 and 417 are in the state "0".

A second shift register 420 is used to store the original series of characters. Of the

The input of the shift register 420 is connected to the output of the second stage of the shift register 401 . The shift pulses for the shift register 420 are derived from the output of the AND gate 421 . This AND gate has a first input connected to the output of the AND gate 402 and a second input connected to the output of the OR gate 422. This OR gate has an input connected to the! Output of flip-flop 415 and a second input connected to the! Output of flip-flop 417. The result of the action of the OR gate 422 and the AND gate 421 is that the shift register 420 in the sub-time intervals 1.5, 2.5 and 3.5 shift pulses are supplied, on condition that the flip-flop

415 or the flip-flop 417 is in the "1" state.

In the following, χ represents a variable that cyclically takes on the values 1, 2 and 3 over time, and λ + 1 represents the value that follows the value of λ-, and x- 2 represents the value following the value of v + 1, etc.

The mode of operation of the arrangement according to FIG. 4 is as follows. A shift pulse is fed to the shift register 401 in each sub-time interval a.5. where em character is pushed into the first level, and

all characters in the shift register are shifted by one place. In the following Subzr: intcrvall λ.6 the states of the comparators 404 and 405 are taken over by the flip-flops 406 and 407. This continues until flip-flop 407 is set to the "1" state, which is the case if, after a shift in shift register 401, the character of the second stage is equal to the character of the third stage. A distinction can be made between two cases. In the first case, hip-flop 406 remains in the "0" state when flip-flop 407 is in the

State "1" is set, and in the second case hip-flop 406 is set to state "1" at the same time as flip-flop 407

set. In the first case, flip-flop 417 becomes a

Sub time interval (x-H) *! under control of the AND

_o Gate 414 is set to the "1" state.

ci? ^aS r ^{! ipflop 417 sets} the AND gate 421 in Betneb via the OR gate 422, whereby in the first of the subtime intervals / iir r ^{to the last mentioned subtime} interval «c tu ^{8 » the sign of} the second Stage of the shift register 401 is transferred to the shift register 420. Fhpflop 417 also sets the output signals of the AND gates 408 and 409 to the state "0" via the AND gate -i2, which in the sub-time interval

te # t! ₍ , ^{The 2} ^ ¹²¹ mentioned sub-time interval (χ + ψ follows, the flip-flops 406 and 407 are reset to the state "0". As a result, the flip-flop "ι / in the first of the sub time intervals (x + 2) .1 the last-mentioned sub-time interval (x + 116 follows, in which

i ^U , ^status vc °! i rt · ** ⁸ «« ⁵ "« · In the first of the sub time interval

/ ^ it. ^{on the 2} ^ ¹²¹ yawned sub-time interval

a I ■ ^{iSt the AND} - ^T ° r «Ι out of order and

no character is transferred to register 420.

After em character is transmitted. is the transmission

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Blocked once, regardless of the states of the comparators 404 and 405.

In the second of the above-mentioned cases, the flip-flop 415 is set to the state “1” in a sub-time interval (x + 1) .l. This flip-flop has the same effect as flip-flop 417, so that a character is transferred to register 420 and flip-flops 406 and 407 are reset to the "0" state. In the next of the sub-time intervals (x + 2) .l, which follows the last-mentioned sub-time interval (x + l) .l, flip-flop 415 is reset to state "0" and flip-flop 416 is set to state "1". As a result, the flip-flops 406 and 407 remain in the first of the sub-time intervals (a + 2) .6, which follows the last-mentioned sub-time interval (x + 2) .l, in the state "0". The AND gate 421 is then inoperative in the first of the sub time intervals (x - \ - 3) -5, which follows the last-mentioned sub time interval (x + 2) .6, as a result of which no character is transferred to the register 420 . After a character has been transmitted, the transmission is blocked twice in this second case, regardless of the status of the comparators 404 and 405.

The first time that, after a shift in shift register 401, equality is found between the characters of the second and third stages, the character of the second stage is transferred to shift register 420 . After the following shift in the shift register 402 , the states of the controllers 404 and 405 are not taken over by the flip-flops 406 and 407, as described. The result is that the flip-flops 415 and 417 remain in the "0" state and that the AND gate 421 is kept locked via the OR gate 422 , so that no character is transferred to the shift register 420 . In other words: after each transmission of a character, the transmission is unconditionally blocked once. If, prior to the transmission of a character, equality between the characters of the first and second stages of the shift register 401 is additionally established, the states of the comparators 404 and 405 are not taken over by the flip-flops 406 and 407 twice in succession, as described above. In this case, after the character has been transmitted, transmission is unconditionally blocked twice in succession.

The mode of operation of the arrangement according to FIG. 1 when receiving the series A, A, A, B, B, B, B, C, C, C, D, D, D is in the table in FIG. 5 shown. Columns 1, 2 and 3 correspond to the first, second and third stages of shift register 401 , respectively. Columns 4, 5, 6 and 7 correspond to the first, second, third and fourth stages of shift register 420 , respectively. Each row provides a time record the contents of the stages of the shift registers. The shift register 401 reaches the state of row 1 after three shifts from the beginning of the row. In this state there is an equality

is established between the characters in columns 2 and 3 and columns 1 and 2. The character A of column 2 is transferred to shift register 420 . The transmission is then unconditionally blocked twice in succession, so that no character is transmitted after the statuses of lines 2 and 3 have been reached. After the state of line 4 has been reached, the character B i is transferred to the shift register 420 , and its content is shifted by one place. The transmission is then unconditionally blocked twice (lines 5 and 6).

In the state of line 7, no equality is found between the characters in columns 2 and 3, so that no transmission takes place here either. After reaching the status of line 8, the character C of column 2 is transferred to shift register 420 , etc. After reaching the status of line 11 and the subsequent transfer of character D , the original row is stored in shift register 420.

In the table of Fig. 6, the corresponding effect on receiving the series AAA B, B, CC C, D. D, D is shown. As a special feature with regard to Kig. 5 it must be mentioned that in the state of line 4 only an equality between the characters of columns 2 and 3 is established, so that after the transfer of the character B of column 2 to shift register 420 the transfer is unconditionally blocked only once.

For this purpose 3 sheets of drawings

Claims (2)

Patent claims: 2.2 Ol 1. Procedure for transmitting various types of information in a PCM switching system, in which the PCM words arriving in a first cycle of channel intervals over a synchronizer is written into a data register in a second cycle of channel intervals channel numbers are assigned to the channel intervals and the position of the Channel numbers of the incoming channel intervals in the second cycle of the channel intervals as a function of on the phase difference between these channel intervals and the channel intervals of the first cycle> s of channel intervals is changed, and the number of time slots when reading out the various Types of information from the data register is greater than the number of time channels in the second cycle of Time channels, characterized in that they contain predetermined types of information Data register parts for lossless transfer of this information in each of the second Cycles are read out at least 3 times and not erased. 2. The method according to claim 1, characterized in that each piece of information read out predetermined type of information with the previous information and with the following information the same type of information is compared that information that is the same as the previous one Information is transmitted to the information receiver if the transmission is not blocked is, and that the transmission after each information transmission once and after each transmission information that is also the same as the following information is locked twice.