DE2152225A1 - Semiconductor device - Google Patents

Description

DlPL-ING. HORST RÜSE DtPUING ₇ PETERKOSEL PATENT LAWYERS

3353 Bad Gan <Ur «h« im, October 18, 1971 Ηοηβηηδίβπ 5 Telephone: (05382) 2842

Telegra'mm-Adresae: Siedpatent Gandarahtlm

Unaer file no .: 2554/3 Shumpei YAMAZAKI

Patent application dated October 18, 1971

Shumpei YAMAZAKI

c / o Yamazaki Kogyo Kabushiki Kaisha 9-7 1-chome Shinkawa, Shizuoka-shi, Shizuoka, Japan

Semiconductor device

The invention relates to a semiconductor arrangement with at least one arranged on a semiconductor substrate insulating cover. It also relates to methods of manufacturing a semiconductor device thereof Art.

The following are those commonly used in semiconductor technology Abbreviations used as they have partly found their way into the DIN standards, e.g. DIN 41 852, 41 855 or the pre-standard DIN 41 858. The terms specified in these standards are also used as far as possible. All abbreviations are used, among other things:

FET field effect transistor

MAS metal-aluminum oxide semiconductorC subtrat)

MNOS metal nitride oxide semiconductor

MIS metal insulating layer half-pus

MNS metal nitride semiconductor

209820/0908

Bank account: Bratinachweiglach State Bank, Bad Ganderehalm branch, account no. 22,118,970 ■ Poetecheckkonto: HennoverM715 Ra / Et N

MECNS metal-nitride-cluster-nitride-semiconductors MOOS metal-nitride-cluster-. -Oxide semiconductors MNGIS metal-nitride-cluster-insulating-layer-semiconductors MINCNOS metal-insulating-layer-nitride-cluster-nitride-

Oxide semiconductors
MICONS metal-insulating-layer-cluster-oxide-nitride-semiconductors.

In the description, further abbreviations are used, which are formed according to the same principle and each indicate the basic structure. -

In the case of conventional semiconductors with an MNOS structure, it has been assumed that they use traps which are formed randomly, and that these trapping points on a so-called irregularity or a lattice defect based, so to search on the atomic level ■ ind.

Bs is an object of the invention, semiconductor devices to improve the type mentioned at the beginning and in particular to create such semiconductor arrangements, which are suitable as semiconductor memories.

According to the invention, this is the case with one mentioned at the beginning Semiconductor arrangement achieved in that clusters or a thin film of semiconductor material layered are arranged at the boundary between two insulating coatings. Namely, the inventor found that the hysteresis signals, which are in the capacitance-voltage curves of semiconductor arrangements with MIS structure and in MNS and MNOS structures to the Cluiter or the thin film, which or which are present in the insulating coating or

209820/0906

is and which act as trapping points for electrons and holes, in addition to the above Defects on the atomic level. With the invention, the cluster or the thin film are now in a certain spatial arrangement provided, which has proven to be particularly favorable to the clusters or to control the charge to be captured by the thin film and thus also the current flowing under this layer and to provide a semiconductor device suitable for storage purposes. The semiconductor material is advantageous here the cluster or the thin film (s) are doped with an impurity which is a P-line or an N-line results. Furthermore, the Semiconductor arrangement designed with particular advantage so that at least the insulating layers, which the clusters or the thin film or the thin films contain between them, poor in clusters or preferably at least are very largely free of clusters.

A method according to the invention for producing such semiconductor arrangements is characterized by the following process steps:

1. that a single or multilayer insulating layer is produced on a semiconductor substrate,

2. that semiconductor clusters or a semiconductor thin film are or will be produced on the insulating layer, and

3β that an at least cluster-poor insulating layer is formed on the semiconductor clusters or the semiconductor thin film.

Further details and advantageous developments of the invention emerge from the following described and shown in the drawing

209820/0906

management examples, as well as from the subclaims.

Show it

Pig «1 shows a cross section through a MISPET according to the invention,

Figo 2 ten different embodiments for semiconductor arrangements according to the invention,

Fig. 3 (A) is an energy band diagram for the embodiments after Pig. 2 (A) and (B),

Pigο 3 (B) an energy band representation for the embodiments according to Pig. 2 (θ) and (D),

Pig. 4 and 5 measured values from an experiment with an MNCNS setup,

Pig. 6 measured values from an experiment with an MHCHOS setup,

Pig. I ₁ 8, 9 measured values from a MISPET, which has the structure according to Pig. 2 (A) and (B) used as gate, and

Pig. 10 the capacitance-voltage characteristic field of a MHGNS diode, which is based on the Pig. 2 (E) and (P).

The structure of an insulating coating described below is suitable, among other things, for a semiconductor memory device. There are semiconductor oil or thin film layers on predetermined boundary surfaces or in placed near them, with an insulating coating of two or more layers on a semiconductor substrate is formed, and in this way it becomes possible to control the charge that is applied to the clusters or the Thin-film layer is captured or accumulated, and this charge can be in terms of polarity and amount

209820/0906

2152223

can be controlled, and this also makes it possible to use the Control current flowing in the semiconductor under these coatings.

^{MESFET and MOSi 1} ET have so far become known as semiconductor arrangements which have the use of trapping points in their insulating layers. The traps in the MIS or MNOS structure have been viewed as a result of the non-uniformity of atomic size due to unexpected changes during manufacture.

As a result, it is difficult with these known arrangements to remove the trapped carriers (electrons or Holes) as it is difficult to control the quantities of traps and their distances from the interface to determine.

The inventor assumed that metal or semiconductor clusters were uniformly distributed in the insulator are and - in addition to the irregularities of atomic size - act as trapping points for the captured porters, in the vicinity of the clusters «,

So if a low-cluster or cluster-free insulating coating is produced, it has few or no traps. When clusters or a thin film of semiconductor material between such poor clusters or cluster-free insulating coatings are arranged, it is possible to determine the number of traps and their To determine the distance from the interface and thereby the possibility of control duroh captured Prove carrier. This is achieved by the invention, which results in a variety of new possibilities as described in the following examples.

209820/0908

The invention "also relates to the structure of the insulating coating, in which the clusters or the thin film are surrounded by insulating layers.

A catch part should be placed under glitter or thin film understood for charges as well as the form of these components are, as they are explained in detail below, in particular with reference to the drawing to be discribed.

The inventor has found that it is impractical to distribute the clusters in the thickness direction of the coatings because they function as leakage current paths for direct current. Furthermore, the inventor has determined that it depends on the distance from the interface to the clusters whether the clusters capture the carriers (electrons or holes). If the distance is irregular, for example a close distance at a certain point, charges are trapped there, and the energy band of the semiconductor in the vicinity of the interface is deformed and the current characteristic in the vicinity of the interface of the semiconductor substrate becomes smoother. From this it follows that when the current in the semiconductor substrate is to be controlled by changing the polarity and amount of the charge trapped in the traps, this charge should be distributed uniformly and with a constant density, the distance from the boundary surface should be kept constant . This has been confirmed experimentally. This Er, the invention toizieht calibrated so a favorable structure as explained in the foregoing discussion of the operation of the trap, and in an advantageous manner of preparation.

In the following description, insulating layer or insulating coating means a single layer

20982070906

BATH ORIGINAL

Isolator, while generically the entire, usually multilayer structure under insulating cover insulating layers, semiconductor clusters and / or semiconductor thin film (s) is understood.

Pig. Fig. 1 shows a cross section of a MISPET in which the present invention is used to manufacture the gate. It should be noted that the semiconductor device, e.g. In other words, when the present invention is applied to a random access memory, such a semiconductor device is intended to sense the information stored in the insulating coating. In order to change the threshold voltage Um ₀ relative to the operating voltages of the semiconductor device bo, the present invention plays a second role.

Referring to Figure 1, the present invention is used to fabricate the gate of the MISFET. An MIS construction consists of a layer 1 made of metal or doped silicon or germanium, insulating layers 2, 4, olusters or a thin film made of semiconductor material (both designated with the reference number 3 ), a semiconductor substrate 5, which here consists of P-silicon, and a lower electrode 17. The current in the semiconductor device flows through the line 13 »the source 14» the under-gate channel, the drain 16 and the lead 15 of the drain. Silicon oxide is used to insulate the leads and the

203820/0906

2152223

Substrate used, whereby the stray capacitance between them is reduced.

Fig. 2 shows the structure of various embodiments of the present invention. The reference number 1 denotes a conductor electrode; 2, 4, 6, 8 and 11 denote insulating layers, and 3 and 7 clusters or a thin film of semiconductor material. In addition to metals such as aluminum, gold, titanium, platinum, etc., impurities of the P or N type, which are made from single or double-sided doped multicrystalline silicon or germanium, are used as conductor electrodes. The clusters that are in the Pig. 2 (A), (C), (E), (G), (I), (J), (K), (L) have about d. ^The shape of hemispheres and, like the thin films, are made of silicon or germanium. An electron micrograph shows that the clusters are compressed and formed as a hemisphere and have a diameter of the order of a few tens of liters to 3000 pounds. The diagonally hatched areas in Figs. 2 (B), (D), (F), (H), (I) and (J) represent the semiconductor thin film. Due to measurement difficulties, the exact thickness of the thin film could not be determined but it is believed to be in the range of 5 to 300 i on average.

The insulating layer 2, which is in close contact with the semiconductor clusters or the semiconductor thin film must be protected against the heat treatment, and for this reason is for the coating material either Silicon nitride, silicon oxynitride, germanium nitride, Silicon oxide, aluminum oxide, tantalum oxide or titanium oxide have been used. Depending on the use one has a combination of these materials was also chosen. in the

209820/0908

2152I2S

-a-

generally, an oxide generates oxygen when subjected to heat treatment, and the gas reacts with it the oluster or the thin film and gives them a compressed shape. Aue for this reason is the invention mostly silicon nitride used. Care should be taken to ensure that silicon or germanium clusters Im be excluded from layer 2 *

In Pig. 2 (A), (B), (B), (P), (G), (H), (I), (J) and (K) a single layer of silicon oxide, Silicon nitride or germanium nitride made insulating layer under the semiconductor patterns or the Semiconductor thin film used. In Pig. 2 (C), (D) and (L) are multiple layers consisting of the coatings 4 and 11 used.

In the case of a silicon semiconductor substrate, a silicon oxide coating with a thickness of less than 200 pounds, typically between 10 and 50 1, with an insulating coating made of silicon nitride or germanium nitride on top chosen which coating has a thickness of about 200 A, typically between £ 10 and £ 50. In general A silicon semiconductor easily forms silicon oxide on a surface, making the surface stable. However, if the silicon oxide in the heat treatment reacts with the semiconductor olusters or the thin film, thereby the leolieraharakterietik, the Grenzsohiohtcharakteristik etc. worse. To overcome these difficulties, nitride film is used in hot water 4 is formed on the surface of the silicon oxide 11, and then the semiconductor clueter or the semiconductor thin film formed on the nitride film 4.

In Pig. 2 (K) and (L) does the insulating layer consist of a nitride coating 2 and another isolii? ^a oi: aoii

- ίο -

Coating, e.g. silicon oxide, doped silicon oxide j or a coating with a higher dielectric constant such as tantalum oxide or titanium oxide. The nitride coating is formed on the latter coating so that the insulating layer is monolithic. The thickness of the insulating coating is roughly in the range of £ 300 to £ 3000, accordingly the present process engineering.

As described above and shown in FIG. 2, there are various possibilities according to the invention for the basic structure of an insulating layer s Either a triple layer in which the clusters after the in the following steps to be discussed manufactured and arranged in a row or formation of the insulating Layer 2 on the semiconductor clusters or the Thin film 3 deposited on the single-layer insulating coating or multilayer insulating coatings 4 and 11 is formed or is. The coatings are as to form thin coatings on the semiconductor substrate 5. In the drawing there are two layers of insulating Coatings shown, but the number of coatings can be increased.

All material for the clusters or the thin film can be either metal or a semiconductor, however semiconductors such as Si or Ge were used in ϋ η experiments because metal would not reversibly change the capacitance-to-gate voltage characteristic in a positive direction while a Semiconductor has a reversible hygienic characteristic.

In one embodiment, the clusters or the thin film are made of Si by chemical vapor deposition Silane, vacuum evaporation or silicon sputtering is made, and the cluster or thin film is made of Ge

is made by vacuum evaporation or pyrolysis of germanium hydrogen. In the case of producing cluster by vacuum evaporation has been experimentally determined that the surface on which the clusters are to be formed, to be maintained at a lower temperature without pre-heating and at about 30O ⁰ C. Also, chemical vapor deposition with silane in the experimental method was easy compared to the use of a reactive gas such as SiH ₂ Cl ₂ , SiHCl. ,,

SiCl- etc. If a three-basic or five-basic 4th

Impurity such as phosphorus or boron, which is responsible for the semiconductor substrate is to be used, is doped with these reactive gases, creating the cluster or the thin film be or will be provided with a B or N line the level in the energy band of the clusters can be changed. In addition, a mixture of metal and semiconductors can be used can be used for the cluster or the thin film.

Fig. 3 shows energy bands for the structures of Fig. 2 (A), (B), (C) and (D). When arranging according to 3 (A), a metal gate 1 made of aluminum, a silicon nitride layer 2, clusters or a thin film 3 are shown made of silicon, a silicon nitride layer 4 and a semiconductor substrate 5 are used! so this arrangement has the Structure MNCNS (metal nitride cluster nitride substrate). It should be noted that the silicon clusters do this designed to trap electrons or holes as trapping sites and that they have the same ribbon configuration like the silicon substrate. For this reason, according to the present invention, the previously customary ones do not become Atom-sized traps are used, which normally take more than a microsecond for injection and recombination require from carriers. Rather, elements are used

209820/0906

which results from the presence of the cluster and / or of the thin film. As a result, the present invention differs completely in its technical concept from the usual MNOS structure.

Fig. 3 (B) corresponds to the Pig. 2 (0) and (D) and has a metal gate 1 made of aluminum, a layer 2 of silicon nitride, cluster or a thin film 3 of silicon, a layer 4 of silicon nitride, a Silicon oxide layer 11 and a silicon semiconductor substrate 5, and consequently has the structure JBaTCUTOS. (The above specified substances were used in the tests; they are only examples).

The semiconductor substrate 5 can optionally be made of germanium, gallium arsenide, etc. instead of silicon exist. Although the band structure is not the same, the material for the layers 2, 4 should be silicon nitride or germanium nitride, the material for

the gate 1 should be doped Si or Ge, and that for 3 germanium.
Example 1;

This refers to Figs. 2 (A) and (B). The following discussion gives the details of manufacture the MNCIS structure and its result. Here stands "I" for "insulating coating".

Silicon, germanium, gallium arsenide, etc. can be used for the semiconductor substrate; while trying a silicon semiconductor with an impurity

15 - "5
density of No = 1 χ 10 cm and the crystal orientation 100 are used. After cleaning the semiconductor substrate, the insulating coatings 2 and 4 were applied by means of solid-state vapor reaction precipitation and chemical vapor deposition. In the former process step

209820/0906

the substrate for the thermal oxidation was placed either in dry or in wet oxygen at a temperature 500 to 1100 G ^0. The time from 5 seconds to a minute was required for thermal oxidation at 900 to 1100 ° 0. In the latter process step, the substrate was placed in either nitrogen or ammonia at 1000 to 1550 ⁰ O to produce a silicon nitride coating on it. The result was a coating thickness of less than 100% at 1150 ... 1200 ⁰ G in 10 minutes to one hour.

A silica coating having a thickness of less than 200 α was obtained by chemical Heaktion between silane of 0.1 ml / min and oxygen of 10 to 500 ml / min with a nitrogen carrier gas of 5 l / min at 200 to 500 ⁰ G.

A Siliziumnitridüberzug was produced in that silane or SiH ₂ CIG or SiHGl or Sigl, was reacted at 500 to 900 ⁰ C for reaction with ammonia or hydrazine. The details are as follows:

Silane or SiH ₂ Cl ₂ : 0.2 to 0.4 ml / min. Ammonia: 100 to 300 ml / min

Nitrogen carrier gas: 2.5 l / min for silicide

0.5 l / min for ammonia furnace: vertical reaction furnace with

reduced nickel oxide than

Catalyst to activate the

Ammonia.

The resulting silicon nitride coating contained no clusters or a negligible amount of Cluster. If you add less than 100 ppm oxygen or nitrogen oxide to the reaction gas

209820/0908

-H-

Adding to the above procedure resulted in silicon oxynitride, thus an oxide-nitride mixed compound.

Germanium nitride was produced by the reaction of GeH ^ or GeGl. with ammonia at 400 to 700 ⁰ C. germane of 0.2 ... 0.4 ml / min was used, with the temperature of the substrate was maintained at the test at 55O ⁰ C. The other data remained the same as when the silicon nitride coating was made.

Chemical vapor deposition using silicon or germanium hydrogen has been effective Method for the cluster or the thin film, however, the use of SiHpCIo facilitated the Production · In the latter process, a hydrogen carrier gas was used with ammonia at 0.5 l / min and with SiHpClp a nitrogen carrier gas at 2.5 l / min is used. A halide of silicon or germanium, e.g. silicon tetrachloride, Germanium tetrachloride, or trichlorosilane, can be used in manufacturing, however, were Silane and germanium hydrogen chosen because they are easier to process. With these a gas of Silicon or germanium, ammonia or hydrazine, both of which have a smaller gas volume than the former, used to increase cluster logoff, In addition to the above, vacuum evaporation or atomization can also be used, but these require Production of the component 3 one of the for the production station separate from the silicon nitride coating. That is why this is where the surface the cluster or the thin film becomes dirty or oxidized.

FIG. 4 shows the result obtained with an MNCNS structure which is used for layer 2 and the

209820/0906

Layer 4 uses a silicon nitride coating by chemical vapor deposition. The total thickness of the coating "was 1250 JL. Fig. 4 is based on the general capacitance s-voltage characteristics of the MNCNS structure such as shown in Pig. 6. In Fig. 4 the x-axis represents the gate voltage or field strength and the y-axis represents the degree of hysteresis in the form of / \ U ₁₃₁₁ ,

(corresponding to the change in voltage in the case of flat belts) or Δ ν (the latter is the change in charge density, which was captured by the clusters or the thin film in flat band).

The experiments with No. 304 and No. 308 show that as the clusters or thin film 3 (in Fig. denoted by C) the hysteresis only increases in thickness. The experiments with No. 308 and 309 show that if the Insulating layer 4 (denoted by I in FIG. 4) increases, the hysteresis decreases. So you make the insulating layer 4 smaller and the clusters or thin film 3 larger, the charge density to be captured is increased. Power however, if the insulating layer 4 is too thin, the trapped charge disturbs the current through the semiconductor or weakens the retention capacity for the trapped cargo.

The data shown in Fig. 4 show that Δ Ν _ρΒ = 8.2 χ 10 ¹² cm " ² .

This value is about five times larger than a usual one MNOS structure, which has a random hysteresis, and which applies

Δ N _pB = 1 ... 2 χ 10 ¹² cm " ² .

It is here that the outstanding novelty of the present invention arises.

209820/0908

Pig. 5 shows the result of an experiment in which the voltage was kept constant (U__ _o ^ = - 50 V,

4- fs ο

E = - 4 x 10 V / cm), while Λ U _FB as well as the lowering side were changed for both the clusters or the thin film 3 and the insulating coating 4. If silicon nitride is used for the insulating coating 4, the surface of the silicon substrate lying under the silicon nitride reacts with the oxygen in the air and produces a silicon oxide coating of 5 ... 20 1 at normal temperature. This oxide coating is removed in ammonia gas at over 1000 ⁰ O in more than 10 minutes, and part of the oxide coating is converted into silicon nitride. The oxide coating, on the other hand, is removed with the special cleaning process of the silicon substrate. If a pure MNS structure is required, the above treatment must be carried out. The oxide thin film which is generated at normal temperatures can be neglected in practice. The so-called natural oxide, as it is here, shows a random thickness profile on the surface of the substrate. For example, the thickness can be 20 Å at one point and 0 SL at another point on the same substrate.

In Fig. 5, the silicon nitride coating shows a growth rate of 1 ... 2.8 / sec. The one mentioned random thickness should be taken into account at 0 see on the y-axis. The point A in Fig. 5 means an MNS diode. The corresponding value von Ujvg is 8 V, with ί 4 x 10 "v / cm. Here is the Hysteresis is very small if the clusters or the thin film are not formed by silane deposition or is. If the coating 4 (Fig. 2) as an oxide coating

209820/0906

had been formed at high temperatures, the hysteresis (Λ ^υ _{? Β} ) t> ei the same thickness Heiner al · 1 T at the same field strength.

Palis is precipitated to form the clusters or the thin film of silane, increases with increasing time for the precipitation ^ TJ-Qg, like that from the successive Kurren 24, 23, 22 and 21 in Pig. 5 emerges. On the other hand, Aüjm increases as the thickness of the silicon nitride coating 4 in Pig increases. 2 (A) and (B). When the low bottom side of the silicon was between about 30 and 60 seconds, silicon clusters were formed. Measurements under the electron microscope showed that the durometers of the silicon clusters were between £ 300 and £ 1500. The silicon thin film was created when the precipitation time more than 300 see. fraud. If the Dioke of the downcast Pilm is more than 500 JL, such a PiIm should be called Diokfilm. - In the present invention, when the average thickness of the deposited semiconductor film is less than 100 R , the clusters are generated. When this diameter is between 100 and 500 liters, the semiconductor thin film is produced. When the semiconductor thick film is formed in the insulating coating, it is commonly referred to as the silicon floating gate of an MIS field effect transistor. In the present experiment, when the thick film is produced, the insulating coating 4 according to Pig. 2 (B) have a dioke of more than 500 Å so that it does not have any pinholes or other conductive paths. When the clusters are formed, the introduction of ammonia or hydrazine of the same volume as that of the silane gas or less than that of the silane gas can increase the rate of pattern formation.

209820/0906

If a small amount of nitride gas is introduced, it becomes difficult to form the silicon semiconductor thin film. The Siliziuncluster be generated when the Aisscheidungszeit see about 300 or more at the same flow rate of silane as in the manufacturing condition of the silicon clusters in FIG · 5 (Instead of the term precipitation "" deposition ^11, the term in the following text "is used.

It is therefore possible, as a result of the trapping Holes wire electrons to the clustem to achieve a long storage, even if the layer 4 is between the gluetem and the substrate 5 or the gate electrode has a number of holes or conductive paths.

If, on the other hand, there are holes in the layer 4 in the case of the semiconductor thin film 3 are present, the electrons or holes trapped on the thin film leak to the substrate 5 · Therefore are here the storage properties are not particularly favorable for a semiconductor memory.

It has been determined experimentally that when using silicon or ßermanium clusters the storage time is more than 2000 hours was less than 500 hours, for example, only one hour when the semiconductor thin film was used. The result obtained will be the same if the ammonia gas is not added.

The above experiment proves that the teaching of the present invention is correct. The hysteresis phenomena, which in the capacitance-voltage characteristics of the MNS structure and of the MNOS structure should not be attributed to the so-called irregularity of the atomic dimensions rather on the clusters which are present in the insulating layer and which are used as trapping points for Electrons and holes work. So that is a

209820/0906

Means given to hand if the wish exists, the size and shape of the hysteresis of the capacitance-voltage characteristics to influence.

Thus, the present invention brings about a novel structure wherein the cluster or the thin film are to be understood as 3 jobs; at this time, the clusters (or the semiconductor thin film) become uniform and with a constant distance from the semiconductor substrate, i.e. in a certain geometric configuration, distributed.

example 2x

This relates to FIGS. 2 (D) and (E), which have an MHCI ₁ IgS structure, where I ₁ and I ₂ mean the insulating layer 4 and the insulating layer 11, respectively. The material and the method for the semiconductor substrate, the insulating coating, the clusters or the thin film and the gate conductor are the same as in Example 1, Pig's structure. 2 (C) and (D) bring the peculiarity of locally forming a silica coating at normal temperature. This type of oxide coating reacts, when the heat treatment for the semiconductor clusters or the semiconductor thin film is carried out at above 500 ⁰ C in one hour, as was previously described. For this reason, it is extremely desirable to surround the semiconductor clusters or the thin film with a layer of silicon nitride or germanium nitride.

The present invention overcomes these difficulties by using the MNCOS or the MUCNS structure converted into a MNONOS structure according to example 1

209820/0906

will. Fig. 2 (L) shows a MINGNOS or MICONS structure, So an improved version of the MNGONS, with an insulating coating of tantalum oxide or titanium oxide with larger specific dielectric constant is applied to the nitride coating 2, which is on the MNOONS structure was formed, i.e., on the clusters or the thin film. The MINCNOS structure has a thin one electrical coating and a thick physical coating and thus protects against mechanical stresses, that are applied to the gate portion of the semiconductor device »In addition, the cluster or the Thin film can be formed in multiple layers to enhance their effect. This is one Further development based on the present invention.

After the silicon semiconductor, which has an impurity density of N = 1 × 10 · cm −− and the crystal orientation 100, had been completely cleaned, a silicon oxide coating 7 was produced by solid-vapor reaction in dry oxygen for 100 seconds at 1000.degree. A silicon nitride coating was then produced in 15 seconds by chemical vapor deposition using silane and ammonia. The experiment also tested SiHpCl ₂ and SiCl, and the results were the same. The clusters or the thin film were formed by a silane deposition method in 300 seconds. It in turn a Siliziumnitridüberzug of 1200 A was formed ^au £ the clusters or the thin film, wherein the temperature of the substrate was maintained at 650 to 75O ⁰ C. Finally, an MKCNOS structure was completed by vacuum evaporation applying an aluminum electrode to the above assembly _β

2 Ü ¹ J H, 'U / 0 9 (JU

Δ Uj, _B decreases as the thickness of the oxide layer 11 added to the nitride layer 4 increases, and it increases as the precipitation time of silane increases; the proportions correspond to those of Pig..5.

The Pig. 6 (A) and (B-) show the capacitance-voltage characteristics, as they turned out in the attempt.

Δ Up-o increases proportionally to TJ (maximum applied

^g max gate voltage in V). Pig. 6 shows no hysteresis

characteristic when TJ is less than 50 V. the

^s max
critical voltage of the test sample of FIG. 6 is 50 V, and the hysteresis, ^ U-nmt increases with the increment of the maximum gate voltage, TJ. A capacity

^s max voltage characteristic without hysteresis is shown in Fig. 6 (A); This figure shows that the interface properties between the substrate 5 and the insulator 11, 4 represent an ideal characteristic for a MISFET gate, because the solid. States and the fixed charge Q_ / q. Existing at the interface are almost equal to zero. Therefore, a practically mandatory prerequisite for the production of the present structure according to the invention is the Teohnik for the production of a low-oluster or cluster-free silicon or germanium nitride coating.

The present example shows that it is possible to determine the degree of hysteresis in capacitance-voltage characteristics by changing the manufacturing conditions, e.g. the lowering speed or precipitation time of a silicide gas, the mixing ratio between the small amount of ammonia or hydrazine, and the distance between the olusters or the thin film, and the interface It is also possible to

209820 / 090B

thereby to influence the degree of hysteresis, in that the changes of the liiedersohlagstemperatur SDLizidgases about 75O ⁰ G ⁰ or G 65O.

The energy band of Example 2 is shown in Pig, 3 (B), the designations being those of Pig. 2 (G) and (D) correspond.

Example 3?

This example describes the characteristics of a MISFET that consists of the structure as shown in the Pig. 2 (A) and (B) is shown with gate. The example uses a Η-channel, and its more fundamental Construction is in Pig. 1 shown! here is the distance between the source electrode 14 and the drain electrode 16, called the channel length, 30 microns, and each gate is 1000 microns in length.

The substrate is of the P-type, crystal orientation 100, and its spessifisoher resistance is 3 ... 5 ohms. cm. Pig 7 to 9 show the result of this experiment. The gate insulator, corresponding to the silicon nitride layer in Fig. 2, iat about 600 ... 700 1 diok. This is about half of the value according to Examples 1 and 2. The thickness of this material can be changed depending on the particular use. If a MISPEI with P-channel is desired, a Η-conductive substrate should be used together with a P ⁺ source and drain.

In Pig * 7, the x-axis represents the gate voltage

U represents and the y-axis the drain current L _n . The Draing D

voltage was kept at a constant value of 100 mV. The ü -! - characteristic remains the same, while the threshold voltage IT _{10 changes} from + 10V to - 10V.

209820/0906

that

The slope of the characteristic shows that the mobility of the carrier in the canal is 400 cm ² / V see.

See the facts from the above experiment lead to a negation of the concept previously adopted in semiconductor technology that at high Surface conditions at the interface the carrier mobility in the channel is low and that at lower the carrier mobility at the interface of the mobility of the carrier in the Inner (bulk carrier) closer.

If a positive or a negative gate voltage is added to the initial threshold voltage of Umo? = + 2 V, the data of the UL _{0 characteristic} curves remain the same if the gate voltage is lower than the critical voltage U. If the gate voltage is above the critical voltage, the data shift in the direction of the applied voltage. In the present example, the critical voltage was ί 23 ... 25 V

The indices 1 ... 9 in Fig. 7 (the indices are surrounded by circles there) show the sequence of the created largest gate voltage (U). With U = OV and

flowing L ₀ one obtains the characteristics with the indices 6 and 8; this is the ON state. If U = 0 V without L ₀ , the characteristic curves with the indices 7 and 9 are obtained; this is the switched-off state (OFF). It can be seen from the characteristics that the transition from ON to OFF and from OFF to ON can be repeated, so that the present invention can be used as a random access memory.

Fig. 8 shows the U ^ - I ^ family of characteristics accordingly the index 9 of FIG. 7 for a maximum gate voltage

2 U ¹ JH / (J / (J 9 0 6

- 24 of +40 V. Fig. 8 shows that L _n ^ O with U> 10 Y and

1) g

I = O at U <+ 10 V. The latter means that it is switched off State (OFF).

FIG. 9 shows the TL.-Xp. Family of characteristics corresponding to index 8 in FIG. 7, the maximum gate voltage being -40 Y. This figure shows that I ^> 0 with XJ = 0 and Ij) = O with U <-10 Y. The former means the switched-on state (ON).

As described above, one can create a single layer or multiple layers of semiconductor clusters or semiconductor thin films arranged in the insulating coating and thereby the insulating Coating gives a MISFET structure, namely an insulating layer for the gate, EIU and OFF states

at U = 0 V or at U «* 0 V, while a gg ''

variable threshold voltage ILq used (where U = 0 V is used as the axis of the symmetrical threshold voltages), e.g. within +10 V to -10 V.

By taking advantage of the above-mentioned fact, an energy independent memory can be obtained. Changing the threshold voltage IL, _O in a positive or negative direction to a certain extent from 0 Y also enables the MISFET to change its dynamic characteristic. With this and with the symmetrical family of characteristics with a center point at U = 0 Y, as is obtained from both the capacitance-voltage-characteristic according to FIG. 6 (B) and the U -! "- characteristic according to FIG Boundary layer charge known from the prior art (mostly positive) and the charge trapped by the olusters differ from one another by the location where these charges are trapped.

209820/0906

Example 4: ~

This example describes the structure according to FIGS. (E) and (F) with an insulating coating. In the example of Figs. 2 (A) and (B), the clusters and the thin film are on the side of the substrate 5; In the present example 4, however, they are on the side of the electrode 1, for which aluminum or gold is usually used as the material. In this case, only electrons are present as carriers, and the resulting device is then a read-only memory and therefore a less flexible memory device, since no holes can be provided in the device which cancels out the electrons to be captured. For this reason, one of three types of impurities, namely P-type, Η-type or both types, as well as highly doped Si adar Ge (in the order of magnitude of 10 ¹⁹ ... 10 ° »cm" ³ ) were used in the experiment. If a silicon gate is used, diborane or phosphine with silane will be deposited as P-type and N-type impurities, respectively, causing TJ ,,,,

Ji Jj

shifted either in the right direction or in the left direction, proportional to the difference the work function between the substrate and the electrode, and many holes are obtained at the same time. Otherwise there are hardly any holes.

Only the ohemische vapor deposition process can be used to produce the coating 2, otherwise ala for the coating 4. As coating 2 silicon nitride is formed with a Dioke of 10 ... 100 Å. He is contributing to a pollution to prevent from the outside.

The results of the trials were all symmetrical. Fig. 10 shows the influence of increasing diokes of the layer

209820/0906

in Fig 2 (E) and (F) ₀ The characteristic diagram similar to that of FIGS _e 2 (A) and (B) with increasing ^'. Thickness of the layer 4 there. The reference symbols in FIG. 10 have the following meanings

Reference symbol layer thickness (K) .;

31 15th ■. , _;

■ -32 25

33 50 -.-, ..

34 200

* The data at U = ± 100 Y were 120 V for U ₇₇₁₁₃ .

To increase the charge to be injected, the Distance to an injection source, that is to say the distance between the semiconductor gate 1 and the clusters or the thin film 7 can be shortened. The tendency is similar to the data according to Example 1, Fig. 5. The experiment proved that the clusters, e.g., cluster 7 of Fig. 2 (E), give high production. When using a Semiconductor thin film, as shown at 7 in Figo 2 (F), leave holes (pinholes) in the insulating Cover 2 to flow away the trapped charge »

It was then determined that for practical use of the embodiment of Fig. 2 (F) the average thickness of the layer 2 should be more than 50 Å. As described in Example 1, it is desirable to add a small amount of silicide gas to the silicide gas to mix gaseous nitride. such as ammonia, when the HaIb- generated cluster manager to obtain a long storage time.

In Fig. 2 the arrangements (Gr), (H), (I) and (J) represent the combination of (A) and (E), (B) and (F),

^ 0920/09 ^

- -27 -

(B) and (E) "or (F) and (A) to double the respective puncture ₀

Thus, the present invention provides, inter alia, the teaching _e, semiconductor clusters or one or more semiconductor thin films and an insulating coating thereon and, in turn, provide on the surface of the semiconductor and thereby maintain a constant distance between them. The present invention provides the means to control the degree of hysteresis in the capacitance-voltage characteristic by considering the conditions in the formation of the cluster or the thin film (s) and the distance between the interface and them changed The basis of the present invention is a theory newly developed by the applicant about charge trapping points; thus the invention also differs quite significantly from the usual MtTOS structure, in which long parts are used which are formed by chance in this technical conception.

It is an object of the present invention to provide improvements in all types of semiconductor devices to create, and especially with MIS pelde effect transistors.

In the preceding description, olusters or a thin film were used as investigations under the electron microscope the existence of clusters alone that. Existence of thin film alone and showed the mixture of both. A structure with a mixture of both manifestations is therefore necessary just as within the scope of the invention as the pure manifestations.

The invention enables an easy and simple

209820/0906

Manufacturing, as well as the arbitrary influencing of parameters.

The size, density and thickness of the clusters can be changed so easily that the device according to the invention Can be used in many ways, e.g. as an energy-independent storage device, MIS field effect transistor with variable threshold voltage, etc.

Patent attorneys Dipl.-Ing. Horst Rose Dipl.-Ing. Peter Kos el

209820/0906

Claims (1)

DIPL-ING. HORST ROSE DIPL-ING. PETER PATENT LAWYERS 3353 Bad Gandereheim, October 18, 1971 Hohenhafen 5 Telephone: (05382) 2842 Telegram address: Siedpatent Gandereheim Our file number: 255 4/3 Shumpei ΪΑΜΑΖΑΚΙ Pat en tge search, October 18, 1971 Pat en-f? talks M ./semiconductor arrangement with at least one on one Semiconductor substrate arranged insulating coating, characterized in that cluster (3f 7) and / or a Thin film (3; 7) made of semiconductor material in a predetermined geometric configuration, preferably layered, are arranged in the area of the Q-rense between two insulating coatings (2, 4; 2, 6) « 2. Semiconductor arrangement according to claim 1 _f, characterized in that several insulating? Coatings (2, 4, 6, 8, 11) are provided, and that clusters (3 »7) and / or thin films (5, 7) arranged in layers at the interfaces of at least one part (2, 4? 6) of this coating are made of semiconductor material « 3 ", semiconductor arrangement according to claim 'or S ₅ dadurek. characterized in that the current flow is controlled under the Überaügc? - ^ (2, 4} 2, 4, 6) using a cluster and / or the thin film or the thin films as a trap for charges _f thereby the type of charge received and the amount of charge of the charge is controlled. ORIGINAL INSPECTED - 2Γ - 4. Semiconductor arrangement according to at least one of claims 1 to 3 »characterized in that it is as MIS field effect transistor (Fig. 1) is formed, its arrangement of insulating layers and clusters and / or a thin film or thin films (3, 7) the gate (1) is assigned. 5ο semiconductor arrangement according to at least one of the Claims 1 to 4 »characterized in that the clusters (3i 7) and / or the thin film or the thin films (31 7) are made of silicon or germanium. "6. Semiconductor arrangement according to at least one of the preceding claims, characterized in that the insulating layers (2, 4 * 6) that make up the clusters (3, 7) and / or the thin film or the thin films (3, 7) contained between them, made of silicon nitride, silicon oxynitride, germanium nitride, silicon oxide and / or Aluminum oxide or a combination of some of these substances are formed. 7. Semiconductor arrangement according to at least one of the preceding claims, characterized in that the cluster (3j 7) or a thin film {5% 7) of semiconductor material at a distance of less than 200 pounds, preferably between 10 and 50 A, from the semiconductor substrate (5 ) are or is arranged. Semiconductor arrangement according to at least one of the preceding claims, characterized in that, in the case of a crayon having a control electrode (1), a cluster (7) or a thin film (7) made of semiconductor material at a distance of less than 200 'L _1, preferably between 10 and 100 £, from this control electrode are or is » : ·; 2 0/090 9. Semiconductor arrangement according to at least one of the preceding claims, characterized in that the semiconductor material of the clusters (3 to 7) and / or the thin film or the thin films (3, 7) with an impurity is doped, which results in a B line or an N line. at least, 10. Semiconductor arrangement according to one of the preceding claims, characterized in that at least the insulating layers (2, 4, 6), which the clusters (3, 7) and / or the thin film or the thin films (3, 7) contained between them, poor in clusters and preferably at least substantially free from clusters. 11. The method for manufacturing a semiconductor device according to at least one of the preceding claims, characterized by the following process Bchrittet ^ s minde least cluster poor. 1. that on a semiconductor substrate (5) a Yein- or multilayer insulating coating (4; 4, 11) is produced, 2. That on dean insulating coating semiconductor clusters (3; 7) or a semiconductor thin film (3 | 7j is produced will or will, and 3. that at least one low-cluster isolating Coating (2j 6) is formed on the semiconductor clusters (3} 7) or the semiconductor thin film (3j7) will. 12. The method according to claim 11, characterized in that that after process step 3 at least some of the process steps mentioned are repeated, to create an arrangement with several in one as required Layers (3, 7) of clusters and / or thin films of semiconductor material arranged in an insulating coating obtain. 209820/0906 13. The method according to claim 11 or 12, characterized characterized in that the cluster and / or the thin film by chemical vapor deposition or by vacuum evaporation getting produced. 14. The method according to at least one of claims 11 his 13, characterized in that for the production the cluster and / or the thin film is a silicide gas or a gaseous germanium compound with ammonia or hydrazine is used in a volume ratio of 1: 1 or less. 15. The method according to claim 14, characterized in that that as silicide gas silane, dichlorosilane, trichlorosilane or Silicon tetrachloride is used. 16. The method according to claim 14, characterized in that the gaseous germanium compound germanium hydrogen or germanium chloride is used. Patent attorneys Dipl.-Ing. Horst Rose Dipl.-Ing. Peter Kose! 209820/0906 Blank page