DE20120385U1 - Circuit arrangement for analog to digital conversion of a time continuous input signal uses comparators to compare with a reference and a logic device - Google Patents

Abstract

A circuit for A/D conversion of a continuous input signal which may have interference uses comparators (20-27) to compare with a reference and a logic device (110) for digital conversion. A device (100) detects the time separation between two directly following sides of signals and amplifies this if less than a minimum. A circuit for A/D conversion of a continuous input signal which may have interference has many comparators (20-27) to compare it to a reference and a logic device (110) to convert their output into a multiplace digital word. A device (100) next to the comparators detects the time separation between two directly following sides of two digital output signals and amplifies this by an adjustable amount if it is less than a minimum value.

Description

OHC 0410DEG iC-Haus GmbH

Circuit arrangement for A/D conversion of at least one continuous-time input signal

The invention relates to a circuit arrangement for converting at least one time-continuous input signal, which may have interference, into a multi-digit digital word according to the preamble of claim 1.

A/D converters for converting continuous-time input signals into a corresponding multi-digit digital word are well known. A/D converters that work according to the parallel method, for example, have several comparators on the input side to which equidistant reference voltages are applied in addition to the continuous-time input signal to be converted. These reference voltages are generated using a voltage divider. Depending on the amplitude of the analog input signal, the comparators generate a logical one or a logical zero at the output. These logical output states of the comparators are converted in a logic device, for example in a priority decoder, into a corresponding multi-digit digital word, for example a binary number that is proportional to the current amplitude value of the continuous-time input signal. Such an A/D converter can be found, for example, in the textbook by U. Tietze et. al. "Semiconductor Circuit Technology", 11th edition, Springer Verlag, page 1047".

One problem with A/D converters is that the time-continuous input signals to be converted can contain interference, for example in the form of spikes, which are short interference pulses. These interferences can lead to the digital signals generated in the logic device having such short pulse lengths that subsequent digital signal processing or evaluation, e.g. in a counter, can no longer be carried out without errors due to its limit frequency.

The invention is therefore based on the object of providing a circuit arrangement for converting at least one time-continuous input signal into a multi-digit digital word, which enables correct processing or evaluation of a converted multi-digit digital word even in the case of an input signal having pulse-like interference.

The core idea of the invention is to ensure that a minimum time interval is maintained between two immediately consecutive edges of different comparator output signals. This is because, as a result of particularly pulse-like disturbances in the input signal, several comparators can be connected in series at very short time intervals. This means that the time interval between two immediately consecutive edges of different comparator output signals becomes so short that a subsequent processing device cannot correctly recognize and further process the converted multi-digit digital word.

The above-mentioned technical problem is solved by the invention with the features of claim 1.

According to this, a circuit arrangement is provided for converting at least one continuous-time input signal, which may be disturbed, into a multi-digit digital word,
wherein the circuit arrangement comprises several comparators for
respective comparisons of the temporally continuous
input signal with a suitable reference signal and a logic device for converting the digital output signals of the comparators into a multi-digit digital word
To avoid that, as a result of interference,
Example in the form of voltage peaks in the input signal the switching times of several comparators are so short

successive that error-free processing of a digital word converted in the logic device is not
is no longer possible, the comparators are provided with a device for detecting the time interval between two
immediately consecutive edges of two digital output signals from different comparators. The device is also designed to increase the detected
time interval by an adjustable amount
trained if this time interval is a
The minimum time interval depends, among other things, on the

Cutoff frequency of a logic device connected downstream
processing facility.

Advantageous further training is the subject of
Subclaims.

For example, the detection and
Magnification device a monoflop to enlarge the

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time interval between the detected successive edges.

The logic device advantageously supplies two incremental output signals which form a two-digit digital word. Such logic devices, which do not generate the proportional, i.e. absolute numerical value of the instantaneous value of a continuous-time input signal to be converted, but only the change and direction of the change in the input signal, are generally known.

In one embodiment, a continuous-time input signal is applied to the first input of each comparator, whereas equidistant reference voltages dropped across a voltage divider are applied to the second input of the comparators.

An alternative embodiment for a sine/digital conversion provides that a sinusoidal input signal is applied to one comparator and a cosinusoidal input signal is applied to another comparator, with an input signal being applied to each of the remaining comparators which corresponds to a predetermined combination of the sinusoidal and cosinusoidal input signals. The combination of the sinusoidal and cosinusoidal input signals is carried out, for example, in such a way that successive switching times of two comparators are equidistant when the input signals are not disturbed, and are therefore proportional to the angle values of the sinusoidal input signal.

The invention is explained below using an embodiment in conjunction with the enclosed

Drawings explained in more detail.
Show it:

Fig. 1 is a schematic block diagram of an A/D converter according to the parallel method in which the invention is implemented, Fig. 2A shows the time course of a disturbance-free

sinusoidal and cosinusoidal input signal, Fig. 2B the time course of the interference-free output states of the comparators shown in Fig. 1,

Fig. 2C the time course of the fault-free

incremental output states of the logic device, Fig. 3A the time course of a disturbed sinusoidal and cosinusoidal input signal, Fig. 3B the time course of the disturbed

Initial states of the shown in Fig. 1

Comparators,
Fig. 3C shows the temporal progression of the faulty incremental output states of the logic device, Fig. 4A shows the temporal progression of the output states of the

Fig. 1 shown correction device, and Fig. 4B the time course of the inventive

corrected incremental output states of the

Logic device.
25

Fig. 1 shows an example of an A/D converter 10, in this case a sine/digital converter, which has eight comparators 20 to 27 on the input side. A sinusoidal input signal is applied to the first input of the comparator 20. A suitable reference signal REF is applied to the second input of the comparator 20, which in the present example is the center voltage (DC potential) of the sinusoidal signal. As Fig. 1 shows, a cosinusoidal

Input signal applied. The reference signal REF is applied to the second input of the comparator 2 4. An input signal is applied to each of the comparators 21 to 23 and 25 to 27, which results from a suitable combination of the sinusoidal and cosinusoidal input signals. The combination rule can, for example, correspond to the addition theorem asin (tut) +bcosinus (tut ). The weighting factors a and b are selected such that the successive switching times of the comparators 20 to 27, i.e. for example the switching times of the comparators 20 and 21, the switching times of the comparators 21 and 22, etc. up to the switching times of the comparators 26 and 27 are equidistant from one another in the case of undisturbed input signals with a constant frequency. The combination of the input signals is symbolically represented in Fig. 1 by the weighting elements 30, 31, 40, 41, 50, 51, 60, 61, 70, 71 and 80, 81 and the adders 90 to 95.

The output signals of the comparators 20 to 27 are applied to a correction device 100, which according to the invention ensures that in the case of disturbed input signals, the time interval between two immediately consecutive edges of two different output states or output signals of two comparators does not fall below a minimum time interval. The functioning of the correction device 100 is described in more detail below.

The output signals of the comparators 20 to 27 corrected in the correction device 100 are then fed to a logic device 110, which in the present example in a manner known per se calculates the

Output signals of the comparators 20 to 27 generate an incremental output signal a and an incremental output signal b as well as a start signal c. The incremental output signals a and b form a two-digit digital word which does not reflect the proportional numerical value of an instantaneous amplitude of the input signal to be converted, but merely the change and the direction of the change in the input signal. In this way, even with a very large number of comparators, it is possible to manage with just two output lines to represent the two-digit word in order to carry out an A/D conversion. In other words, a time-continuous input signal received by &eegr; comparators is converted into a digital two-digit word.

The functionality of the A/D converter 10 shown in Fig. 1 is explained in more detail below using Figures 2A to 4B.

As already mentioned, it is assumed that a sinusoidal input signal is applied to the comparator 20 and a cosinusoidal input signal is applied to the comparator 24, a complete period of each of which is shown in Fig. 2A.

It should be noted that Figures 2A to 2C represent the ideal, i.e. trouble-free operating state.

Fig. 2B shows the output states of the comparators 20 to 27, with the lowest curve showing the logical output or switching state of the comparator 20 and the fourth curve from the top showing the logical output or switching state of the comparator 24. The second curve from the bottom shows the output state of the comparator 21, the third curve from

bottom shows the output state of comparator 22 and the fourth curve from the bottom shows the output state of comparator 23. The sixth curve from the bottom shows the output state of comparator 25, the seventh curve from the bottom shows the output state of comparator 26 and the top curve shows the temporal output state of comparator 27, during one period length.

As Fig. 2B clearly shows, the time interval between two immediately successive edges of the output states of the comparators 20 to 27 is equidistant.

Fig. 2C shows the incremental output signals a and b of the logic device 110. The upper curve in Fig. 2C shows the output signal a, whereas the lower curve represents the output signal b. From the temporal progression of the output states a and b at the output of the logic device 110, it can be seen that with each change in the output state of one of the comparators, the output states a or b change, and indeed alternately.

The starting time for the conversion operation of the A/D converter 10 is determined by the start signal c. In the present example, the conversion of the input signals begins at the time t=0, i.e. the cosine-shaped input signal is maximum while the sine-shaped input signal is zero.

For further explanation, we now consider the operation of the A/D converter 10 with noisy input signals. As Fig. 3A shows, a noisy sine signal is present at the comparator, whereas a noisy cosine signal is present at the comparator 24. Fig. 3B again shows the

temporal progressions of the output states of the comparators 20 to 27. Up to time ti, the input signals are undisturbed, so that the output signals of the comparators, as shown in Fig. 3B, also have the same temporal distance from each other up to time ti. At time ti, however, there is a sudden disturbance of the sinusoidal and cosinusoidal input signal. This means that the switching times of the comparators 24 to 26 essentially coincide.

Without the interposition of the correction device 100, the logic device 110 would generate the temporal output states a and b shown in Fig. 3C. The second pulse of the output signal b would be so short that a downstream of the logic device 110

Processing device, for example a digital counter, would not count this pulse due to its limit frequency and would therefore deliver an incorrect counting result.

In order to avoid such distortions in the output signals a and b of the logic device 110, the output signals of the comparators 20 to 27 are fed to the correction device 100. The correction device 100 detects the edges in the output signals of the comparators 20 to 27 and compares the time intervals between two immediately consecutive edges of two output signals. In other words, the correction device 100 determines, among other things, the time interval between the rising edge of the output signal of the comparator 20 and the rising edge of the output signal of the comparator 21. The time interval between the rising edge of the output signal of the comparator 21 and the rising edge of the

Output signal of comparator 22 is compared, etc. The correction device 100 determines that up to time ti the time intervals between immediately successive edges, which correspond to the switching times of the respective comparators, comply with the required minimum time interval. When the disturbance of the input signals begins, approximately at time ti, the correction device 100 recognizes that the time intervals between the rising edges of the two output signals of comparators 24 and 25 and 25 and 26 have fallen below the minimum time interval. The correction device 100 also detects an undershoot of the minimum time interval between the rising edges of the output signals of the comparators 25 and 26. A delay device, designed for example as a monoflop, ensures that the time interval of the rising edges between the output signals of the comparators 24 and 25 and the rising edges of the output signals of the comparators 2 and 6 are shifted relative to one another in such a way that the required minimum time interval between the respective output signals is achieved. The corrected output signals of the comparators 20 to 27 present at the output of the correction device 100 are shown in Fig. 4A. The incremental output signals a and b of the logic device 140 resulting thanks to the corrected comparator output signals are shown in Fig. 4B. As can be clearly seen, as a result of the corrective measure carried out in the correction device 100, the length of the second pulse in the incremental output signal b of the logic device 110 could be extended, so that a counter connected downstream of the logic device 110 could detect the pulses of the incremental output signals a and b without error and

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can process.

Thanks to the correction device 100, which is arranged between the comparators 20 and 27 and the logic device 110, it is possible to suppress interference peaks occurring in the input signals by correcting the time behavior of the disturbed output signals of the comparators 20 to 27 so that, for example, counting pulses are lost in a downstream digital counter.

Claims (5)

1. Circuit arrangement for converting at least one time-continuous input signal, which may have interference, into a multi-digit digital word, the circuit arrangement having a plurality of comparators (20-27) for comparing the time-continuous input signal with a reference signal (REF) and a logic device ( 110 ) for converting the digital output signals of the comparators ( 20-27 ) into a multi-digit digital word, characterized by a device ( 100 ) assigned to the comparators ( 20-27 ) for detecting the time interval between two immediately successive edges of two digital output signals of corresponding comparators ( 20 , 21 ; 21 , 22 ; 22 , 23 ; 23 , 24 ; 24 , 25 ; 25 , 26 ; 26 , 27 ) and for enlarging of the detected time interval by an adjustable amount if the time interval falls below an adjustable minimum time interval. 2. Circuit arrangement according to claim 1, characterized in that the device ( 100 ) has a monoflop for increasing the time interval. 3. Circuit arrangement according to claim 1 or 2, characterized in that the logic device ( 110 ) supplies two incremental output signals which form a two-digit digital word. 4. Circuit arrangement according to one of claims 1 to 3, characterized in that the logic device ( 110 ) is connected to a digital evaluation and/or processing device, in particular a counter. 5. Circuit arrangement according to one of claims 1 to 4, characterized in that a sinusoidal input signal is applied to one comparator ( 20 ), a cosinusoidal input signal is applied to another comparator ( 24 ), and an input signal is applied to each of the remaining comparators ( 21-26 ), which corresponds to a predetermined combination of the sinusoidal and cosinusoidal input signals.