DE19821539C1 - Switching arrangement, and method for recognition and control, of attached electrical load - Google Patents

Abstract

The arrangement uses a capacitor attached to the output of the load switch. A voltage is applied to the capacitor (C) for one time period during which the load is applied at load output (LA). The voltage divider (R1,R2) feeds voltage back to the input port of the microprocessor which recognizes whether a load is attached or not. The port (P) has a digital value which is applied for a second time period.

Description

The invention relates to a circuit arrangement for detection and control a connected electrical load with a microprocessor and with a electrical load switch, whose control input is connected to a port of the Microprocessor is connected and at its load output the electrical load can be connected, and one to be executed by the circuit arrangement Procedure for the detection of a switched on load.

Devices and methods for controlling and monitoring electrical Loads are for example from DE 40 05 609 A1 and DE 43 38 462 A1 known.

Such devices use a first signal channel Control and a second signal channel for monitoring the load. Is the Control device a microprocessor, this means that for each load to be controlled and monitored thus two ports of the microprocessor are occupied. If there are several connected loads, they are the ones few port connections for simple and inexpensive microprocessors quickly exhausted.

From DE 43 44 013 C1 an electrical circuit arrangement with one of a microcomputer controllable semiconductor switching element, by means of which a Consumer can be switched on or off, known. This circuit serves the consumer with regard to fault currents (e.g. short-circuit currents) to monitor. This circuit arrangement is wired so that only one Microcomputer connection for the control and monitoring of the Consumer group is needed.

For some applications it can now be particularly important that the Microprocessor automatically detects whether on a through a specific port controlled load output a load is connected or not or, at several ports, of which loads are connected, so that the  Microprocessor its control program according to the connected loads can adjust.

It is therefore the object of the invention to create a circuit arrangement which is simple and inexpensive and with which the microprocessor both recognize and recognize the same digital port an electrical load can control. In a further embodiment of the invention, a  The simplest possible method to be carried out by the circuit arrangement to identify a connected load. This task is solved according to the invention in that with the load output Capacitor is connected and that the voltage across the capacitor is led to the port of the microprocessor via a voltage divider arrangement and that the total resistance of the voltage divider arrangement is greater than that Internal resistance of the connected load, and further by the associated method claim 3.

The circuit arrangement according to the invention thus has to implement the Load detection function only three additional passive - and therefore inexpensive - Components (2 resistors and 1 capacitor). It is also advantageous that for Load detection no external cabling is required, as z. B. for Load detection via coding is required.

Another advantage is that the dimensioning of the components Circuit to be adapted to the internal resistance of the load to be recognized can. The load switch used can also be particularly simple and be inexpensive because he himself has no means of load detection needs.

The proposed method is also very simple and therefore Can be implemented inexpensively in the program of the microprocessor.

In the following an embodiment of the invention with reference to the drawing shown and explained in more detail.

Show it

Fig. 1 shows a circuit arrangement according to the invention

Fig. 2 is a diagram showing the time course of two voltages.

Fig. 1 shows a microprocessor (MP), the port (P) with the control input (SE) of an electronic load switch (LS), z. B. is connected as a bipolar transistor or as a power MOS-FET. If the microprocessor (MP) controls the load switch (LS), the load switch (LS) switches a positive voltage (U +) to its load output (LA). An external load (L) can be connected to the load output (LA).

A capacitor (C) is also connected to the load output (LA) and is charged to the voltage (U _out ) present at the load output (LA). In parallel to the capacitor (C) is a voltage divider arrangement (R ₁ , R ₂ ) whose tap point is connected to the port (P) of the microprocessor (MP), so that a resistance ratio (R1 / (R ₁ + R ₂ ) A predetermined fraction of the capacitor voltage (U _out ) reaches the port (P) of the microprocessor (MP) A Zener diode (ZD) connected in parallel with the resistor (R1) ensures that the maximum permissible input voltage at the port (P) is not exceeded.

The dimensioning of the resistors (R1, R2) and the capacitor (C) depends on the internal resistance of the load (L) intended for connection as well on the timing of the test program of the microprocessor and can can be easily adapted to the respective requirements. An exemplary Dimensioning of the components is indicated in the figure.

It is striking that the total resistance (210 kΩ) of the voltage divider arrangement (R ₁ , R ₂ ) is very large compared to the internal resistance (1 kΩ) of the load (L). Therefore, the charged capacitor (C) is discharged very slowly when the load switch (LS) is switched off via the voltage divider arrangement (R ₁ , R ₂ ) and, in contrast, comparatively quickly when a load (L) is also connected to the load output (LA).

This is the basis for the method for load detection, which is explained in more detail below with the aid of FIG. 2.

FIG. 2 shows in the upper half of the diagram the time course of the voltage (U _out ) applied to the capacitor (C); in the lower half the signal voltages (U _sig ) output by the port (P).

In the first process step, the microprocessor (MP) switches the port (P) to HIGH for a first predetermined time (T1) of two milliseconds. This switches the load switch (LS) on and charges the capacitor (C) to the maximum output voltage. The microprocessor (MP) then switches the signal voltage (U _sig ) of the port (P) to LOW for a second predetermined time period (T2) from 4 milliseconds. During this period (T2), the capacitor (C) is discharged via the voltage divider arrangement (R ₁ , R ₂ ) and, when the load (L) is switched on, above all via its comparatively low internal resistance. As FIG. 2 shows, the voltage across the capacitor (U _out ) drops much faster when the load is switched on than without a load.

After the second predetermined time period (T2), the microprocessor (MP) switches its port (P) as an input and checks whether the fraction of the capacitor voltage (U _out ) passed to the port (P) via the voltage divider arrangement (R ₁ , R ₂ ) ) corresponds to a logical HIGH or LOW level. The former interprets the microprocessor (MP) as a missing load, the latter on the other hand as an on load (L) at the load output (LA).

The microprocessor (MP) then repeats the process to move to Certainty to reproduce the result. The procedure is scheduled after two identical test results or after a specified maximum Number of test runs.

Reference list Circuit arrangement and method for the detection and control of a connected electrical load

C capacitor
Lload
Load load output
LS load switch
MP microprocessor
R1 Resistance
R2 resistance
(R ₁

, R ₂

) Voltage divider arrangement
SES control input
ZDZener diode
First predetermined period of time
T2 second predetermined time period
U + positive voltage
U _out

voltage present at the capacitor
U _sig

Signal voltage

Claims (4)

1. Circuit arrangement for the detection and control of an connected electrical load (L) with a microprocessor (MP) and with an electrical load switch (LS), the control input (SE) of which is connected to a port (P) of the microprocessor (MP) and at the latter Load output (LA) the electrical load (L) can be switched on, characterized in that a capacitor (C) is connected to the load output (LA) and that the voltage (U _out ) applied to the capacitor (C) is connected via a voltage divider arrangement (R ₁ , R ₂ ) to the port (P) of the microprocessor (MP) and that the total resistance of the voltage divider arrangement (R ₁ , R ₂ ) is greater than the internal resistance of the connected load (L). 2. Circuit arrangement according to claim 1, characterized in that a Zener diode (ZD) is connected to the port (P). 3. A method for detecting a connected load, to be carried out by a circuit arrangement according to claim 1, characterized by the sequence of the following method steps:

• a) the microprocessor (MP) controls the load switch (LS) for a first predetermined time (T1), so that the load output (LA) is switched on;
• b) the microprocessor (MP) ends the activation of the load switch (LS) and, after a second predetermined time period (T2), checks which digital logic value the voltage applied to the port (P) corresponds to.

4. The method according to claim 3, characterized in that the Microprocessor (MP) the process sequence several times as long executes the same result in succession until twice in succession is present or a maximum, predeterminable number of process runs has been carried out.