DE19811578A1 - Multiple layer circuit board especially for chip card - Google Patents

Abstract

The circuit board has at least two electrically insulated carrier layers (2,3) which are arranged one on top of the other in different planes. It also has at least two conductive track layers (6,11) at least one arranged on each carrier layer. The two carrier layers are connected to each other at a common side edge (4). The carrier layers may be formed in one piece. They may be connected together at facing surfaces. In the latter case at least one adhesive layer may be provided between the carrier layers.

Description

The invention relates to a multilayer printed circuit board which ins is especially intended for the production of a chip card. The The invention further relates to a method of manufacture a multilayer printed circuit board, a method of manufacturing a multi-layer electrical circuit and a chip card with a multilayer printed circuit board.

With multilayer printed circuit boards there are often at least two electrically insulating base layers, in particular made of art fabric arranged on top of each other in different levels. On the insulating base layers are at least two conductors provided web layers, here at least one of the support has at least one interconnect layer.

In the chip cards of the prior art, the genus appropriate multilayer printed circuit board used for high win numbers with a transmission / reception coil of the chip card realize. For this purpose, several layers of coil turns in Multi-layer technology generated on top of each other, by a Etching technology on the respective card circumference. In addition, at increasing complexity and increasing number of in the chip Components included in the map also include a larger scope Wiring needed.

In the generic chip cards and in the known Lei terplatten is disadvantageous that they are expensive to manufacture are.

It is therefore an object of the invention, a circuit board and egg ne chip card to provide a multi-layer structure allowed with little manufacturing effort. It is beyond that Object of the invention, corresponding manufacturing processes  for multilayer printed circuit boards and multilayer electrical To provide circuits.

This task is the subject of the independent An sayings solved. Advantageous configurations result from the respective subclaims.

According to the invention it is provided that the insulating Base layers on one side edge of the multilayer conductor plate or the multi-layer electrical circuit with each other who are connected.

This training has numerous advantages the manufacture of the circuit board according to the invention or electrical circuit. Because of the special training namely ensures that the two base layers on simp che way can be aligned to each other before be connected to each other. For this, the two need Base layers only along the common side edge be folded together. According to the basic idea of the inventor can more than two base layers in the inventions Intended circuit board or electrical circuit to be seen. Then there are two base layers on a ge common side edge joined together.

The base layers can be egg along before folding ner common side edge to be connected or also integrally formed in one piece from the outset be. With a one-piece training, the front results part that the multi-layer circuit board or electrical scarf tion initially as a continuous circuit of a corre sponding Larger format can be produced. For this you can NEN known and inexpensive methods are used. In a final step of folding the lei then the multi-layer arrangement of the different base layers.  

In a further embodiment of the invention, we can at least two base layers, one adhesive layer each be seen with which the base layers ver ver be bound. This will increase the durability of the circuit board or the electrical circuit improved.

The conductor track layers can be made of copper cladding have conductor tracks. In this version of the Er invention, the circuit board can advantageously with conventional Lichen manufacturing process for single-layer circuits be put.

If between each of two base layers a Di punched layer is provided, then the desired thickness the PCB can be adapted to any requirements. It is also possible to have at least one in the spacer layer Vorzuse recess for receiving an electrical component hen. In this training can in the recess or in the recesses in electrical components such as microchips be set so that they are no longer accessible from the outside. In addition, it can protect electrical construction sometimes against environmental influences.

In a further embodiment of the invention it is provided that we at least one base course at least one across the main Through direction extending the base layer has clocking opening. With such a through contact The opening can also be complex multilayer circuits generated when the via opening with a Filling made of conductive material such as conductive adhesive, silver paste or solder is provided. This means that traces can be created connect at different levels.

In particular, a coil with a very high height can be used Form number of turns if at least two conductor tracks layer each coil turns with connection ends sen. The connection ends of the coil turns of the respective  Conductor layers are then through-plated openings connected to each other that the respective coils turns into a single coil with increased turns number are connected in series.

The inventive method for producing a multilayer printed circuit board or a multilayer electrical circuit device thus provides the following steps:

• - Provide at least one interconnect layer the electrically insulating material,
• - Folding the circuit board material by folding along at least one bending line, so that at least two each separated by a bending line and superimposed PCB sections be det.

There is at least one before the step of providing Conductive layer, electrically insulating Lei plate material the step of manufacturing the conductor plate material provided.

Further procedural steps relate to the provision of the characteristics of the multilayer Lei according to the invention terplatte or multi-layer electrical circuit.

Finally, the invention is also ver in a chip card really light, which has a circuit board according to the invention.

Since the chip card production anyway a laminating or Heat sealing process for the permanent connection of all components contains the realization of a coil and wiring device on the chip card from two thin flexible printed Circuits suggested that only in the laminating or Heat sealing process can be connected to each other. This will a relatively expensive conventional multilayer circuit board technology avoided. In addition, circuits in tape format can be used be manufactured and there are a number of design variants  ten possible, which a cost adjustment to the under allow different levels of complexity of the card.

So depending on the requirements of the coil and wiring For example, two single-layer circuits combined be kidneyed. It can also be a single-ply and a two-ply or two two-layer circuits combined become. There are also several single-layer or two-layer scarves possible on top of each other. The circuits can each because as a continuous circuit of a correspondingly large Outer measure are made, from which by the Invention appropriate conductor routing and by a fold around one side edge several turns arise. The need forth conventional electrical vias are directed according to the requirements of wiring. The electrical con Clocking of the pure coil layers is mini according to the invention lubricated and can also be done by other methods.

An inventive structure preferably sees a double sided flexible circuit of about double chip card size in front. With a special coil layout it is achieved that after the folding process all turns are rectified where is ensured by special training that a maximum of two plated-through holes between the individual win situations are necessary. By folding around an axis along a common side edge of the two turns The final format of the chip card is roughly the same. This makes it a coil-shaped antenna with four layers testifies.

After that, the circuit is usually like a circuit board plated through. Are no or only a few more through Contacting necessary, so inexpensive Al alternative method to common chemical and galvanic measurement use metal deposits. For example, are an embossing welding, solder or conductive adhesive contact possible.  

If a through contact for the wiring of the components tated and possibly even multi-layer circuit board necessary is, the two circuit halves can be separately be put and the electrical connection of both halves can be done via a solder or conductive adhesive connection.

Furthermore, it is also possible to assemble the components Use conductive adhesive connections with the heat sealing process are compatible. With these connections can also through contacts are replaced. Components within the inventions electrical circuit according to the invention can also in wire con clockings are connected.

The structure of the chip card according to the invention consists of several contiguous base layers, whether folded or ge are also offers the advantage of chip and construction Arrange elements between the base layers, making them are protected from environmental influences. Will not be the complete one Production of the chip card desired in one hand, so can also only a spacer layer can be provided with Circuits and components are provided ready-made becomes. Such a spacer layer depends on the individual then only to be provided with decorative outer layers.

The invention is in the drawing based on several Ausfü examples.

Fig. 1 shows a cross section of a multi-layered electrical circuit according to the invention in a side view,

Fig. 2 1 shows a plan view of the electric circuit of Fig. Apart in folded position,

Fig. 3 shows a view of the electric circuit of Fig. 2 from below,

Fig. 4 shows a cross section through a further OF INVENTION dung correct electrical circuit,

Fig. 5 shows a cross section through a further OF INVENTION dung correct electrical circuit,

Fig. 6 shows a cross section through a further OF INVENTION dung correct electrical circuit,

Fig. 7 shows a cross section through a via opening,

Fig. 8 shows a cross section through a further through contact hole,

FIG. 9 shows the via opening from FIG. 8 after contacting,

Fig. 10 shows a cross section through a further through contact hole,

Fig. 11 shows a cross section through the Durchkontaktie convergence opening of FIG. 10 after Durchkontaktie ren.

Fig. 1, Fig. 2 and Fig. 3 show a multilayer printed circuit board 1 in different views.

The circuit board 1 has an upper base layer 2 and a lower base layer 3 , which are integrally connected to one another at a bending edge 4 . In Figs. 1 to 3, a coordinate system 5 is provided is on the upper support layer 2, the layer of the positional representation of the upper support 2 in the several views sets. In Fig. 2, the chip card 1 from Fig. 1 in the opened state in the plan view of the upper support layer 2 from Fig. 1 shows ge. In the view of Fig. 2, the upper base layer 2 and the lower base layer 3 are in one and the same plane.

In contrast to the illustration from FIG. 2, FIG. 3 shows the top support layer 2 from FIG. 1 in a view from below. Thus, Fig. 3 shows the representation of the unfolded th circuit board 1 of Fig. 2 in the view from below.

As can be clearly seen from FIGS . 1 to 3, the upper support layer 2 and the lower support layer 3 are formed in one piece from a plastic material as a coherent circuit board area. On the upper sides of the upper base layer 2 and the lower base layer 3 is a first conductor 6 hen hen, which has a single continuous first conductor 7 . One end of the first guide 7 opens into a quadra tables upper contact 8 and the other end of Lei first ters 7 opens into a round upper contact. 9 The first conductor 6 is designed so that there are two coil-shaped structures on the upper side of the upper support layer 2 and lower support layer 3 , which are connected by an upper connec tion conductor 10 .

The circuit board section shown in FIG. 3, formed from the upper support layer 2 and the lower support layer 3 , has a second conductor track 11 on its underside, which corresponds to the first conductor track 6 from FIG. 2. It is formed from a second conductor 12 which is arranged continuously on the underside of the upper base layer 2 and the lower base layer 3 . The second conductor 12 opens into a square lower contact 13 , which is arranged exactly opposite to the square upper contact 8 . The other end of the second conductor 12 opens into a round lower contact 14 , the ge opposite of the round upper contact 9 is net angeord. The second conductor 12 forms two coil structures which are connected to one another by a lower connecting conductor 70 .

In the folded state, the upper support layer 2 and the lower support layer 3 lie one on top of the other, as shown in FIG. 1. The round upper contact 9 and the round lower contact 14 are connected to each other by a via, so that there is a coil changeover point. The coil thus formed can be closed via the square upper contact 8 and the square lower contact 13 . If the beginning and end of the coil are desired at the end of the same level, the contacts 8 and 13 are not exactly opposite, but offset. A further transfer point with plated-through holes allows one contact to be routed to the other's level. As can be seen in Fig. 1, the coil thus formed has four Spulenab sections, which are electrically connected in series, so that there is a four times the number of coil turns compared to a single coil section.

The upper support layer 2 and the lower support layer 3 can be provided with conductor tracks or openings in the coil sections as desired. As an alternative to that shown in FIG. 1. Arrangement can also be made several folds of more than two base layers, wherein a flexible plastic film provided only on one side with conductors can be used.

Fig. 4 shows a cross section through a part of a multi-layered electrical circuit 15. The electrical circuit has an upper support layer 16 and a lower support layer 17 made of insulating material. Between the upper support layer 16 and the lower support layer 17 , a spacer core 19 is fastened with each egg ner adhesive layer 18 . The Di punch core 19 has a through hole 20 .

On the top and on the underside of the upper support layer 16 , conductor tracks 21 are provided, and on the upper side and the underside of the lower support layer 17 , conductor tracks 22 are provided. The conductor tracks 21 and 22 are electrically conductive because verbun by each other at the via opening 20 is attached to the conductive material 23.

Fig. 5 shows a portion of a further electric circuit 24 in cross section. The electrical circuit 24 has an upper base layer 25 with conductor tracks 26 on its top and bottom and a lower base layer 27 with conductor tracks 28 on its top and bottom. Between the upper support layer 25 and the lower support layer 27 , a spacer core 29 is provided which has a recess 30 . In the recess 30 , a chip component 31 is inserted and electrically conductively connected to the conductor tracks 26 and 28 via conductive adhesive fillings 32 .

For the firm connection of the lower support layer 27 with the OBE ren support layer 25 between the core spacer 29 and the lower support layer 27 and the upper support layer 25 is provided in each case an adhesive layer 33rd

Fig. 6 shows a portion of another inventive electric circuit SEN 34 in cross section. The electrical circuit 34 has an upper base layer 35 which is provided on its top and bottom with conductor tracks 36 . The, conductor tracks 36 are conductively connected to one another at a via 37 .

Furthermore, a lower support layer 38 is provided, which is provided with conductor tracks 39 . The conductor tracks 39 are conductively connected to one another at a second via point 40 .

The conductor tracks 36 and 39 are made of a copper cladding with a thickness of 25 microns. The material from which the upper base layer 35 and the lower base layer 38 is made has a thickness of 50 μm.

Between the upper support layer 35 and the lower support layer 38 , a spacer core 41 is provided, which contains a first recess 42 for receiving a first microchip 43 and a second recess 44 which contains a second microchip 45 . The first microchip 43 is connected to the conductor tracks 39 via conductive adhesive connections, the conductive adhesive connections being compatible with a heat sealing process. A remaining cavity between the first microchip 43 and the surface of the first recess 42 is filled with a filler 46 . The spacer core 41 has a thickness of 300 µm.

The second microchip 45 in the second recess 44 is in contact with the conductor tracks 39 via wire connections 47 . On the second microchip 45 , a protective layer 48 is applied, which protects the second microchip 45 and the wire connections 47 against environmental influences. A space between the protective layer 48 and the inner surface of the second recess 44 is filled with a filler 49 .

In the embodiment shown in FIG. 6, it should be noted that the upper support layer 35 has broken out in the region of the second recess 44 , so that the second microchip 45 can be fitted on the spacer core 41 after the assembly of the upper support layer 35 and the lower support layer 38 . For the firm connection of the upper base layer 35 , the lower base layer 38 and the spacer core 41 , two thin adhesive layers 50, each with a thickness of 50 μm, are used.

Outside are on the upper base layer 35 and the lower base layer 38 each have a cover and decorative layer 51 brought up, which protects the internal components of electrical circuit 34 against environmental influences and which can be seen ver with imprints.

Fig. 7 shows a portion of a Lei terplatte 52 according to the invention in cross section. The circuit board 52 has a support layer 53 , on the upper side of which an upper conductor track 54 is provided. On the underside of the support layer 53 , a lower conductor track 55 is arranged. Upper interconnect 54 and lower interconnect 55 are connected via a via 56 provided in the support layer 53 , which is introduced using an embossing welding process. Due to the pressure generated during the production of the via 56 , the upper conductor track 54 is provided with a recess 57 in the region of the via 56 .

Fig. 8 shows a portion of another inventive SEN circuit board 58 in cross section. The circuit board 58 has a support layer 59 , on the top of which an upper conductor track 60 is arranged. A conductor track 61 is provided on the underside of the support layer 59 . In the region shown in FIG. 8, the support layer 59 has a through-opening 62 which extends through the upper conductor track 60 and the lower conductor track 61 . When the via opening 62 is brought in, a depression 63 has been formed in the upper conductor track 60 .

Fig. 9 shows the circuit board 58 of Fig. 8, wherein the through hole 62 and the recess 63 is filled with a solder or conductive adhesive 64 , so that there is a lei connection between the upper conductor 60 and the lower conductor 61 results.

Fig. 10 shows a portion of another inventive SEN circuit board 65 in cross section. The circuit board 65 has a support layer 66 which has an upper conductor 67 on the upper side and a lower conductor 68 on the underside. The upper conductor track 67 and the support layer 66 are provided with a via opening 69 . In the exemplary embodiment shown in FIG. 10, the through-contact opening 69 is produced with the aid of a method for carrier structuring such as laser ablation, plasma etching or the like, so that the lower conductor track 68 is not impaired by the production of the through-contact opening 69 .

FIG. 11 shows the printed circuit board 65 from FIG. 10 after a further method step. The Durchkontaktie approximately opening 69 is filled with solder or conductive adhesive 70 , so that there is a conductive connection between the upper interconnect 67 and the lower interconnect 68 .

Reference list

1

Circuit board

2nd

upper base layer

3rd

lower base layer

4th

Bending edge

5

Coordinate system

6

first ladder train

7

first leader

8th

square top contact

9

round top contact

10th

upper connecting conductor

11

second conductor line

12th

second leader

13

square bottom contact

14

round bottom contact

15

electrical circuit

16

upper base layer

17th

lower base layer

18th

Adhesive layer

19th

Spacer core

20th

Through hole

21

Conductor track

22

Conductor track

23

conductive material

24th

electrical circuit

25th

upper base layer

26

Conductor track

27

lower base layer

28

Conductor track

29

Spacer core

30th

Recess

31

Chip component

32

Conductive adhesive filling

33

Adhesive layer

34

electrical circuit

35

upper base layer

36

Conductor track

37

Via point

38

lower base layer

39

Conductor track

40

second via point

41

Spacer core

42

first recess

43

first microchip

44

second recess

45

second microchip

46

filler

47

Wire connection

48

Protective layer

49

filler

50

Adhesive layer

51

Top and decor layer

52

Circuit board

53

Base course

54

upper trace

55

lower trace

56

Plated-through hole

57

deepening

58

Circuit board

59

Base course

60

upper trace

61

lower trace

62

Through hole

63

deepening

64

Conductive adhesive

65

Circuit board

66

Base course

67

upper trace

68

lower trace

69

Through hole

Claims (24)

1. Printed circuit board, in particular for a chip card, which has the following features:

• - At least two electrically insulating base layers th ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ), which are arranged one above the other in different levels,
• - At least two interconnect layers ( 6 , 11 ; 21 , 22 ; 26 , 28 ; 36 , 39 ), whereby on each support layer ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) we at least one conductor track layer ( 6 , 11 ; 21 , 22 ; 26 , 28 ; 36 , 39 ) is arranged,
• - At least two base layers ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) are connected to each other on a common side edge ( 4 ).

2. Printed circuit board according to claim 1, characterized in that the support layers ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) are integrally formed integrally. 3. Printed circuit board according to claim 1 or claim 2, characterized in that the base layers ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) are interconnected on mutually facing surfaces. 4. Printed circuit board according to claim 3, characterized in that between at least two base layers ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) at least one adhesive layer ( 18 ; 33 ; 50 ) is provided . 5. Printed circuit board according to one of the preceding claims, characterized in that the conductor track layers ( 6 , 11 ; 21 , 22 ; 26 , 28 ; 36 , 39 ) made of copper lamination have conductor tracks ( 7 , 12 ). 6. Printed circuit board according to one of the preceding claims, characterized in that a spacer layer ( 19 ; 29 ; 41 ) is provided between at least two base layers ( 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ). 7. Printed circuit board according to claim 6, characterized in that the spacer layer ( 19 ; 29 ; 41 ) has at least one recess ( 30 ; 42 , 44 ) for receiving an electrical construction part ( 31 ; 43 , 45 ). 8. Printed circuit board according to one of the preceding claims, characterized in that at least one support layer ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) has at least one via opening ( 20 ). 9. Printed circuit board according to claim 8, characterized in that the via opening ( 20 ) has a filling ( 23 ) made of conductive material. 10. Printed circuit board according to claim 8 or claim 9, characterized in that at least two conductor track layers ( 6 , 11 ) each have coil turns with connecting ends ( 8 , 9 , 13 , 14 ), the connecting ends ( 8 , 9 , 13 , 14 ) the Spulenwindun gene are connected via via openings such that the respective coil turns are connected in series to form a coil. 11. A method for producing a multilayer printed circuit board, comprising the following steps:

• Providing at least one conductor track layer on an electrically insulating circuit board material,
• - Folding the circuit board material by kinking along bending lines, so that at least two circuit board sections ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ), each separated by a bending line, are formed.

12. Method for producing a multilayer printed circuit board according to claim 11, characterized in that before the step of providing at least one lei interlayer, electrically insulating PCB material the step of manufacturing the having at least one conductor track layer, elec trically insulating circuit board material provided is. 13. A method for producing a multilayer printed circuit board according to claim 11 or claim 12, characterized in that the step of the flat connection of printed circuit sections ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) by gluing is provided. 14. A method for producing a multilayer printed circuit board according to one of claims 11 to 13, characterized in that the step of introducing at least one through-contact opening in at least one printed circuit board section ( 2 , 3 ; 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) is provided. 15. Process for producing a multilayer printed circuit board according to claim 14, characterized in that the step of introducing conductive material into the via opening or the via openings is provided. 16. A method for producing a multilayer printed circuit board according to one of claims 11 to 15, characterized in that the step of introducing at least one distance layer between at least two printed circuit board sections ( 16 , 17 ; 25 , 27 ; 35 , 38 ; 54 , 55 ) is provided is. 17. Process for producing a multilayer printed circuit board according to claim 16, characterized in that the step of inserting at least one recess to accommodate an electrical component at a distance layer is provided. 18. A method for manufacturing a multilayer electrical circuit, comprising the following steps:

• Provision of at least one conductor track layer on pointing, electrically insulating circuit board material,
• Equipping the circuit board material with at least one electrical component,
• - Folding the printed circuit board material by folding along bending lines, so that at least two ge each separated by a bending line and superimposed printed circuit board sections are formed.

19. Method of making a multilayer electrical Circuit according to claim 18, characterized in that the step of flatly connecting printed circuit boards sections is provided by gluing. 20. Method of making a multilayer electrical Circuit according to one of claims 18 or 19, characterized in that the step of introducing at least one through hole clocking opening in at least one circuit board cut is provided. 21. Method of making a multilayer electrical Circuit according to claim 20, characterized in that the step of introducing conductive material into the via opening or the via openings is provided. 22. Method of making a multilayer electrical Circuit according to one of claims 18 to 21, characterized in that the step of bringing in at least a distance layer between at least two circuit board sections is provided. 23. Method of making a multilayer electrical Circuit according to claim 22, characterized in that the step of inserting the electrical component or the electrical components in recesses of the Di punched layer is provided.   24. Electrical circuit like a chip card with at least a printed circuit board according to one of claims 1 to 10.