DE1621532A1 - Precision setting of semiconductor components - Google Patents

Description

Western Electric Company, Incorporated Kragness-

New York Waggener 1-2

Precision etching of semiconductor components

Semiconductor components are, regardless of whether they are of the of the single element or the integrated circuit are, in general made of single crystal material in disc shape. Each disc provides a large number of components. As well as for the individual element as well as for the component of the integrated circuit, the precise removal of Dividing the material into separate devices or making insulating slots or grooves is an important part of the manufacturing process. In particular, it is important in this manufacture to use a minimum of material under precisely controlled conditions To remove conditions in order to produce high quality components economically and in compact form.

For example, in the manufacture of semiconductor components in certain integrated circuits the necessary electrical isolation between parts of the circuit within the Semiconductor by removing the semiconductor material within predetermined limits to produce partial or continuous Slits made in the semiconductor material. In the case of continuous slots through the pane, the components of the integrated circuit either by a predetermined arrangement strong metal feeders including the supportive ones Intermediate connections completed or by attaching insulating ßüekenatützen. With another

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Process where the grooves are only partial, they are with a suitable dielectric such as silicon dioxide, backfilled, flipped the disc and removed the material from the opposite surface to a depth that the bottoms cut through the backfilled grooves. Examples of the aforementioned types of manufacturing processes are in the United States patent 3 287 612 (German application W.38002 VIIIc / 21g), ÜSA patent 3 290 753 (German application W 37267 VIIIc / 21g) and in French Patent 1 417 760 (German application W 38017 VIIIc / 21g) described »

In manufacturing processes of the type referred to below, it is important and advantageous to adjust the width of the insulation slots to be reduced in such a way that the device density is increased and the overall scope is reduced and thus cost-effectiveness and efficiency can be increased. In particular, it is important to determine the width of the slot on the device side of the To reduce semiconductor wafer by a process that a allows precise arrangement of the slot boundaries on the device side. In this description, the device side refers of the platelet on the surface - usually from an epitaxial deposited layer consisting - on which the switching elements and on which the metal pattern of the interconnecting circuit is made. Typically, these switching elements are made up of oxide-masked diff fusaeons procedure, and usually the effective one lies

■ - ■■ -.- - "" ■ ■ -. - "* ■ - ■ - ■ ■ - - - —3 Device thickness at 1.0 χ 10 * or 1.3 x 10 ¹ ^ approx. A number of methods are available and are also used

0 0 9843/1733 .3.

in order to carry out this type of material removal in semiconductor wafers. In addition to chemical etching processes, certain mechanical cutting processes, including ablation with air or ultrasonic cutting processes, are available. In the chemical etching field, the isotropic type processes have found general application in
which the etching speeds in all directions of the
Starting surface from are practically uniform. As will be explained in more detail below, this technique does not provide the level of control or accuracy that is advantageous for the ongoing manufacture of semiconductor devices.

In general, in connection with the invention it is assumed that the material used is single crystalline, and the explanation of the invention is directed to a silicon which is a face-centered, cubic crystal of the shape
of the diamond lattice. It goes without saying that germanium and the semiconductors of the III-V group of compounds of generally

mine are the same crystal structure, and that is why that
The principle of the invention is not limited to silicon. In particular, in connection with this invention, use is made of the known behavior of anisotropic etching, in which the different etching speeds of the different crystallographic planes or surfaces are used to effect precise removal of material Orientation of the etching masks with borders arranged at right angles on special crystallographic planes, the mask borders being parallel to

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special intersection lines of two crystallographic planes are arranged, the formulated etchant for the exposed Planes have suitable etching speeds that close, well-defined grooves or slots to the desired depth generate under relatively simple treatment conditions. Also where certain cutting lines of the mask edges a another crystallographic plane with an insufficiently different etching speed from that of the first etching surface the mask size is changed to prevent undercutting * the mask.

In particular, in a particular embodiment of the Invention an etching mask with mutually right angles on a larger area of a disk made of semiconductor material arranged parallel to the (100) plane. In this case the (100) plane is the primary etched area, i.e. it has the highest Etching speed for the specific etchant. Jie orthogonal arranged borders of the mask are parallel to the intersection lines of the (III) plane with the primary etching plane of the (lÜO) plane arranged. Then, as the etching progresses downwards from the primary etched surface, there is practically no lateral Etching against the exposed (III) plane occur, insofar than the etchant is so composed that it has practically zero etch speed thereon. In the meantime at the cut edges of the mask boundaries, which are effective Form outer edges, exposed planes, their etching speed on the etching speed of the (llo) plane

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depends. This etching rate is, although less than that of the (100) level, always significant in a special version. This means undercutting the mask in these places. Accordingly, it is in agreement with the invention to also change the size of the etching mask by enlarging corner areas of a predetermined size and shape provides to the undercut effect of the above to compensate for the procedure described.

A more complete understanding of the invention can be obtained from the following detailed description in conjunction with the drawings.

Figure 1 is a top plan view of an air-insulated monolithic (AIM) Semiconductor component in an integrated circuit with rigid leads and explains a Component which, using the etching process, ge · = mass invention and for the purpose of creating an insulation has been made;

Fig. 2 is a perspective view of a crystallographic Model of a silicon crystal;

Fig. 3 is a partial perspective view of more particular crystallographic planes based on a partial view of the model according to FIG. 2 and the etching mask orientation explained according to the present invention;

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i ί "■; ■■. ': ■ - ■ Ζ -: - -6-

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Figures 4 and 5 are specific partially sectioned images

a slot isotropically etched in a crystal;

6 and 7 correspond to FIGS. 4 and 5, but with anisotropically etched grooves according to the invention;

Figs. 8 and 9 are graphs showing the degree of control opposing the etching fronts by isotropic and anisotropic etching;

FIG. 10 is another view similar to FIG. 7 illustrating the FIG Problem of "pyramids" formation explained;

Figs. 11 and 12 are perspective views showing the aniso-

tropical etched mesa surfaces with a non-compensated mask shape or a compensated mask show shape;

Fig. 13 is a diagram showing the difficulty of control. isotropic etching explained;

Fig. 14 is a diagram of a mask shape showing the boundary ) compensating forms explained.

An important feature of the invention is the formulation of etchants that have a suitably different etch rate to provide the desired semiconductor devices. In the general isotropic etching of semiconductor material, for example, the hydrofluoric acid-nitric acid mixture used as the etchant for silicon is not desirable to a significant extent for a specific orientation. As illustrated in Fig. 4, such an etchant has in all

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Alignments the same etching speed and penetrates "with the Semiconductor wafers 44 along a curved front 48 which is roughly defined by the radii of the edges 42 of the mask 43, forward.

There is thus a considerable undercutting of the etching mask, which in itself would be acceptable for the method. However does The isotropic nature of the etch makes precise control of its termination difficult, if not a substantial one, nearly accepts prohibitive overestimation. This effect is at Consider more clearly FIG. 5, in which the masked isotropic etch creates a groove running right through the wafer 44 passes through. The etch does not remove the layer 46 of silicon dioxide on the device side of the wafer 44. The proximity of the switching elements is determined by the adjacent zones 45 with p-type conductivity. Figures 4, 5, and 7 depict the etching of a groove of such a geometry that they remove the effect of the edges for the purposes of this investigation, which compares isotropic and anisotropic etching.

One factor of importance in the present etching process is the speed of the edge 51 of the etching front 48 in its line of intersection with the surface 50 of the device side of the disc. if If this speed is high, it is difficult to finish the etching at a desired location by timing. This problem is explained by the following relationships, which are developed from the diagram of Fig. 13:

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w is the thickness of the pane,

χ is the ordinate of the edge 51 »that from the cutting edge of the etched front with the side surface of the device is formed

r is the radius of the mask edge 42 with the etched front,

t is the etching time,

R is the etching speed.

The following equations can then be set up:

r = Rt. (l)

dr - Rdt + tdR. . (2)

therefore

2 2 2, _ *

r = χ + w (3)

By differentiating and dividing by the

2
pressure χ results

2rdr 2xdx 2wdw /, \

XXX

Simplification .Substition results in

rdr dx wdw

2 2 " ⁺ 2 2

r - w χ r - ir

(5)

In the above equation (2), the term dt represents the time increment or the degree of temporal control of the etching process. The term dR represents the change in the etching speed. For the ideal case, it is assumed that both dt and dft are zero. Then dr also becomes zero

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and the left side of equation (5) also becomes zero, and the expression can be written in absolute terms as follows will:

WdW

2 2
r - w

dx
The term - represents the increment of movement of the edge 51 on the disc surface and is desirably a low value for good control. Meanwhile, at the moment of "breakthrough", when the etching front 48 has just cut through the wafer surface 50, r is approximately equal to w and the right-hand side of equation (6) becomes infinite. Only when r has become noticeably larger than w does the value of the expression get a reasonable size. A qualitative representation of this change is shown in the diagram of FIG. As indicated by the curve, the edge speed is extremely high when χ equals w, ie at the moment of the "breakthrough". Then the edge speed decreases with increasing r and asymptotically approaches a constant value. One thinks that in all of the foregoing the realization is implicitly contained that the slice thickness w shows slight changes, as indicated by the expression dw. Current technology, even the best trained, enables, as a matter of practical economy, such fluctuations within a slice to be reduced to less than a few tenths of a fraction.

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Accordingly, when using isotropic etching, if satisfactory control over the final position (x) of the etching front 31 is to be achieved quickly, one must resort to the part of curve 8 where χ is noticeably large »This results in wider grooves and one consequently a greater distance between the pn junctions 52 on opposite sides of the insulating grooves, as shown in FIG.

It also causes the fluctuation (dw) in the disc ™ 'thick (w) an etch tolerance to prevent breaking through on the to ensure the thickest areas, which causes considerable overetching in the thinner areas.

6, 7 and 9, the benefit of the anisotropic etching according to the invention in overcoming this becomes apparent Problem explained. It is known that certain chemical Etchants have preferred etch speeds with respect to certain crystal orientations. According to the invention found it practical, terms for the special semiconductor material and look for the shape you want. Fig. 2 shows a model of a cubic silicon crystal which the three mainly interesting crystallographic planes, namely the (100) -, the (HO) - and the (III) -planes. This designation corresponds to the Miller index, and in the present description the designation system indicates one individual level or a group of levels. The importance these are low order levels and their unique properties with respect to certain processes

. 009843/1733 ^bathroom original

known in crystallography. Monocrystalline semiconductor material in block form can have one of the preceding three crystallographic orientations. Accordingly can be semiconductor wafers made transversely from such single-crystal lines Blocks are cut, have larger areas, which are composed of one of the three levels (lOO), (lio) and (ill).

In accordance with a preferred embodiment of the invention it has been found advantageous to provide monocrystalline silicon wafers whose larger surfaces are parallel run to the (100) plane. The etchants of primary interest in connection with this embodiment, namely the Alkali hydroxides have a high etching rate on the (100) level and their slowest etching rate with reference to the (1-11) level. If a limited area is on the (100) -plane is presented to the etchant, the attack proceeds downwards parallel to the (100) plane with high speed, but laterally against the (III) surfaces with very little Speed that can be practically zero. The other levels of interest, such as the (110) level, can have an etching speed comparable to that of the (100) plane or smaller.

In Fig. 2, part of a (100) plane with a hypothetical Section 41 shown. This section 41 can be seen as a disc through the crystal below,

^009843/1733 BADO «

but cut parallel to the (100) plane, as indicated on the upper surface of the crystal model. The limits of the plane section 41 run parallel to the intersection lines of the (III) plane with the (100) plane.

In Fig. 3, the cutout 41 is moved to the side and is shown with part of the adjoining (III) planes and indicates an ideal mesa figure made by the semiconductor material is assumed if it is etched anisotropically according to the invention will.

In Fig. 6, a mask 43 is shown on the (100) plane of a silicon crystal 44 and a slot has been etched down from the exposed portion of the surface exposing the sides of the groove and the (ill) crystallographic surface, which is defined by the boundaries of the mask. As previously indicated, the (III) plane is etched at a speed of practically zero. The slope of the side wall forms an angle with the disk surface which is determined by the crystallographic structure. The value of the angle is expressed by the expression arc tang \ / ~ 2 and corresponds to about 54.7 degrees of arc. Accordingly, one can see that the etching proceeds downwards to the bottom of a groove of decreasing width at a constant speed determined by the etching speed of the (lOö) -plane is determined, in contrast to the kind shown in FIGS. 4 and 5 for isotropic etching. ·

009843/173 3 ⁶ ^ o _{RlQ / NAt}

532

The advantage of this anisotropic etching is appreciated when comparing FIG. 7 with that of FIG Do not etch a groove through a disk.

The difficulties of checking the position of the edge 51, which is etched in the isotropic process, is described in connection with FIGS. 5 and 8. In the anisotropic method of FIG. 7, the edge 51 of the etching front at the moment of the breakthrough has a speed component in the x ~ direction and along the disk surface 50 of Hull. At this moment the etching has been completed, in that only the (ill) faces exposed are _s on which the etching speed is virtually zero _o Thus, as a point of "By Bracht" precisely the position of the mask edge on the backside of the wafer and the silicon Fixed thickness "With this arrangement there is no risk of overetching and no need for tolerance in the etching time despite the change in thickness of the wafer, ie the change in thickness only requires a slight deviation from the nominal slot width in order to penetrate at all To secure etch points.

Figure 9 is an illustration of the anisotropic process that corresponds to the isotropic image shown in Fig. 8 and shows edge velocity curves for the etching process on the crystallographic levels of interest. For the anisotropic case the edge speed is a constant, that of a straight line at the height of the corresponding etching speed the relevant exercise is reproduced.

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BATH ORIGINAL

By avoiding the problem of overetching which in the isotropic technique is permitted accordingly the anisotropic method a considerably closer spacing of the p-n junction 52, which is adjacent to the groove on the device side.

The alkali hydroxides used as etchants, related to with this embodiment of the invention of interest are not only selective with regard to the crystallographic orientation of the monocrystalline silicon,

but also in relation to silicon dioxide. So is silicon dioxide a standard masking material and is fabricated in mask form using well known photoetching techniques. In addition, there are integrated semiconductor circuits in many, especially in the air-insulated types referred to above Layers of silicon dioxide specifically on the device side of the circuit, and the etching process does not allow removal these layers.

Hence, in accordance with an embodiment of the invention the anisotropic etching is carried out with relatively precise control on monocrystalline silicon by using a Etch mask parallel to the (100) plane aligns with the edges of the mask mutually at right angles and parallel to the Intersection of the (III) plane with the (100) plane. This is an «ideal configuration if the etchant used is a high one Has etching speed with respect to the (100) plane and a Virtually zero etching rate with respect to the others

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"both levels (llO) and (ill). Meanwhile it was established that local disturbances and irregularities during the Etching process are sufficient to prevent the etching process and cause the formation of pyramids that their tips in the disorder or irregularity. This effect is discovered, for example, on a polished surface, that is scratched and etched. It is reasonable to assume that a sufficient number of such pyramids will be the practical interruption of the etching process in the (100) plane when the sides of the pyramids intersect.

Fig. 10 illustrates the effect of pyramid formation. Based on some irregularity in the tip 201 the pyramid 202 has grown as the etching process progresses until its sides finally intersect the (III) plane and the groove walls 49 a part 203 for bridging the groove left.

In order to exclude the formation of such pyramids, the etchant is put together in such a way that it has an etching speed with respect to the (110) -plane, which lies between those of the (III) - and (100) -plane. This gives a sufficient Etching to remove pyramids.

However, if the etchant is so composed that this higher etching rate applies in relation to the (11O) plane, the consideration of FIG. 11 explains a consequent disadvantageous effect on the outer edges where the (III) planes intersect.

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Figs. 12 and 14 show a technique of compensation by means of Mask to overcome this effect and should therefore be viewed in conjunction with the explanation below.

11 shows an etching mask 151 on the crystal 153 to be etched. At the outer intersection of the (III) planes, an undercut of the mask 151 occurs, indicated by the dashed line is indicated. This undercut is related to the etching of the (110) plane. There is an ab-

^w deviation from the mask outline 151, as represented by the dashed lines 152 on each side of the outer corners of the crystal. Such a result is of course undesirable in that the most useful device geometry is rectangular or is a series of right angles.

This effect can be compensated and so the right-angled geometry can be approximated by creating a compensation form used in the mask in the corners. This) form can take on various outlines, one of which is in Fig. 12 is shown. In FIG. 12, the sides of the compensation shape are parallel to the section of the (III) planes and the Starting level (100). The important consideration regarding the Compensation form for close adaptation to the right-angled Geometry is that the horizontally shaded zones 171 in Fig. 14 must be masked, and that no area except * half of the vertically and horizontally shaded region 172 is masked. In addition, each is to the best of their ability

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designed shape at the corners of the mask outside the Limits of the output rectangle a certain compensation form for etching the edges.

To achieve the right-angled geometry, the dimension a in Figure 14 should be equal to _o;

a - ^ kw / 2

k = ^a ii ₀ / ^a i00

and _t

w = silica thickness

The minimum average mask width dimension is:

/. m 2kw + b
mm

b = s the smallest non-zero groove width

that can be achieved with your masking process.
The ^M inimum the mesa dimension 63 on the device's page:

L. » ~ \ / ~ 2yf + kw + b. now V

Although the corner compensation described in the above section is specifically for the crystallographic orientation (100) the principle of corner compensation can be achieved by skillfully applying special outlines on the mask to others Crystal orientations as well as specially shaped geometric ones Dimensions, transferred, __ _ ^

00 98 43/17 33 'BADi «rk? Inal

A specially suitable formulation for use on monocrystalline silicon, which is oriented as discussed here, contains a solution with 15 g of potassium hydroxide (COC) of commercially available heat, 50 ml of water and 15 ml of n-propanol. This particular formulation was found to be an etchant with respect to the (110) plane in the range of three tenths to four tenths of the etch rate with respect to the (100) plane. The etch rate is affected by resulting in the potential solutions, ie ^ above-mentioned rate of three-tenths to four-tenths applies to the etching of wired circuits that contain gold. The etch rate for pure silicon with no metal present is slightly slower.

In a specific embodiment, and using the above composition at a temperature of about 85 C, etch rates of about 1.2 microns / min were observed at the (100) plane. In general, other alkali hydroxides including those of sodium, cesium, lithium and rubidium can equally be used. These various hydroxides differ mainly in the speed with which they attack silica. The rate of attack of each of these classes of etchants on silica can be reduced by the controlled addition of aluminum. The etching rate on the (110) level can be determined by changing the by-product content of the etching solution and by adding lower alcohols, such as

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Methanol and ethanol instead of n-propanol influenced will. In general, silicates resulting from the etching process tend to increase the etching rate (11O), Other suitable etchants can be used using organic reagents that are capable of free Generate hydroxyl ions, including amines, such as Ethylene diamine and water.

In a special embodiment according to the invention a wafer of semiconducting silicon according to the teachings of the aforementioned French patent 1,417-60 and the United States patent 3 287 612 for the production of an air-insulated Monolith or the isolite shown in Fig. 1 produced. For this purpose a disc is prepared, one or subjected to several masked diffusion treatments in the solid state to produce switching elements on one side of the body, how to create transistors, dbden and resistors. Correspondingly wired metal connections are made on one side of the disc, and it is ultimately used for prepared the final separation process according to the invention.

For this purpose, the wired side is mounted downwards using a suitable durable material and typically about 12.7 x 10 cm thick

-3-3

Worked down to about 5.1 x 10 cm or 7.6 χ 10 cm.

The surface is then covered with a film of silicon dioxide coated, which serves as a rear etching mask.

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BATH ORIGINAL

It will be noted that the semiconductor wafer is disadvantageous in this point as a result of the treatment with higher temperatures associated with the formation of a silicon dioxide film can be influenced. Plus it's in In connection with this aspect of the invention, it is important that mafa form an intimate, firmly adhering oxide layer through a Process comparatively lower temperature forms. In particular, it is important to prevent the formation of any intermediate layers of fast-etching material,

w which result in the separation of the mask layer from the silicon

could.

A technique for obtaining a satisfactory silicon, Dioxide layer on the rear side of the disc comprises an anodic oxidation as a first step in order to form a thin layer of silicon dioxide. (Such a method is described, for example, in the earlier application W 43 825.) The anodized surface is then sputtered back in a vacuum to clean it and then in situ using an electron beam evaporation process to form an oxide layer about 6,000 to 10,000 ÄE thick or with a thickness sufficient for the etching time.

As the next step, the photo-etch mask is formed on the oxide surface and the borders of the mask with the cuts aligned with the (lll) plane, as set out above. One can use appropriate crystallographic techniques including (»Apply oniometric methods to the crystal orientation

0 0 9 8 4 3/17 3 3

and identify the appropriate material by establishing a plane on the greeting pad in an appropriate manner. After the pattern has been developed in the photo-etch mask, suitable standard etchants, such as buffered hydrofluoric acid in aqueous solution, are used to remove the unmasked silica. Finally, the wafer is immersed in the alkali hydroxide etchant and anisotropically etched in order to carry out the precise separation between parts thereof, as shown in the arrangement of FIG. The A rectangular plates 112 to 123 become the isolated parts of the circuit. Each such plate can contain one or more switching elements. The structure in the assembly is supported by a plurality of wire leads 126 with a similar type of wiring terminal 125 for external connection. The pyramid sides of the various parts of the circuit, as seen from the rear etched surface, indicate the anisotropic shape of the etching process.

i As proposed below, the anisotropic technique described herein can also be applied to a method in which one desires to cut out only a predetermined-depth material, rather than to cut through the whole material. Such techniques are useful in processes such as that in the aforementioned U.S. Patent J 290 753 which has been referred to as the EPIC process. For such an EPIC method, the implementation of the invention is simplified to such an extent that a suitable thermal oxide film is usually available, insofar as the groove cutting is one of the first steps in fabrication . . - - *

Ö 0 9 8 ti 1 1 7 ft _8ÄD original _ ₂₂ _

The anisotropic etching technique provides a simple way of generating fabrication digits, such as on the plate 1 shown. Such figures are composed of unconnected grooves and thus avoid corner effects and make the process self-terminating with a run that is fixed by the width of the groove. It is of course important making the etching through the disk impossible for this purpose while avoiding grooves that are too wide.

Although the procedure is so far based on a shaping technique has been described in which one of the low order crystallographic planes has an etch rate of practically Has zero, it goes without saying that the shaping technique can be carried out in a controllable manner if this Speed is sufficiently slower than that of the other two planes. Such a system, although useful, will not be so beneficial from the standpoint of self-terminating property. Besides the use of silicon dioxide 'As a mask, certain other materials can also be used as a mask

found useful, including other dielectrics, such as silicon nitride.

The foregoing description is from the point of view of treating single-crystal silicon semiconductor materials he follows. It is clear to a person skilled in the art that these methods are generally similar to other single-crystal semiconductor materials criatallographic structure, including the

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Germanium, as well as the well-known semiconductor compounds of the III-V group can be used. The etchant formulas will change for the different connections. Meanwhile, it is in accordance with the present invention the precise etching effected by the knowledge and the application of different etching speeds, which below the three low-order crystallographic planes which are characteristic of these substances.

In connection with such procedures in the case of composite "

In semiconductors, it will be appreciated that a different etch success occurs depending on the two elements of the compound that prevail in the particular layer. Specifically, for example in the case of a gallium arsenide crystal, when considering the model in FIG. 4, the (III) plane shown in the center of the model can have a predominance of the gallium atoms. On the other hand, when rotating this (III) plane, which is on the opposite underside of the model, a predominance of arsenic i

Atoms occur. Accordingly, the etchant can be formulated so that one doesn't just take advantage of the primary crystallographic orientation, but in the case of composite semiconductors also the factor which the Levels being exposed.

The etchants that attack the (110) plane can be formulated in this way that they attack the (100) plane with a comparable etching speed. With such a 009843/1733

Arrangement in which the (110) plane - the primary etching plane is, the mask edges are parallel to the cuts with the (11O) plane with the different (III) - and (11O) planes arranged. The mask edges are then not necessarily at right angles to one another and, due to the etching, Different mesa configurations are formed in the process. It is important to consider the geometric effectiveness of the generated outlines from the standpoint of the compactness of the devices consider*

In any system, the considerations for obtaining one remain precise etching the relative etching speeds between three lower order crystallographic planes for a given etchant and the formation of the corners of the etching mask exist in such a way that interference effects of disturbances and Irregularities are avoided, as is the associated one Undercutting at corners, which is done by setting the medium etching speed to avoid pyramids is initiated.

Accordingly, it is also understood that modifications of the preceding specific teaching will be made by the person skilled in the art which, however, are still within the scope of the invention. For example, it is that It is clear to those skilled in the art that other distances from crystal planes ale lower order ones can be used.

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Claims (10)

Claim e 1. A method for producing a semiconductor component, consisting of the production of a single crystal Disc of semiconductor material having at least first, second and third crystallographic planes low order, which has its main surfaces in the mentioned first crystallographic planes, where an etching mask on one of the larger surfaces mentioned forms surfaces and this mask surface presents an etching solution, characterized in that the etching agent solution is composed in such a way that it has a relatively high etching speed on the first level, a relatively low etching speed on the second level and one relatively between that of the the first and second planes has etching speed on the third plane, and further characterized in that that the edges of the etch-resistant mask are arranged so that they line up with the lines of intersection between the mentioned third crystallographic level and the second crystallographic Jübene run parallel. 2. The method according to claim 1, characterized in that dasd the etching rate of the etchant on the second crystallographic level is practically zero. -26- 0 0 9 8 A 3/1 7 3 3 ■: '....-; > . BATH 3 · The method according to claim 1 or 2, characterized in that the mask in a compensation form on their outer corners is designed and that the dimensions of the compensation shape the ratio of the etching speed of the third level are related to the etching speed of the first level. 4. The method according to any one of the preceding claims, characterized in that the semiconductor material consists of of the group comprising silicon and germanium and of the III-V group of semiconductor compounds. 5. The method according to claim 4, characterized in that the semiconductor material is silicon, and that the Etching solution is able to free hydroxyl ions during of the etching process. 6. The method according to claim 5, characterized in that the etchant is selected from the group consisting of Mixtures of amines and water are made. 7. The method according to claim 5> characterized in that the etching solution contains an alkali metal hydroxide from the the hydroxides of sodium, potassium, lithium, cesium and rubidium group. 8. The method according to claim 7 »characterized! that the etching solution contains an alcohol. 009843/1733 - ² 7- BATH ORIGINAL 9. Procedure; according to claim 7 »characterized in that that the first level the (IQO) -, the second level the (ill) - and the third level is the (11O) -plane, and that the mask edges are at right angles to each other are arranged, and that the etching solution consists of a solution of potassium hydroxide, water and n-propanol consists. 10. The method according to claim 9 »characterized in that that the caustic solution mentioned 15 g of potassium hydroxide (commercial ^ unit), 50 ml of water and 15 ml Contains n-propanol. BAD 0RJG1WÄL 0.09 84 3/173 3