DE1234056B - Counting register for parallel addition or subtraction of binary numbers - Google Patents

Description

Counting register for parallel addition or subtraction of binary numbers The invention relates to a counting register with magnetic cores with an approximately rectangular hy #steresis loop for parallel addition or subtraction of binary numbers and for non-destructive reading of the stored information. Circuit arrangements with magnetic cores to solve this problem are already known (German Auslegeschrift 1179 252). With them, a transfer that may result in one stage of the counting register is sent to the next stage and processed there. However, since each transfer of a transfer has a certain duration, it takes a time, depending on the number of transfers carried out or the number of digits in the counting register, until the new counting result is available, even if the counting process was only triggered by a single signal. In this way, the operating speed, in particular of a multi-digit counting register, can be significantly reduced compared to that of a single stage.

The counting register with magnetic cores with an approximately rectangular hysteresis loop for parallel addition or subtraction of binary numbers according to the invention, on the other hand, has the advantage that the result of the operation is actually available in all places simultaneously. The counting register works according to the inversion rule known per se, according to which when "1 = 2 '" is added to a binary number, starting from the lowest digit, all digits including the first "0" are inverted (German Auslegeschrift 1082 435). The subtraction is obtained in a similar way by inversion of all lower digits occupied by "0" up to and including the first "l". The addition or subtraction of a higher power of 2 also takes place according to this rule, although all those positions in the original register content that correspond to a lower power than the power to be added or subtracted remain unchanged.

The counting register with a matrix-like three-column arrangement of Magnetic core transistor elements with current switches (switch elements) are characterized by that in each column a number of switch elements corresponding to the number of digits is connected in series, in series with the second and third column respectively a controllable, preferably electronic switch is arranged and the first Column about a first constant current generator, the second and third columns together fed through a second constant current generator, and that in the row direction each of the turnout elements belonging to the same binary digit (register level) mutually are coupled so that the first element of a stage on the second and third Element of the stage and the second or third element of the stage back to the first can act immediately.

The counting register formed in this way can be used if information is entered once can be queried as often as required. It is also possible while typing a new information the old information by a delete command without a special delete cycle to delete and by an addition command the information by a power of 2 without increasing a special addition cycle or with a slight modification of the circuit arrangement to humiliate.

The circuit arrangement according to the invention is illustrated below with reference to FIGS. 1 to 8 explained in more detail. F i g. 1 the MT element used as the basic building block and its symbol used in the following circuit diagrams, FIG . 2 the voltages induced when switching over the magnetic core at different loads, F i g. 3 diode-transistor switches, F i g. 4 a register for non-destructive reading of the information, F i 1-. 5 a by supplementing the register according to F i g. 4 formed parallel-l-adder, F i g. 6 shows an advantageous further development of the adder, FIG. 7 shows a modification of the adder for the optional addition of a higher power of 2 and finally FIG. 8 shows a modification of the adder for the subtraction of 1 or a higher power of 2. To make the circuit arrangements according to the invention easier to understand, the MT elements known per se should first be discussed. FIG. 1 shows an annular magnetic core K with two setting windings Ei and E2, an interrogation winding A and a fourth winding connected to the base b and the emitter e of a transistor Tr are shown. The none is set by a (sufficiently large) current pulse on one of the setting windings (set windings) . H. a logical "l" is stored ("content of the core" = 1, abbreviated #K) = 1). A current pulse via the query winding resets the none (logical "0", (K) = 0). The base winding is connected in such a way that the voltage induced when interrogating a set core controls the transistor Tr to be conductive. Since the transistor is generally controlled to saturation, the collector current is determined by the (real) resistor L and the operating voltage + U, - U. Setting windings of further cores can also be looped into the collector circuit in order to transfer the requested information.

A circuit arrangement with many MT elements would be shown in the representation according to FIG. la become very confusing. There is therefore no simplified symbol according to FIG. 1 b used. Here the none is drawn as a narrow, lying rectangle. The two initially parallel lines attached to the right narrow side represent the collector or. Emitter connection of the switching transistor Tr is. A mutual differentiation of the connections is generally not necessary, since the transistor acts as a pure switch (but with current amplification). The core windings are represented by simple lines drawn perpendicular to the longitudinal direction of the rectangle. The following rule must be observed for the effect of current pulses on the individual windings: The core is set for all windings that are not specially marked. Windings that are marked with a dot on the upper side of the rectangle are blocking windings, impulses on these windings generally only occur together with other impulses and should, despite these, hold the none in the previous position. Windings marked with a cross within the rectangle serve to reset the set core to the "0" position. The windings for the interrogation cycle play a special role, each of which is also identified by the identifier of the cycle in question (clock pulse Ti in FIG. 1b).

As already mentioned, the voltage induced in the base winding when interrogating a set core makes the connected transistor conductive. However, since the base-emitter path of the transistor limits the voltage to an approximately constant value UBE (approximately equal to the threshold voltage), the magnetization reversal process is dragged out over time. In the lower row 9 C of the F i lo ,. 2 shows such a voltage profile as a response to the interrogation pulse IA above it. The falling edge and thus the duration of the voltage pulse can, however, vary greatly, primarily because of the different (and also temperature-dependent) values of UBE. Of course, the collector currents also scatter in the same way.

If, however, one wishes to make certain logical links with the output currents of such MT elements in other elements, then all currents must match in amplitude and duration. It is already known for this purpose to apply the operating voltage for the transistors only briefly, so that they can only carry current during a precisely defined period of time t "(FIG. 2) (keyed operating voltage, German design guide 1189 588) Auftastimpuls must be covered by the output signals of all none.

Instead of the gated operating voltage, at which the MT elements are terminated in parallel, a gated current injection can advantageously be carried out in many cases, with all elements being in series. All currents in a series circuit then have exactly the same duration and amplitude. To prevent the circuit from being interrupted by a blocked transistor, a diode is connected in parallel to the collector-emitter path of each transistor and takes over the current when the transistor is blocked ( FIG. 3). It is necessary that the residual voltage of the conductive transistor is lower than the threshold voltage of the diode, otherwise part of the current flows through the diode. Several diodes may have to be connected in series. The windings of the cores to be set by such an extended element (switch element) cannot be placed in the collector circuit of the transistor, but must be switched into the diode branch; the counter-voltage induced when setting the core would add to the voltage drop across the conductive transistor, so that an interference current could easily flow off via the diode (s).

A setting pulse for a subsequent core whose winding is in The diode branch is only found if the none belonging to the switch element was in the "0" position before the query. The switch element thus fulfills the function of negation.

In Fig. 3 three switch elements are connected in series with a constant current generator KG. The constant current generator KG is gated by a control pulse I, 'only during the time t "and then supplies the current pulse II. The semicircular arcs drawn in the diode branches indicate windings of further cores.

According to the method described so far, information is written directly into the none by the setting currents. With an intermediate measure Tz, however, another path can also be taken. A none should be written to during the clock phase T 1, and it is queried during the clock phase T 1. You now write through the intermediate clock Tz located between the clock phases T "and T, or at the beginning of the clock phase T, but always before the input currents an " 1 " and magnetize the none with the input currents back into the" O "position. The induced base voltage is not evaluated, which does not cause any problems with the help of the alternating gating. When the query is actually made by T, the MT element only supplies a collector current as an output signal if the input current is missing.

The advantage of this mode of operation is that through the input current only a relatively small counter voltage is induced in the winding, since the none is loaded by the conductive base-emitter path of the output transistor. In this case it is also permissible, the input winding of an MT element or a switch element in the collector branch of a preceding switch element to switch without the counter voltage causing a nent> 22 significant current in the diode branch caused. The possibility of increasing the number of diodes if necessary, has already been pointed out.

The circuit arrangement according to the invention for parallel addition or subtraction (counting register) made up of the elements described above (MT element or switch element) should, as already mentioned, enable, among other things, the non-destructive reading of information that has been stored. The main component is a register that allows temporary storage and rewriting to preserve the information. Its structure and its function should be based on FIG. 4 will be explained first. The register consists of n levels corresponding to the number of digits in the binary information.

The main cores K, 0 to K1 "are set via the input lines 20 to 2n. The clock T, queries the main cores. Via the constant current source KG, the gating current pulse I, is switched by L, '. Depending on the information in the Cores K, the current pulse I will flow via the transistors Tri or the diodes Di. The reset windings of the intermediate storage core K2, which were preset by the intermediate clock Tz, are located in the transistor branches (which is permissible because of the load on these none).

This results in also (K21) ## #K: t1) - (1) The intermediate storage cores K2 thus contain the inverse information of the corresponding main no Kl.

The intermediate storage cores K2 are also components of switch elements. All these switches are in turn connected in series and connected to the constant current source KG via the switch WE for rewriting (e.g. a switching transistor). The rewrite windings for the main cores Kl belonging to the respective stage are located in the diode branches D. The intermediate storage cores are queried by the clock T2. During part of the duration of a pulse from T, the keying pulse I is also supplied by the constant current generator KG. If switch WE is conductive for at least the same period of time, then I2D21 (K21) applies and with (1) I2D2i (Kli) (2) d. H. A setting current 2 D, 2 1 only flows through the rewrite winding if the main none was previously set. The previous information is thus rewritten.

By a delete command simultaneously with a pulse 12 or with a pulse of the clock T2, the switch WE is blocked. The old information will no longer registered. at the same time a new information can be entered.

The register for the 1-adder according to FIG. 5 can be added. In the No K, of this third element column, the inverse content of the equivalent No K2 is written in accordance with the rule made by the addition principle for negating all lower-order digits up to the first A , i.e. also (K3 i) # (KL 1) ( 3) This is achieved by presetting the None K, (analogous to the cores K2) with the intermediate clock and resetting it with the current pulse 11 Di. As far as the information stored in the cores K, of the third column back into the corresponding main cores K,. is accepted, it is written there in negated form.

This third column must now be switched in such a way that the information stored in it is only written up to the first "1" (from the least significant digit). For this purpose, the diodes in question D, 1 (after F i 1. 5) each from the emitter e of the associated transistor Tr31 via a Einstellwicklung of the core K, 1 across to the collector of the transistor Tr k. Guided i. The series connection of the transistors of the third element column is connected to the constant current source KG2 via the switch Z for counting.

The counting process takes place as follows: By an impulse the clock phase T, the cores K are queried and their information content through the delayed opening current pulse I, to which none K2 inversely and to pass the cores K3 directly. During the following clock phase T, the cores K, and K, queried. With a simultaneous counting command, the switch Z for Counting made permeable, the WE switch for rewriting must be blocked be.

As long as the information "l" is contained in the cores K, (calculated from position 20) (corresponding to (K,) = 1) the constant current pulse I, from the source KG2, runs through the transistors Tr. And bypasses the main cores K " which are therefore not set. In the first stage with (K3) = 0 , the transistor Tr. remains blocked; the constant current pulse 12 must flow through the diode D " and thereby sets the core K of this stage, i. that is, the original content "0" of this core is also inverted. In all further (higher-value) stages, the constant current 12 flows via the switch elements in the second column, so the unchanged information is adopted as in the simple register described above.

The actual addition therefore takes place during a single pulse 12; the time depends only on the duration of the setting of the nuclei Ki. There are no running times as a result of the transfer of transfers. The new register content can be used immediately in the next clock phase T ,. evaluated, the next count command in the subsequent clock phase T, are delivered. If no counting command is received, the last existing register content is rewritten in clock phase T. As with the previously described register, deletion and rewriting are carried out by blocking the WE switch. The circuit arrangement according to FIG. However, 5 to parallel 1 addition has certain disadvantages, which can be particularly noticeable in multi-digit registers.

As already mentioned, a small interference current can flow through the diode of a diode transistor switch even when the transistor is conducting. This interference current is generally insignificant if the switch is correctly dimensioned, all the more so since it is returned to the common circuit of the series circuit after each switch. However, this does not apply to the interference currents through the according to FIG. 5 connected diodes D3 to D ",. All interference currents that flow through the diodes of the lower stages, previously occupied with" 1 " with conductive transistors Tr., Are missing in the total current of the upper stages. On the other hand, the interference currents add up in the second switch column , where, because of the transistors blocked in the lower stages, they flow via the diodes D, and thus via the setting windings of the cores K. There is a risk, especially in the case of many positions in the information with> A " before the first " 0 ", that the Cores K, are set incorrectly.

The disadvantage described can be avoided by an advantageous development of the invention according to FIG. 6 can be avoided.

The strength of the interference currents can be significantly reduced by connecting a second diode in series to each diode in the third column of elements. In addition, in order to reliably prevent incorrect setting of the cores K, a blocking winding of the core K, belonging to the same stage, is included in the series connection of the transistors Ti- 3 of the third element column, so that one that flows through one of the transistors Tr3 Useful current also flows through the core K, belonging to the stage. The number of turns of these blocking windings is selected to be so large that even a minimum useful current can still reliably compensate for the maximum interference current flowing through the setting windings. Each individual diode branch D 3 is guided via a blocking winding of the cores K. If the target current now flows in the stage with the first zero through the relevant diode D., it simultaneously interrupts the interrogation of the core K for the duration of the keying pulse I, the associated transistor Tr. Remains blocked, so the interference current is added in this stage in the correct sense to the useful current, so that a safe setting of the core K is guaranteed.

The interrogation of the core K2 in the stage with the first zero «K,) = 1) was initiated before the arrival of the blocking pulse (with 12). As a result of the high excitation by this blocking winding, K is set again. The remainder of the clock pulse T, which remains after the blocking pulse, can therefore be used for a complete reset of the loaded core K? to be too short in the "0" -La-e. However, this does not matter, since this core is already fully set again by the subsequent intermediate clock pulse Tz.

A further modification of the circuit arrangement according to the invention makes it possible, in addition to 20 = 1, to add a higher power of 2 to 2n. To do this, the switches WE and Z must be placed in the constant current circuit I before the stage corresponding to the power. If one arranges according to F i g. 7 a pair of switches WE, Z to each stage, then the power of two to be added can be selected by control commands. For the control of the individual switches during the duration of a constant current pulse I, the following conditions apply: a) At least the switches WE, and Z, must be blocked in order to delete the previous contents of the register and write new information. The other switches can be in any state; b) for reading out and rewriting the previous information, all switches WEO ... WE "must be permeable and all switches Zo ... Z" must be blocked; c) To add a power of 2, the switch WE belonging to the corresponding stage must be blocked and the switch Z must be permeable.

All other switches WE are permeable, and all other switches Z are blocked. For the addition of 22 = 4 applies e.g. B. switches WE2, Zo, Z, and 2 #., ... Z "are blocked, switches Z2, WEO, WEI and WE" ... WE "are permeable.

By slightly modifying the circuit arrangements according to the invention shown in FIGS. 6 and 7 , it is possible, instead of an addition, to carry out a subtraction of 1 or any power of 2 to 2n. In Fig. 8 shows one stage of the subtracter. With an otherwise completely identical arrangement and wiring, it is not the transistors Tr ″, but the diodes D, that are connected in series. For this purpose, the collector connections of the transistors Tr. And Tr. Belonging to a stage are connected to one another. The arrangement and control of a pair of switches WE , Z,) for the subtraction of 1 and a further switch pairs WE1, Z, ... WE ", Z" for subtraction higher power of 2 corresponds. entirely the circuit arrangements for F i g. 6 and 7.

According to the rule for subtraction already mentioned, all positions of the register content that correspond to a power lower than the power to be subtracted remain unchanged. All other positions, starting with the point inverted to Subtract power of two, up to the first subsequent "l" and this first "1". All subsequent positions remain unchanged. For example, when 20 = 1 is subtracted into the main kernel K, each lower-order step via the branch with the diode D, an "1" is written if (K ..) = (K3) = 0 originally. In the stage with the first "1" , the constant current pulse I flows through the transistor Tr ", which prevents the setting of the core K, with the help of the blocking winding. In addition, practically no (setting) current flows through the diode D.

Switching from addition to subtraction can of course also be done using mechanical contacts or electronic switches, e.g. B. similar to the switches WE and Z, can be made.

Claims (2)

Claims: 1. Counting register for parallel addition or subtraction of a power of 2 to (from) a multi-digit binary number with a matrix-like, three-column arrangement of magnetic core transistor elements with current switches (switch elements), characterized in that one in each column The number of switch elements corresponding to the number of digits is connected in series, with a controllable, preferably electronic switch (WE or Z) arranged in series with the second and third column and the first column via a first constant current generator (KG,), the second and third column are fed together via a second constant current generator (KG2), and that the switch elements belonging to the same binary digit (register level) in the line direction are mutually coupled so that the first element # K ",) of a level is connected to the second and third element (K2 "and K., J of the level and the second or the third element of the level again on the first can act immediately. 2. Counting register according to claim 1, characterized in that the diodes assigned to the switch elements in the first and second columns are each indirectly parallel to the input-collector path of the transistors and the diodes of the third column are each indirectly between the emitter terminal of the transistor of the third column and the collector connection of the transistor of the second column belonging to the same stage are connected (F i g. 5, 6). 3. Counting register according to spoke 2, characterized in that within each stage in the diode branch (the switch element) of the first column one or more windings of further cores to take over the information and a reset winding of the core of the third column preset by an intermediate clock (Tz) in The transistor branch of the first column has a reset winding of the core of the second column, which is also preset by the intermediate clock (Tz), in the diode branch of the second column there is a setting winding of the core of the first column, in the diode branch of the third column there is another setting winding of the core of the first column. 4. Counting register according to claim 3, characterized in that within each stage in the diode branch of the third column there is also a blocking winding of the core of the second column and a blocking winding of the core of the first column is located in the transistor branch of the third column. 5. count register according to claim 4, characterized in that each switch element of the second column a controllable, preferably electronic switch (WE,... WE "), and each switching element of the third column a controllable, preferably electronic switches (ZO ... Z, Publications considered: Deutsche Auslegeschriften No. 1 082 435, 1097183.