DE112014003998T5 - Inverter device - Google Patents

Abstract

An inverter device (201) includes a 3-level voltage generating circuit (20) and a switching control circuit (100). The 3-level voltage generating circuit (20) has switching elements (S1 to S4) and a flying capacitor (Cf), and generates a three-level voltage at a node between the second switching element (S2) and the third switching element (S3). The switching control circuit (100) detects an error in a capacitor voltage detected by a capacitor voltage detection circuit (3) from 1/2 of an input voltage Vdc, and corrects an error of charging and discharging time of the capacitor (Cf) for reducing the capacitor voltage error while the switching elements (S1 to S4) are switched based on a PWM signal.

Description

Technical area

The present invention relates to an inverter device comprising a 3-level circuit with a flying capacitor.

Technical background

Patent Document 1 describes an inverter device that includes a 3-level circuit for outputting a 3-level voltage using four switching elements and a flying capacitor, and outputs an AC voltage by PWM control to the switching elements.

List of quoted writings

Patent

• Patent document 1: unaudited Japanese Patent Application Publication No. 6-67204

Summary of the invention

Technical problem

Circuits utilizing a flying capacitor have the advantage of miniaturization due to a reduced size of the capacitor and a reduced number of components as compared to circuits which generate 1/2 of an input voltage using two capacitors in series.

In a 3-level voltage generating circuit for outputting a 3-level voltage using a flying capacitor, switching elements are controlled so that a charging time of the flying capacitor per unit time is equal to a discharging time thereof. Accordingly, a voltage across the flying capacitor is equal to 1/2 of an input voltage. The above-described 3-level voltage generating circuit is a circuit that utilizes these characteristics.

However, in the characteristics of the switching elements and the characteristics of a drive circuit for driving the switching elements, fluctuations occur, and thus, due to a failure in the turn-on and turn-off timings of the switching elements, a difference (charging and discharging time) between the charging time and the discharging time of the flying capacitor Discharge time difference) are present. Therefore, there is a phenomenon (voltage error) in which the voltage across the flying capacitor deviates from 1/2 the input voltage. This voltage error increases as a current value increases.

The larger the above voltage error, the higher an applied maximum voltage on the switching elements increases, causing the problem of withstand voltage. In other words, the switching elements have the risk of failure. For the purpose of preventing the failure, it is necessary to use high withstand voltage switching elements, resulting in an increase in loss and cost.

In an inverter apparatus for power system connection, the above voltage error results in deterioration of the quality of output current of the inverter apparatus.

An object of the present invention is to provide an inverter device which solves the problem of withstand voltage as well as the problem of deterioration of the quality of output current caused by the voltage error in the flying capacitor.

the solution of the problem

• (1) An inverter device according to the invention comprises: a 3-level voltage generating circuit having first to fourth switching elements connected in series between a first input terminal and a second input terminal of a DC power supply, and a capacitor having a first terminal connected to a node between the first and second input terminals and a second terminal connected to a node between the third switching element and the fourth switching element, wherein a node between the second switching element and the third switching element is used as the output terminal of the 3-level voltage generating circuit ; a pulse width modulator that performs a pulse width modulation (in a sine waveform) and outputs the modulated voltage from the output terminal by switching the first to fourth switching elements according to the comparison between a three-wake wave signal and a modulation signal at an input voltage between the first input terminal and the second input terminal; a capacitor voltage detector detecting the voltage of the capacitor; a detector detecting an error of the voltage of the capacitor from 1/2 the input voltage; a capacitor charging and discharging time adjusting device that adjusts a charging time and a discharging time of the capacitor to reduce the error; and a modulation signal corrector generating a first modulation signal, the modulation signal corrected by a correction amount for emphasis, and generating a second modulation signal, wherein the modulation signal is corrected by the correction amount for lowering, wherein the pulse width modulator comprises a first pulse width modulator selected according to the comparison between and a second pulse width modulator which generates a control signal for generates and includes the second switching element and the third switching element, and the capacitor charging and discharging time adjusting device increases or decreases the amount of correction according to the error.
• (2) The pulse width modulator preferably comprises the first pulse width modulator which generates the control signal for the first switching element and the fourth switching element according to the comparison between the modulation signal and the first triangular wave signal, and the second pulse width modulator according to the comparison between the modulation signal and the second triangular wave signal which is 180 ° out of phase of the first triangular wave signal, generates the control signal for the second switching element and the third switching element, the inverter apparatus preferably further comprises a dead time corrector which corrects a dead time of a PWM signal generated by the first pulse width modulator by a correction amount for raising and corrects a dead time of a PWM signal generated by the second pulse width modulator by a correction amount for lowering, and the capacitor charging and discharging time adjusting device preferably increases or decreases the amount of correction according to the error.
• (3) In the above (1) or (2), the correction amount is preferably the product of the error multiplied by a coefficient associated with the capacitance of the capacitor and a coefficient associated with an electric current flowing through the capacitor stands.
• (4) In the above (1) to (3) The inverter device preferably further comprises a differential amplifier circuit having a balanced input and an unbalanced output whose input section is connected across the capacitor, and the capacitor voltage detector preferably detects the voltage of the capacitor by calculating the average of an output voltage of the differential amplifier circuit in a charging current shut-off period after charging the capacitor and an output voltage of the differential amplifier circuit in a discharge current off period after discharging the capacitor.
• (5) In the above (1) to (3), the capacitor voltage detector preferably detects the voltage of the output terminal at a middle timing in a period in which the second switching element and the fourth switching element are turned on.

Advantageous Effects of the Invention

According to the invention, the inverter device is designed to solve the problem of the withstand voltage of the flying capacitor and the switching elements and the problem of the quality of electric current caused by the voltage error in the flying capacitor.

Brief description of the drawings

1 is a circuit diagram of an inverter device 201 according to a first embodiment.

2 FIG. 12 is a table showing the relationship between the states of four switching elements S1 to S4 of a 3-level voltage generating circuit 20 and an output voltage (potential) Vo.

3 Fig. 10 is an equivalent circuit diagram of the 3-level voltage generating circuit 20 in four states.

4 FIG. 12 is a waveform diagram showing pulse width modulation (PWM) of the four switching elements S1 to S4.

5 FIG. 15 is a waveform diagram of a load current (a current flowing through an inductor L1) Io, a voltage Vcf across a capacitor Cf, and the output voltage Vu of FIG 1 shown inverter device 201 ,

6 FIG. 12 is a waveform diagram showing the voltage and state of each part of the inverter device. FIG 201 shows when a target signal Fp is a sinusoidal signal.

7 Fig. 12 is a diagram showing the timing of detection of the voltage Vcf across the capacitor Cf.

8A FIG. 15 is a waveform diagram showing PWM control for changing the average of the voltage Vcf across the capacitor Cf and showing the waveform of each part when the target signal Fp is smaller than a value equivalent to Vdc / 2.

8B FIG. 12 is a waveform diagram showing the PWM control for changing the average of the voltage Vcf across the capacitor Cf, and illustrates the waveform of each part when the target signal Fp exceeds the value equivalent to Vdc / 2.

9 is a schematic diagram of an in 1 shown switching control circuit 100 ,

10 is a truth table of a switching element drive circuit 90 ,

11 FIG. 12 is a graph showing the relationship between the load current Io and a coefficient k (Io) associated with the load current Io.

12 (A) FIG. 12 is a waveform diagram of the voltage Vcf across the capacitor Cf of the inverter device 201 according to the first embodiment. 12 (B) FIG. 12 is a waveform diagram of the voltage Vcf across the capacitor Cf in the case of missing correction of charge and discharge time of the capacitor.

13 FIG. 15 is a waveform diagram showing timings for measuring the voltage of a flying capacitor in an inverter device according to a second embodiment. FIG.

14 FIG. 10 is a block diagram showing a charging and discharging time adjusting circuit for a flying capacitor in an inverter device according to a third embodiment. FIG.

15 Fig. 10 is a circuit diagram of a main portion of an inverter device 204A according to a fourth embodiment.

16 Fig. 10 is a circuit diagram of a main portion of another inverter device 204B according to the fourth embodiment.

17 Fig. 10 is a circuit diagram of a main portion of an inverter device 205A according to a fifth embodiment.

18 Fig. 10 is a circuit diagram of a main portion of another inverter device 205B according to the fifth embodiment.

19 FIG. 10 is a block diagram of a three-phase inverter device according to a sixth embodiment. FIG.

Description of embodiments

Hereinafter, embodiments for embodying the present invention will be described using some specific examples with reference to the drawings. In each drawing, the same reference numerals denote identical components. Each embodiment is merely an example, and the configurations of the different embodiments may of course be partially replaced or combined.

<< First Embodiment >>

1 is a circuit diagram of an inverter device 201 according to a first embodiment. The inverter device 201 comprises a first input terminal IN1 and a second input terminal IN2 to which a DC voltage is fed, a first output terminal OUT1 and a second output terminal OUT2 from which an AC voltage is output. In this example, the second input terminal IN2 and the second output terminal OUT2 are both connected to a reference potential (ground). At the first input terminal IN1 and the second input terminal IN2, the DC voltage generated by, for example, a solar power generation panel is applied.

Between the first input terminal IN1 and the second input terminal IN2 is a 3-level voltage generating circuit 20 connected. The 3-level voltage generation circuit 20 consists of first to fourth switching elements (S1 to S4) connected in series between the first input terminal IN1 and the second input terminal IN2, and a flying capacitor (hereinafter simply referred to as "capacitor") Cf whose first terminal is connected to a node is connected between the first switching element S1 and the second switching element S2 and the second terminal is connected to a node between the third switching element S3 and the fourth switching element S4.

All switching elements S1 to S4 are MOS-FETs, and in 1 Body diodes are also shown. It should be noted that the switching element is not limited to the MOSFET, but may be another type of transistor or the like.

A node between the second switching element S2 and the third switching element S3 corresponds to an output terminal of the 3-level voltage generating circuit 20 , and between the output terminal of the 3-level voltage generating circuit 20 and the first output terminal OUT1, an inductor L1 is connected in series. Between the output terminal of the 3-level voltage generating circuit 20 and the first output terminal OUT1 is also an output current detection circuit 2 connected.

Between the first input terminal IN1 and the second input terminal IN2 is an input voltage detection circuit 1 connected. Above the capacitor Cf is a capacitor voltage detection circuit 3 connected. This capacitor voltage detection circuit 3 consists of a differential amplifier circuit.

A switching control circuit 100 performs PWM control on the switching elements S1 to S4 to output predetermined voltages to the output terminals OUT1 and OUT2. Since the reference potential 0V is applied to the second input terminal IN2 and Vdc is applied to the first input terminal IN1, the inverter device outputs 201 a voltage in a range of 0 to Vdc.

As will be described later, the switching control circuit detects 100 Further, as the voltage of the capacitor Cf, the average between the output voltage of the capacitor voltage detection circuit 3 in a charge-off period after charging the capacitor Cf and the output voltage of the capacitor voltage detection circuit 3 in a discharge current cut-off period after discharging the capacitor Cf. The capacitor voltage detection circuit 3 and the above middle processing section of the switching control circuit 100 correspond to the "capacitor voltage detector" according to the appended claims of this application.

Furthermore, the switching control circuit performs 100 an adjustment in the PWM control according to detection results of the input voltage detection circuit 1 , the output current detection circuit 2 and the capacitor voltage detection circuit 3 out. This adaptation will be described later.

2 FIG. 12 is a table showing the relationship between the states of the four switching elements S1 to S4 of the 3-level voltage generating circuit 20 and an output voltage (potential) Vo. The four switching elements S1 to S4 here assume four states H, Mc, Md and L.

3 Fig. 10 is an equivalent circuit diagram of the 3-level voltage generating circuit 20 in the four previous states. In the state H, the switching elements S1 and S2 are turned on while the switching elements S3 and S4 are turned off, so that the output voltage Vo is equal to Vdc. In the state L, the switching elements S3 and S4 are turned on while the switching elements S1 and S2 are turned off so that the output voltage Vo is 0. In the state Mc, the switching elements S1 and S3 are turned on while the switching elements S2 and S4 are turned off, so that the output voltage Vo is equal to Vdc-Vc. Vc here is a charging voltage of the capacitor Cf. When Vc = Vdc / 2, the output voltage Vo = Vdc / 2. In the state Md, the switching elements S2 and S4 are turned on while the switching elements S1 and S3 are turned off, so that the output voltage Vo is equal to Vc. When Vc = Vdc / 2, the output voltage Vo = Vdc / 2. Since the amount of the electric charge charged in the capacitor Cf is made equal to the amount of electric charge discharged therefrom, the output voltage Vo in the state Mc is equal to the output voltage Vo in the state Md. The charging voltage Vc of the capacitor Cf becomes different Words centered at Vdc / 2, ie the 1/2 of Vdc, charged and discharged. When the charging and discharging time constant of the capacitor Cf is sufficiently larger than a switching frequency, the above charging voltage Vc has a low fluctuation range, and Vc ≈ Vdc / 2 can be adopted. Variations in the output voltage Vo due to the charging and discharging of the capacitor Cf will be described later.

4 FIG. 12 is a waveform diagram showing pulse width modulation (PWM) of the four switching elements S1 to S4. In 4 For example, a first triangular wave signal Vcr1 and a second triangular wave signal Vcr2 are mutually 180 ° out of phase (of opposite polarity). A first PWM signal AQ1 is at a high level (hereinafter, "H level") when the target signal Fp is higher than the first triangular wave signal Vcr1. A second PWM signal AQ2 is at the H level when the target signal Fp is higher than the second triangular wave signal Vcr2.

A gate signal for the first switching element S1 rises with a delay of a dead time td from the rise of the AQ1 and coincides with the fall of the AQ1. A gate signal for the fourth switching element S4 coincides with the rise of the AQ1 and increases with a delay of the dead time td from the fall of the AQ1.

A gate signal for the second switching element S2 increases with a delay of the dead time td from the rise of the AQ2 and coincides with the fall of the AQ2 AQ2. A gate signal for the third switching element S3 coincides with the rise of the AQ2 and increases with a delay of the dead time td from the fall of the AQ2.

In 4 CONDITION IS the in 3 shown states. Thus, when the target signal Fp is smaller than Vdc / 2, the state transition Mc → L → Md → L → ... is repeated. Similarly, if the target signal Fp is Vdc / 2 or more, the state transition Mc → H → Md → H → ... is repeated.

5 is a waveform representation of a load current (a current flowing through an inductor L1) Io, a voltage Vcf across the capacitor Cf, and the output voltage Vu of FIG 1 shown inverter device 201 , These results are obtained under the following conditions.
Vdc = 100V
Capacitance of Cf = 75 μF
Inductance of the inductor L1 = 500 μH
Parallel RC load: R = 20 Ω, C = 1.1 μF

Here, when there is a difference between a charging time of the capacitor Cf in the above state Mc and a discharging time of the capacitor Cf in the state Md, the mean of the voltage Vcf across the capacitor Cf deviates from 1/2 of the input voltage Vdc. For example, when the charging and discharging time difference of the capacitor Cf is 10 ns per charging and discharging period, the average of the voltage Vcf across the capacitor Cf is 53.6 V when a duty ratio is 80%. Therefore, the imbalance (hereinafter referred to as "voltage error") ΔV between a charging voltage and a discharging voltage is 3.6V. When the charging and discharging time difference is 100ns, the average of the voltage Vcf across the capacitor Cf is 89V (Voltage error ΔV = 39 V).

The switching control circuit 100 in the in 1 shown inverter device 201 performs the PWM control on the switching elements S1 to S4 to bring the above voltage error ΔV to zero. The control will be described below.

6 FIG. 12 is a waveform diagram showing the voltage and state of each part of the inverter device. FIG 201 shows when the target signal Fp is a sinusoidal signal. The switching elements S1 and S4 are controlled by the signal in which the dead time is added at the time of the first PWM signal AQ1, and the switching elements S2 and S3 are controlled by the signal at which the dead time at the time of the second PWM signal. Signal AQ2 is added (see 4 ). The dead time is in 6 however, as 0 for the purpose of avoiding a complicated drawing. In 6 a voltage Vo 'is the output voltage of the 3-level voltage generating circuit 20 when the voltage across the capacitor Cf is always assumed to be Vdc / 2. In fact, the voltage Vcf across the capacitor Cf and the output voltage Vo of the 3-level voltage generating circuit fluctuate 20 as in 6 5, since the capacitor Cf is charged during a period of the above state Mc and discharged during a period of the above state Md.

7 FIG. 15 is a diagram showing the timing of detection of the voltage Vcf across the capacitor Cf. The voltage Vcf across the capacitor Cf increases in the period of the state Mc and falls in the period of the state Md. The voltage Vcf across the capacitor Cf is maintained at a constant value in the state L or the state H. In an in 7 In the example shown, the voltage Vcf in the periods of the state L (in 7 times shown in circles) before and after the state Mc or Md are sampled, and the means thereof is treated as a voltage across the capacitor Cf. The time period between the state Mc and the state Md corresponds to the "charging current cut-off period" according to the appended claims of this application, while the period between the state Md and the state Mc corresponds to the "discharge current cutoff period" according to the appended claims of this application.

8A and 8B are waveform diagrams showing the PWM control for changing the mean of the voltage Vcf across the capacitor Cf. 8A FIG. 15 is a diagram in which the target signal Fp is smaller than a value equivalent to Vdc / 2 while FIG 8B is the illustration in which the target signal Fp exceeds the value equivalent to Vdc / 2. When the target signal Fp + α is to cause a PWM circuit to generate the first PWM signal AQ1, the rise timing of the first PWM signal AQ1 advances by ΔT and the fall timing thereof retards by ΔT. In other words, a pulse width thereof widens 2ΔT. When the target signal Fp-.alpha. For the PWM circuit to generate the second PWM signal AQ2, the rise timing of the second PWM signal AQ2 is delayed by .DELTA.T and the fall timing thereof advances by .DELTA.T. A pulse width of the same narrows in other words by 2ΔT. The above target signal Fp + α corresponds to the "first modulation signal" in the appended claims of this invention, and the above target signal Fp - α corresponds to the "second modulating signal" in the appended claims of this invention.

4 FIG. 12 shows state transmission when the above adaptation is not performed using ± α. How to compare with 4 1, the above adaptation using ± α extends the state Mc (a charging period to the capacitor Cf) and shortens the state Md (a discharge period from the capacitor Cf). As a result, the average of the voltage Vcf across the capacitor Cf increases.

The above embodiment describes a case where an electric current flows in a positive direction, in other words, the load current Io in an in 1 shown direction flows. In a case where the electric current flows in a "negative" direction, the charging and discharging are reversed and the periods Mc and Md are exchanged. Thus, the direction of the correction is also reversed, and thus the above α should be multiplied by "-1".

9 is a schematic of the in 1 shown switching control circuit 100 , The switching control circuit 100 consists of a capacitor charging and discharging time matching circuit 70 , a PWM circuit 80 and a switching element drive circuit 90 , The PWM circuit 80 corresponds to a "pulse width modulator" according to the invention. The capacitor charging and discharging time matching circuit 70 includes a correction amount generation circuit 71 and an adder circuit 73 and a subtracter circuit 74 for performing addition or subtraction on the target signal by the correction amount α. The capacitor charging and discharging time matching circuit 70 corresponds to the "capacitor charging and discharging time adjusting device" according to the invention. The correction amount generation circuit 71 determines the correction amount α of the target signal according to the input voltage Vdc, the voltage Vcf across the capacitor Cf and the load current Io. A target signal generation circuit 72 is a circuit provided in a higher-level controller (outside the switching control circuit 100 ) and is realized, for example, by an arithmetic processing for sequentially calculating the values of a sine wave.

The PWM circuit 80 includes triangular wave generating circuits 81 and 82 and comparators 83 and 84 , The triangular wave generating circuit 81 generates the first triangular wave signal Vcr1, and the second triangular wave generating circuit 82 generates the second triangular wave signal Vcr2.

10 is a truth table of the switching element drive circuit 90 , The switching element drive circuit 90 generates the gate signals of the four switching elements S1 to S4, as in FIG 8A and 8B is shown.

The above description regarding PWM is based on the premise that analog circuits perform the PWM for ease of illustration. The PWM can however be performed by digital circuits or by digital arithmetic processing. In the case where the capacitor charging and discharging time matching circuit 70 and the PWM circuit 80 , in the 9 are configured using the digital circuits, the triangular wave generating circuits become 81 and 82 realized by counter and the comparators 83 and 84 are realized by digital comparators. The correction amount generation circuit 71 determines the value of the target signal according to the correction amount or the correction amount in the counts of the triangular waves. Ie. the "triangular wave signal" of this invention is not limited to an analog signal, but includes "a value changing in the form of a triangular wave".

Here, Ic represents an electric current flowing through the capacitor, Tc is a charging time, C represents the capacitance of the capacitor, ΔVc represents a voltage change of the capacitor voltage during charging, and ΔVd represents a voltage change of the capacitor voltage during discharging and have the following relationship. ΔVc = Ic × Tc / C ΔVd = -Ic × Td / C

The voltage error ΔV thus has the following relationship. ΔV = (Tc - Td) × Ic / C (1)

Meanwhile, an error ΔT in the charging and discharging time has the following relationship. ΔT = ΔV × C / Ic (2)

Ie. the charge and discharge time error ΔT is directly proportional to the voltage error ΔV and the capacitance C of the capacitor Cf. Further, the charge and discharge time error ΔT is inversely proportional to the capacitor current Ic. The capacitor current Ic is equivalent to the load current Io.

The voltage error ΔV is obtained from the difference between 1/2 of the input voltage Vdc and the voltage Vcf across the capacitor Cf, and the correction amount with respect to ΔT is the product of the voltage error ΔV multiplied by a feedback gain k. The above feedback gain k is the product of a coefficient associated with the reciprocal of the load current Io, a coefficient associated with the capacitance C, and a Coefficients for securing stability in a feedback system.

11 FIG. 12 is a graph showing the relationship between the load current Io and the coefficient k (Io) associated with the load current Io. The coefficient k (Io) associated with the load current Io is inversely proportional to the load current Io, as in FIG 11 is shown by a dashed line, but is not necessarily mathematically inversely proportional, and the coefficient k (Io) may change stepwise as in 11 is shown by a solid line.

12 (A) FIG. 12 is a waveform diagram of the voltage Vcf across the capacitor Cf of the inverter device 201 according to the first embodiment. 12 (B) FIG. 12 is a waveform diagram of the voltage Vcf across the capacitor Cf when the charging and discharging time of the capacitor is not corrected. Both representations show a period of the target signal. If there is a difference between the charging time and the discharging time of the capacitor Cf, as in 12 (B) is shown, the average voltage across the capacitor Cf varies with a voltage change of the sine wave of the target signal. On the other hand, according to this embodiment, since the voltage error caused by the difference between the charging time and the discharging time of the capacitor Cf is corrected, the average voltage of the capacitor Cf is always kept at about Vdc / 2, as in FIG 12 (A) is shown.

It should be noted that the correction value has limit values. Here must be in 8A and 8B The target signals Fp + α and Fp -α are within a range of a maximum value (Dmax) and a minimum value (Dmin) of the PWM control, and (2) the target signals Fp + α and Fp-α Means of the target signals, ie, ((Fp + α) + (Fp-α)) / 2, does not change. Accordingly, the absolute value of αα is limited between (Dmax-Fp) and (Fp-Dmin).

<< SECOND EMBODIMENT >>

13 FIG. 12 is a waveform diagram showing the timing of measuring the voltage of a flying capacitor in an inverter device according to a second embodiment. FIG. The inverter device has the same circuit configuration as that of the first embodiment. Since discharging is started at the start of the period of the state Md and terminated at the end thereof, the voltage Vcf at the middle time of the state Md indicates the average voltage of the flying capacitor. As with reference to 1 and 3 the switching elements S2 and S4 are turned on in the above state Md, the voltage of the flying capacitor Cf appears at the output terminal of the 3-level voltage generating circuit 20 in the state Md. By sampling the output voltage Vo of the 3-level voltage generating circuit 20 at the middle time tc of the state Md, as in FIG 13 is shown, therefore, the average voltage of the flying capacitor can be obtained. A processing section which performs the above sampling in the switching control circuit corresponds to the "capacitor voltage detector" according to the appended claims of this application.

This embodiment has a longer sampling period than the first embodiment and makes the operation for calculating the mean unnecessary, thereby reducing an operating load. Since there is no need for a differential detection, can also be dispensed with a sensor, which leads to cost reduction.

<< THIRD EMBODIMENT >>

14 FIG. 10 is a block diagram showing a charging and discharging time adjusting circuit for a flying capacitor in an inverter device according to a third embodiment. FIG.

In the first embodiment, the charging and discharging time of the flying capacitor is controlled by ± α by adjusting the target signal of the PWM control. In the third embodiment, the charging and discharging time of the flying capacitor is corrected by adjusting the dead time of the PWM signals.

In the 14 The inverter device shown includes a dead time adjustment circuit 50 , a PWM circuit 60 , Delay circuits 51 to 54 and the dead time increasing and decreasing circuits 55 and 56 , In 14 calculates the dead time adjustment circuit 50 the voltage error ΔV from the voltage Vcf across the capacitor Cf and the input voltage Vdc and determines the correction amount ΔT of the dead time (see td of FIG 4 ) of the switching elements S1 to S4 according to the coefficient associated with the reciprocal of the load current Io. The dead time adjustment circuit 50 corresponds to the "dead time corrector" according to the invention. The PWM circuit 60 generates a PWM signal for the first switching element S1 and the fourth switching element S4 and a PWM signal for the second switching element S2 and the third switching element S3. A control signal (gate signal) for the first switching element S1 is an inverse of a control signal (gate signal) for the fourth switching element S4. A control signal (gate signal) for the second switching element S2 is an inversion of a control signal (gate signal) for the third switching element S3. The delay circuits S1 to S4 output the Control signals for the switching elements S1 to S4 with a delay of increasing or decreasing time of .DELTA.T relative to the constant dead time.

As described above in this embodiment, the charging and discharging time of the flying capacitor can be corrected by adjusting the dead time of the PWM signals.

<< FOURTH EMBODIMENT >>

A fourth embodiment describes an example in which a neutral potential of the DC input voltage is set as a reference potential of the output voltage of the inverter device.

15 Fig. 10 is a circuit diagram of a main portion of an inverter device 204A according to the fourth embodiment. Between the first input terminal IN1 and the second input terminal IN2 of the inverter device 204A Vdc is applied and the intermediate voltage (neutral voltage) therebetween is a potential of the second output terminal OUT2. The other configurations are the same as those in 1 shown circuit arrangement.

16 Fig. 10 is a circuit diagram of a main portion of another inverter device 204B according to the fourth embodiment. Between the first input terminal IN1 and the second input terminal IN2 of the inverter device 204B a series circuit with capacitors Ci1 and Ci2 is connected, and at the second output terminal OUT2 a potential is applied to a node between the capacitors Ci1 and Ci2. The other configurations are the same as those in 1 shown circuit arrangement.

<< FIFTH EMBODIMENT >>

A fifth embodiment describes an inverter device including an H-bridge circuit 30 after the 3-level voltage generating circuit 20 includes.

17 Fig. 10 is a circuit diagram of a main portion of an inverter device 205A according to the fifth embodiment. The H-bridge circuit 30 is after the 3-level voltage generation circuit 20 connected. The other configurations are the same as those in 1 shown circuit arrangement. In the H-bridge circuit 30 four switching elements S11, S12, S21 and S22 are connected by bridge. By switching the four switching elements S11, S12, S21 and S22, the output voltage of the 3-level voltage generating circuit 20 alternately reversed for output.

The 3-level voltage generation circuit 20 generates a voltage of half a wave of the sine wave, and the H bridge circuit 30 the voltage reverses in a period of sine wave. Thus, the sine wave voltage is output to the load.

18 Fig. 10 is a circuit diagram of a main portion of another inverter device 205B according to the fifth embodiment. The inverter device 205B includes the first input terminal IN1 and the second input terminal IN2 to which the DC voltage is input, and the first output terminal OUT1 and the second output terminal OUT2 from which the AC voltage is output. At the first input terminal IN1 and the second input terminal IN2, the DC voltage generated by, for example, the solar power generation panel is applied. In 18 Su and Sw represent a single-phase three-phase current system with a U-phase and a W-phase.

In this inverter device 205B are two 3-level voltage generating circuits 20H and 20L connected between the first input terminal IN1 and the second input terminal IN2. The 3-level voltage generating circuits 20H and 20L each have the same configuration as the one in 1 3-level voltage generating circuit shown 20 on. However, the polarities of the target signals are between the 3-level voltage generating circuits 20H and 20L opposite each other. A node between the two 3-level voltage generating circuits 20H and 20L is at a neutral potential of the inverter device. The output of the H-bridge circuit 30 is connected by inductors L1 and L2 to the single-phase three-wire system. An AC voltage having an effective voltage of 100 V is applied between the first output terminal OUT1 and a neutral point NP, and an AC voltage having an effective voltage of 100 V is applied between the neutral point NP and the second output terminal OUT2, so that an AC voltage with an effective voltage of 200 V is applied between the first output terminal OUT1 and the second output terminal OUT2.

<< SIXTH EMBODIMENT >>

19 FIG. 10 is a block diagram of a three-phase inverter device according to a sixth embodiment. FIG. Inverter devices 206U . 206V and 206W are the inverter devices, such as those in 16 are shown, which use the neutral potential of the DC input voltage as the reference potential of the inverter device. The voltages at the output terminals U, V and W of the inverter devices 206U . 206V and 206W are sinusoidal voltages and phase shifted by 120 ° in this order.

Note that, in each of the above-described embodiments, the MOS-FET is used as a switching element, but an IGBT (Insulated Gate Bipolar Transistor) may be used instead.

LIST OF REFERENCE NUMBERS

AQ1, AQ2

PWM signal

Cf

flying capacitor

Ci1, Ci

capacitor

fp

target signal

H, Mc, Md, L

Status

IN1

first input terminal

IN 2

second input terminal

io

load current

K

Feedback gain

L1, L2

inductor

NP

neutral point

OUT1

first output terminal

OUT2

second output terminal

S1

first switching element

S2

second switching element

S3

third switching element

S4

fourth switching element

tc

middle time

td

dead

AND MANY MORE

output terminal

Vc

charging voltage

vcf

Voltage of the capacitor

VCR1

first triangular wave signal

VCR2

second triangular wave signal

Vdc

input voltage

Vo

output voltage

Vu

output voltage

1

Input voltage detection circuit

2

Output current detection circuit

3

Capacitor voltage detection circuit

20, 20H, 20L

3-level voltage generation circuit

30

bridge circuit

50

Totzeitanpassschaltung

51-54

delay circuit

55, 56

the dead time increasing or decreasing circuit

60

PWM circuit

70

Capacitor charging and discharging time adjusting circuit

71

Correction amount generating circuit

72

Target signal generating circuit

73

adder

74

subtractor

80

PWM circuit

81, 82

Triangular wave generating circuit

83, 84

comparator

90

Switching element drive circuit

100

Switch control circuit

201

Inverter device

204A, 204B

Inverter device

205A, 205B

Inverter device

206U, 206V, 206W

Inverter device

Claims (5)

An inverter device comprising: a 3-level voltage generating circuit having first to fourth switching elements connected in series between a first input terminal and a second input terminal of a DC power supply, and a capacitor having a first terminal connected to a node between the first switching element and the first terminal a second terminal connected to a node between the third switching element and the fourth switching element, wherein a node between the second switching element and the third switching element is used as the output terminal of the 3-level voltage generating circuit; a pulse width modulator that performs a pulse width modulation and outputs the modulated voltage from the output terminal by switching the first to fourth switching elements according to the comparison between a three-wake wave signal and a modulation signal at an input voltage between the first input terminal and the second input terminal; a capacitor voltage detector detecting the voltage of the capacitor; a detector detecting an error of the voltage of the capacitor from 1/2 the input voltage; a capacitor charging and discharging time adjusting device that adjusts a charging time and a discharging time of the capacitor to reduce the error; and a modulation signal corrector generating a first modulation signal, wherein the modulation signal is corrected by a correction amount for emphasis, and generating a second modulation signal, wherein the modulation signal is corrected by the amount of correction for lowering, wherein the pulse width modulator comprises a first pulse width modulator selected according to the comparison between generating a control signal for the first switching element and the fourth switching element to the first modulation signal and a first triangular wave signal, and a second pulse width modulator, a control signal according to the comparison between the second modulation signal and a second triangular wave signal, which is 180 ° out of phase of the first triangular wave signal for the second switching element and the third switching element, and the capacitor charging and discharging time adjusting device increases or decreases the correction amount according to the error. Inverter apparatus comprising: a 3-level voltage generating circuit having first to fourth switching elements connected in series between a first input terminal and a second input terminal of a DC power supply, and a capacitor having a first terminal connected to a node between the first switching element and the second switching element and a second terminal connected to a node between the third switching element and the fourth switching element, wherein a node between the second switching element and the third switching element is used as the output terminal of the 3-level voltage generating circuit; a pulse width modulator that performs a pulse width modulation and outputs the modulated voltage from the output terminal by switching the first to fourth switching elements according to the comparison between a three-wake wave signal and a modulation signal at an input voltage between the first input terminal and the second input terminal; a capacitor voltage detector detecting the voltage of the capacitor; a detector detecting an error of the voltage of the capacitor from 1/2 the input voltage; and a capacitor charging and discharging time adjusting device that adjusts a charging time and a discharging time of the capacitor to reduce the error, wherein the pulse width modulator comprises a first pulse width modulator which generates a control signal for the first switching element and the fourth switching element according to the comparison between the modulation signal and a first triangular wave signal, and a second pulse width modulator which is selected from the first one according to the comparison between the modulation signal and a second triangular wave signal Triangular wave signal is 180 ° out of phase, generates a control signal for the second switching element and the third switching element comprises, the inverter apparatus further comprises a dead time corrector which corrects a dead time of a PWM signal generated by the first pulse width modulator by a correction amount for raising and corrects a dead time of a PWM signal generated by the second pulse width modulator by a correction amount for lowering, and the capacitor charging and discharging time adjusting device increases or decreases the correction amount according to the error. An inverter apparatus according to claim 1 or 2, wherein the correction amount is a product of the error multiplied by a coefficient associated with the capacitance of the capacitor and a coefficient associated with an electric current flowing through the capacitor. An inverter device according to any one of claims 1 to 3, further comprising: a differential amplifier circuit having a balanced input and an asymmetrical output whose input section is connected across the capacitor, wherein the capacitor voltage detector calculates the average of an output voltage of the differential amplifier circuit in a charge current cut-off period after charging the capacitor and an output voltage of the differential amplifier circuit in a discharge current cut-off period after discharging the capacitor. An inverter device according to any one of claims 1 to 3, wherein the capacitor voltage detector detects the voltage of the output terminal at a middle timing in a period in which the second switching element and the fourth switching element are turned on.

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