DE112014001423T5 - Semiconductor structures with InGaN comprehensive active areas, methods for forming such semiconductor structures and light emitting devices formed from such semiconductor structures - Google Patents

Abstract

Semiconductor structures include an active region between a plurality of layers of InGaN. The active region can at least essentially be formed from InGaN. The plurality of layers of InGaN include at least one InwGa1-wN comprising source layer and at least one InbGa1-bN comprehensive barrier layer near the at least one source layer. In some embodiments, the value of w in the InwGa1-wN of the source layer may be greater than or equal to about 0.10 and less than or equal to about 0.40, and in some embodiments, the value of b in the InBGa1-bN of the at least one Barrier layer greater than or equal to about 0.01 and less than or equal to about 0.10. Methods for forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Lighting devices include such LEDs.

Description

Technical area

The present disclosure relates to semiconductor structures and light-emitting devices made of such semiconductor structures, which have an active region comprising InGaN, methods of manufacturing such light-emitting devices, and devices including such light-emitting devices.

background

Light emitting devices, such as light emitting diodes (LEDs), are electrical devices that emit electromagnetic radiation in the form of visible light when a voltage is applied to an active region of the LED between an anode and a cathode. LEDs typically comprise one or more layers of semiconductor material within which electrons supplied by the anode and holes recombined by the cathode recombine. As the electrons and holes recombine within the active region of the LED, energy is released in the form of photons emitted from the active region of the LED.

LEDs can be fabricated to include a wide range of different types of semiconductor materials, including, for example, III-V semiconductor materials and II-V semiconductor materials. The wavelength of the light emitted by a particular LED is a function of the amount of energy released when an electron and a hole recombine. Therefore, the wavelength of the light emitted by the LED is a function of the relative energy difference between the energy level of the electron and the energy level of the hole. The energy levels of the electrons and the energy levels of the holes are at least partially a function of the composition of the semiconductor materials, the doping type and concentration, the configuration (i.e., crystal structure and orientation) of the semiconductor materials, and the quality of the semiconductor materials, within which there is recombination of the electrons and holes occurs. Thus, the wavelength of the light emitted by an LED can be selectively adjusted by selectively adjusting the composition and configuration of the semiconductor materials within the LED.

From the prior art, the production of LEDs is known, which include III-V semiconductor materials, such as group III nitride materials. Such group III nitride LEDs are known to be able to emit radiation in the blue and green visible regions of the electromagnetic radiation spectrum and to operate at comparatively high power and luminous intensity.

Quick Facts

The present summary is cited to introduce a selection of concepts in a simplified form. These concepts are described in more detail below in the detailed description of exemplary embodiments of the disclosure. The present summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In some embodiments, the present disclosure includes a semiconductor structure that includes a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 Angstroms. An active region is disposed over the base layer, wherein the active region comprises a plurality of layers of InGaN. The plurality of layers of InGaN include at least one In _w Ga _1-w N source layer of 0.10 ≦ w ≦ 0.40 and at least one In _b Ga _1-b N barrier layer of 0.01 ≦ b ≦ 0.10 , An electron blocking layer is disposed on a side of the active region opposite to the GaN base layer. A p-type bulk layer is disposed on the electron-blocking layer, and the p-type bulk layer comprises In _p Ga _{1 -p} N with 0.00 ≦ p ≦ 0.08. A p-type contact layer is disposed on the p-type bulk layer with the p-type contact layer In _c Ga _1-c N including 0.00 ≦ c ≦ 0.10.

In additional embodiments, the disclosure includes light emitting devices fabricated from such semiconductor structures. For example, in additional embodiments, the present disclosure includes a light emitting device that includes a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 angstroms. An active area is arranged above the base layer. The active area includes a plurality of layers of InGaN, and the plurality of layers of InGaN include at least one source layer and at least one barrier layer. An electron barrier layer is disposed over the active region. A p-type In _p Ga _{1 -p} N bulk layer is disposed over the electron-blocking layer, and there is a p-type In _c Ga _{1 -c} N contact layer over the p-type In _p Ga _{1 -p} N -Bulk layer arranged. In addition, a critical load energy of the light-emitting device may be equal to about 4500 or less.

Additional embodiments of the disclosure include methods of making such structures and devices. For example, in some embodiments, the present disclosure includes a method of forming a semiconductor structure in which a GaN base layer is provided that has a polar growth plane having a growth plane lattice parameter greater than or equal to about 3.189 angstroms. A plurality of layers of InGaN are grown to form an active region over the base layer. Growing the plurality of layers of InGaN includes growing at least one source layer comprising In _w Ga _1-w N of 0.10 ≦ w ≦ 0.40, and growing at least one barrier layer over the at least one source layer, wherein the at least one a barrier layer In _b Ga _1-b N with 0.01 ≤ b ≤ 0.10. An electron-blocking layer is grown over the active area. A p-type In _p Ga _{1 -p} N bulk layer is grown over the electron-blocking layer at 0.00 ≦ p ≦ 0.08, and a p-type In _c Ga _{1 -c} N contact layer is grown over the p -Type In _p Ga _1-p N bulk layer grown with 0.00 ≤ c ≤ 0.10.

Brief description of the drawing

1A FIG. 4 is a simplified side view of a semiconductor structure including one or more InGaN source layers and one or more InGaN barrier layers in an active area of the semiconductor structure according to embodiments of the present disclosure.

1B FIG. 4 is a simplified diagram illustrating the relative differences in the energy level of the conduction band in an energy band diagram for the various materials in the various layers of the semiconductor structure of FIG 1A ,

2A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG 1A however, further including an electron trapping layer between an active region and a base layer of the semiconductor structure.

2 B is a simplified conduction band diagram for the semiconductor structure of 2A ,

3A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG 1A however, further including a stress relaxation layer between an active region and a base layer of the semiconductor structure.

3B is a simplified conduction band diagram for the semiconductor structure of 3A ,

4A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG 1A however, further includes thin GaN additive barrier layers within the active region of the semiconductor structure.

4B is a simplified conduction band diagram for the semiconductor structure of 4A ,

5A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG 1A however, further includes a source flow structure within the active region of the semiconductor structure.

5B is a simplified band diagram for the semiconductor structure of 5A ,

6A FIG. 4 is a simplified top plan view of an intermediate semiconductor structure that may be used to fabricate a growth template used to fabricate semiconductor structures in accordance with embodiments of methods of the present disclosure.

6B FIG. 16 is a partial cross-sectional side view of the intermediate semiconductor structure of FIG 6A ,

6C 13 is a partial cross-sectional side view of a growth template that may be used to fabricate semiconductor structures in accordance with embodiments of methods of the present disclosure.

6D shows layers of a growth stack with epitaxial deposition on a growth template like that in FIG 6C ,

7 FIG. 10 is a partial cross-sectional side view of a light-emitting device fabricated from semiconductor structures in accordance with embodiments of methods of the present disclosure. FIG.

8th 13 is a partial cross-sectional side view of an additional light-emitting device fabricated from semiconductor structures in accordance with embodiments of methods of the present disclosure.

9 FIG. 10 is a graph illustrating the relationship between internal quantum efficiency and the total load energy of semiconductor structures formed according to embodiments of methods of the present disclosure. FIG.

10A Figure 4 is a simplified side view of an already known LED incorporating InGaN source layers and GaN barrier layers in an active region of the LED.

10B is a simplified line band diagram for the LED of 10A ,

11A FIG. 14 is a graph illustrating calculated band edges for the conduction band and the valence band with a vanishing applied voltage at the active region of the LED of FIG 10A in which the calculations are obtained using a computer model of the LED.

11B is a graph similar to that of 11A which, however, represents the calculated band edges for the conduction band and the valence band at a current density of 125 A / cm ² when flowing over the active region of the LED due to an applied voltage at the active region.

11C FIG. 12 is a graph illustrating the calculated intensity of emitted radiation as a function of wavelength for each InGaN quantum well layer in the LED of FIG 11A ,

11D FIG. 12 is a graph illustrating the calculated carrier injection efficiency as a function of applied current density at the active region of the LED of FIG 11A ,

11E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density at the active region of the LED of FIG 11A ,

12A FIG. 3 is a simplified side view of an LED of the present disclosure similar to that of FIG 1A and includes InGaN source layers and InGaN barrier layers in an active area of the LED.

12B is a simplified line band diagram for the LED of 12A ,

13A FIG. 14 is a graph illustrating calculated band edges for the conduction band and the valence band with a vanishing applied voltage at the active region of the LED of FIG 12A in which the calculations are obtained using a computer model of the LED.

13B is a graph similar to that of 13A which, however, represents the calculated band edges for the conduction band and the valence band at a current density of 125 A / cm ² when flowing over the active region of the LED due to an applied voltage at the active region.

13C FIG. 12 is a graph illustrating the calculated intensity of emitted radiation as a function of wavelength for each InGaN quantum well layer in the LED of FIG 13A ,

13D FIG. 12 is a graph illustrating the calculated carrier injection efficiency as a function of applied current density at the active region of the LED of FIG 13A ,

13E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density at the active region of the LED of FIG 13A ,

14 FIG. 12 shows an example of a lighting device incorporating an LED of the present disclosure. FIG.

detailed description

The illustrations provided herein are not intended to be realistic views of any particular semiconductor material, structure, or device, but rather purely idealized representations used to describe embodiments of the disclosure.

1A shows an embodiment of a semiconductor structure 100 , The semiconductor structure 100 includes a plurality of Group III nitride layers (e.g., indium nitride, gallium nitride, aluminum nitride and their alloys) and includes a base layer 102 , a p-type contact layer 104 and an active area 106 that's between the base layer 102 and the p-type contact layer 104 is arranged, wherein the active area 106 comprises a plurality of layers of InGaN. In addition, the activity area includes 106 at least one InGaN swelling layer and at least one InGaN barrier layer. In some embodiments, the active area 106 at least substantially formed of InGaN (except for the presence of dopants). The semiconductor structure 100 further comprises an electron barrier layer 108 that are above the active area 106 is arranged, a p-type bulk layer 110 that over the electron barrier 108 is arranged, and a p-type contact layer 104 that over the p-type bulk layer 110 is arranged.

The base layer 102 can be a GaN base layer 112 wherein a growth plane of the GaN base layer 112 is a polar plane having a growth plane lattice parameter greater than or equal to about 3.189 angstroms. A light-emitting device, such as a light-emitting diode, may be of the semiconductor structure 100 , which will be described in detail below. In short, there may be a first electrode contact over a portion of the GaN base layer 112 may be formed, and there may be a second electrode contact over a portion of the p-type contact layer 104 be formed, so that an electrical voltage between the electrode contacts over the active area 106 can be supplied, thereby causing electromagnetic radiation (for example, visible light) from one of the semiconductor structure 100 produced light emitting device is emitted.

Embodiments for semiconductor structures of the present disclosure that include an active region that includes at least one InGaN swelling layer and at least one InGaN barrier layer may be formed using various types of methods for growing or otherwise forming Group III nitride layers. Layers, such as InGaN produced. In non-limiting examples, the various Group III nitride layers may be grown or otherwise formed using one or more of a CVD process (Chemical Vapor Deposition CVD), a MOCVD process (Metalorganic Chemical Vapor Deposition MOCVD , organometallic chemical vapor deposition), a Vapor Phase Epitaxy (VPE) process, an Atomic Layer Deposition (ALD) process, an atomic layer deposition (HVPE) process, an MBE process (Hydride Vapor Phase Epitaxy HVPE). Process (Molecular Beam Epitaxy MBE, Molecular Beam Epitaxy), an Atomic Layer Deposition (ALD) process, a Chemical Beam Epitaxy CBE (CBE) process, and the like.

For growing or otherwise depositing the various layers of Group III nitride, in some embodiments, methods disclosed in any or all of the following references, namely, U.S. Patent No. 5,315,015 to Letertre et al. US Patent Application Publication No. US 2010/0176490 A1, published May 6, 2010, for Arena Publication of US Patent Application No. US 2010/0109126, published on August 23, 2012 for Figuet, US Patent Application Publication No. Hei US 2012/0211870 and US Patent Application Publication No. US 2012/0225539, issued to Figuet on Sep. 6, 2012. Such methods may enable the fabrication of Group III nitride layers, such as InGaN layers (and other optional Group III nitride layers) having compositions and thicknesses described below. Such methods may be used to form a growth template 113 can be used on the subsequent group III nitride layers can be formed.

An example of such a method used to make the growth template 113 according to embodiments of the disclosure can be used, will be described below 6A to 6C briefly described.

6A FIG. 10 is an upper plan view of an intermediate semiconductor structure. FIG 650 involved in the formation of the growth template 113 (from 1A ), on which one or more semiconductor structures and subsequently light-emitting devices of the present disclosure can be made, while 6B a simplified cross-sectional view of a portion of the intermediate semiconductor structure 650 That is, in the formation of the growth template 113 is being used. The growth template 113 can be prepared as disclosed in the aforementioned publication of US Patent Application No. US 2010/0176490 A1 and / or the publication of US Patent Application No. US 2010/0109126. As disclosed herein, the intermediate semiconductor structure 650 a victim substrate 652 , a layer of an associated material 654 with arrangement on the sacrificial substrate 652 and one or more In _s Ga ₁ -s N seed layers 656 each comprising a layer of a Group III nitride material overlying the associated material 654 is arranged. The one or more In _s Ga ₁ -s N seed layers 656 may be used as a "seed" to which the various subsequent layers of the semiconductor structure 100 as described herein.

The initial In _s Ga ₁ -s N seed layer may be formed on an initial growth substrate and then on a sacrificial substrate 652 using methods such as ion implantation, bonding, and then separating a portion of the initial In _s Ga ₁ -s N seed layer (not shown). The initial growth substrate may include a growth substrate characterized by having a growth level lattice mismatch with the initial In _s Ga ₁ -s N seed layer such that the In _s Ga ₁ -s N seed layer is stained , For example, the initial growth substrate may include a sapphire substrate that includes a gallium-polar GaN seed layer such that the formed In _s Ga ₁ -s N seed layer includes a gallium-Polar-In _s Ga ₁ -s N seed layer that exhibits tensile strain is exposed.

The initial In _s Ga ₁ -s N seed layer may be formed or grown such that the In _s Ga ₁ -s N seed layer comprises a growth plane comprising a polar plane of the Group III nitrides. The growth plane can be formed, for example, such that the In _s Ga ₁ -s N seed layer comprises a gallium polar plane. Moreover, the initial In _s Ga ₁ -s N seed layer may be grown or otherwise formed such that the composition of the In _s Ga ₁ -s N seed layer is such that 0.02 ≦ s ≦ 0.05 applies. In a particular non-limiting example, the value of n in the In _s Ga ₁ -s N seed layer may be equal to about 0.03. The In _s Ga ₁ -s N seed layer may also be grown or otherwise formed to a thickness of greater than about 200 nm. However, the In _s Ga _1-s N-seed layer is formed such that the In _s Ga _1-s N-seed layer which does not exceed the In _s Ga _1-s N-seed layer to own critical thickness is that thickness at which relaxes the stress in the In _s Ga ₁ -s N seed layer by forming additional defects. This phenomenon is commonly referred to in the art as phase separation. Therefore, the In _s Ga ₁ -s N seed layer may contain a contaminated high quality seed material.

By way of example, and not by way of limitation, a process known in the industry as the SMART-CUT process may be used to form the In _s Ga ₁ -s N seed layer 656 on the victim substrate 652 using the layer of the associated material 654 as a bonding layer to transfer. Such processes are described in detail, for example in the U.S. Patent No. RE39,484 from Bruel, in the U.S. Patent No. 6,303,468 by Aspar et al., in which U.S. Patent No. 6,335,258 by Aspar et al., in the publication 6,756,286 by Moriceau et al., in the publication 6,809,044 by Aspar et al. and in the publication 6,946,365 by Aspar et al. described.

The sacrificial substrate 652 may comprise a homogeneous material or a heterogeneous (that is composite or composite) material. In non-limiting examples, the support substrate 652 Sapphire, silicon, Group III arsenide, quartz (SiO ₂ ), fused silica glass (SiO ₂ ), a glass-ceramic composite (such as that available from Schott North America, Inc. of Duryea, PA under the tradename ZERODUR ^® ), a fused silica glass composite material (such as SiO ₂ -TiO ₂ or Cu ₂ -Al ₂ O ₃ -SiO ₂ ), aluminum nitride (AlN) or silicon carbine (SiC).

The layer of the associated material 654 For example, it may comprise a material having a glass transition temperature (T _g ) less than or equal to about 800 ° C. The layer from the associated material 654 may have a thickness in a range extending from about 0.1 μm to about 10 μm and in particular from about 1 μm to about 5 μm. In one non-limiting example, the layer of the associated material 100 at least one of an oxide, a phosphosilicate glass (PSG), a borosilicate glass (BSG), a borophosphosilicate glass (BPSG) a polyimide, a doped or undoped quasi-siloxane spin-on glass (SOG), an inorganic spin-on Glass (ie methyl, ethyl, phenyl or butyl) or a doped or undoped silicate.

The layer of the associated material 654 For example, by using an oven, a furnace, or an application reactor, it may be brought to a temperature to lower the viscosity of the layer of the associated material 654 for a reflow of the layer of the associated material 654 are heated, thereby causing the one or more In _s Ga ₁ -s N seed layers 656 for at least partially relaxing the crystal lattice loading. By lowering the viscosity of the layer of the associated material 654 can reduce the tensile load in the In _s Ga _1-s N seed layer 656 at least partially relaxed or even eliminated, whereby an In _s Ga ₁ -s N seed layer 656 having a growth plane lattice parameter greater than or equal to about 3.189 angstroms.

Therefore, by relaxing at least a portion of the lattice strain within the In _s Ga ₁ -s N, a growth plane lattice parameter greater than or equal to about 3.189 angstroms can be achieved in the In _s Ga ₁ -s N. A growth plane lattice parameter greater than or equal to 3.189 angstroms may correspond to the equilibrium growth plane lattice constant for wurtzite GaN. Therefore, in accordance with some embodiments of the disclosure, one or more GaN layers formed on or over the In _s Ga - 1 _s N layers of the present disclosure may be formed in a no load, that is, substantially free of lattice loading.

With at least partial relaxation of the one or more In _s Ga ₁ -s N seed layers 656 may be the In _s Ga _1-s N seed layers 656 be transferred to a support substrate, wherein substantially the associated material 654 and the sacrificial substrate 652 can be removed to the growth template 113 to form, as in 1A and 6C is shown. More detailed and with reference to 6B and 6C shown, the at least partially relaxed In _s Ga ₁ -s N seed layer 656 on a support substrate 658 can be attached, and it can be the victim substrate 652 and the associated material 654 using methods such as one or more of laser lift off, wet etching, dry etching, and chemical mechanical polishing.

The support substrate 658 may comprise a homogeneous material or a heterogeneous (composite) material. In non-limiting examples, the support substrate 658 Sapphire, silicon, Group III arsenide, quartz (SiO ₂ ), fused silica glass (SiO ₂ ), a glass-ceramic composite (such as that available from Schott North America, Inc. of Duryea, PA under the tradename ZERODUR ^® ), a fused silica glass composite material (such as SiO ₂ -TiO ₂ or Cu ₂ -Al ₂ O ₃ -SiO ₂ ), aluminum nitride (AlN) or silicon carbine (SiC).

As in 6C In some embodiments, the growth template may be shown 113 optionally a layer of a dielectric material 660 which are above the support substrate 100 lies. The layer of the dielectric material 660 can optionally over a main surface of the support substrate 658 or the one or more In _s Ga ₁ -s N seed layers 656 are formed, wherein the dielectric material 660 can be used as the bonding layer to bond the In _s Ga ₁ -s N seed layer 656 to the support substrate 658 to facilitate. The layer of the dielectric material 660 For example, it may include silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ), or silicon dioxide (SiO ₂ ), and may be formed using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Therefore, the growth template includes 113 , as in 1A and 6C is shown, a support substrate 658 and an In _s Ga ₁ -s N seed layer 656 attached to the support substrate 658 is arranged.

In addition, the In _s Ga ₁ -s N seed layer 656 over the support substrate 658 be formed such that the composition of the In _s Ga ₁ -s N seed layer 656 in a range 0.02 ≤ s ≤ 0.05. In a non-limiting example, the value of s in the In _s Ga ₁ -s N seed layer 656 equal to about 0.03. In addition, the In _s Ga _1-s N seed layer 656 a polar growth plane 662 having a growth plane lattice parameter greater than or equal to about 3.189 angstroms. The In _s Ga ₁ -s N seed layer may also be formed to a total layer thickness T _s greater than about 100 nm.

The growth template 113 forms a section of the base layer 102 from 1A , The base layer may also include a GaN base layer in some embodiments 112 wherein the GaN base layer has the crystal properties of the adjacent In _s Ga ₁ -s N seed layer 656 inherits. Therefore, the GaN base layer 112 also comprise a polar growth plane, such as a gallium polar growth plane, having a growth plane lattice parameter greater than or equal to about 3.189 angstroms.

The GaN base layer 112 may be formed at least substantially of GaN (except for the presence of dopants). The GaN base layer 112 may have an average layer thickness T _n of between about 10 nm and about 3000 nm or, in some embodiments, of between about 10 nm and about 1000 nm. Optionally, the GaN base layer 112 be doped. The GaN base layer 112 can be n-type doped by doping with elements that are electron donors, such as silicon or germanium. The concentration of dopants in the GaN base layer 112 may range from about 3e ¹⁷ cm ^-3 to about 1e ²⁰ cm ^-3, or in some embodiments from about 5e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 .

A first electrode contact may be at a portion of the GaN base layer 112 after forming one or more of the other different layers of the InGaN-comprising semiconductor structure 100 are formed to a light-emitting device of the semiconductor structure 100 manufacture.

The finished base layer 102 includes, as in 1A is shown, the growth template 113 as described above and the GaN base layer 112 , The different group III nitride layers of the semiconductor structure 100 may be grown or otherwise formed in a layer-by-layer process, which will be described in more detail below. In some embodiments, the base layer 102 a base on which the other layers of the semiconductor structure 100 grown up or otherwise formed. Thus, the various group III nitride layers of the semiconductor structure 100 one after the other at the beginning of the base layer 102 and with movement in a direction from left to right with respect to the perspective of 1A grown or otherwise formed in succession. The structure, however, may actually be oriented such that the base layer 102 is arranged on the bottom or the underside during production. In other words, the structure can be rotated 90 ° counterclockwise with respect to the orientation of 1A be oriented during production.

As will be explained in detail below, the active area is 106 between the base layer 102 and the p-type contact layer 104 arranged. The active area 106 comprises at least one InGaN source layer 114 and at least one InGaN barrier layer 116 , In some embodiments, the active area 106 at least essentially InGaN (except for the presence of dopants), the indium content of the InGaN swelling layer 114 consistently or strictly greater than the indium content of the InGaN barrier layer 116 is. In particular, the active area 106 at least one source layer 114 which includes In _w Ga _1-w N with 0.10 ≤ w ≤ 0.40 or in some embodiments with 0.12 ≤ w ≤ 0.25 or in other embodiments with w equals approximately 0.14. The active area 106 also includes at least one barrier layer 116 which comprises In _b Ga _{1 -b} N with b <w and with 0.01 ≤ b ≤ 0.10 or in some embodiments with 0.03 ≤ b ≤ 0.08 or in other embodiments with b equal to approximately 0.05 , In some embodiments, the InGaN barrier layer 116 close to (for example, directly adjacent to) the at least one InGaN source layer 114 be located.

The active area 106 For example, when fabricated as a light emitting device, such as a light emitting diode (LED), the semiconductor structure is that portion of the semiconductor structure in which electrons and holes recombine with each other to produce photons emitted from the LED. In some embodiments, the photons are emitted in the form of visible light. At least a portion of the visible light may have a wavelength or wavelengths within a range of the electromagnetic radiation spectrum extending from about 380 nm to about 560 nm.

As mentioned above, the active area comprises 106 the semiconductor structure 100 one or more InGaN source layers 114 and one or more InGaN barrier layers 116 and may be at least substantially formed of InGaN (except for the presence of dopants) in some embodiments. This can be the active area 106 consist essentially of InGaN in some embodiments. The active area 106 includes one or more pairs of adjacent layers that form a source layer 114 and a barrier layer 116 include, with each source layer 114 In _w Ga _1-w N with 0.10 ≤ w ≤ 0.40 and where each barrier layer 116 In _b Ga _1-b N with 0.01 ≤ b ≤ 0.10 and b <w.

At the in 1A and 1B illustrated embodiment includes the active area 106 the semiconductor structure 100 a pair of active layers (swelling layer 114 and barrier layer 116 ), although in additional embodiments the active area 106 the semiconductor structure 100 may also involve more than one pair of active layers. The active area 106 the semiconductor structure 100 For example, it may include 1 to 25 adjacent pairs of active layers, each pair being a source layer 114 and a barrier layer 116 includes, so the active area 106 a stack of alternating swelling layers 114 and barrier layers 116 (in embodiments involving more than one pair). It should be understood, however, that the number of barrier layers 116 if necessary, not equal to the number of source layers 114 is. The source layers 114 can from each other through the barrier layers 116 be separated. Thus, in some embodiments, the number of barrier layers 116 greater than the number of source layers 114 , but also equal to this or less than this.

As continues in 1A can represent any source layer 114 have an average layer thickness T _w of between about 1 nm and about 1000 nm, between about 1 nm and about 100 nm, or between about 1 nm and about 10 nm. The source layers 114 may include quantum wells in some embodiments. In such embodiments, each source layer 114 have an average layer thickness T _w of about 10 nm or less. In other embodiments, the swelling layers 114 also do not include quantum sources, with each source layer 114 has an average layer thickness T _w greater than about 10 nm. In such embodiments, the active area 106 include what is known in the art as "double heterostructures". Every barrier layer 116 may have an average layer thickness T _B of between about 1 nm and about 50 nm, or between about 1 nm and about 10 nm, although the barrier layers 116 in other embodiments may also be thicker.

One or both from the source layers 114 and the barrier stories 116 can be doped. For example, one or both of the source layers 114 and the barrier stories 116 n-type doped by doping with elements that are electron donors, such as silicon or germanium. The concentration of dopants in the swelling layers 114 may range from about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 or from about 3e ¹⁷ cm ^-3 to about 5e ¹⁷ cm ^-3 in some embodiments. Similarly, the concentration of dopants in the barrier layers 116 from about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 or from about 1e ¹⁸ cm ^-3 to about 3e ¹⁸ cm ^-3 in some embodiments.

One or both from the source layers 114 and the barrier stories 116 may have a wurtzite crystal structure. In addition, in some embodiments, one or both of the swelling layers 114 and the barrier stories 116 a polar growth surface, such as a gallium polar growth surface, having an average lattice constant in the growth plane parallel to the interface or interfaces between the source layers 114 and the barrier stories 116 which is greater than or equal to about 3.189 angstroms. In particular, in some embodiments, the average growth level lattice constant c may be between about 3.189 angstroms and about 3.2 angstroms.

The active area 106 having at least one swelling layer and at least one barrier layer, may have an average total thickness in a range between about 40 nm and about 1000 nm, in a range between about 40 nm and about 750 nm, or even in a range between about 40 nm and about 200 nm.

As continues in 1A is shown, the semiconductor structure 100 optional additional layers between the active area 106 and the p-type contact layer 104 and / or between the active area 106 and the base layer 102 include. The semiconductor structure 100 For example, in some embodiments, a spacer layer may be used 118 between the active area 106 and the base layer 102 include.

The optional spacer layer 118 may comprise a layer of In _sp Ga _{1 -sp} N with 0.01 ≦ sp ≦ 0.10 or with 0.03 ≦ sp ≦ 0.06 or with sp equal to about 0.05. The spacer layer 118 can be used for a more gradual transition between the base layer 102 and the layers of the active area 106 which has a different composition (that is, a different lattice parameter) relative to the GaN base layer 112 has to provide. Thus, the In _sp Ga _1-sp N spacer layer 118 directly between the base layer 102 and the active area 106 arranged in some embodiments. By providing a more gradual transition between the base layer 102 and the active area 106 For example, stresses within the crystal lattice of the various layers of InGaN and thus defects due to such stresses can be reduced. The In _sp Ga _1-sp N spacer layer 118 can a average layer thickness T _sp of between about 1 nm and about 100 nm or between about 1 nm and about 25 nm. In a particular non-limiting example, the average layer thickness T _{sp may be} equal to about 10 nm.

Optionally, the In _sp Ga _{1 -sp} N spacer layer 118 be doped. The In _sp Ga _1-sp N spacer layer 118 For example, it can be n-type doped by doping with elements that are electron donors, such as silicon or germanium. The concentration of dopants in the spacer layer 118 may range from about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 . In a particular non-limiting example, the concentration of dopants in the spacer layer 118 be equal to about 2e ¹⁸ cm ^-3 .

As continues in 1A is shown, the semiconductor structure 100 furthermore, an optional In _cp Ga _1-cp N capping layer 120 involve between the active area 106 and the p-type contact layer 104 is arranged. The optional In _cp Ga _1-cp N cap layer 120 may comprise a layer of In _cp Ga _1-cp N at 0.01 ≤ cp ≤ 0.10 or at 0.03 ≤ cp ≤ 0.07. In a particular non-limiting example, the value of cp may be equal to about 0.05. The In _cp Ga _1-cp N cap layer 120 may be used to prevent the dissolution and / or evaporation of indium in the underlying layers of the active region 106 during subsequent processing at elevated temperatures, and / or may perform the same function as a spacer layer.

The In _cp Ga _1-cp N cap layer 120 may have an average layer thickness T _cp of between about 1 nm and about 100 nm or between about 1 nm and about 25 nm. In a non-limiting example, T _cp may be equal to about 10 nm. Optionally, the cap layer 120 be doped. So can the cap layer 120 For example, p-type doping may be done by doping with elements that are electron acceptors, such as magnesium, zinc and carbon. In other embodiments, the cap layer 120 be doped n-type-like. The concentration of dopants in the cap layer 120 may range from about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 or from about 1e ¹⁸ cm ^-3 to about 5e ¹⁸ cm ^-3 . In a particular non-limiting example, the concentration of dopants in the cap layer 120 equal to about 2e ¹⁸ cm ^-3 in some embodiments.

The semiconductor structure 100 The present disclosure may further include one or more electron blocking layers (EBLs) disposed between the active region 106 and the p-type contact layer 104 are arranged. Such electron blocking layers may comprise a material in which the energy level of the band edge of the conduction band compared to the band edge of the conduction band in the active region 106 is comparatively high, which can serve to electrons to the interior of the active area 106 narrow down and overflow the wearer from the asset area 106 to prevent.

In a non-limiting example 1A an electron barrier layer 108 which is on one side of the cap layer 120 opposite or opposite to the active area 106 is arranged. In embodiments, a p-type bulk layer 110 , as in 1A can be shown, the electron barrier layer 108 directly between the cap layer 120 and the p-type bulk layer 110 be arranged.

The electron barrier layer 108 includes a Group III nitride. In one non-limiting example, the electron barrier layer 108 at least substantially In _e Ga ₁ -e N (except for the presence of dopants) of 0.00 ≦ e ≦ 0.02, and in some embodiments may be at least substantially GaN (except for the presence of dopants). In further embodiments, the electron barrier layer 108 at least substantially Al _e Ga _{1 e} eN be formed with 0.00 ≤ e ≤ 0.20. In some embodiments, the electron-blocking layer 108 at least substantially Al _e Ga _1-e eN be formed (except for the presence of dopants).

The electron barrier layer 108 may be p-type doped with one or more dopants selected from a group consisting of magnesium, zinc and carbon. The concentration of the one or more dopants within the electron barrier layer 108 may be in a range extending from about 1e ¹⁷ cm ^-3 to about 1e ²¹ cm ^-3 , or may be equal to about 3e ¹⁹ cm ^-3 in some embodiments. In some embodiments, the electron-blocking layer 108 an average film thickness T _e comprise in a range extending from about 5 nm to about 50 nm, or may in some embodiments comprise about 20 nm, an average film thickness T _e equal.

In further embodiments of the semiconductor structure 100 According to the present disclosure, the semiconductor structure 100 an electron-blocking layer similar to the electron-blocking layer 108 however, the electron barrier layer has a superlattice structure comprising alternating layers of different materials as in the cutout 122 from 1A is shown. So can the electron barrier layer 108 For example, have a superlattice structure, the alternating layers of GaN 124 and In _e Ga _1-e N 124 with 0.01 ≤ e ≤ 0.02. In further embodiments, the electron-blocking layer may comprise a superlattice structure comprising alternating layers of GaN 124 and Al _e Ga _1-e eN 126 with 0.01 ≤ e ≤ 0.20. Each of the layers in such superlattice structures may have an average layer thickness of from about 1 nm to about 20 nm.

As mentioned above, the semiconductor structure 100 Further, according to the present disclosure, a p-type bulk layer 110 involve, between the electron barrier layer 108 and the p-type contact layer 104 is arranged. Such p-type bulk layers may comprise p-doped group III nitride material, such as p-doped In _p Ga _{1 -p} N. Such p-type bulk layers can be used, for example, as a source of hole carriers as well as for promoting electrical conduction and light extraction to the active region 106 be used towards and away from this. The inclusion of indium in the p-type bulk layer 110 is helpful for reasons of carrier flow as well as to confine the wearer to the interior of the active area.

The p-type bulk layer 110 may be at least substantially formed of In _p Ga _{1 -p} N (except for the presence of dopants) of 0.00 ≦ p ≦ 0.08 and preferably 0.01 ≦ p ≦ 0.08. In a particular non-limiting example, the p-type bulk layer 110 at least substantially formed of In _p Ga _{1 -p} N with p equal to about 0.02. The p-type bulk layer 110 may be p-type doped with one or more dopants selected from a group consisting of magnesium, zinc and carbon. The concentration of the one or more dopants within the p-type bulk layer 110 may be in a range extending from about 1e ¹⁷ cm ^-3 to about 1e ²¹ cm ^-3 . In a particular non-limiting example, the concentration of dopants in the p-type bulk layer 110 be equal to about 3e ¹⁹ cm ^-3 . In some embodiments, the p-type bulk layer 110 an average layer thickness T _p in a range extending from about 50 nm to about 600 nm. In a particular non-limiting example, the p-type bulk layer 110 have an average layer thickness T _p equal to about 175 nm.

The semiconductor structure 100 Further, a p-type contact layer 104 include, on one side of the p-type bulk layer 110 opposite or opposite to the electron barrier layer 108 is arranged. The p-type contact layer 104 may include a Group III nitride. Such p-type contact layers can be used, for example, to improve the conduction of holes in the active region 106 be used in it. The p-type contact layer 104 may comprise a higher concentration of one or more dopants, such as p-type dopants, so as to limit the electrical resistance of an electrode contact extending over a portion of the p-type contact layer during the fabrication of a light emitting device from the semiconductor structure 100 forms.

In a non-limiting example, the p-type contact layer 104 In _c Ga _1-c N, which is p-type doped. So can the p-type contact layer 104 For example, at least substantially In _c Ga _{1 -c} N may be formed with 0.01 ≦ c ≦ 0.10 (except for the presence of dopants), and in some embodiments may be the p-type contact layer 104 at least substantially GaN (except for the presence of dopants) may be formed. The inclusion of indium in the p-type contact layer 104 is advantageous in that it can reduce the energy barrier to the metal electrode that results from the device due to a lower operating voltage for the device. The p-type contact layer 104 may be p-type doped with one or more dopants selected from a group consisting of magnesium, zinc and carbon. The concentration of the one or more dopants within the p-type contact layer 104 may be in a range extending from about 1e ¹⁷ cm ^-3 to about 1e ²¹ cm ^-3 . In a particular non-limiting example, the concentration of the one or more dopants within the p-type contact layer 104 equal to about 1e ²⁰ cm ^-3 . The p-type contact layer 104 may have an average layer thickness T _c in a range extending from about 2 nm to about 50 nm. In a particular non-limiting example, the p-type contact layer 104 have an average layer thickness T _c equal to about 15 nm. As in 1A can be shown, the p-type contact layer 104 directly on the p-type contact layer 110 be formed.

As will be described in detail below, the completed semiconductor structure 100 in the manufacture of one or more semiconductor light-emitting devices, such as an LED, be used. In short, electrode contact may occur over a portion of the semiconductor layers of the base layer 102 , such as over a portion of the GaN base layer 112 , and further may be an electrode contact over a portion of the p-type contact layer 104 be formed, thereby allowing charge carriers in the active area 106 be injected, resulting in an emission of electromagnetic radiation, which can be in the form of visible light results.

1B is a simplified diagram illustrating the relative differences in the energy levels of the conduction band 128 (in an energy band diagram) for different semiconductor materials in the different layers of the semiconductor structure 100 from 1A (Note that the support substrate 658 and the bonding layer 660 are omitted). 1B is vertical to the semiconductor structure 100 from 1A aligned. The vertical dashed lines in 1B are with the interfaces between the different layers in the semiconductor structure 100 from 1A aligned. The vertical axis in 1B is the energy, with higher energy levels being vertically above lower energy levels. Note that 1B a non-limiting example of the conduction band energy levels for an exemplary semiconductor structure 100 shows. As a result, the relative horizontal conduction band energy levels may differ in their relative position as a function of at least the composition and doping of the individual semiconductor layers, with the compositional ranges of the various semiconductor layers within a range as described above. So that can 1B be used for the relative differences in the energy levels of the conduction band 128 in the different layers of the semiconductor structure 100 consider. As in 1B can be shown, the energy level of the conduction band 128 in the source layer 114 lower than the energy level of the conduction band 128 in other layers of the semiconductor structure 100 be.

As is known in the art, in group III nitride layers, such as InGaN, the energy level of the conduction band is 128 a function of several variables, including but not limited to indium content and dopant levels. The source layers 114 and the barrier stories 116 may be formed to have a composition and other configuration such that the energy level of the conduction band 128 in the source layers 114 lower than the energy level of the conduction band 128 in the barrier stories 116 is. As a result, the charge carriers (for example, electrons) in the source layers 114 during operation, one of the semiconductor structure 100 accumulated light-emitting device, and there may be the barrier layers 116 serve for a migration of charge carriers (for example electrons) over the active area 106 to prevent. Thus, in some embodiments, the indium content in each source layer 114 higher than the indium content in each barrier layer 116 be. The difference between the indium content in each source layer 114 and the indium content in each barrier layer 116 For example, it may be greater than or equal to about 0.05 (ie, w-b ≥ 0.05), or may be greater than or equal to about 0.20 (that is, w-b ≥ 0.20) in some embodiments. In some embodiments, the dopant concentration in the barrier layers 116 different from the dopant concentration in the swelling layers 114 be. High dopant concentrations can lead to defects in the crystal structure of InGaN, and such defects can lead to nonradiative combinations of electron-hole pairs. In some embodiments, the dopant concentration in the swelling layers 114 lower than the dopant concentration in the barrier layers 116 for reducing the rate of non-radiative combinations of electron-hole pairs in the swelling layers 114 relative to the rate of non-radiatable combinations of electron-hole pairs in the barrier layers 116 be. In other embodiments, the dopant concentration in the barrier layers 116 higher than the dopant concentration in the swelling layers 114 be.

As in 1B Shown is the energy barrier coming from the electron barrier layer 108 is provided from the difference in the energy level of the conduction band 128 in the electron barrier layer 108 and the cap layer 120 (or another layer immediately adjacent to the electron barrier layer 108 on the side thereof closest to the active area 106 is). The height of the energy barrier can be changed by changing the composition of the electron barrier layer 108 will be changed. For example, as in 1B shown is the line power level 130 (shown as a solid line) represent the conduction band energy level for an electron-blocking layer formed at least substantially of GaN (except for the presence of dopants). The conduction band energy level within the electron-blocking layer may be reduced relative to a GaN electron-blocking layer, such as through the conduction band energy level 132 (shown by a dashed line) is formed by forming an electron barrier layer formed at least substantially of In _e Ga _{1 -e} N where 0.01≤e≤0.02. In further embodiments, the conduction band energy level may be increased relative to a GaN electron barrier layer, such as by the conduction band energy level 134 (shown as a dashed line) is represented by an electron barrier layer is formed is formed at least substantially of Al _e Ga _{1 -e} N where 0.01≤e≤0.20. Therefore, the energy level of the conduction band within the electron-blocking layer can be changed such that a desired conduction band offset between the electron-blocking layer 108 and the other group III nitride layers of the semiconductor structure 100 provided.

In embodiments of the semiconductor structure 100 in which the electron barrier layer 108 has a superlattice structure comprising alternating layers of different materials, the conduction band energy level may increase and decrease in a periodic manner as in the cutout 136 from 1B is shown. For example, the electron barrier layer 108 have a superlattice structure comprising alternating layers of GaN 138 and Al _e Ga _1-e N 140 with 0.01 ≤ e ≤ 0.20. Alternatively, the superlattice structure may include alternating layers of GaN and In _e Ga _{1 -e} N where 0.01≤e≤0.02. The size of the conduction band energy offset between the alternating layers of different materials can be selected by the composition difference between the GaN layers and the Al _e Ga ₁ -e N or In _e Ga _1-e N layers.

Semiconductor structures of the present disclosure may further include electron retention layers disposed between the active region of the semiconductor structure and the GaN base layer of the semiconductor structure. Such electron retention layers may comprise an n-doped Group III nitride material in which the energy level of the band edge of the conduction band comparatively to the band edge in the conduction band in the GaN base layer and / or the In _sp Ga _1-sp N base layer higher, which serves to further confine the electrons to the interior of the active region and prevent overflow of carriers from the active region, thereby providing improved uniformity of carriers within the active region.

In a non-limiting example 2A and 2 B an embodiment of a semiconductor structure 200 which is such an electron-retaining layer 202 includes. The semiconductor structure 200 is similar to the semiconductor structure 100 and includes an active area 106 containing one or more InGaN source layers 114 and one or more InGaN barrier layers 116 includes, as above in connection with the semiconductor structure 100 has been described. The semiconductor structure 200 also includes a base layer 102 a spacer layer 118 , a cap layer 120 , an electron-blocking layer 108 , a p-type bulk layer 110 and a p-type contact layer 104 as above in connection with the semiconductor structure 100 has been described. The electron retention layer 202 the semiconductor structure 200 is between the GaN base layer 102 and the spacer layer 118 arranged.

The electron retention layer 202 includes a Group III nitride. In one non-limiting example, the electron capture layer may be 202 AlGaN, which is n-type doped. Thus, in some embodiments, the electron trapping layer 202 For example, at least substantially Al _st Ga _1-st N be formed (except for the presence of dopants) with 0.01 ≤ st ≤ 0.20. In other embodiments, the electron capture layer may 202 a superlattice structure, as in the clipping 204 having alternating layers of Al _st Ga _1-st N 206 with 0.01 ≤ st ≤ 0.20 and layers of GaN 208 includes. The semiconductor structure 200 may be any number (for example, from about 1 to about 20) of alternating layers of Al _st Ga _1-st N 206 and layers of GaN 208 include. The layers 206 and 208 in such a superlattice structure may have an average layer thickness of about 1 nm to about 100 nm.

The electron retention layer 202 may be n-type doped with one or more dopants selected from a group consisting of silicon and germanium. The concentration of the one or more dopants within the electron capture layer 202 may be in a range which extends from about 0.1E ¹⁸ cm ^-3 to 20e ¹⁸ cm ^-3. In some embodiments, the electron capture layer may 202 have an average layer thickness T _st in a range extending from about 1 nm to about 50 nm.

2 B is a simplified conduction band diagram illustrating the relative energy levels of the conduction band 228 for the different materials in the semiconductor structure 200 as in 2 B is shown in the embodiment of the semiconductor structure 200 from 2A the energy level of the conduction band 228 within at least a portion of the electrodeposition layer 202 the semiconductor structure 200 ( 2 B ) comparatively higher than the energy level of the conduction band 200 within the GaN base layer 112 and / or the energy level of the conduction band 228 within the spacer layer 118 , In embodiments in which the electron capture layer 202 a superlattice structure, as in the clipping 210 from 2 B which in turn comprises alternating layers of Al _st Ga _1-st N 206 with 0.01 ≤ st ≤ 0.20 and layers of GaN 208 includes, the conduction band energy level may vary periodically.

In additional embodiments, semiconductor structures of the present disclosure may include one or more layers of material between the active region and the GaN base layer that are used to facilitate fabrication of the semiconductor structure. For example, in some embodiments, the semiconductor structure and the one or more light-emitting devices fabricated from such structures of the present disclosure may include one or more stress relaxation layers disposed between the active region and the GaN base layer, wherein the stress relaxation layers are composed and configured such that that they receive the stress in the crystal lattice of the crystal structures of the different layers of the semiconductor structure between the GaN base layer and the p-type contact layer, wherein the layers can be epitaxially grown on top of each other in a layer-by-layer process.

As a non-limiting example 3A and 3B an embodiment of a semiconductor structure 300 that is a stress relaxation layer 302 includes. The semiconductor structure 300 is to the semiconductor structure 100 similar and includes an active area 106 containing one or more InGaN source layers 114 and one or more InGaN barrier layers 116 includes as above in connection with the semiconductor structure 100 has been described. The semiconductor structure 300 also includes a base layer 102 a spacer layer 118 , a cap layer 120 , an electron-blocking layer 108 , a p-type bulk layer 110 and a p-type contact layer 104 as above in connection with the semiconductor structure 100 has been described. The stress relaxation layer 302 of the semiconductor substrate 300 is between the GaN base layer 112 and the spacer layer 118 arranged. In the embodiment of 3A and 3B is the stress relaxation layer 302 directly between the GaN base layer 112 and the In _sp Ga _{1 -sp} N spacer layer 118 arranged.

The stress relaxation layer 302 may include a Group III nitride. In a non-limiting example, the stress relief layer 302 a superlattice structure, as in the clipping 304 is shown _having the alternating layers of In _sra Ga _{1 -sra} N 306 with 0.01 ≤ sra ≤ 0.10 and layers of In _srb Ga _{1 -srb} N 308 with 0.01 ≤ srb ≤ 0.10. Furthermore, sra can be larger than srb. The semiconductor structure 300 may be any number (for example, from about 1 to about 20) of alternating layers of In _sra Ga _{1 -sra} N layers 306 and In _srb Ga _{1 -srb} N 308 include. The layers 306 and 308 in such a superlattice structure may have an average layer thickness of about 1 nm to about 20 nm.

The stress relaxation layer 302 may be n-type doped with one or more dopants selected from a group consisting of silicon and germanium. The concentration of the one or more dopants within the stress relaxation layer 302 may be in a range which extends from about 0.1E to about ¹⁸ cm ^-3 20e ¹⁸ cm ^-3. In some embodiments, the stress relaxation layer 302 have an average layer thickness in a range extending from about 1 nm to about 50 nm.

3B is a simplified conduction band diagram showing the relative energy levels of the conduction band 328 for the different materials in the semiconductor structure 300 , As in 3B can be shown in the embodiment of the semiconductor structure 300 from 3A the energy level of the conduction band 328 within at least a portion of the stress relief layer 302 the semiconductor structure 300 ( 3A ) is comparatively lower than the energy level of the conduction band 328 within the GaN base layer 112 and / or the energy level of the conduction band 328 within the spacer layer 118 be. In other embodiments, the energy level of the conduction band 328 within at least a portion of the stress relief layer 302 the semiconductor structure 300 ( 3A ) comparatively higher than the energy level of the conduction band 328 within the InGaN base layer 112 and / or the energy level of the conduction band 328 within the spacer layer 118 be. In embodiments where the stress relaxation layer 302 a superlattice structure, as in the clipping 310 from 3B is shown comprising the alternating layers of In _sra Ga _{1 -sra} N 306 and In _srb Ga _{1 -srb} N 308 includes, the conduction band energy level may vary periodically.

4A and 4B show again another embodiment of a semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the semiconductor structure 100 and includes an active area 406 containing one or more InGaN source layers 114 and one or more InGaN barrier layers 116 includes as above in connection with the semiconductor structure 100 described has been. The semiconductor structure 400 also includes a base layer 102 a spacer layer 118 , a cap layer 120 , an electron-blocking layer 108 , a p-type bulk layer 110 and a p-type contact layer 104 as above in connection with the semiconductor structure 100 has been described. The active area 406 the semiconductor structure 400 further includes GaN additional barrier layers 402 , Each of the GaN additional barrier layers 402 can be between an InGaN source layer 114 and an InGaN barrier layer 116 be arranged. The GaN additional barrier layers 402 can serve the electrons inside the source layers 114 further narrow down, where they are more likely to recombine with holes, resulting in an increased likelihood of radiation emission.

In some embodiments, each GaN barrier layer 402 n-type doped with one or more dopants selected from a group consisting of silicon and germanium. The concentration of the one or more dopants within the GaN barrier layers 402 For example, it may be in a range extending from about 1.0 e ¹⁷ cm ^-3 to about 50 e ¹⁷ cm ^-3 . In some embodiments, each GaN barrier layer 402 have an average layer thickness T _b2 in a range extending from about 0.5 nm to about 20 nm.

4B is a simplified conduction band diagram illustrating the relative energy levels of the conduction band 428 for the different materials in the semiconductor structure 400 as in 4B can be shown in the embodiment of the semiconductor structure 400 from 4A the energy level of the conduction band 428 within the GaN barrier layers 402 ( 4A ) comparatively higher than the energy level of the conduction band 428 within the InGaN barrier layers 116 and higher than the energy level of the conduction band 428 within the InGaN source layers 114 be.

5A and 5B Again, other embodiments of the present disclosure that illustrate a semiconductor structure 500 include. In these embodiments, methods disclosed in the disclosure in the January 31, 2012, for Arena et al. US Patent Application Serial No. 13 / 362,866 for forming an active area 506 be used. The semiconductor structure 500 is similar to the semiconductor structure 100 and includes an active area 506 containing one or more InGaN source layers 514 and one or more InGaN barrier layers 516 includes as above in connection with the semiconductor structure 100 has been described. The semiconductor structure 500 Also includes a base layer, a spacer layer, a capping layer, an electron-blocking layer, a p-type bulk layer, and a p-type contact layer as described above in connection with the semiconductor structure 100 has been described. For clarity, only those layers are the active area 506 surrounded, wherein these layers are the optional spacer layer 118 and the cap layer 120 as well as the GaN base layer 112 and the electron barrier layer 108 may include. Are the optional layers of the semiconductor structure 500 omitted, so the active area 506 directly between the GaN base layer 112 and the electron barrier layer 108 be arranged.

The active area 506 the semiconductor structure 500 is similar to the active region of the semiconductor structure 100 but also includes two or more InGaN barrier layers, where the bandgap energy between successive barrier layers is stepped from right to left as viewed in FIG 5A and 5B that is, in a direction different from the cap layer 120 to the spacer layer 118 extends, increases. Such a configuration of the active area 506 in the semiconductor structure 500 can be used when confining charge carriers inside the active area 500 by preventing overflow of carriers from the active area 506 be conducive, thereby increasing the efficiency of out of the semiconductor structure 500 produced light emitting devices is increased.

The barrier areas 516 _ACs may have a material composition and structure configuration chosen such that each of the barrier regions 516 _AC with respective bandgap energies 550 _AC , where the bandgap energy is due to the energy difference between the conduction band energy 528 and the valence band energy 552 of each of the semiconductor materials comprising the semiconductor structure 500 include, is given. The bandgap energy 550 _A in the first barrier area 516 _A can be smaller than the bandgap energy 550 _B in the second barrier area 516 _B , and the bandgap energy 550 _B in the second barrier area 516 _B can be smaller than the bandgap energy 550 _C in the third barrier area 516 _C , as in the energy band diagram of 5B is shown. Furthermore, each of the bandgap energies of the quantum well regions 552 _AC may be substantially the same and may be less than each of the bandgap energies 516 _{AC of} the barrier areas 550 Be _AC .

In this configuration, a hole energy barrier 554 _A between the first quantum source 514 _A and the second quantum source 514 _B smaller than a hole energy barrier 554 _A between the second quantum well 516 _B and the third quantum source 516c be. In other words, the hole energy barriers 554 _AC over the barrier areas 516 _AC can be phased over the active area 506 in a direction different from the cap layer 120 to the spacer layer 118 extends, increase. The electron hole energy barriers 554 _AC are the differences of the energies of the valence band 552 across the interfaces between the quantum well regions 514 _AC and the adjacent barrier areas 516 _AC . As a result of increasing electron hole energy barriers 554 _AC over the barrier areas 516 _AC upon movement from the cap layer 120 towards the spacer layer 108 may increase the distribution uniformity of holes within the active area 506 be achieved, resulting in improved efficiency during the operation of a semiconductor 500 produced light-emitting device leads.

As mentioned above, the barrier areas 516 _{AC have} a material composition and structure configuration chosen such that each of the barrier regions 516 _AC with a different bandgap energy 550 _{AC is} provided. By way of example and not by way of limitation, any barrier may be used 516 _AC include a ternary III nitride material, such as In _{b 3} Ga _{1-b 3} N, wherein b _{3 is} at least about 0.01. A decrease in indium content (that is, a decrease in the value of b3) in the In _b3 Ga1 _-b3 N of the barrier regions 516 _AC can be the bandgap energy of the barrier areas 516 _{Increase AC} . This can be the second barrier area 516 _{B is} a lower indium content relative to the first barrier region 516 _A , and it may be the third barrier area 516 _{C has} a lower indium content relative to the second barrier region 516 _B have. In addition, the barrier areas 516 _AC and the source areas 514 _AC doped and may have an average layer thickness, as described above in connection with the semiconductor structure 100 has been described.

As mentioned above, according to embodiments of the present disclosure, the active area 106 (from 1A ) comprise at least one InGaN swelling layer and at least one InGaN barrier layer, and in some embodiments may be at least substantially InGaN (eg, may consist essentially of InGaN except for the presence of dopants). A plurality of the heretofore known light-emitting device structures comprising the InGaN source layers include (at least substantially indium-free) GaN barrier layers. The difference in the energy level of the conduction band between InGaN source layers and GaN barrier layers is comparatively high, which according to the teaching of the prior art enables an improved confinement of the charge carriers in the interior of the source layers and can lead to an improved efficiency of the LED structures. However, the prior art structures and methods may result in a decrease in device efficiency due to carrier overflow and piezoelectric polarization.

In the carrier overflow theory, the one or more quantum well layers may be considered analogous to a water bucket, with its ability to trap and maintain injected carriers decreasing with greater carrier injection. If injected carriers are not captured or held, they will overflow the active area, and they will be wasted or wasted, contributing to a drop in device efficiency. In prior art structures comprising InGaN quantum wells and GaN barrier layers, the band offset, that is, the difference in conduction band energy levels between the quantum wells and the barriers, is significantly greater than the band offset for an active region that is substantially absent InGaN is as described in the embodiments. The reduction in the band offset in the structures described herein enables the injected carriers to distribute more efficiently across the quantum well regions of the active region, thereby increasing the efficiency of the light emitting devices fabricated from the semiconductor structures described herein.

Moreover, due to a lattice mismatch between the InGaN source layers and the GaN barrier layers, a comparatively strong piezoelectric polarization occurs within the active region in such light emitting device structures. The piezoelectric polarization can reduce the overlap between the wave functions for the electrons and the wave functions for the holes within the active regions of the light emitting device structures. For example, as described in "Numerical Analysis of Efficiency Droop Induced by Piezoelectric Polarization in InGaN / GaN Light Emitting Diodes" by J.H. Son and J.L. Lee, published by Appl. Phys. Lett. 97, 032109 (2010), piezoelectric polarization can lead to what is termed efficiency droop in such light emitting device structures (eg, LEDs). The efficiency drop phenomenon is a decrease (decrease) of the internal quantum efficiency (IQE) graph of the LED structure with increasing current density.

Embodiments of a light-emitting structure, such as LED structures of the present disclosure, may present problems with previously known LED structures including InGaN source layers and GaN barrier layers in the context of lattice mismatch, carrier overflow, piezoelectric polarization phenomenon, and the like reduce or eliminate efficiency droop. Embodiments of LEDs of the present disclosure, such as those of the semiconductor structure 100 from 1A and 1B fabricated LED structure may be configured such and the energy band structure thereof may be designed such that the active area 106 has a reduced piezoelectric polarization effect and an increased overlap of the wave function of the electrons and the wave function of the holes. As a result, the light-emitting device, such as LEDs, can have improved carrier uniformity over the active region 106 and have a reduced efficiency decrease with increasing current density.

The advantages that can be achieved by the embodiments of the present disclosure will be further discussed below 10A and 10B . 11A to 11E . 12A and 12B such as 13A to 13E explained. 10A and 10B show an embodiment of an LED 556 similar to previously known LEDs. The LED 556 includes an active area 558 , the five InGaN source layers 562 wherein GaN barrier layers 564 between the InGaN source layers 562 are arranged. The LED 556 also includes a base layer 560 , a first spacer layer 566 , a second spacer layer 568 , an electron-blocking layer 570 and an electrode layer 572 , In the LED 556 include the InGaN source layers 562 Layers of In _0.18 Ga _0.82 N, each having an average layer thickness of about 2.5 nm. The barrier stories 564 include layers of GaN which may have an average layer thickness of about 10 nm. The base layer 560 comprises a layer of doped GaN which has an average layer thickness of about 325 nm and which is n-type doped with silicon at a concentration of about 5e ¹⁸ cm ^-3 . The first spacer layer 566 may comprise undoped GaN having an average layer thickness of about 25 nm. The second spacer layer 568 may also comprise undoped GaN having an average layer thickness of about 25 nm. The electron barrier layer 570 may include p-doped AlGaN. The electrode layer 572 may comprise a layer of doped GaN, such an electrode layer may have an average layer thickness of about 125 nm and is p-type doped with magnesium at a concentration of about 5e ¹⁷ cm ^-3 . 10B is a simplified conduction band diagram similar to that of FIG 1B and shows the relative differences of the energy level of the conduction band 574 (in an energy band diagram) for the different materials in the different layers of the LED 556 from 10A , The vertical dashed lines in 10B are with the interfaces between the different layers in the LED 556 from 10A aligned.

As is known in the art, the 8x8 Kane model described, for example, in "kp Method for Strained Wurtzite Semiconductors" by SL Chuang and CS Chang, published by Phys. Rev. B 54, 2491 (1996), may be used to characterize the valence band structure for Group III nitride materials, such as GaN and InGaN. It is assumed here that the splitting into heavy, light and spin-off branches of the valence bands in the center of the Brilluoin zone is independent of the built-in electric field. Therefore, the valence subbands can be determined from the solution of the coupled Poisson and transport equations. The wave functions of electrons and holes can be assumed in the following form. u _n · Ψ _v · exp (k _n · r) u _{p, s} · _{v, s} · exp (k _p · r)

Here, u _n and u _{p, s are} respectively the Bloch amplitudes of electrons and holes corresponding to the center of the Brillouin zone, k _n and k _p are the in-plane quasimoment vectors, Ψ _v and Ψ _{v, s} are the Envelope functions, where the lower index "s" may denote heavy (heavy), light (light) or spin-off (so-called) holes. The one-dimensional Schrödinger equations for electron and hole envelope functions are:

Here, U _C ^eff and U _{V, s} ^{eff are} the effective potential for electrons and holes in the quantum well, E _v and E _{v, s} are electron and hole energy levels, and m _n "and m _p " are electron and hole effective masses in the epitaxial growth direction. By solving the Schrödinger equations listed above under appropriate constraints, the overlap integral between the electron and hole wave functions is then determined from the following.

As disclosed in the second edition of "Physics of Phonic Devices" by SL Chuang, published by Wiley, New Jersey, in 2009, the rate of radiative recombination of electrons and holes can be given by:

Here, B is the coefficient of radiative recombination, n is the electron concentration, p is the hole concentration, and F _n - F _p is the quasi-Fermi native separation. The electron and hole concentration and the quasi-Fermi level separation vary with position over the active area of an LED. The maximum rate of radiative recombination can be identified in any quantum well and considered to be the extreme rate of radiative recombination for the particular quantum well.

11A is a graph showing the calculated energy of the band edge of the conduction band 574 and the valence band 576 for the LED 550 from 10A and 10B with a disappearing applied current to the LED 556 as a function of the position (in nm) on the LED 556 starting at the surface of the base layer 560 opposite or opposite to the active area 558 , 11B is a graph similar to that of 11A , but with representation of the calculated energy of the band edge of the conduction band 574 and the valence band 576 for the LED 556 from 10A and 10B at an applied current density at the LED 556 of 125 A / cm ² . 11C Fig. 12 is a graph showing the calculated intensity as a function of wavelength for each of the five quantum well layers 562 the LED 556 at an applied current density at the LED 550 of 125 A / cm ² . QW1 is the leftmost quantum well layer 562 while QW5 is the rightmost quantum well layer 562 from the perspective of

10A and 10B is. 11D shows the calculated injection efficiency of the LED 556 as a function of the applied current density. As in 11D Shown is the LED 550 have an injection efficiency of about 75.6% at an applied current density of 125 A / cm ² . 11E shows the calculated internal quantum efficiency (IQE) of the LED 556 as a function of the applied current density. As in 11E Shown is the LED 556 have an internal quantum efficiency of about 45.2% at an applied current density of 125 A / cm ² . Like also in 11E can be shown, the internal quantum efficiency of the LED 556 from over 50% at an applied current density of about 20 A / cm ² to less than 40% at an applied current density of 250 A / cm ² drop. As discussed above, such a drop in IQE is referred to in the art as efficiency droop.

Table 1 shows the calculated wavefunction overlap and the extreme rate of radiative recombination for each of the five quantum well layers 562 in the LED 550 from 10A and 10B , Table 1 QW 1 QW2 QW3 QW4 QW5 Wavefunction overlap 0.328 0.326 0,325 0.341 0.362 extreme rate of radiative recombination 6,5e ²⁶ 3,3e ²⁶ _{3 , 3e} 26 6.8e ²⁶ 2,4e ²⁷

How out 11C and Table 1 above, the radiative recombinations are mainly from the last quantum layer 562 (closest to the p-doped side or anode), which is the quantum well # 5 (ie, QW5) in the LED 556 is.

Furthermore, shows how in 11E shown is the LED 556 an efficiency drop resulting, at least in part, from the piezoelectric polarization due to the use of InGaN source layers 562 and GaN barrier layers 564 as explained above.

Embodiments of the LEDs of the present disclosure which include an active region comprising at least one InGaN source layer and at least one InGaN barrier layer, such as the active region 106 the LED 100 , may include improved uniformity of the radiative recombinations that occur in the swelling layers and reduced efficiency degradation. A comparison of an embodiment of an LED of the present disclosure with the LED 550 is based 12A and 12B such as 13A to 13E presented below.

12A and 12B show another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active area 106 , the five InGaN source layers 1 14, wherein InGaN barrier layers 1 16 between the InGaN source layers 114 are arranged. The InGaN source layers 114 and the InGaN barrier layers 1 16 may be as above in connection with the semiconductor structure 100 based 1A and 1B has been described. The LED 600 also includes a base layer 112 , a first spacer layer 118 , a cap layer 120 and an InGaN electrode layer 104 , In the LED 600 include the InGaN source layers 114 Layers of In _0.18 Ga _0.82 N, each having an average layer thickness of about 2.5 nm. The barrier stories 116 comprise layers of In _0.08 Ga _0.92 N, each having an average layer thickness of about 10 nm. The base layer 112 comprises a layer of doped In _0.05 Ga _0.95 N, each having an average layer thickness of about 300 nm and n-type doped with silicon at a concentration of about 5e ¹⁸ cm ^-3 . The first spacer layer 118 may include undoped In _0.08 Ga _0.92 N which has an average layer thickness of about 25 nm. The cap layer 120 may also comprise undoped In _0.08 Ga _0.92 N which has an average layer thickness of about 25 nm. The electrode layer 104 may comprise a layer of doped In _0.05 Ga _0.95 N which has an average layer thickness of about 150 nm and which is p-type doped with magnesium at a concentration of about 5e ¹⁷ cm ^-3 . 12B is a simplified conduction band diagram illustrating the relative differences in the energy level of the conduction band 602 (in an energy band diagram) for the different materials in the different layers of the LED 600 from 12A ,

13A is a graph showing the calculated energy of the band edge of the conduction band 602 and the valence band 604 for the LED 600 from 12A and 12B with a disappearing applied current to the LED 600 as a function of the position (in nm) on the LED 600 starting at the surface of the base layer 112 opposite or opposite to the active area 106 , 13B is a graph similar to that of 13A , but with representation of the calculated energy of the band edge of the conduction band 602 and the valence band 604 for the LED 600 from 12A and 12B at an applied current density at the LED 600 of 125 A / cm ² . 13C Fig. 12 is a graph showing the calculated intensity as a function of wavelength for each of the five quantum well layers 108 the LED 600 with the applied current density at the LED 600 of 125 A / cm ² . QW1 is the leftmost quantum well layer 108 while QW5 is the rightmost quantum well layer 108 from the perspective of 12A and 12B is. 13D shows the calculated injection efficiency of the LED 600 as a function of the applied current density. As in 13D Shown is the LED 600 have an injection efficiency of about 87.8% at an applied current density of 125 A / cm ² and may have a carrier injection efficiency of at least about 80% over a range of current densities extending from about 20 A / cm ² to about 250 A / cm ² . 13E shows the calculated internal quantum efficiency (IQE) of the LED 600 as a function of the applied current density. As in 13E Shown is the LED 600 have an internal quantum efficiency of about 58.6% at an applied current density of 125 A / cm ² . Like also in 13E can be shown, the internal quantum efficiency of the LED 600 between about 55% and about 60% at an applied current density in a range extending from about 20 A / cm ² to 250 A / cm ² . This shows the LED 600 a very low efficiency drop and a considerably lower efficiency drop than the efficiency drop that the LED 500 shows (where the LED 500 does not correspond to the embodiments of the present disclosure).

Table 2 shows the calculated wavefunction overlap and the extreme rate of radiative recombination for each of the five quantum well layers 108 in the LED 600 from 12A and 12B , Table 2 QW 1 QW2 QW3 QW4 QW5 Wavefunction overlap 0,478 0.493 0.494 0.494 0.471 extreme rate of radiative recombination 7.8e ²⁶ 7.7e ²⁶ 7,9e ²⁶ 8,1e ²⁶ 8,3e ²⁶

How out 13C and Table 2 above, the radiative recombinations are over the quantum layers 508 in the LED 600 compared to the source layers 108 in the LED 500 even.

The LED 550 from 10A and 10B and the LED 600 from 12A and 12B were modeled using the SiLENSe software commercially available from STR Group, Inc.

is available. The software SiLENSe was also used to generate the graphs of 11A to 11E such as 13A to 13E and for the determination of the in tables 1 and 2 used data.

The LEDs, according to some embodiments of the present disclosure, may have an internal quantum efficiency of at least about 45% over a range of current density ranging from about 20 A / cm ² to about 250 A / cm ² , of at least about 50% over a range the current density extending from about 20 A / cm ² to about 250 A / cm ² , or even at least about 55% over a range of current density ranging from about 20 A / cm ² to about 250 A / cm ² extends. Furthermore, the LEDs may have at least substantially constant carrier injection efficiency over a range of current density ranging from about 20 A / cm ² to about 250 A / cm ² . In some embodiments, LEDs of the present disclosure may have a carrier injection efficiency of at least about 80% over a range of current densities ranging from about 20 A / cm ² to about 250 A / cm ² .

Non-limiting examples of methods used to fabricate semiconductor structures and light-emitting devices, such as LEDs, in the embodiments of the disclosure will be briefly described below 6C to 6D while examples of light emitting devices made by such methods are described 7 and 8th to be discribed.

As 6C The growth template may be shown 113 (as fabricated as described above) within an application chamber, and layers comprising group III nitride materials, commonly referred to as growth stacks 682 (please refer 6D ), epitaxially and sequentially on one or more seed layers 656 the growth template 113 to be raised. Note that notwithstanding that the seed layer is depicted as one or more islands of Group III nitride materials, in some embodiments, the seed layer has a continuous film over the backing substrate 658 may include.

6D shows a semiconductor structure 680 holding a growth template 113 includes, in turn, two seed layers 656 each comprising different layers of the semiconductor structure deposited thereon 100 from 1A and 1B exhibit. In particular, a GaN base layer 112 a semiconductor structure 100 epitaxially directly on each of the seed layer structures 656 grown, with an InGaN spacer layer 118 , an InGaN source layer 114 , an InGaN barrier layer 116 , an InGaN cap layer 120 , an electron-blocking layer 108 , a p-type bulk layer 110 and a p-type contact layer 104 successively epitaxially over the growth template 112 be applied.

The different layers of the semiconductor structure 680 that the growth pile 682 For example, using an MOCVD (Metal Organic Chemical Vapor Deposition) process and a MOCVD system may be applied within a single application chamber, that is, without the need for introduction or removal of the growth batch during the deposition process. The pressure inside the application chamber can be reduced to between about 50 mTorr and about 500 mTorr. The pressure within the reaction chamber may be during the application process during the application of the growth stack 682 enlarged and / or reduced and therefore adapted for the applied in layer specific layer. In a non-limiting example, the pressure within the reaction chamber during the application of the GaN base layer 112 , the spacer layer 118 , one or more source layers 114 / Barrier layers 116 , the cap layers 120 and the electron barrier layer 108 in a range between about 50 mTorr and about 500 mTorr, and may be equal to about 440 mTorr in some embodiments. The pressure inside the reaction chamber for the application of the p-type bulk layer 110 and the p-type contact layer 104 may be between about 50 mTorr and about 250 mTorr, and may be equal to about 100 mTorr in some embodiments.

The growth template 113 can be heated to a temperature between about 600 ° C and about 1000 ° C inside the application chamber. Organometallic precursor gases and other precursor gases (and optionally carrier and / or cleaning gases) may then flow through the deposition chamber and over the one or more seed layers 656 the growth template 113 to be brought. The organometallic precursor gases may react, decompose, or both react and decompose in a manner that results in epitaxial deposition of Group II nitride or Group III nitride layers, such as InGaN layers, for example. at the growth template 113 leads.

By way of non-limiting examples, trimethylindium (TMI) may be used as the organometallic precursor to the indium of InGaN, triethylgallium (TMG) may be used as the organometallic precursor to the gallium of InGaN, triethylaluminum (TMA) may be used as the organometallic precursor for the AlGaN and ammonia may be used as a precursor to the nitrogen of the group III nitride layers. SiH ₄ may be used as a precursor for introducing silicon into the InGaN when n-type doping of the group III nitride is desired, and may use Cp 2 Mg (bis (cyclopentadiene) magnesium) as a precursor for introducing magnesium into the InGaN the Group III nitride may be used when p-type type Group III doping is desired. It may be advantageous to adjust the ratio of the indium precursor (e.g., trimethylindium) to the gallium precursor (e.g., triethylgallium) resulting in the indium contained in the InGaN at a concentration close to a saturation point for indium in the InGaN at the application temperature. The percentage of indium incorporated in the InGaN can be controlled when the InGaN is epitaxially grown by controlling the growth temperature. Comparatively higher levels of indium are consumed at comparatively lower temperatures, while relatively lower levels of indium are consumed at relatively higher temperatures. In non-limiting examples, the InGaN source layers 108 be applied at temperatures in a range extending from about 600 ° C to about 950 ° C.

The deposition temperature of the various layers of the growth stack 100 can be increased and / or reduced during the application process and therefore adapted for the applied specific layer. In one non-limiting example, the deposition temperature may be during application of the GaN base layer 112 , the p-type bulk layer 110 and the p-type contact layer 104 in a range between about 600 ° to about 950 ° C and may be equal to about 900 ° C in some embodiments. The growth rate of the GaN base layer 112 , the p-type bulk layer 110 and the p-type contact layer 104 may range from about 1 nm / min to about 50 nm / min, while in some embodiments, the growth rate of the GaN base layer 112 , the p-type bulk layer 110 and the p-type contact layer 104 may be about 6 nm / min.

In additional non-limiting example embodiments, the deposition temperature may be during the deposition of the spacer layer 118 , one or more source layers 114 containing one or more barrier layers 116 , the cap layer 120 and the electron barrier layer 108 in a range between about 600 ° to about 950 ° C, and may be equal to about 750 ° C in some embodiments. The growth rate of the spacer layer 118 containing one or more source layers 114 containing one or more barrier layers 116 , the cap layer 120 and the electron barrier layer 118 may range from about 1 nm / min to about 30 nm / min, and in some embodiments may increase the growth rate of the spacer layer 118 , one or more source layers 114 / Barrier layers 116 , the cap layer 120 and the electron barrier layer 108 equal to about 1 nm / min.

In embodiments involving application of InGaN layers, the flow rate ratio of the precursor gases can be selected to produce high quality InGaN layers. The methods of forming the InGaN layers of the semiconductor structure 100 For example, gas selection may include selecting the gas ratio to produce one or more low defect density InGaN layers that are substantially free of stain relaxation and substantially free of surface pits.

By way of non-limiting examples, the flow ratio (%) of trimethylindium (TMI) to triethylgallium (TMG) may be defined as follows: Flow ratio (%) = flow rate (TMI) / flow rate (TMI + TEG) × 100

Such flow ratio can be increased and / or decreased during the deposition process and therefore adapted for the applied InGaN layer. In one non-limiting example, the flow ratio during the deposition of the p-type bulk layer 110 between about 50% to about 95 ° C and 95%, respectively, and may be about 85% in some embodiments. In further embodiments, the flow ratio during the deposition of the spacer layer 118 containing one or more barrier layers 116 and the cap layer 120 between about 1% to about 50%, and may be about 2% in some embodiments. In still other embodiments, the flow ratio may be during the deposition of the one or more quantum well layers 114 may range between about 1% to about 50%, and may be about 30% in some embodiments.

The growth template 113 can optionally be rotated within the application chamber during the application process. In a non-limiting example, the growth template may 113 are rotated within the application chamber during the deposition processes at a rotational speed of between about 50 rpm to about 1500 rpm and, in some embodiments, can be rotated at a rotational speed of about 450 rpm. The rotational speed may be increased and / or decreased during the deposition process and therefore adapted for the applied specific layer. In one non-limiting example, the rotational speed of the growth stencil may be during the application of the GaN base layer 112 , the spacer layer 118 , one or more source layers 114 containing one or more barrier layers 116 , the cap layers 120 and the electron barrier layer 108 in a range between about 50 rpm and about 1500 rpm, and in some embodiments may be at a rotational speed of about 440 rpm. The rotational speed of the growth template 113 during the application of the p-type bulk layer 110 and the p-type contact layer 104 may be in a range between about 50 rpm and about 1500 rpm, and in some embodiments may be at a rotational speed of about 1000 rpm.

In embodiments of the semiconductor structures of the present disclosure that include application of a Group III nitride, and particularly InGaN layers, the stress energy of the one or more InGaN layers that make up the growth stack 682 containing epitaxially over the growth template 113 which affect the efficiency of the light emitting devices fabricated from such semiconductor structures. In some embodiments, the total load energy that is within the growth stack 682 developed in connection with the efficiency as defined by the internal quantum efficiency (IQE) of the semiconductor structures of the present disclosure.

This means in detail that the strain energy stored within an n-th layer of InGaN is proportional to the average total thickness T _{n of} the n-th layer of InGaN and to Concentration of indium% In _n in the n-th layer of InGaN. Moreover, the total stress energy stored in the plurality of InGaN layers is the growth stack 682 proportional to the sum of the average total thickness T _n of each of the InGaN layers and to the concentration of indium% In _n in each of the InGaN layers, therefore, the total stress energy within the InGaN layers surrounding the growth stack 702 can be estimated using the following relationship. Total load energy (a.e) α Σ (% In _n × T _n )

Here, the average total thickness T _{n of} the n-th layer is expressed in nm, and the concentration of indium% In _n in the n-th InGaAN layer is expressed in atomic percent. For example, when an n-th layer of InGaN has an average total thickness T _n of 150 nm and an indium concentration% In _n of 2.0 at%, the strain energy within the n-th layer of InGaN can be equal to 300 a. E. (300 = 150 (2)).

9 shows a graph 900 to illustrate the relationship between IQE (a.e.) and the total load energy (a.E.) for the semiconductor structures of the present disclosure. The IQE of the semiconductor structures of the present disclosure may decrease to a value of the total load energy, referred to as the "critical load energy" of the semiconductor structure, as through the line 902 of the graph 900 is shown. The IQE of the semiconductor structures under the critical load energy (as shown by line 904 ) may be substantially larger than the IQE of the semiconductor structures above the critical load energy (as shown by line 906 ) be. The graph 900 For example, Figure 12 shows IQE values (indicated by rectangular marks) for a plurality of semiconductor structures of the present disclosure. In some embodiments, the IQE under the critical load energy may be about 500% greater than the IQE over the critical load energy. In further embodiments, the IQE may be about 250% greater than the IQE above the critical load energy under the critical load energy. In still other embodiments, the IQE may be about 100% greater than the IQE above the critical load energy under the critical load energy.

For the semiconductor structures of the present disclosure, the critical load energy 902 which is defined by the sum of the product of each layer thickness (in nm) and each layer indium content (in%), has a value of about 1800 or less, about 2800 or less, or even about 4500 or less.

In the present disclosure, the plurality of Group III nitride layers that comprise the growth stack 682 from 6D comprises, are applied so that the growth stack 682 is substantially fully loaded to the crystal lattice of the In _s Ga ₁ -s N seed layer 656 the growth template 113 to be coordinated. In such embodiments, when the growth stack 682 is substantially fully loaded, that is, substantially free of strain relaxation, the growth stacks inherit the lattice parameter of the In _s Ga ₁ -s N seed layer. In certain embodiments of the present disclosure, the In _s Ga ₁ -s N seed layer may have a growth plane lattice parameter greater than or equal to about 3.189 angstroms, and the growth stack may have a growth plane lattice parameter greater than or equal to about 3.189 angstroms. Therefore, in non-limiting examples, the semiconductor structures 100 . 200 . 300 . 400 and 500 may be formed to be composed of fully loaded materials and may have such a growth level grid parameter. In some embodiments, the GaN base layer becomes 112 above the In _s Ga _1-s N seed layer 656 is formed, grown relaxed when the GaN base layer 112 on the In _s Ga _1-s N seed layer 656 grown up lattice-matched.

In further embodiments, the plurality of group III nitride layers may comprise the growth stack 682 from 6D comprises, are applied so that the growth stack 682 partially relaxed, that is, the lattice parameter of the growth stack 682 differs from the underlying In _s Ga _1-s N seed layer. In such embodiments, the percent stress relaxation (R) may be defined as follows.

Here, a is the average growth level lattice parameter for the growth stack 682 , a _s is the average growth level lattice parameter of the In _s Ga _{1 -s} N seed, and a _l is the equilibrium-based (or natural state) average growth level lattice parameter for the growth stack. In some embodiments, the growth stack may 682 For example, having a percent stress relaxation (R) of less than about 0.5%, in other embodiments, the growth stack 682 have a percent load relaxation (R) of less than about 10%, and in still other embodiments, the growth stack 682 have a percent stress relaxation (R) of less than about 50%.

After epitaxially depositing the various layers of semiconductor structures comprising Group I nitride materials, further processing may be performed to complete fabrication of the light emitting devices, such as the LEDs, from the semiconductor structures. For example, electrode contacts may be formed on the layers of Group III nitride materials using processes known in the art, and briefly discussed below 7 and 8th to be discribed.

An example of a light-emitting device 700 , such as an LED, made of the semiconductor structure 100 is manufactured in is 7 shown. Although the present description describes embodiments for fabricating light-emitting devices from the semiconductor structure 100 It should be appreciated that such fabrication processes also apply to semiconductor structures 200 . 300 . 400 and 500 Application can be found.

In detail, this means that a section of the semiconductor structure 100 by exposing a portion of the GaN base layer 112 can be removed. The removal of a selected portion of the semiconductor structure 100 can be applied to the exposed surface of the p-contact layer by applying a photosensitive chemical 100 the semiconductor structure 100 (not shown). Upon exposure to electromagnetic radiation through a patterned transparent plate and subsequent development, the photosensitive layer may be utilized as a "masking layer" to selectively remove the group III nitride layers over the GaN base layer 112 to enable. The removal of selected portions of the Group III nitride layers over the GaN base layer 112 may include an etching process, such as wet chemical etching and / or plasma-based dry etching (eg, reactive ion etching, inductively coupled plasma etching).

A first electrode contact 702 may be over a portion of the exposed GaN base layer 112 be formed. The first electrode contact 702 may include one or more metals, which may include titanium, aluminum, nickel, gold and one or more alloys thereof. A second electrode contact 704 can over a section of the p-contact layer 104 are formed, the second electrode contact layer 704 may include one or more metal layers, which may include nickel, gold, platinum, silver, and one or more alloys thereof. In the formation of the first electrode contact 702 and the second electrode contact 704 may be a current through the light-emitting device 700 flow to generate electromagnetic radiation, for example in the form of visible light. Note that the light-emitting device 700 commonly referred to in the art as a "lateral device" because at least a portion of the current path between the first electrode contact 702 and the second electrode contact 704 includes a lateral path.

Another example of a light emitting device 800 , such as an LED, made of the semiconductor structure 100 is manufactured in is 8th shown. Although the following description describes embodiments for fabricating light-emitting devices from the semiconductor structure 100 It should be appreciated that such fabrication processes also apply to the semiconductor structure 200 . 300 . 400 and 500 Application can be found.

In detail, this means that a section or the entirety of the growth template 113 from the semiconductor structure 100 can be removed to expose either the In _s Ga _{1 -s} N layer 656 or, in one embodiment, exposing the GaN base layer 112 to enable. Removing a section or the entirety of the growth template 113 may include one or more removal processes, including wet etching, dry etching, chemical mechanical polishing, laser ablation and laser ablation. When removing a section or the whole of the growth template 113 may be a first electrode contact 802 for the GaN base layer 112 as described above. Subsequently, a second electrode contact 804 at a portion of the p-contact layer 104 are applied, whereby the light-emitting device 800 is formed. In the Formation of the first electrode contact 802 and the second electrode contact 804 can conduct electricity through the light-emitting device 800 flow to generate electromagnetic radiation, for example in the form of visible light. Note that the light-emitting device 800 is commonly referred to in the art as a "vertical device" because the current path between the first electrode layer 802 and the second electrode layer 804 comprises a substantially vertical path.

In addition to the manufacturing methods and processes described above for the manufacture of non-limiting exemplary light emitting devices 700 and 800 It should be appreciated that additional methods and processes known in the art may also be used, such as surface roughening to enhance light extraction, bonding to metal substrates to improve heat dissipation, a process known in the art as "flip chip bonding" is known, as well as other known manufacturing methods.

Light-emitting devices, such as LEDs, according to embodiments of the present disclosure may be fabricated and used in any type of light-emitting device incorporating one or more LEDs. In particular, embodiments of LEDs of the present disclosure may be suitable for use in applications that utilize LEDs that operate at comparatively high power and that require comparatively high luminance. For example, LEDs of the present disclosure may be suitable for use in LED lamps and LED based light bulbs that may be used to illuminate buildings, illuminate roads, illuminate motor vehicles, and the like.

Additional embodiments of the present disclosure include light emitting devices that include one or more of the LEDs described herein, such as the light emitting device 700 from 7 and the light-emitting device 800 from 8th , By way of non-limiting examples, the light emitting devices may be as described, for example, in U.S. Pat. other members U.S. Patent No. 6,600,175 is disclosed, the disclosure of which is hereby incorporated by reference in its entirety, but may also include one or more LEDs as described herein.

14 shows an exemplary embodiment of a lighting device 900 of the present disclosure, which includes a light-emitting device, such as the device 700 . 800 based on 7 and 8th has been described. As in 14 is shown, the lighting device 900 a container 902 at least a portion of which is at least substantially transparent to electromagnetic radiation in the visible region of the electromagnetic radiation spectrum. The container 902 For example, it may comprise an amorphous or crystalline ceramic metal (eg, a glass) or a polymeric material. The LED 800 is inside the container 902 arranged and can be attached to a support structure 904 (For example, a printed circuit board or other substrate) inside the container 902 be mounted. The lighting device 900 further includes a first electrical contact structure 906 and a second electrical contact structure 908 , The first electrical contact structure 906 may be in electrical connection with one of the electrode contacts of the LED, such as the first electrode contact 802 ( 8th ), and it may be the second electrical contact structure 908 be in electrical connection with the other electrode contact of the LED, such as the second electrode contact 804 ( 8th ). In a non-limiting example, the first electrical contact structure 906 in electrical connection with the first electrode contact 804 through the support structure 904 be, and it can be a wire 910 for electrically coupling the second electrical contact structure 904 with the second electrode contact 804 be used. This allows a voltage between the first electrical contact structure 906 and the second electrical contact structure 908 the lighting device 900 for providing a voltage and a corresponding current between the first and second electrode contacts 802 . 804 be applied to the LED causing the LED to emit radiation.

The lighting device 900 Optionally, it may further include a fluorescent or phosphorescent material containing electromagnetic radiation (eg, visible light) upon stimulation or excitation by absorbing electromagnetic radiation from the one or more LEDs 800 inside the container 902 is emitted, self-emitted. An inner surface 912 of the container 902 For example, it may be at least partially coated with such a fluorescent or phosphorescent material. The one or more LEDs 800 may emit electromagnetic radiation at one or more specific wavelengths, and the fluorescent or phosphorescent material may include a mixture of different materials including radiation of different visible wavelengths, such that the lighting device 900 white light to the outside of the container 902 emitted. Various types of fluorescent and phosphorescent materials are known in the art and may be employed in embodiments of light emitting devices of the present disclosure. Some of these materials are, for example, in the aforementioned U.S. Patent No. 6,600,175 disclosed.

Additional non-limiting examples of embodiments of the disclosure are listed below.

Embodiment 1: A semiconductor structure comprising: a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 Angstroms; an active region disposed over the base layer, the active region comprising a plurality of layers of InGaN, the plurality of layers of InGaN having at least one In _w Ga _1-w N source layer of 0.10 ≤ w ≤ 0.40 and includes at least one In _b Ga _1-b N barrier layer with 0.01 ≤ b ≤ 0.10; an electron barrier layer disposed on a side of the active region opposite to the GaN base layer; a p-type bulk layer disposed on the electron-blocking layer, wherein the p-type bulk layer comprises In _p Ga _{1 -p} N at 0.00≤p≤0.08; and a p-type contact layer disposed on the p-type bulk layer, wherein the p-type contact layer comprises In _c Ga _{1 -c} N at 0.00 ≦ c ≦ 0.10.

Embodiment 2: The semiconductor structure of Embodiment 1, wherein the base layer further comprises a growth template, wherein the growth template comprises: a support substrate; and an In _s Ga ₁ -s N seed layer disposed on the support substrate, wherein a growth plane of the In _s Ga ₁ -s N seed layer is a polar plane having a growth plane lattice parameter of greater than or equal to about 3.189 angstroms with 0.02 ≤ s ≤ 0.05, and wherein the GaN base layer is substantially lattice-matched to the growth plane of the In _s Ga ₁ -s N seed layer.

Embodiment 3: A semiconductor structure according to Embodiment 3, further comprising an In _sp Ga _{1 -sp} N spacer layer disposed on the In _s Ga ₁ -s N seed layer on a side thereof opposite to the GaN base layer with 0, 01 ≤ sp ≤ 0.10 is arranged.

Embodiment 4: The semiconductor structure according to any one of Embodiments 1 to 3, further comprising an In _cp Ga _1-cp N cap layer of 0.01 ≦ cp ≦ 0.10 disposed between the active region and the electron-blocking layer.

Embodiment 5: A semiconductor structure according to any one of Embodiments 1 to 4, wherein the electron _- blocking layer comprises In _e Ga _{1 -e} N where 0.01≤e≤0.02.

Embodiment 6: A semiconductor structure according to any one of Embodiments 1 to 5, wherein the electron-blocking layer is formed at least substantially of GaN.

Embodiment 7: A semiconductor structure according to any one of Embodiments 1 to 6, wherein the electron _- blocking layer is formed at least substantially of Al _e Ga _{1 -e} N where 0.1≤e≤0.2.

Embodiment 8: A semiconductor structure according to Embodiment 7, wherein the electron-blocking layer has a superlattice structure comprising alternating layers of GaN and Al _e Ga _{1 -e} N of 0.1≤e≤0.2.

Embodiment 9: A semiconductor structure according to any one of Embodiments 1 to 9, further comprising an electron trapping layer disposed between the GaN base layer and the active region, wherein the electron trapping layer is Al _st Ga _1-st N where 0.01 ≦ st ≦ 0.20 includes.

Embodiment 10: A semiconductor structure according to Embodiment 9, wherein the electron trapping layer has a superlattice structure comprising alternating layers of GaN and Al _st Ga _1-st N of 0.01≤st≤0.2.

Embodiment 11: The semiconductor structure according to any one of Embodiments 1 to 10, further comprising a stress relaxation layer disposed between the GaN base layer and the active region, the stress relaxation layer having a superlattice structure comprising alternating layers of In _sra Ga _sra N of 0.01 ≤ sra ≤ 0.10 and In _srb Ga - 1 _srb N with 0.01 ≤ srb ≤ 0.10, and wherein sra is larger than srb.

Embodiment 12: The semiconductor structure according to any one of Embodiments 1 to 11, wherein the active region further comprises an additional barrier layer comprising GaN interposed between the at least one source layer and the at least one barrier layer.

Embodiment 13: The semiconductor structure according to any one of Embodiments 1 to 12, wherein a critical load energy of the semiconductor structure is about 4500 or less.

Embodiment 14: The semiconductor structure according to any one of Embodiments 1 to 13, wherein the GaN base layer, the active region, the electron blocking layer, the p-type bulk layer, and the p-type contact layer define a growth stack having a percent stress relaxation of less than 1%. having.

Embodiment 15: A semiconductor structure according to any one of Embodiments 1 to 14, wherein the p-type contact layer is formed at least substantially of GaN.

Embodiment 16: The semiconductor structure according to any one of Embodiments 1 to 15, further comprising a first electrode contact over at least a portion of the GaN base layer and a second electrode contact over at least a portion of the p-type contact layer.

Embodiment 17: A light emitting device comprising: a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 angstroms; an active region disposed over the base layer, the active region comprising a plurality of layers of InGaN, the plurality of layers of InGaN including at least one swelling layer and at least one barrier layer; an electron barrier layer disposed over the active region; a p-type In _p Ga _{1 -p} N bulk layer disposed over the electron-blocking layer; and a p-type In _c Ga _{1 -c} N contact layer disposed over the p-type In _p Ga _{1 -p} N bulk layer, wherein a critical load energy of the light-emitting device is about 4500 or less.

Wherein the at least one well layer In _w Ga _1-w N 0.10 ≤ w ≤ comprises light emitting device according to Embodiment 17, 0.40: Embodiment eighteenth

Embodiment 19: A light-emitting device according to embodiment 17 or 18, wherein the at least one barrier layer comprises In _b Ga _1-b N with 0.01 ≤ b ≤ 0.10.

Embodiment 20: A light-emitting device according to any one of Embodiments 17 to 19, wherein the electron-blocking layer is formed at least substantially of GaN.

Embodiment 21: The light emitting device according to any one of Embodiments 17 to 20, wherein 0.00≤p≤0.08 in the p-type In _p Ga _{1 -p} N bulk layer.

Embodiment 22: A light-emitting device according to any one of Embodiments 17 to 21, wherein 0.01≤c≤0.10 in the p-type In _c Ga _1-c N contact layer.

Embodiment 23: A semiconductor structure according to any one of Embodiments 17 to 22, wherein the p-type In _c Ga _{1 -c} N contact layer is formed substantially of GaN.

Embodiment 24: A light-emitting device according to any one of Embodiments 17 to 23, further comprising a first electrode contact over at least a portion of the GaN base layer and a second electrode contact over at least a portion of the p-type In _c Ga _{1 -c} N contact layer ,

Embodiment 25: A semiconductor structure according to any of embodiments 17 to 24, wherein the GaN base layer, the active region, the electron blocking layer, the p-type bulk layer, and the p-type contact layer define a growth stack having a percent stress relaxation of less than 1%. having.

Embodiment 26: A method of forming a semiconductor structure, comprising: providing a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 Angstroms, growing a plurality of layers of InGaN to form an active region over the base layer, growing the plurality of layers of InGaN, comprising: growing at least one source layer comprising In _w Ga _1-w N at 0.10 ≤ w ≤ 0.40, and growing at least one barrier layer over the at least one source layer, the at least one barrier layer being in _b Ga _1-b N is 0.01 ≤ b ≤ 0.10; Growing an electron barrier over the Active area; Growing a p-type In _p Ga _{1 -p} N bulk layer over the electron-blocking layer with 0.00 ≦ p ≦ 0.08; and growing a p-type In _c Ga _{1 -c} N contact layer over the p-type In _p Ga _{1 -p} N bulk layer with 0.00 ≤ c ≤ 0.10.

Embodiment 27: The method of embodiment 26, wherein forming the base layer further comprises forming a growth template, wherein forming the growth template comprises: providing a backing substrate; and bonding an In _s Ga ₁ -s N seed layer to the support substrate, wherein a growth plane of the In _s Ga ₁ -s N seed layer is a polar plane having a growth plane lattice parameter of greater than or equal to about 3.189 angstroms and where 0.02 ≤ s ≤ 0.05 in the In _s Ga ₁ -s N seed layer applies.

Embodiment 28: The method of Embodiment 27, further comprising growing an In _sp Ga _{1 -sp} N spacer layer over the In _s Ga ₁ -s N seed layer on a side thereof opposite to the GaN base layer, respectively 0.01 ≦ sp ≦ 0.10 in the In _sp Ga _1-sp N spacer layer.

Embodiment 29: The method of any one of Embodiments 26 to 28, further comprising growing an In _cp Ga _{1 -cp} N cap layer interposed between the active region and the electron barrier layer, wherein 0.01 ≤ cp ≤ 0.10 in FIG In _cp Ga _1-cp N capping layer applies.

Embodiment 30: The method of any one of Embodiments 26 to 29, wherein the growing of the electron _- blocking layer comprises growing the electron _- blocking layer to be at least substantially formed of In _e Ga _{1 -e} N where 0.00 ≤ e ≤ 0.02.

Embodiment 31: The method of any one of Embodiments 26 to 30, wherein growing the electron barrier layer includes growing the electron barrier layer to be at least substantially GaN.

Embodiment 32: A method according to any one of Embodiments 26 to 31, wherein growing the electron barrier layer comprises growing the electron barrier layer to be at least substantially formed of Al _e Ga _{1 -e} N where 0.1≤e≤0.2.

Embodiment 33: The method of any one of Embodiments 26 to 29, wherein growing the electron barrier layer includes growing the electron barrier layer to have a superlattice structure comprising alternating layers of GaN and Al _e Ga _{1 -e} N where 0.1≤e≤ 0.2 includes.

Embodiment 34: The method of any one of embodiments 26 to 33, further comprising growing an electron-trapping layer disposed between the GaN base layer and the active region, wherein the electron-trapping layer is at least substantially Al _st Ga _1-st N 0.01 ≦ st ≦ 0.20 is formed.

Embodiment 35: The method of any one of embodiments 26 to 34, further comprising growing a stress relaxation layer disposed between the GaN base layer and the active region, wherein the stress relaxation layer comprises a superlattice structure comprising alternating layers of In _sra Ga _{1 -sra} N with 0.01 ≤ sra ≤ 0.10 and In _srb includes Ga _1-srb N with 0.01 ≤ srb ≤ 0.10, and wherein sra is greater than srb.

Embodiment 36: The method of any one of embodiments 26 to 35, wherein forming the active region further comprises growing one or more GaN-comprising additive barrier layers disposed between the at least one source layer and the at least one barrier layer.

Embodiment 37: The method of any of embodiments 26 to 36, wherein the GaN base layer, the active region, the electron barrier layer, the p-type bulk layer, and the p-type contact layer together define a growth stack having a percent stress relaxation of less than one % having.

Embodiment 38: The method of embodiment 37, further comprising forming the growth stack to have a critical load energy of about 2800 or less.

Embodiment 39: The method according to one of the embodiments 26 to 38, wherein the growth of the p-type contact layer comprises growing the p-type contact layer such that it is at least substantially formed of GaN.

Embodiment 40: The method of embodiment 37 or 38, further comprising growing the growth pad in a single chemical vapor deposition system at pressures of between about 50 and about 500 mTorr.

Embodiment 41: The method of any one of embodiments 26 to 40, further comprising growing the p-type In _p Ga _{1 -p} N bulk layer in a chamber during the flow of trimethylindium (TMI) and triethylgallium (TMG) through the chamber wherein a flow ratio (%) of the flow rate of trimethylindium (TMI) to the flow rate of triethylgallium (TMG) is between about 50% and about 95%.

The exemplary embodiments of the above disclosure do not limit the scope of the invention, as these embodiments are mere examples of embodiments of the invention, which is defined by the scope of the appended claims and the equivalent legal equivalents thereof. Any equivalent embodiments are intended to be within the scope of the present invention. Various modifications of the disclosure in addition to those shown and described herein, such as alternative useful combinations of the elements described, will be apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims (15)

A semiconductor structure comprising: a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 Angstroms; an active region disposed over the base layer, the active region comprising a plurality of layers of InGaN, the plurality of layers of InGaN having at least one In _w Ga _1-w N source layer of 0.10 ≤ w ≤ 0.40 and includes at least one In _b Ga _1-b N barrier layer with 0.01 ≤ b ≤ 0.10; an electron barrier layer disposed on a side of the active region opposite to the GaN base layer; a p-type bulk layer disposed on the electron-blocking layer, wherein the p-type bulk layer comprises In _p Ga _{1 -p} N at 0.00≤p≤0.08; and a p-type contact layer disposed on the p-type bulk layer, wherein the p-type contact layer comprises In _c Ga _{1 -c} N at 0.00 ≦ c ≦ 0.10. The semiconductor structure of claim 1, wherein the base layer further comprises a growth template, the growth template comprising: a support substrate; and an In _s Ga ₁ -s N seed layer disposed on the support substrate, wherein a growth plane of the In _s Ga ₁ -s N seed layer is a polar plane having a growth plane lattice parameter of greater than or equal to about 3.189 angstroms with 0.02 ≤ s ≤ 0.05, and wherein the GaN base layer is substantially lattice-matched to the growth plane of the In _s Ga ₁ -s N seed layer. The semiconductor structure of claim 1, wherein the electron-blocking layer is formed at least substantially of GaN. The semiconductor structure according to claim 1, further comprising an electron trapping layer disposed between the GaN base layer and the active region, wherein the electron trapping layer comprises Al _e Ga ₁ -e N where 0.01 ≦ St ≦ 0.20. The semiconductor structure of claim 1, further comprising a stress relaxation layer disposed between the GaN base layer and the active region, the stress relaxation layer having a superlattice structure comprising alternating layers of In _sra Ga _{1 -sra} N where 0.01 ≤ sra ≤ 0, 10 and In _srb includes Ga _1-srb N with 0.01 ≤ srb ≤ 0.10, and wherein sra is larger than srb. The semiconductor structure of claim 1, wherein the active region further comprises an additional barrier layer comprising GaN disposed between the at least one source layer and the at least one barrier layer. The semiconductor structure of claim 1, wherein a critical load energy of the semiconductor structure is defined by the sum of the product of each layer thickness (in nm) and each layer indium content (in%) and equal to or less than 4500. The semiconductor structure of claim 1, wherein the p-type contact layer is formed at least substantially of GaN. A method of forming a semiconductor structure, comprising: providing a GaN base layer having a polar growth plane with a growth plane lattice parameter greater than or equal to about 3.189 Angstroms, growing a plurality of layers of InGaN to form an active region over the base layer, growing the plurality of layers InGaN, comprising: growing at least one source layer comprising In _w Ga _1-w N by 0.10 ≤ w ≤ 0.40, and growing at least one barrier layer over the at least one source layer, wherein the at least one barrier layer is In _b Ga _{1- b} includes N with 0.01 ≤ b ≤ 0.10; Growing an electron-blocking layer over the active region; Growing a p-type In _p Ga _{1 -p} N bulk layer over the electron-blocking layer with 0.00 ≦ p ≦ 0.08; and growing a p-type In _c Ga _{1 -c} N contact layer over the p-type In _p Ga _{1 -p} N bulk layer with 0.00 ≤ c ≤ 0.10. The method of claim 9, wherein forming the base layer further comprises forming a growth template, wherein forming the growth template comprises: providing a support substrate; and bonding an In _s Ga ₁ -s N seed layer to the support substrate, wherein a growth plane of the In _s Ga ₁ -s N seed layer comprises a polar plane having a growth plane lattice parameter greater than or equal to about 3.189 Angstroms and having 0.02 ≤ s ≤ 0 , 05 is in the In _s Ga _1-s N seed layer. The method of claim 9, wherein growing the electron-blocking layer comprises growing the electron-blocking layer such that it is at least substantially formed of GaN. The method of claim 9, further comprising growing an electron-trapping layer disposed between the GaN base layer and the active region, wherein the electron-trapping layer is formed at least substantially of Al _st Ga _1-st N where 0.01 ≤ st ≤ 0.20 is. The method of claim 9, further comprising growing a stress relaxation layer disposed between the GaN base layer and the active region, the stress relaxation layer having a superlattice structure comprising alternating layers of In _sra Ga _sra N where 0.01 ≤ sra ≤ 0, 10 and In _srb Ga - 1 _srb N with 0.01 ≤ srb ≤ 0.10, and where sra is greater than srb. The method of claim 9, further comprising forming the semiconductor structure to have a critical strain energy defined by the sum of the product of each layer thickness (in nm) and each layer indium content (in%) and equal to or less than 2800. The method of claim 9, wherein growing the p-type contact layer comprises growing the p-type contact layer such that it is at least substantially formed of GaN.

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