DE10331528A1 - DRAM semiconductor memory cell and method for its production - Google Patents

Abstract

The invention relates to a DRAM semiconductor memory cell and to a method for the production thereof, wherein a trench capacitor (160) with a trench (ET), a capacitor dielectric (161) and a trench fill layer (162) is formed in a substrate (100). For the realization of a selection transistor (AT), a nanoelement (NE), on whose side walls a gate dielectric (GD) is formed, is located on the surface of the trench filling layer (162). In the central region of the nanoelement (NE) is for controlling the selection transistor (AT) a control layer (G) on the gate dielectric (GD), wherein an upper portion of the nano-element (NE) via a connection layer (S) is electrically connected. In this way, one obtains a surface-optimized and highly integrated DRAM semiconductor memory cell with a simplified process flow.

Description

The The present invention relates to a DRAM semiconductor memory cell and a process for their preparation and in particular to a surface-optimized DRAM semiconductor memory cell with trench capacitor and an associated manufacturing method.

DRAM semiconductor memory cell be especially for the realization of dynamic storage or so-called DRAMs (Dynamic Random Access Memory).

1 shows a conventional DRAM semiconductor memory cell with trench capacitor, as for example from the document US 5,945,704 is known. Such a DRAM semiconductor memory cell essentially consists of a trench capacitor 160 that in a substrate 100 is trained. For example, the substrate is lightly doped with p-type dopants such as boron (B). A trench is usually made with a thin dielectric insulation layer 161 occupied and with polysilicon 162 filled with, for example, arsenic (As) or phosphorus (P) strongly n ⁺ -doped. A buried plate doped with, for example, arsenic (As) 163 is located in the substrate 100 at a lower portion of the trench. Usually, the arsenic (As) or the dopant from a dopant source such as an arsenic silicate glass ASG, which is formed on the side walls of the trench, in the silicon substrate 100 diffused. The polysilicon 162 and the buried plate 163 serve as electrodes of the capacitor, wherein a dielectric layer or a capacitor dielectric 161 the electrodes of the capacitor separates.

The DRAM semiconductor memory cell according to 1 moreover has a selection transistor AT implemented as a field-effect transistor. The transistor AT has a gate G formed on a gate dielectric GD and diffusion regions such as a source region S and a drain region D. The diffusion regions spaced apart by a channel CH are usually formed by implantation of dopants such as phosphorus (P). , educated. A contact diffusion region or buried strap BS in this case connects the trench capacitor 160 with the transistor AT or with its drainage area D.

An isolation collar C is formed at an upper portion of the trench. The insulation collar C prevents leakage current through a vertical parasitic transistor from the contact diffusion region BS to the buried plate 163 , Such a leakage current is undesirable, particularly in memory circuits, since it reduces the charge retention time or retention time of a semiconductor memory cell.

According to 1 The conventional trench capacitor semiconductor memory cell further has a buried well 170 , wherein the peak concentration of the dopants in the buried n-well is approximately at the lower end of the insulating collar C. The buried tub or layer 170 essentially serves to connect the buried plates 163 of a plurality of adjacent DRAM semiconductor memory cells and trench capacitors, respectively 160 in the semiconductor substrate 100 ,

Activation of the selection transistor AT by applying a suitable voltage to the gate G essentially allows access to the trench capacitor 160 , where usually the gate 112 is connected to a word line WL and the source diffusion region S is connected to a bit line BL in the DRAM array. The bit line BL is hereby from the substrate 100 separated by a dielectric insulating layer I and electrically connected via a contact K with the source region S.

Furthermore, to isolate a respective semiconductor memory cell with associated trench capacitor from adjacent cells, a shallow trench isolation STI (Shallow Trench Isolation) is applied to the surface of the semiconductor substrate 100 educated. According to 1 For example, the word line WL may be formed above the trench and insulated by the shallow trench isolation STI, thereby obtaining a so-called folded bit line architecture.

2 shows a simplified equivalent circuit diagram of the DRAM semiconductor memory cell according to 1 , wherein like reference numerals denote like elements and a repeated description is omitted below.

However, this conventional DRAM semiconductor memory cell has a variety of disadvantages. On the one hand, the process steps and materials used for the trench capacitor require an extremely high temperature stability, since the trench capacitor must be formed before the shallow trench isolation STI, which in turn is realized by a high-temperature process. The use of improved new materials in the trench capacitor, such as the dielectric or the electrode materials, is therefore very limited or not possible. Furthermore, in particular, the process for producing the isolation collar or Collars is a very complicated manufacturing process, since the insulation collar must be made rather thick, ie about 30 nanometers inside the trenches, which becomes increasingly small have smaller diameter. However, the increasingly smaller diameters limit trenching during, for example, a reactive dry etch process. The additional insulation collar consequently reduces the trench diameter to very small openings, which in turn results in very high ohmic series resistances between the trench capacitor and the selection transistor or the contact diffusion region BS.

Of the The invention is therefore based on the object of a DRAM semiconductor memory cell and an associated To provide a manufacturing process, which in simple production enables further integration and area optimization.

According to the invention this Task with respect to the DRAM semiconductor memory cell by the features of claim 1 and in terms of the method through the measures of claim 9 solved.

Especially by the use of a trench formed in a substrate with one to the substrate surface reaching capacitor dielectric and an electrically conductive trench filling, which fills the trench up to the substrate surface, a first insulating layer, at the substrate surface is formed and an opening to trench filling having a nanoelement in the opening on the trench filling layer is educated and over the first insulating layer protrudes, one on the protruding sidewalls of the nanoelement formed gate dielectric, one on the gate dielectric formed control layer and an electrically conductive connection layer to connect An upper area of the nanoelement may have an available building block area substantially be better utilized, resulting in increased integration densities.

Especially Now, however, shallow trench isolations do not become insulated required by adjacent DRAM semiconductor memory cells, wherein Furthermore, the elaborate Process for the production of the insulation collar deleted. Next the area optimization This results in improved trench capacities and thus charge retention times in simplified manufacturing processes.

Preferably the nanoelement has a single crystal nanowire, resulting in realize a selection transistor very simple and space-saving leaves.

Between the nanoelement and the trench filling layer is preferably a nanoelement seed layer consisting of gold or a silicable one Material formed, which gives excellent connection resistance and Conductive properties self-adjusting receives.

Regarding of the method is preferably first a trench in a substrate formed, which at least a first insulating layer on its surface subsequently becomes a capacitor dielectric at the trench surface as well an electrically conductive trench filling layer on the surface of the Kondensatordieletrikums formed to fill the trench and then that Nanoelement on the surface the trench filling layer designed so that it over the first insulating layer protrudes. For the realization of the selection transistor By means of the nanoelement, a gate dielectric is then applied the over the first insulating layer protruding side walls of the nanoelement and a about that lying control layer at least in the middle region of the nanoelement designed and for the realization of a connection a connection layer formed in an upper region of the nanoelement. In this way can first novel materials in a temperature-saving process Be used, and above In addition, in particular, the process for producing the trench capacitor essential is simplified.

Preferably For example, a control layer trench is created using a second mask layer to the surface the first insulating layer for exposing a middle and upper Formed area of the nanoelement, which makes it particularly easy a matrix structure for receives respective word and bit lines for control.

Especially the connection layer can in this case using a so-called Damascene method using a third mask layer and it trained spacer for the realization of a required structural fineness and quality realized become.

In the further claims Further advantageous embodiments of the invention are characterized.

The Invention will now be described with reference to an embodiment with reference closer to the drawing described.

It demonstrate:

1 a simplified sectional view of a conventional DRAM semiconductor memory cell;

2 an equivalent circuit of the DRAM half Ladder memory cell according to 1 ; and

3A to 3K simplified sectional views and plan views to illustrate essential process steps in the manufacture of a DRAM semiconductor memory cell according to the invention.

3A to 3K show simplified sectional views and plan views to illustrate essential process steps in the manufacture of a DRAM semiconductor memory cell according to the invention, wherein like reference numerals denote the same or corresponding layers or elements as in 1 and 2 denote and a repeated description is omitted below.

According to 3A is on a substrate 100 , which is preferably a (eg p-) doped semiconductor substrate (silicon substrate), initially a first insulating layer I1 formed on the surface over the entire surface. Preferably, a pad oxide having a thickness of 1 to 10 nm is deposited, whereby not only an etch stop layer is realized, but also mechanical stresses can be advantageously collected and compensated during a subsequent trench etching process. Further, a second insulating layer I2 may be formed on the surface of the first insulating layer I1, preferably depositing a pad nitride layer having a thickness of 50 to 200 nm. Finally, a first mask layer M1 is formed on this first and / or second insulating layer I1, I2, which is patterned to realize the trench T (trench) to be formed. Preferably, a hard mask layer is used, which is patterned by means of conventional photolithographic methods. Subsequently, the trench etching processes customary in DRAM processes take place, the description of which is omitted below.

Although in the present embodiment, preferably a semiconductor material and in particular silicon as a substrate 100 Similarly, other conductive or non-conductive substrates may be used as well.

According to 3B For example, in a subsequent step, the trench T can be widened into an enlarged trench ET, wherein, for example, the trench diameter is widened or enlarged underneath the first insulating layer I1, resulting in an enlarged trench surface and thus an increased capacitance of the trench capacitor to be produced. Although a trench is usually understood to be an elongated depression, in DRAM semiconductor memory cells under trenches, in general, circular, oval or rectangular depressions or holes are understood which extend deeply into the substrate 100 extend.

Either the trench etching as well as the extension of the trench is using the trench mask or first mask M1 performed. About that can out Further methods for surface enlargement of the Trench T and the extended trench ET are performed, such as so-called HSG methods (Hemispherical Grains), wherein a roughening or formation of grains on the trench surface a further significant surface enlargement and thus realized capacity increase becomes.

Subsequently, according to 3B For example, after removing the first mask layer M1, a capacitor dielectric 161 formed at least at the trench surface, wherein preferably by means of a deposition Si ₃ N ₄ and / or SiO ₂ layer or dielectric layers with high dielectric constant such as Al2O3 or HfO2 or ZrO2 over the entire surface, ie also on the side walls of the first and second insulating layer I1 , I2 and on the surface of the second insulating layer I2 the capacitor dielectric 161 is deposited. The following is an electrically conductive Grabenfüllschicht 162 on the surface of the capacitor dielectric 161 formed to fill the trench T and the extended trench ET. In this case, it is preferable to use a highly doped semiconductor material such as, for example, n ⁺ -doped polysilicon and / or a metallic material as a trench fill layer 162 deposited and by a planarization method such as a CMP (Chemical Mechanical Polishing) method to a level of the capacitor dielectric formed on the surface of the second insulating layer I2 161 planarized.

In particular, when using an electrically conductive substrate, such as a doped semiconductor material or a metallic material, thereby already obtained the desired trench capacitor with one of the Grabenfüllschicht 162 existing inner electrode and the outer electrode consisting of the substrate, which dielectricikum through the capacitor 161 isolated from each other. Especially when using a semiconductor substrate 100 For example, in order to improve a conductivity of the outer electrode, it is also possible to optionally carry out the methods known from the prior art for forming a buried plate by means of gas phase doping or deposition of a dopant source in the trench, such as an arsenic glass layer or an arsilicosilicate glass, and outdiffusion into the substrate gives the illustrated in the figures n-doped trench environment in the substrate.

According to 3C Now a reversal takes place that of the trench filling layer 162 to a level of the substrate surface, wherein preferably a wet etching process is performed.

Subsequently, the formation of a so-called nanoelement NE takes place substantially at the surface of the trench filling layer 162 , wherein the nanoelement NE protrudes beyond the first insulating layer I1. More specifically, in this case, first, a nanoelement seed layer SL (seed layer) is directly attached to the surface of the trench fill layer 162 formed in the opening required for the trench etching in the first and second insulating layer I1 and I2. Preferably, in this case gold, titanium, platinum, nickel, cobalt and / or a silizierfähiges material is deposited.

In particular, when using a material capable of siliciding, a self-aligning process is obtained in which a highly conductive seed layer is deposited on the exposed regions of the trench filling layer consisting of polysilicon 162 is trained. The silicable material (metal), which is furthermore generally deposited over the entire surface, can be removed from the surface in a simple manner by wet-chemical means.

On This nanoelement seed layer SL is now forming of the nanoelement NE, wherein preferably a single crystal nanowire as a nanoelement NE grown on the seed layer SL. The thickness of the nanowire fills this the opening the first and possibly present second insulating layer I1 and I2 completely out, with the openings may have a diameter of up to 400 nm. When growing the single-crystal nanowire can additionally Doping modulation methods are performed by adding doping gases, whereby one receives an optimized nanoelement. Nanoelements are the expert sufficiently known, which is why at this point only on References C.M. Dear: "Nanowire Super Lattices ", Nanoletters, 2002, 2 (2), 81-82; Y. CUI et al .: "High Performance Silicon Nanowire Field Effect Transistor ", Nanoletters, 2003; ASAP article; and Y. CUI et al .: "Diameter-controlled synthesis of single-crystal silicon nanowires ", Applied Physics Letters Vol. 78, No. 159, April 2001, pages 2214 to 2216 is referenced.

According to 3D In addition, an auxiliary layer HS may be formed on the surface of the second insulating layer 12 or the capacitor dielectric layer formed on this layer 161 for defining a predetermined length of the nanoelement NE. Preferably, this auxiliary layer consists of one of the first and second insulating layer I1, I2 different layer, wherein, for example, polysilicon deposited over the entire surface and regressed to a predetermined level by means of, for example, a CMP method.

On In this way, the nanoelement or the nanowire NE can be completely embedded and his height to a fixed predetermined height be set.

3E shows a simplified plan view of such a processed substrate, wherein usually a plurality of nano-elements NE matrix-like, ie in rows and columns, in the substrate 100 be formed.

Although so far substantially sectional views taken along a section AA according to 3E In the following, substantially sectional views along a section BB are shown in FIG 3E for further description of the method according to the invention.

According to 3E and 3F Accordingly, in a subsequent method step, first a control layer trench GT is formed using a second mask layer M2, which represents, for example, a resist mask. More specifically, in this case, the control layer trench GT is formed to the surface of the first insulating layer I1 for exposing a middle and upper region, ie, channel and terminal region, of the nanoelement NE, the auxiliary layer HS being the possibly present capacitor dielectric 161 and the second insulating layer I2 on the sidewalls of the nanoelement NE are removed. In this way one obtains, as it were, free-standing nano-elements which are limited only in their lower region, ie in the opening of the first insulating layer I1 of this layer or the capacitor dielectric.

After this step, to expose the nanoelement NE and to form a control layer trench GT, respectively 3G formed a gate dielectric at least in a central region of the nanoelement NE. By way of example, the gate dielectric GD is formed at least on the side walls of the nanoelement NE projecting beyond the first insulating layer I1, in which case a full-area deposition of a gate dielectric is preferably carried out on the surface of the first insulating layer I1 and of the nanoelement NE. Preferably, so-called "high k" dielectrics are used to realize the gate dielectric GD Preferably, the gate dielectric GD is deposited over the entire area and / or formed by a thermal transformation of the exposed surfaces of the nanoelement NE, thereby obtaining a high-quality gate insulating layer.

Subsequently, at least in a middle region, ie the channel region, of the nanoelement NE at the surface of the gate dielectric GD an electrically conductive control layer G is formed. Preferably, a highly doped semiconductor material such as highly doped polysilicon and / or a gate metal is deposited over the entire area as a control layer G and etched back to the central region of the nanoelement NE. The central region in this case represents a channel region of a field-effect transistor realized by the nanoelement.

According to 3H For example, after performing a CMP planarization and an etching back of the control layer G, a further or third insulating layer 13 is formed at least on the surface of the control layer G. Preferably, in this case, the third insulating layer I3 in the form of a dielectric layer is again deposited over the entire area and is formed back to the gate dielectric GD, which is formed on the nanoelement NE, or planarized.

Finally, it will a terminal layer S in an upper portion of the nanoelement NE for electrical connection of the nanoelement NE is formed and structured.

According to 3I For example, an optionally deposited third mask layer M3 can be deposited therefor and patterned by means of conventional photolithographic methods such that connection openings in the region of the nanoelement NE result. Furthermore, spacers can optionally be formed at the openings of the third mask layer M3 and, using the third mask layer M3 and the spacers formed thereon, the gate dielectric GD can be opened or removed to expose the nanoelement NE.

According to 3J Subsequently, an electrically conductive layer is deposited over the entire surface and planarized to the surface of the third mask layer M3, whereby one obtains the connection layer or the illustrated source region S, which is electrically connected to the upper region of the nanoelement and in addition a bit line BL for the DRAM memory cell represents. The formation of this connection layer S is known, for example, from so-called single or dual damascene methods, for which reason a detailed description is omitted below.

In this way, one obtains a DRAM semiconductor memory cell whose trench capacitor 160 the entire sidewall area is used for maximum capacitor capacity. The selection transistor AT is here used by a nanoelement NE for the realization of a vertical transistor, wherein the entire wiring is located above the substrate surface. In this context, it should be noted that the control layer G simultaneously represents a word line WL. The wiring in particular for the bit line BL and the source terminals S are preferably realized in damascene technology, wherein for the first time no STI (shallow trench isolation) insulation with its disadvantageous high-temperature processes and insulation collars with their complex technologies are required.

3K shows, for further illustration, a simplified plan view of a plurality of matrix-shaped DRAM semiconductor memory cells, according to the present invention, wherein like reference numerals designate like or corresponding elements and a repeated description is omitted below. The space requirement is therefore minimal, which is why highest integration densities can be realized with excellent electrical properties.

The The invention has been described above with reference to a silicon semiconductor material described as a substrate. However, it is not limited to and includes in the same way other substrates. In the same way is the Invention not on the described other materials limited, but equally includes alternative materials, which have substantially the same effect.

100

substratum

161

capacitor

162

trench filling

163

buried plate

170

buried tub

C

insulation collar

STI

area grave insulation

S

source region

D

drain region

CH

channel region

BS

Contact diffusion region

DG

gate dielectric

G

control layer

K

Contact

I, I1, I2

 insulating

WL

wordline

BL

bit

AT

selection transistor

M1, M2, M3

 mask layers

HS

auxiliary layer

T

dig

ET

extended dig

SL

Nano element seed layer

NE

Nano element

GT

Control layer trench

Claims (23)

DRAM semiconductor memory cell having a substrate ( 100 ); a trench (ET) in the substrate ( 100 ) is trained; a capacitor dielectric ( 161 ) formed on the trench surface of the trench (ET) at least to the substrate surface; an electrically conductive trench filling layer ( 162 ), which on the surface of the capacitor dielectric ( 161 ) is formed and the trench (ET) fills up to the substrate surface; a first insulating layer (I1) formed on the substrate surface and an opening to the trench filling layer (I1); 162 ) having; a nanoelement (NE) formed in the opening so as to project beyond the first insulating layer (I1); a gate dielectric (GD) formed at least on the side walls of the nanoelement (NE) protruding beyond the first insulating layer (I1); a control layer (G) formed on at least a central portion of the nanoelement (NE) on the gate dielectric (GD) for driving the nanoelement; a further insulating layer (I3) formed at least on the surface of the control layer (G); and an electrically conductive terminal layer (S, BL) formed in an upper portion of the nanoelement (NE) to the terminal thereof. DRAM semiconductor memory cell according to claim 1, characterized in that the nanoelement (NE) is a single crystal nanowire having. A DRAM semiconductor memory cell according to claim 1 or 2, characterized in that a nanoelement seed layer (SL) in the opening at the trench fill layer (12) 162 ) is trained. DRAM semiconductor memory cell according to claim 3, characterized in that the nanoelement seed layer (SL) Gold, titanium, platinum, nickel, cobalt and / or a silicatable material having. DRAM semiconductor memory cell according to one of the claims 1 to 4, characterized in that the first insulating layer (I1) a Has 1 to 10 nm thick oxide layer. DRAM semiconductor memory cell according to one of the claims 1 to 5, characterized in that the gate dielectric (GD) is a deposited dielectric and / or a thermally converted sidewall layer of the nanoelement having. DRAM semiconductor memory cell according to one of the claims 1 to 6, characterized in that the control layer is a doped Semiconductor material and / or metallic material. DRAM semiconductor memory cell according to one of the claims 1 to 7, characterized in that the connection layer (S, BL) a Damascene-Leitbahnstruktur has. Method for producing a DRAM semiconductor memory cell comprising the steps of: a) forming a trench (T, ET) in a substrate ( 100 ), which has on its surface at least a first insulating layer (I1); b) forming a capacitor dielectric ( 161 ) at least at the trench surface; c) forming an electrically conductive trench filling layer ( 162 ) on the surface of the capacitor dielectric ( 161 ) for filling the trench (T, ET); d) forming a nanoelement (NE) on the surface of the trench filling layer ( 162 ), which projects beyond the first insulating layer (I1); e) forming a gate dielectric (GD) at least on the side walls of the nanoelement (NE) projecting beyond the first insulating layer (I1); f) forming a control layer (G) at least in a central region of the nanoelement (NE) on the surface of the gate dielectric (GD); g) forming a further insulating layer (I3) at least on the surface of the control layer (G); and h) forming a connection layer (S, BL) in an upper region of the nanoelement (NE) for electrically connecting the nanoelement. A method according to claim 10, characterized in that in step a) a pad oxide as a first insulating layer (I1) on the surface of the substrate ( 100 ) is formed; a pad nitride is formed as a second insulating layer (I2) on the surface of the first insulating layer (I1); a first mask layer (M1) is formed and patterned on the surface of the second insulating layer (I2); and etching an opening in the first and second insulating layers (I1, I2) and the substrate ( 100 ) using the patterned first mask layer (M1). Method according to claim 9 or 10, characterized in that in step a) an enlargement of the trench in the substrate ( 100 ) for forming an extended trench (ET) and / or a method for increasing the surface area of the trench surface. Method according to one of the claims 9 to 11, characterized in that in step b) a Si ₃ N ₄ and / or SiO ₂ layer or dielectrics with high dielectric constant as capacitor dielectric ( 161 ) is deposited over the entire surface. Method according to one of the claims 9 to 12, characterized in that in step c) highly doped semiconductor material and / or a metal as Grabenfüllschicht ( 162 ) and etched back to a level of the substrate surface. Method according to one of the claims 9 to 13, characterized in that in step d) a nanoelement seed layer (SL) on the surface of Grabenfüllschicht ( 162 ) and the nanoelement (NE) is grown on the nanocouple seed layer (SL). Method according to claim 14, characterized that the nanoelement seed layer (SL) gold, titanium, platinum, nickel, Cobalt and / or a silicable Material has. Method according to one of the claims 9 to 15, characterized in that as nanoelement (NE) a single-crystal nanowire is trained. Method according to one of the claims 10 to 16, characterized in that in step d) further comprises an auxiliary layer (HS) on the surface the second insulating layer (I2) for setting a length of Nanoelement (NE) is formed. Method according to one of the claims 9 to 17, characterized in that in step d) a control layer trench (GT) using a second mask layer (M2) to the surface of the first Insulating layer (I1) for exposing a middle and upper area of the nanoelement (NE) is formed. Method according to one of the claims 9 to 18, characterized in that in step e) the gate dielectric (GD) over the entire surface deposited and / or by a thermal transformation of the free lying surface of the nanoelement (NE) is formed. Method according to one of the claims 9 to 19, characterized in that in step f) a highly doped Semiconductor material and / or a gate metal as control layer (G) over the entire surface deposited and etched back to the middle region of the nanoelement (NE). Method according to one of the claims 9 to 20, characterized in that in step g) a third insulating layer (I3) over the entire surface deposited and planarized to the gate dielectric (GD). Method according to one of the claims 9 to 21, characterized in that in step h) the gate dielectric (GD) in the upper part of the nanoelement (NE) is opened, and an electrically conductive Material as connecting layer (S, BL) deposited and structured becomes. Method according to claim 22, characterized in that that a third mask layer (M3) is deposited over the entire surface and for forming from a connection opening is structured; Spacer (SP) on the side walls of the Connection opening be formed; the gate dielectric (GD) using the third mask layer (M3) and the spacer (SP) is removed; and the connecting layer (S, BL) is deposited over the entire surface and up to the surface the third mask layer is planarized.