DE10308644A1 - Amplifier circuit with regulated power and method for power amplification - Google Patents

Abstract

The amplifier circuit according to the invention with regulated power has an amplifier (1) with an amplifier input (1.1) for applying a signal (MS1) to be amplified, a control input (1.3) and an amplifier output (1.2). A control device (4, 5, 6, 7, 10) is also provided for detecting the power output by the amplifier (1) and for generating a control signal (Ucontr). The control device (4, 5, 6, 7, 10) has an adjustable control time constant (Tg, Tk) and is connected to the control input (1.3) of the amplifier (1).

Description

The invention relates to an amplifier circuit with regulated power and a method for power amplification, which can be used particularly in the field of mobile communications.

In mobile communications, there is usually a amplitude-modulated transmission signal, which is also referred to below as AM transmit signal is called, using a power amplifier, the often referred to as a power amplifier, amplified and as a high-frequency amplitude-modulated transmission signal via a Radiated antenna. It is, for example, with enhanced data Rates for GSM Evolution (EDGE) on the one hand required the power amplification of the power amplifier exactly to regulate and on the other hand by the amplitude modulation in the power fluctuating useful signal, i.e. the AM transmit signal, not to be changed.

A corresponding solution for this is not yet available known.

An object of the invention is an amplifier circuit with regulated power and specify a method for power amplification, where on the one hand the power amplification is precisely regulated can and on the other hand the fluctuating in performance due to the modulation The useful signal is not influenced by the control.

The task is done through an amplifier circuit with regulated power with the features according to claim 1 and by a method of power amplification with the features according to claim 12 solved.

The amplifier circuit according to the invention with a regulated Power has an amplifier with an amplifier input to create one to be reinforced Signals, a control input and an amplifier output. In addition is a control device for detecting the power output by the amplifier and provided for generating a control signal. The control device has an adjustable control time constant and is with the control input of the amplifier connected.

In the method according to the invention for power amplification becomes a power-amplified transmission signal by means of a power amplifier generated. In addition, the performance is controlled by a control device of the transmission signal and depending on it a control signal generated that the power amplifier supplied becomes. The control device works while the power is ramping up with a first control time constant and during transmission with a second control time constant.

Advantageous further developments of Invention result from the specified in the dependent claims Features.

In one embodiment of the invention the control device of the amplifier circuit differential amplifier with a first input, a second input and an output on, with a signal at the first input for specifying the power can be created, the second input having a means for specification the control time constant is connected and the output of the differential amplifier with connected to the control input of the amplifier is. This allows the output of the amplifier to be output in a simple manner Power compared with the target power and the dependent control signal be generated.

The agent advantageously has a controllable switch, one for specifying the control time constant Resistor and a capacitor, the capacitor for Difference amplifier is connected in parallel, and the resistor is the capacitor and connects the switch together. There is a first one over the switch or a second time constant can be set.

According to a preferred variant of the amplifier circuit according to the invention the controllable switch has an N-channel MOS transistor and one P-channel MOS transistor on the output side between the input of the differential amplifier and a unit for power recording are connected. The two Transistors are connected on the input side in such a way that both are conductive or both are blocking.

In addition, the amplifier circuit according to the invention an inverter is connected upstream of the control input of the P-channel MOS transistor with regulated power his. It is achieved in a simple manner that both the P-channel MOS Transistor as well as the N-channel MOS transistor are always the same switching states assume, namely either both transistors are conductive or both transistors are blocking.

To achieve the object, it is also proposed that a unit for forming a ramp be connected upstream of the two transistors in the amplifier circuit. This has the advantage that the controllable switch no longer generates a switching pulse, thereby significantly reducing the charge injection via the capacitance of the control electrode of the transistor. During the hold state, in which the control device operates with a large control time constant, there can be a change in the power due to external influences, such as temperature drift, change in the supply voltage, leakage currents, etc. If now, after the power has changed due to these external influences, a quick change from a large to a small control time constant can result in a charge surge. This in turn causes a disturbance in the control loop. However, if the changeover from one to the other control time constant takes place, as proposed here, in the form of a ramp or continuously, that is to say slowly, this can result in the spectral effects of the impact are significantly reduced.

In another embodiment the amplifier circuit according to the invention with regulated power the unit can form the ramp have the first RC element and a second RC element, the first RC element connected between the output and the input of the N-channel MOS transistor is, and wherein the second RC link between the output and the Input of the P-channel MOS transistor is switched. About the Dimensioning the resistors and the capacitors of the two RC elements, the length of time, the one for switching from one control time constant to the other Control time constant is required to be set.

In a development of the amplifier circuit according to the invention With controlled power, the control device can use a directional coupler to detect the from the amplifier have delivered power.

The control device advantageously has the amplifier circuit according to the invention a level rectifier, which is connected downstream of the directional coupler is.

In addition, the control device can amplifier circuit according to the invention a level amplifier have, which is connected downstream of the level rectifier.

Finally, in the amplifier circuit according to the invention the amplifier output be connected to an antenna.

In one embodiment of the method according to the invention for power amplification can the control device during the Shut down the power using the first control time constant. This will not only when power up, but also precise power control possible when the power is shut down.

In a further development of the method according to the invention for power amplification the transition takes place continuously from one to the other control time constant. This means that when you switch quickly from one Reduced disturbances caused to the other control time constant. To the solution The task is also proposed that in the method according to the invention for power amplification the first control time constant is smaller than the second control time constant is.

Finally, the amplifier circuit according to the invention and / or the method according to the invention for power amplification in the transmission path of a mobile device be used.

The following is the invention several embodiments explained with reference to eight figures.

1 shows in the form of a block diagram a possible embodiment of the amplifier circuit according to the invention with regulated power.

2 shows the basic structure of a controllable switch, as it can be used in the amplifier circuit according to the invention.

3 shows the basic structure of a second possible embodiment of the controllable switch, as it can be used in the amplifier circuit according to the invention.

4 shows a possible specification of the in 2 principally illustrated controllable switch.

5 shows a possible specification of the in 3 principally illustrated controllable switch.

6 shows the performance over time when the in 2 fast switch shown is used.

7 shows the course of the performance with a change in performance during transmission, the in 2 fast switch shown is used.

8th shows the course of the performance with a change in performance during transmission, the in 3 slow switch shown is used.

9 shows the basic structure of a third possible embodiment of the controllable switch in a further development of the circuit of 3 ,

At the in 1 shown basic illustration of the amplifier circuit according to the invention with regulated power is at an RF input terminal 2 an amplitude-modulated transmit signal MS1, which comes from a transceiver and is applied to the radio frequency input 1.1 , HF input for short, of the power amplifier 1 guided. The power amplifier 1 amplifies the amplitude-modulated RF transmission signal MS1, which is then amplified as an amplitude-modulated RF transmission signal MS2 at the amplifier output 1.2 is applied and to an antenna 3 to be led. With the help of a directional coupler 4 is from the amplifier 1 output power recorded and on a level rectifier 5 guided. Strictly speaking, the directional coupler is used 4 detects a voltage proportional to that of the amplifier 1 output is. This voltage is measured using a rectifier diode 5.2 of the level rectifier 5 rectified. The resistance 5.1 serves as the terminating resistor of the HF line and can, for example, have a value of 50 ohms. The level rectifier 5 also has a capacitor 5.3 leading to resistance 5.4 is connected in parallel. At the exit 5.6 of the level rectifier 5 is a rectified voltage that is used by the amplifier 1 output is proportional, tapped. It should be mentioned here that the level rectifier 5 in 1 is only shown in principle. The rectified voltage is applied to the input 6.1 a level amplifier 6 guided. The one at the exit 6.2 of the level amplifier 6 if necessary, rectified rectified voltage Ui can be applied via a switch 7 and a resistance 9 to an inverting input 10.2 a differential amplifier 10 and a capacitor 11 be performed. In this case, the amplified rectified voltage Ui with a target voltage Us, which via a control connection 12 to a non-inverting input 10.1 of the differential amplifier 10 is compared. The target voltage Us is a control signal that comes from the baseband processor of a mobile radio device and the desired power of the power amplifier 1 pretends. At the exit 10.3 of the differential amplifier 10 there is a control voltage Ucontr, which depends on the target voltage Us, the amplified rectified voltage Ui and a control time constant T. Via the control voltage Ucontr, which on the control input 1.3 of the power amplifier 1 is performed, the performance of the power amplifier 1 can be set.

If via the control connection 8th that with the control input 7.4 of the controllable switch 7 is connected, a corresponding control signal etc. at the controllable switch 7 is present, the switch 7 closed, i.e. conductive or low-resistance. Otherwise the controllable switch 7 open, i.e. non-conductive or high-resistance.

In the event that the switch 7 is conductive, the control time constant T has a small value, namely: T = R × C = Tk in which
R = value of resistance 9 .
C = capacitance of the capacitor 11 and
Tk = small control time constant.

In the event that the switch 7 is non-conductive, the control time constant T has a large value, namely: T = (R + R2) × C = Tg in which
R2 = value of resistance 41 and
Tg = large control time constant.

In 2 is a schematic diagram of a first embodiment of a fast switching controllable switch 7 shown. Via the control input 7.4 two transistors N1 and P1 are controlled. The control input 24 of the transistor N1, which is designed as an N-channel MOS transistor, is directly connected to the control input 7.4 connected. The control input 25 of the transistor P1, which is designed as a P-channel MOS transistor, is via an inverter 21 with the control input 7.4 connected. Changes that at the control input 7.4 applied control signal, etc., as by the signal curve 22 indicated, from the low level to the high level, the two transistors N1 and P1 become conductive and connect the two connections 7.1 and 7.2 low impedance with each other. In the event that the control signal etc. at the input 7.4 as through the waveform 23 indicated, changes from the high state to the low state, the two transistors N1 and P1 have a high resistance, so that the two connections 7.1 and 7.2 are no longer connected to one another via the forward resistances of transistors N1 and P1. The two connections 7.1 and 7.2 are then via a fixed resistor that is in 3 is not shown connected. At the in 2 controllable switch shown 7 it is a so-called fast switching switch.

At the in 3 controllable switch shown 7 on the other hand, it is a slow-switching switch. The transition of the two transistors N1 and P1 from blocking to conducting takes place as by the two signal profiles 32 and 33 indicated, ramp-shaped. To generate the ramp is between the control inputs 24 and 25 of the two transistors N1 and P1 and the control input 7.4 of the controllable switch 7 a ramp generator 31 connected.

The in 3 slow-switching switches shown 7 has compared to that in 2 shown fast switching switch 7 following advantages. At the in 2 Fast switching switch shown can be generated by the switching pulse of the transistors N1 and P1, a charge injection via the capacitances of the control electrodes of the transistors N1 and P1 used. This can lead to malfunctions in the control loop. Such a charge injection can be significantly reduced by the slow, that is to say ramp-like, change in the forward resistance of the transistors N1 and P1. In addition, the in 2 shown fast switching switch during the hold state, in which the control time constant assumes a large value Tg, that is to say the on-state resistances of transistors N1 and P1 are high-resistance, resulting in a change in performance due to external influences, such as temperature drift, change in supply voltage, leakage currents, etc. come. When switching from the large to the small control time constant, a charge surge can occur, which in turn can cause disturbances in the control circuit. Such spectral effects of the shock can be achieved by slow switching, as is the case in 3 shown switch is possible to be reduced. To illustrate this, reference is made to the 6 . 7 and 8th directed.

In 6 is the time course of the power P when using a fast switching switch 7 shown. The power P is plotted on the y-axis and the time t on the x-axis. At time t1, a switch is made from a small control time constant Tk to a large control time constant Tg. At time t2, the large control time constant Tg changes back to the small control time constant Tk switched. This means that during the start-up of the transmit signal MS2, which is completed by the time t1 at the latest, the control loop operates with a small control time constant Tk. During the transmission of the amplitude-modulated signal MS2, which occurs between the times t1 and t2, the control loop also works a large control time constant Tg and during the shutdown of the transmit signal MS2, which occurs after the time t2, the control circuit works again with the small control time constant Tk. The course of the control signal etc. for controlling the switch 7 is in 6 shown in the lower area. Basically, this also applies to those in the 7 and 8th shown waveforms.

Even with the in 7 shown waveform is worked with a fast switching switch. However, during transmission, that is between times t1 and t2, there is a change in performance due to external influences, which is indicated in 7 is characterized by the drop in performance until time t2. As can be seen, a fast-switching switch causes a jump in signal MS2 at time t2. This jump can lead to malfunctions in the control loop.

At the in 8th The course of the signal MS2 shown also leads to a slow change in the power. However, since a slow-switching switch is used, there is no sudden change in the power, but only a slowly adjusted change in the power of the signal MS2. The switchover from the small control time constant Tk to the large control time constant Tg takes place between times t1 'and t1, whereas the switchover from the large control time constant Tg to the small control time constant Tk takes place between times t2' and t2. This can reduce interference in the control loop caused by switching after a drop in performance during transmission.

At the in 4 The illustrated embodiment of a fast-switching switch is between the two connections 7.1 and 7.2 of the switch 7 a resistance 41 provided with the value R2, above which, in the event that the two transistors N1 and P1 are in the non-conductive state, together with the resistor 9 and the capacitor 11 the control time constant T is specified. The two additional transistors P2 and N2, the transistor P2 being a further P-channel MOS transistor and the transistor N2 being a further N-channel MOS transistor, each serve to compensate for the gate charge, which can build up in the gate capacitance , The gate charge of transistor N1 is compensated for via transistor P2 and the gate charge of transistor P1 is compensated for via transistor N2. With the control input 7.4 of the controllable switch 7 is both the control input 42 of transistor P2 as well as the control input 24 of transistor N1 connected. Via the control input 7.5 of the controllable switch 7 , at which the control input 7.4 control signal is present, is the control input 25 of transistor P1 and the control input 43 of transistor N2 connected. The control input 7.5 in 4 corresponds to the output of the inverter 21 in 2 ,

When switching from the high-resistance to the low-resistance state and vice versa, the in 2 shown fast switching switch, also called transmission gate, jumps in charge at its output 7.2 on. These are caused by the reloading of the transistor's own capacities, the gate capacities. Some of these capacities are located directly at the exit 7.2 so that part of the charge movement is at the exit 7.2 plays and causes a jump in tension. As mentioned, this in turn can lead to malfunctions in the control loop. With the help of 4 illustrated embodiment, that is, with the transistors P2 and N2, a compensation of these charge jumps is achieved. Complementary transistors must be used so that the voltage jump receives the opposite sign necessary for compensation. Since only a part of the gate capacitance acts directly on the output and the amount of the N and P-channel MOS transistors is different, this must be taken into account when dimensioning. The different mobility of charge carriers in N- and P-channel MOS transistors is also taken into account. This factor and the division factor in the source and drain-side portion of the gate capacitance depend on the technology. The realization of the compensation capacities through the use of two total gate capacities, the amount of which is equal to that of the proportionately present gate capacities of the actual switching transmission gate, is in 4 shown. The compensation capacitors are connected to the output in the form of compensation transistors N2 and P2, since the charge compensation is to take place here.

In 5 is a more detailed representation of the in 3 slow-switching switch shown 7 shown. A first RC element consisting of a resistor 53 and a capacitor connected in parallel 51 , is between the connector 7.1 and the control input 24 of the transistor N1 switched. The time period required to bring the transistor N1 from the non-conductive to the conductive state can be set via this RC element. In addition, there is a second RC element, consisting of a resistor 54 and a capacitor connected in parallel 52 provided that between the connector 7.1 of the switch 7 and the control input 25 of the transistor P1 is switched. The time period required to bring the transistor P1 from the conductive to the non-conductive state can be set via this RC element. In scan mode, too Called sample mode, the forward resistances of the two transistors N1 and P1 are low-resistance and the two current sources 57 and 58 , which impress the two sampling currents Is, active. The two controllable current sources are in the hold mode, also referred to as hold mode, in which the forward resistances of the two transistors N1 and P1 are high-resistance 55 and 56 , which specify the holding currents Ih, active.

9 shows a development of the embodiment of the controllable switch of 3 , in which a control circuit is provided to control a slow switch. The circuit of 9 corresponds largely in its structure and its advantageous mode of operation to the circuit of 3 and so far will not be described again here. The gate connections 24 . 25 The transistors N1, P1 of the transmission gate each have an output of a control circuit 59 connected, which is driven with a ramp-shaped signal at a first input. A signal A can be applied to a second control input of the control circuit, which, based on a variable derived from an external resistor, provides a reference value for the forward resistance of the transmission gate 24 . 25 forms in the closed switching state. A third control input can be connected to the input 7.1 of the transmission gate 24 . 25 be connected to supply the detector output voltage. This means that the set on-state resistance is also dependent on the power level.

The control circuit 59 regulates the forward resistance of the transmission gate 24 . 25 after a voltage applied to a control input. By applying a ramp-shaped, that is to say rising or falling voltage over time, the forward resistance is changed over time and the transmission gate is switched slowly.

With the control of the control circuit 59 at the second and third inputs there is an improvement in the overall behavior of the control circuit over time.

The previous description of the embodiments according to the present Invention serves only for illustrative purposes and not for the purpose the restriction the invention. Various changes are within the scope of the invention and modifications possible, without departing from the scope of the invention and its equivalents.

1

power amplifier

1.1

RF input

1.2

RF output

1.3

control input

2

RF input port

3

antenna

4

directional coupler

5

Level rectifier

5.1

resistance

5.2

diode

5.3

capacitor

5.4

resistance

5.5

entrance

5.6

output

6

level amplifier

6.1

entrance

6.2

output

7

controllable switch

7.1

entrance

7.2

first switch position

7.3

second switch position

7.4

control input

7.5

inverted entrance

7.6

supply terminal

8th

first control connection

9

resistance

10

control amplifier

10.1

Not inverting input

10.2

inverting entrance

10.3

output

11

capacitor

12

second control connection

21

inverter

22

rising flank

23

falling flank

24

gate

25

gate

P1

PMOS transistor

N1

NMOS transistor

31

ramp generator

32

rising ramp

33

falling ramp

41

resistance

42

gate

43

gate

GND

reference potential

51

first capacitor

52

second capacitor

53

first resistance

54

second resistance

55

first controlled power source

56

second controlled power source

57

third controlled power source

58

fourth controlled power source

59

control circuit

t1

first time

t2

second time

t1 '

time

t2 '

time

Ucontr

control voltage

MS1

amplitude modulated RF transmit signal

MS2

amplified amplitude-modulated RF transmission signal

Tg

large control time constant

tk

small Control time constant

A

reference value

B

Detector output voltage

Claims (16)

Amplifier circuit with regulated power, in which an amplifier ( 1 ) with an amplifier input ( 1.1 ) for applying a signal to be amplified (MS1), a control input ( 1.3 ) and an amplifier output ( 1.2 ) is provided in which a control device ( 4 . 5 . 6 . 7 . 10 ) for detecting the from the amplifier ( 1 ) output and for generating a control signal (Ucontr) is provided which has an adjustable control time constant and with the control input ( 1.3 ) of the amplifier ( 1 ) connected is. Amplifier circuit according to claim 1, in which the control device comprises a differential amplifier ( 10 ) with a first entrance ( 10.1 ), a second entrance ( 10.2 ) and an output ( 10.3 ), where the first input ( 10.1 ) a signal (Us) for specifying the power can be applied, in which the second input ( 10.2 ) with a means for specifying the control time constant ( 7 . 9 . 11 ) and where the output ( 10.3 ) with the control input ( 1.3 ) of the amplifier ( 1 ) connected is. Amplifier circuit according to claim 2, in which the means for specifying the control time constant ( 7 . 9 . 11 ) a controllable switch ( 7 ), a resistance ( 9 ) and a capacitor ( 11 ), the capacitor ( 11 ) to the differential amplifier ( 10 ) is connected in parallel, with the resistor ( 9 ) the capacitor ( 11 ) and the switch ( 7 ) connects with each other and with the switch ( 7 ) a first or a second time constant (Tg, Tk) can be set. Amplifier circuit according to claim 3, in which the controllable switch ( 7 ) has an N-channel MOS transistor (N1) and a P-channel MOS transistor (P1), which on the output side between the input of the differential amplifier ( 10 ) and a unit for recording services ( 4 . 5 . 6 ) are switched and are connected on the input side in such a way that both are conductive or both are blocking. Amplifier circuit according to claim 4, in which the control input of the P-channel MOS transistor (P1) is an inverter ( 21 ) is connected upstream. Amplifier circuit according to Claim 4 or 5, in which the two transistors (P1, N1) have a unit for forming a ramp ( 31 ) is connected upstream. Amplifier circuit according to Claim 6, in which the unit for forming a ramp ( 31 ) a first RC link ( 51 . 53 ) and a second RC link ( 52 . 54 ), the first RC element ( 51 . 53 ) between the output (S) and the control input ( 24 ) of the N-channel transistor (N1) is switched, and the second RC element ( 52 . 54 ) between the output (S) and the control input ( 25 ) of the P-channel transistor (P1) is switched. Amplifier circuit according to one of the claims 1 to 7 , in which the control device has a directional coupler ( 4 ) for recording the from the amplifier ( 1 ) has delivered power. Amplifier circuit according to claim 8, in which the control device comprises a level rectifier ( 5 ) which the directional coupler ( 4 ) is connected downstream. Amplifier circuit according to claim 9, in which a level amplifier ( 6 ) is provided to the level rectifier ( 5 ) is connected downstream. Amplifier circuit according to one of the claims 1 to 10 where the amplifier output ( 1.2 ) with an antenna ( 3 ) connected is. Method for power amplification, in which a power amplifier ( 1 ) a power-amplified transmission signal (MS2) is generated, in which a control device ( 4 . 5 . 6 . 7 . 10 ) the power of the transmission signal (MS2) is recorded and, depending on this, a control signal (Ucontr) is generated which is sent to the power amplifier ( 1 ) is supplied, the control device ( 4 . 5 . 6 . 7 . 10 ) works with a first control time constant (Tk) during power-up and with a second control time constant (Tg) during transmission. Method according to claim 12, in which the control device ( 4 . 5 . 6 . 7 . 10 ) works with the first control time constant (Tk) while shutting down the power. A method according to claim 12 or 13, in which a transition takes place continuously from one to the other control time constant. Method according to one of the claims 12 to 14 , in which the first control time constant (Tk) is smaller than the second control time constant (Tg). Use of the amplifier circuit and / or the Procedure for power amplification according to one of the claims 1 to 15 in the transmission path of a mobile device.