DE10260753B4 - Method for producing a semiconductor component - Google Patents

Abstract

A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a first insulating film (21) on a semiconductor substrate (11) having a cell region (I) and a peripheral circuit region (II), a gate electrode being formed on each region;
(b) forming an LDD region (14) on the substrate (11) on both sides of the gate electrode; after that
(c) forming a first interlayer insulating film (23) on the entire surface of the resulting structure;
(d) forming a first insulating film spacer (22) on the sidewalls of the gate electrode in the cell region by etching the first inter-layer insulating film (23) and the first insulating film (21) in the cell region using a contact mask as an etching mask which defines an area for a Bit line contact and a storage electrode contact leaves free;
(e) forming a conductive layer (27) electrically connected to the exposed portion of the bit line contact and the storage electrode contact;
(f) removing the first interlayer insulating film (23) in the peripheral circuit region;
(g) Making a second insulating fume on the ...

Description

The Invention relates to methods of manufacturing a semiconductor device in particular a method for producing a semiconductor device, by the operating characteristics and reliability of the component thereby can be improved that a contact plug is produced differently than before.

in the In general, a pn junction by ion implantation of an n- or a p-type impurity into one p- or an n-type semiconductor substrate, wherein the resulting Substrate through a thermal process to create a diffusion region is activated.

Around a short channel effect due to lateral diffusion from the diffusion region in a semiconductor device with small channel width to prevent is a shallow transition required.

Now becomes a conventional, the Applicant known, method for producing a semiconductor device explained.

In a cell area and a peripheral circuit area of a Semiconductor substrate becomes an active region defining Component separation insulating film made. On the entire surface of the the resulting structure becomes a stacked structure of a gate insulating film, a conductive layer for a gate electrode and a mask insulating film. These Stack structure is then made using a gate electrode mask as an etching mask etched thereby forming a stacked structure of a gate insulating film pattern, a gate electrode and a mask insulating film pattern.

After that will be on the entire surface of the The resulting structure is a nitride first Insulating film produced. In the entire surface of the resulting structure becomes a low concentration impurity by internal implantation introduced to thereby on the substrate on both sides of the gate electrode to create a LDD (Lightly Doped Drain) area.

On the entire surface the resulting structure becomes a second insulating film of a nitride made to form the LDD structure.

At the side walls the stack structure of the gate insulating film pattern, the gate electrode and the mask insulation film pattern is by etching the first and second insulating films in the peripheral circuit area of the substrate an Iso lierfilm spacers made.

Then is by internal implantation of a foreign substance with high concentration in the substrate on both sides of the insulating film spacer a source / drain region is formed. In the case of a process for a high-speed logic circuit produced in the source / drain region, a silicide film.

Then will be on the entire surface the resulting structure is a first interlayer insulating film produced.

After that is by etching the first interlayer insulating film, the second insulating film, and of the first insulating film using a contact mask, the a predetermined range for one Bit line contact and a storage electrode contact in the cell area of the substrate, as an etching mask formed a contact hole, and on the side walls of the stack structure the gate insulating film pattern, the gate electrode and the mask insulating film pattern An interlayer insulating film is produced. This consists the interlayer insulating film made of the first insulating film.

On the entire surface the resulting structure becomes a conductive layer of polysilicon produced.

By Removing the conductive layer and the first interlayer insulating film through a process with chemical-mechanical Polishing (CMP) is formed a contact plug.

On the entire surface the resulting structure becomes a second interlayer insulating film subsequently produced is etched using a bit line contact mask as an etch mask to form a bit line contact hole.

As described above, in the conventional method of manufacturing a semiconductor device, the source / drain region is formed in the peripheral circuit region of the semiconductor substrate before the contact plug that is connected to the predetermined region for the bit line contact and the storage electrode contact in the cell region is fabricated. However, the subsequent process must be performed below 800 ° C to maintain low contact resistance in the source / drain region. This impairs the filling properties of the interlayer insulating film and restricts the deposition temperature of the conductive layer forming contact plug. In addition, since the entire second insulating film in the cell region has to be removed, the first insulating film surrounding the gate electrode is unevenly damaged. Further, the characteristics of a logical process using a technique for producing a silicide film after Producing the source / drain region by a thermal process for making the Kontaktpfropfens impaired, whereby the DRAM technique and a process for producing a high-speed logic circuit can not be used together.

The US 6,284,592 B1 describes a method of manufacturing a semiconductor device. This method comprises the steps of forming a field oxide layer on a first line type semiconductor substrate having a cell region and a peripheral circuit region, the field oxide layer defining active and field regions in the device; forming respective first and second gates with cap layers thereon in the cell and peripheral circuit areas after depositing a gate insulating film on the semiconductor substrate; forming first and second doping regions in the cell and peripheral circuit regions by internally implanting a second conductivity-type dopant using the cap layers as a mask; forming an etch stop layer on the semiconductor substrate to cover the field oxide layer and sides of the first and second gates, forming a sacrificial layer of the etch stop layer and a contact hole exposing the first conduction type region; forming a plug communicating with the first conductive type region within the contact hole and removing the remaining sacrificial layer to expose the top of the plug and the etch stop layer, forming a third sidewall spacer on an exposed side of the top of the plug while first and second Sidewall spacers are formed so that the Ätzstoppschicht is arranged between the first and second Seitenwandabstandshaltem accordingly; and forming a third conductive-type region to be superimposed on the second conductive-type region of the peripheral circuit region using the cover layer and the first sidewall spacer as a mask.

The US 5,856,219 A describes a method of fabricating a highly integrated DRAM for forming source / drain contact between word lines in a self-aligned manner. After gate electrodes, that is to say word lines, are formed, a first thin insulating layer is deposited. The source / drain contact is etched according to the thickness of the first insulating layer to form a polycrystalline silicon electrode. Thereafter, a second insulating layer is deposited, wherein the first and second insulating layers are etched back by a distance corresponding to the sum of the layer thicknesses of the second insulating layer and the layer thickness of the first insulating layer, so that a spacer remains on the side walls of the gate electrode. Implantation of dopants is performed to form heavily doped source and drain regions of a peripheral transistor. Self-aligning contact is thereby enabled while the offset length of the heavily doped source and drain regions remains the same.

The JP 09-260 607 A describes the fabrication of a semiconductor device. Here, a planarized interlayer insulating film is formed on an insulating layer to form a sidewall of a transistor to form a capacitance increasing electrode on this interlayer insulating film. The intermediate insulating layer is etched away after its formation, and thereafter the insulating layer is etched away to form a side wall. Finally, the formation of a transistor is completed by means of a heavily doped layer. Since the capacitance-increasing electrode can be formed on a flat surface, it is possible to perform a rapid and accurate etching before the formation of the transistor.

The US 6,297,136 B1 describes a method of manufacturing a semiconductor device. The method for manufacturing an embedded semiconductor device in which a logic device and a memory device are integrated within a semiconductor substrate comprises the following steps. First, an insulating region and an active region are formed on a semiconductor substrate having a first region and a second region, after which a gate insulating layer is formed on a predetermined portion of a surface of the active region of the first region and the second region. After forming a first conductive layer pattern and a protective layer pattern on the gate insulating layer, a first sidewall spacer is formed on the side surfaces of the first conductive layer pattern and the protective layer pattern. Thereafter, implantation with a dopant into the surface of the semiconductor substrate is performed on both sides of the first sidewall spacer to form source / drain regions. After making a second sidewall spacer on an outer surface of the first sidewall spacer, the protective layer pattern is removed, and a second conductive layer pattern is formed on the surfaces of the first conductive layer pattern and the first and second regions and the source / drain regions of the second region, so that it is possible to reduce the number of manufacturing steps.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing properties from deteriorating by performing a thermal process in which a contact plug is in a predetermined range producing a bit line contact and a memory electrode contact in a cell region of a semiconductor substrate, and then producing a source / drain region in a peripheral circuit region.

These The object is achieved by the method according to claim 1. advantageous Embodiments and developments are the subject of dependent claims.

The The invention will be better understood with reference to the accompanying drawings, which are by way of illustration serve, better understandable become.

The 1 to 4 10 are sectional views illustrating successive steps in a method of manufacturing a semiconductor device according to a preferred embodiment of the invention.

Now With reference to these drawings, there will be a method of manufacturing a semiconductor device according to a preferred embodiment of the invention.

According to the 1 becomes a component separation insulating film 13 defining an active area in a cell area I and a peripheral circuit area II a semiconductor substrate 11 produced.

On the entire surface of the resultant structure, a stacked structure of a gate insulating film (not shown) of a gate electrode conductive layer (not shown) and a mask insulating film (not shown) is prepared and then etched using a gate electrode mask as an etching mask to form a stacked structure a gate insulating film pattern 15 , a gate electrode 17 and a mask insulation film pattern 19 train.

Thereafter, a first insulating film is formed on the entire surface of the resultant structure 21 produced. This is preferably prepared as a nitride film with a thickness of 2 to 40 nm.

In the substrate 11 becomes on both sides of the gate electrode 17 a low-concentration impurity is introduced by internal implantation to an LDD region 14 train.

As it is in the 2 is shown, on the entire surface of the resulting structure, a first interlayer insulating film 23 preferably as a BPSG film, TEOS film, HDP oxide film, or combinations thereof.

Thereafter, the first interlayer insulating film 22 and the first insulating film 21 etched using a contact mask leaving a predetermined area for a bit line contact and a storage electrode contact in the cell area I free, around a contact hole 25 and a first insulating film spacer 22 on the sidewalls of the stacked structure of the gate insulating film pattern 15 , the quality electrode 17 and the mask insulation film pattern 19 train.

As it is in the 3 is shown in the cell area I one the contact hole 15 filling conductive layer 27 preferably made of n-impurity doped polysilicon.

Instead of the conductive layer 27 can in the cell area I an epitaxially grown silicon region can be used, which is exposed by means of the contact hole 25 on the substrate 11 was produced.

Thereafter, the first interlayer insulating film becomes 23 on the peripheral circuit area II using a cell mask covering the peripheral circuitry area II vacant, removed. Here, the process for removing the first interlayer insulating film is 23 preferably a dry etching or a wet etching process. The wet etching process is carried out using HF or BOE (Buffered Oxide Etchant) as an etchant.

On the entire surface the resulting structure becomes a second insulating film (not shown). To form the LDD structure, the second insulating film, preferably a nitride film.

As it is in the 4 is formed on the side walls of the stack structure of the gate insulating film pattern 15 , the gate electrode 17 and the mask insulation film pattern 19 in peripheral circuit area II by back etching the second insulating film and the first insulating film 21 a second insulating film spacer 29 educated.

By internal implantation of a high concentration impurity into the substrate 11 on both sides of the second insulating film spacer 29 becomes a source / drain region 31 produced. In the case of a high-speed logic circuit process, a silicide film is preferably formed by using a Ti or Co film on the source / drain region.

On the entire surface of the resulting structure becomes a second interlayer insulating film 33 preferably as HDP oxide film, TEOS film, USG film or a combination made of these films.

A contact plug 28 is made by forming the second interlayer insulating film 33 , the first interlayer insulating film 23 and the conductive layer 27 be removed by means of a CMP process. In the CMP process, the mask insulation film pattern becomes 19 used as an etching barrier.

Thereafter, a third interlayer insulating film is formed on the entire surface of the resultant structure 35 produced. Preferably, the third interlayer insulating film is 35 a silane film, a USG film, a TEOS film, or an HDP oxide film. When the third interlayer insulating film 35 is an HDP oxide film, it is deposited with a thickness of 100 to 500 nm, after which 20 to 300 nm thereof are etched back. When the third interlayer insulating film 35 A is a USG film, this is deposited with a thickness of 10 to 200 nm.

By an etching process becomes an etching mask using a bit line contact mask Bit line contact hole made.

As already discussed, is in the process for producing a semiconductor device according to the invention the one with the predetermined range for the Bitleitungskontakt and the contact electrodes connected to the storage electrode contact in the cell region of the Semiconductor substrate prepared before the source / drain region in the peripheral circuit portion thereof, wherein in the high-temperature process, the epitaxially grown silicon film is used to make a contact plug with good filling properties and to obtain low contact resistance. In addition, an additional Ion implantation process with a p-impurity in the subsequent production of the bit line contact, thereby eliminating the manufacturing process is simplified. The method is for a combination of a DRAM process and a process for producing a high-speed logic circuit suitable for high-speed operation of the semiconductor device and it becomes process yield and reliability of the component improved.

Claims (8)

A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a first insulating film ( 21 ) on a semiconductor substrate ( 11 ) with a cell area ( I ) and a peripheral circuit area ( II ), a gate electrode being produced on each area; (b) producing an LDD region ( 14 ) on the substrate ( 11 ) on both sides of the gate electrode; thereafter (c) preparing a first interlayer insulating film ( 23 ) on the entire surface of the resulting structure; (d) producing a first insulating film spacer ( 22 ) at the sidewalls of the gate electrode in the cell region by etching the first interlayer insulating film ( 23 ) and the first insulating film ( 21 ) in the cell region using a contact mask as an etch mask, leaving an area for a bit line contact and a storage electrode contact free; (e) producing a conductive layer ( 27 ) electrically connected to the exposed portion for the bit line contact and the storage electrode contact; (f) removing the first interlayer insulating film ( 23 ) in the peripheral circuit area; (g) forming a second insulating film on the entire surface of the resulting structure; (h) producing a second insulating film spacer ( 29 ) on the sidewalls of the gate electrode in the peripheral circuit region by etching the second and first insulating films; (i) forming a source / drain region ( 31 ) by internal implantation of a high-concentration impurity into the substrate ( 11 ) on both sides of the second insulating film spacer; then (j) forming a second interlayer insulating film ( 33 ) on the entire surface of the resulting structure; and (k) producing a contact plug ( 28 ) by leveling the second interlayer insulating film ( 33 ), the first interlayer insulating film ( 23 ) and the conductive layer ( 27 ). Method according to claim 1, characterized in that the first insulating film ( 21 ) is produced as a nitride film having a thickness of 2 to 40 nm. A method according to claim 1, characterized in that the first interlayer insulating film ( 23 ) is prepared as a film of borophosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS), a high density plasma (HDP) oxide, or a combination thereof. Method according to claim 1, characterized in that the conductive layer ( 27 ) is prepared from n-impurity doped polysilicon. Method according to claim 1, characterized in that the conductive layer ( 27 ) is produced as an epitaxially grown silicon film. Method according to claim 1, characterized in that the step of forming the source / drain region ( 31 and a step of forming a silicide film on the source / drain region ( 31 ) belongs. Method according to claim 1, characterized in that that the second insulating film as a nitride film with a thickness of 2 to 40 nm is produced. Method according to claim 1, characterized in that the second interlayer insulating film ( 33 ) is produced as a film of high density plasma (HDP) oxide, tetraethylorthosilicate (TEOS), undoped silicate glass (USG), or combinations thereof.