DE10243786A1 - Coding method for data bit sequence in optical transmission system using column or row coding of data bit sequence matrix and re-arrangement of each row or column data bit sequence - Google Patents

Abstract

The coding method uses column coding of the data bit sequence matrix (M1), with the bits of each row arranged in a new series sequence, or row coding of the data bit sequence matrix with the bits of each column arranged in a new series sequence. The coding can be effected via a Reed-Solomon code or a Bose-Chaudhuri-Hocquenghem code. Also included are Independent claims for the following: (a) a decoding method for a coded data bit sequence; (b) a decoding device for a coded data bit sequence

Description

Multiple coding method a data bit sequence for decoding this data sequence and arrangement The invention relates to methods for coding and Decoding according to the preambles of claims 1 and 7, and an arrangement according to the preamble of claim B.

In systems for high bit rate optical transmission Coding methods are used for data signals. This coding method use the data signals or data bit sequences to determine control or Check bits. A number of data bits form a so-called code word with the associated control bits. These code words are transmitted from the sender to the receiver. The code words are received at the receiving end evaluated or decoded and bit errors resulting from the transmission corrected or repaired.

With this coding, bit errors, the while the transfer arise, are corrected upon receipt. This creates a Coding gain that can be used, for example, that deliberately a larger transmission distance chosen will be a correspondingly higher one Number of bit errors caused by the decoding at the receiving end can be immediately compensated or corrected. The better the coding and decoding process with the same proportion of check bits is the bigger the achievable coding gain and the more data can be obtained from one transmit greater distance become.

Optical transmission systems enable through high bit rates large transmission capacities.

Become the usual coding and decoding methods used, the problem arises that due to the high data rates only simple coding and decoding methods are used can. This is due to the processing time for coding and decoding conditionally. Enable complex coding and decoding processes high coding gains but also a lot of processing time. As a result, they cannot work at the same time with data transfer accomplished become.

Have simple coding and decoding processes the disadvantage of a low coding gain.

Object of the present invention is to improve coding and decoding methods so that faster coding and decoding is made possible.

This task is accomplished through a process according to the characteristics of claims 1 and 7 and by an arrangement with the features of the claim 8 solved.

The advantage of the invention is in that faster coding and decoding of data bit sequences or code words allows which is especially for optical transmission systems of great Advantage is.

Advantageous embodiments of the Invention are in the subclaims specified.

An embodiment of the invention is shown in the drawing and is described below.

It shows:

1 a matrix consisting of n rows and n columns.

2 a matrix, according to 1 , with additional control bit lines.

3 a modified matrix, according to 3 ,

4 a matrix after 3 , with additional control bit lines.

5 a modified matrix, according to 4 ,

6 a matrix after 5 , with additional control bit lines.

7 an arrangement for decoding multi-coded code words according to the invention.

1 shows a matrix consisting of n rows and n columns. The number of rows and columns does not have to be identical, but was chosen arbitrarily in the example. This matrix contains data or information bits that were read line by line. The data or information bits can also be symbols. In a first step, the columns of the matrix are coded using a bit error-correcting coding method, for example using a Reed-Solomon code, RS code for short, or a Bose-Chaudhuri-Hocquenghem code, BCH code for short. This means that control and test bits are determined from each column using the coding method. These are added to the respective column, see 2 , Data and check bits of a column together form a code word of the first kind.

This new resulting second matrix M2 is now fed to a first interleaver, which leaves the bits of the first line unchanged, the bits of the second line rotates one bit to the right, the bits of the third line rotates two bits to the right, etc., see 3 ,

This third matrix M3 thus created is in turn coded in columns using a bit error-correcting coding method. This means that control and test bits are determined from each column using the coding method. These are added to the respective column, see 4 , A column forms a code word of the second kind.

This fourth matrix M4 is now a two th interleaver, which leaves the bits of the first line unchanged, the bits of the second line rotates two bits to the left, the bits of the third line rotates four bits to the left, the bits of the fourth line rotates six bits to the left, etc ., please refer 5 ,

This fifth matrix M5 is now coded in columns using a bit error-correcting coding method. Ie from each column according to the coding method control or Check bits determined. These are added to the respective column, see 6 , A column forms a third-type code word.

The sixth matrix determined in this way M6 is now transmitted line by line and transmitted to the receiver.

The process example can also done in reverse become, i.e. the rows are encoded, the bits of the columns are rearranged and the matrix is broadcast column by column.

The bits of the lines can also be different be ordered. For example, the first line rotates by one bit, the second line by two bits, etc.

The decoding process is inverse Way to coding process. This can be done through the line-by-line reorganization of the bits and column-wise coding the decoding process is parallelized become. This saves time. Likewise, by this arrangement procedure of the bits a receiving deinterleaver process the bits without caching and thus process them directly next Add decoding stage.

7 shows a matrix M6, according to 6 , This is fed in columns to a first decoder bank DecBl, which consists of several individual decoders arranged in parallel. The individual decoders operate in a clock-controlled manner, that is to say they read in the bits step by step, for example starting with the first line, and output the decoded bits in the same order. This means, for example, that the first individual decoder of the first decoder bank DecB1 reads in the bit of the first row and the first column of the matrix M6, then the second bit, ie the bit of the second row and the first column of the matrix M6, etc. and outputs the decoded bits accordingly, ie the bit of the first row of the first column, then the bit of the second row of the first column, etc.

The first decoder bank DecBl is included connected to a first deinterleaver Delntl. This arranges the bits every line new. Since the decoders are clock-controlled, the first one receives Deinterleaver DeInt1 each a complete line, which he rearrange got to. This can be done by means of a fixed assignment that changes in cycles take place, i.e. the first deinterleaver DeIntl does not have to store the bits exhibit.

The outputs of the first deinterleaver DeIntl are with the entrances a second decoder bank DecB2 connected. This also works like previously described, clock-controlled. The outputs of the second decoder bank DecB2 are with the inputs connected to a second deinterleaver DeInt1, which is analogous to the first Deinterleaver DeInt1 works. The outputs of the second deinterleaver DeInt1 are with the entrances a third decoder bank DecB3 connected, which is analogous to the previous described works. The exits the third decoder bank DecB3 output decoded code words from which data bits can be extracted or which can be used again Decoding over returns not drawn fed back to the first decoder bank DecB1 become.

In the example, the decoding process is as follows: at the receiving end, the n column-wise code words become n individual decoders fed to the first decoder bank DecB1. These decode the as last coded code words the third type.

The n single decoders of the first decoder bank DecBl work clock-controlled. The first decoder bank DecB1 is there quasi simultaneously all decoded bits of the first line, then all bits of the second line, etc.

The bits of a line are now one first deinterleaver DeIntl fed. This works inversely to second interleaver. The bits of a line become accordingly back in order. Since the deinterleaver only has to rearrange the bits of the line, this can be done without intermediate storage due to a clockwise fixed wiring, etc. realized become. The bits can after reordering quasi simultaneously a second decoder bank DecB2 made up of n individual decoders supplied which are the code words decoded the second type. This second decoder bank DecB2 works also clock controlled.

The second decoder bank DecB2 gives the decoded bits again clockwise, i.e. all bits of the first Line, all bits of the second line, etc.

The bits of a line are now one second deinterleaver DeInt2 fed. This works inversely to the first interleaver. The bits of a line become accordingly back in order. Since the deinterleaver only has to rearrange the bits of the line this without intermediate storage through a clockwise fixed wiring, etc. realized become. The bits of the line become quasi-simultaneous after reordering a third decoder bank DecB3 from n individual decoders, which the code words decoded the first kind. This decoder bank also works clock-controlled. The third decoder bank DecB3 outputs the decoded code words. These decoded or corrected code words can be used with the decoding results the previous decoding and again be decoded, i.e. be iterated so that bit errors are avoided become. It can any number of repetitions of these decodings can be performed. For example, until no significant improvements can be seen or a maximum number of iterations has been reached.

The user data obtained in this way can then be processed further or forwarded.

With differently coded and ordered bit sequences the decoding process must be adjusted accordingly.

Claims (10)

Method for multiple coding of a data bit sequence, which is arranged in a matrix form, consisting of rows and columns, and is optionally rearranged after a coding process, characterized in that the data bit sequence only codes in columns and only the bits of each line are rearranged in a different order or vice versa. A method according to claim 1, characterized in that the data bit sequence is sent out on the level in which the Bits rearranged. A method according to claim 1 or 2, characterized in that that the data sequence is encoded with a bit error correcting code becomes. Method according to claim 1, 2 or 3, characterized in that that control bits determined from the data bits during the following coding and ordering processes coded or rearranged. Method according to one of the preceding claims, characterized in that the data bit sequence line by line into a Matrix is read in columns with a bit error correcting Code is coded, which determines control bits from the data bit column, which are added to the respective column that then this matrix is rearranged in a first embodiment such that the Bits of each line differ from the bits of other lines Number to be rotated that this matrix with one bit error correcting code is encoded, which consists of each data bit column Control bits are determined, which are added to the respective column, that subsequently this matrix rearranged in a second embodiment is that the bits of each line are each one of the bits of the other Lines of different numbers are rotated, so that these Matrix is encoded with a bit error correcting code which Control bits are determined from each data bit column and sent to the respective Column added or the treatment of rows and columns is reversed. A method according to claim 5, characterized in that the top line of the matrix receives line number 0 and the Rows are numbered consecutively, that in the matrix first Design the bits by the number of bits corresponding to the line number are rotated that the bits in the matrix of the second embodiment of the rows rotated back twice their first rotation become. Method for decoding according to one of claims 1 to 6 coded data bit sequence, characterized in that the data bit sequence is decoded in columns in parallel and rearranged row by row or vice versa. Arrangement for decoding according to one of claims 1 to 6 coded data bit sequence, using decoders and deinterleavers, thereby in that the decoder from a first decoder bank with several individual decoders arranged parallel to each other, which is connected to the output of the matrix storing the code words, that the exits the first single decoder via one first deinterleaver are connected to a second decoder bank, whose outputs via a second Deinterleaver with the inputs a third decoder bank are connected. Arrangement according to claim 8, characterized in that according to the number of coding steps, further deinterleavers and decoder are provided. Arrangement according to claim 8 or 9, characterized in that at least the exits the third decoder bank on the inputs of the first decoder bank fed back are.