DE102022121350A1 - Gate driver and display device containing it - Google Patents

Abstract

A gate driver and a display device incorporating the same are disclosed. The gate driver includes a plurality of signal sending units connected in cascade via a carry line to which a carry signal from a previous signal sending unit is applied, wherein an n-th (n is a positive integer) signal sending unit includes: a first circuit unit that a first Q-logic generator configured to receive the carry signal from the previous signal transmission unit to charge a first control node and a second Q-logic generator configured to discharge the first control node ; a second circuit unit configured to discharge a second control node according to a voltage of the first control node; and an output unit configured to output the carry signal and a gate signal based on potentials of the first control node and the second control node, wherein the second Q-logic generator comprises: a second 1st transistor having a first electrode, a gate electrode, a back gate electrode and a second electrode; and a second-2nd transistor having a first electrode, a gate electrode, a back gate electrode, and a second electrode.

Description

Cross reference to related application

This application claims priority from Korean Patent Application No. 10-2021-0127134 filed on Sep. 27, 2021 and Korean Patent Application No. 10-2021-0181988 filed on Dec. 17, 2021.

background

1. Field of the Invention

The present disclosure relates to a gate driver and a display device including the same.

2. Discussion of the Prior Art

Display devices include a liquid crystal display (LCD) device, an electroluminescent display device, a field emission display (FED) device, a plasma display panel (PDP), and the like.

Electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices depending on the material of a light-emitting layer. An active matrix type organic light emitting display device displays an input image using a self-emitting element that itself emits light, such as an organic light emitting diode (hereinafter referred to as “OLED”). An organic light emitting display device has advantages that a response speed is fast, and luminous efficiency, luminance, and viewing angle are large.

Some of the display devices, such as a liquid crystal display device or an organic light-emitting display device, include a display panel having a plurality of sub-pixels, a driver that outputs a drive signal for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, and the same. The driver includes a gate driver that supplies a scanning signal or a gate signal to the display panel, and a data driver that supplies a data signal to the display panel.

In such a display device, when a drive signal such as a scanning signal, an EM signal and a data signal is supplied to a plurality of sub-pixels formed in the display panel, the selected sub-pixel transmits light or emits light directly to thereby display an image.

At this time, there is a case where a transistor for improving discharge characteristics is added to the gate driver. However, since a bezel may grow due to the addition of the transistor and the added transistor operates at Vgs=0V in a turn-off portion, a leakage current is generated and accordingly power consumption may increase and output degradation of a gate signal may be caused.

Summary

The present disclosure is directed to solving all of the needs and problems described above.

The present disclosure aims to provide a gate driver capable of reducing a leakage current and the number of transistors at the same time, and a display device including the same.

It should be noted that the objects of the present disclosure are not limited to the objects described above, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

A gate driver according to an embodiment of the present disclosure includes a plurality of signal sending units connected in cascade via a carry line to which a carry signal from a previous signal sending unit is applied, including an nth (n is a positive integer) signal sending unit : a first circuit unit including a first Q-logic generator configured to receive the carry signal from the previous signal sending unit to charge a first control node, and a second Q-logic generator configured to charge the to discharge first control node comprises; a second circuit unit configured to discharge a second control node according to a voltage of the first control node; and an output unit configured to output the carry signal and a gate signal based on potentials of the first control node and the second control node, wherein the second Q-logic generator comprises: a second 1st transistor having a first electrode connected to the first control node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from a next signal transmission unit, and a second electrode connected to a buffer node; and a second-2nd transistor having a first electrode connected to the buffer node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from the next signal transmission unit, and a second electrode connected to a low potential voltage line.

The second 1st and the second 2nd transistor can be turned on by a charging voltage of the second control node to discharge the first control node to a low potential voltage.

The second 1st and the second 2nd transistor can receive a carry signal of a gate low voltage from the next signal sending unit at the back gate electrode while being turned off when the second control node is discharged.

The second Q-logic generator may further include a second-third transistor having a first electrode connected to the first control node, a gate electrode receiving a start signal, and a second electrode connected to the buffer node , exhibit.

The second Q logic generator may further include a second-4th transistor having a first electrode connected to the buffer node, a gate electrode receiving the start signal and a second electrode connected to the low potential voltage line. exhibit.

The first Q-logic generator may include a one-1st transistor having a first electrode and a gate electrode receiving the carry signal from the previous signal sending unit and a second electrode connected to the buffer node.

The first Q-logic generator may be a one-2nd transistor having a first electrode connected to the buffer node, a gate electrode receiving the carry signal from the previous signal sending unit, and a second electrode connected to the first Control node is connected, have.

The first Q-logic generator may include a one-third transistor having a first electrode connected to a high-potential voltage line to which a high-potential voltage is applied, a gate electrode connected to the first control node, and a second having an electrode connected to the buffer node.

The second circuit unit may include a third transistor having a first electrode connected to the high-potential voltage line, a gate electrode connected to a first node, and a second electrode connected to the second control node .

The second circuit unit may include a third-2nd transistor having a first electrode and a gate electrode connected to the high potential voltage line and a second electrode connected to the first node.

The second circuit unit may include a third-third transistor having a first electrode connected to the first node, a gate electrode connected to the first control node, and a second electrode to which a low-potential voltage is applied .

The second circuit unit may include a third-fourth transistor having a first electrode connected to the second control node, a gate electrode connected to the first control node, and a second electrode to which the low-potential voltage is applied .

The second circuit unit may be a third-fifth transistor having a first electrode connected to the second control node, a gate electrode to which the carry signal from the previous signal sending unit is applied, and a second electrode to which the low potential voltage is applied is, exhibit.

The output unit may include a first pull-up transistor having a first electrode applied with a first clock signal, a gate electrode connected to the first control node, and a second electrode connected to a first output node .

The output unit may include a first pull-down transistor having a first electrode connected to the first output node, a gate electrode connected to the second control node, and a second electrode to which a first low-potential voltage is applied .

The output unit may include a second pull-up transistor having a first electrode applied with a second clock signal, a gate electrode connected to the first control node, and a second electrode connected to a second output node .

The output unit may include a second pull-down transistor having a first electrode connected to the second output node, a gate electrode connected to the second control node, and a second electrode to which a second low-potential voltage is applied .

The second circuit unit may include an inverting circuit that inverts a voltage of the first control node and applies the inverted voltage to the second control node.

The inverter circuit may include a first Qb logic generator and a second Qb logic generator.

The first Qb logic generator may include a fourth transistor having a first electrode connected to a high-potential voltage rail, a gate electrode connected to a first node, and a second electrode connected to the second control node .

The first Qb logic generator may be a fourth-1st transistor having a first electrode connected to the high potential voltage line, a gate electrode connected to the second control node of the previous signal sending unit, and a second electrode connected to connected to the first node.

The second Qb logic generator may be a fourth-qth transistor having a first electrode connected to the first node, a gate electrode connected to the buffer node, and a second electrode connected to the second control node is connected, have.

The second Qb logic generator may be a fifth-qth transistor having a first electrode connected to the second control node, a gate electrode connected to the buffer node, and a second electrode connected to the low-potential voltage line is, exhibit.

The first Qb logic generator may further include a capacitor connected between the gate electrode and the second electrode of the fourth transistor.

A gate driver according to an embodiment of the present disclosure includes a plurality of signal sending units connected in cascade via a carry line to which a carry signal from a previous signal sending unit is applied, including an nth (n is a positive integer) signal sending unit : a circuit unit configured to receive the carry signal from the previous signal transmission unit to charge or discharge voltages of a first control node and a second control node; and an output unit configured to output a gate signal and the carry signal based on potentials of the first control node and the second control node, the output unit comprising: a first pull-up transistor having a first electrode connected to a first high-potential voltage line a gate electrode connected to the first control node and a second electrode connected to a first output node; a first pull-down transistor having a first electrode connected to the first output node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from a next signal transmission unit, and a second electrode connected to a first low potential voltage line; a second pull-up transistor having a first electrode connected to a second high-potential voltage line, a gate electrode connected to the first control node, and a second electrode connected to a second output node; and a second pull-down transistor having a first electrode connected to the second output node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from the next signal transmission unit, and a second electrode connected to a second low potential voltage line.

The first and second pull-down transistors can be turned on by a charge voltage of the second control node to discharge the first output node to a low potential voltage.

The first and second pull-down transistors can receive a carry signal of a gate low voltage from the next signal sending unit at the back gate electrode while being turned off when the second control node is discharged.

The circuit unit may include a first circuit unit configured to receive the carry signal from the previous signal sending unit to charge the first control node.

The first circuit unit may include a first transistor having a first electrode receiving the carry signal from the previous signal transmission unit, a gate electrode applied with a clock signal, and a second electrode connected to a buffer node.

The first circuit unit may include a second transistor having a first electrode connected to the buffer node, a gate electrode to which the clock signal is applied, and a second electrode connected to the first control node.

The first circuit unit may include a third transistor having a first electrode connected to the second high-potential voltage line to which a second high-potential voltage is applied, a gate electrode connected to the first control node, and a second electrode connected to the buffer node is connected, have.

The circuit unit may include a second circuit unit configured to discharge the second control node according to a voltage of the first control node.

The second circuit unit may include a fourth transistor having a first electrode connected to the second high-potential voltage line, a gate electrode connected to a first node, and a second electrode connected to the second control node.

The second circuit unit may include a fifth transistor having a first electrode connected to the second high-potential voltage line, a gate electrode to which a voltage of the second control node from the previous signal sending unit is applied, and a second electrode connected to the first node is, exhibit.

The second circuit unit may include a sixth transistor having a first electrode connected to the first node, a gate electrode connected to the buffer node, and a second electrode connected to the second control node.

The second circuit unit can include a seventh transistor having a first electrode connected to the second control node, a gate electrode connected to the buffer node, and a second electrode connected to the second low-potential voltage line to which a second low-potential voltage is created, have.

A display device according to an embodiment of the present disclosure includes a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are arranged; a data driver configured to supply a data voltage of pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, the gate driver comprising: a plurality of signal sending units connected via a carry line to the a

carry signal is applied from a previous signal sending unit are connected in cascade, wherein an nth (n is a positive integer) signal sending unit comprises: a first circuit unit including a first Q-logic generator configured to output the carry signal receiving the previous signal sending unit to charge a first control node and a second Q-logic generator configured to discharge the first control node; a second circuit unit configured to discharge a second control node according to a voltage of the first control node; and an output unit configured to output the carry signal and a gate signal based on potentials of the first control node and the second control node, wherein the second Q-logic generator comprises: a second 1st transistor having a first electrode connected to the first control node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from a next signal transmission unit, and a second electrode connected to a buffer node , having; and a second-2nd transistor having a first electrode connected to the buffer node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from the next signal transmission unit, and a second electrode connected to a low potential voltage line.

The second 1st and the second 2nd transistor can be turned on by a charging voltage of the second control node to discharge the first control node to a low potential voltage.

The second 1st and the second 2nd transistor can receive a carry signal of a gate low voltage from the next signal sending unit at the back gate electrode while being turned off when the second control node is discharged.

The second Q-logic generator may further include a second-third transistor having a first electrode connected to the first control node, a gate electrode receiving a start signal emp catches, and a second electrode connected to the buffer node.

The second Q logic generator may further include a second-4th transistor having a first electrode connected to the buffer node, a gate electrode receiving the start signal and a second electrode connected to the low potential voltage line. exhibit.

The first Q-logic generator may include a one-1st transistor having a first electrode and a gate electrode receiving the carry signal from the previous signal sending unit and a second electrode connected to the buffer node.

The first Q-logic generator may be a one-2nd transistor having a first electrode connected to the buffer node, a gate electrode receiving the carry signal from the previous signal sending unit, and a second electrode connected to the first Control node is connected, have.

The first Q-logic generator may include a one-third transistor having a first electrode connected to a high-potential voltage line to which a high-potential voltage is applied, a gate electrode connected to the first control node, and a second having an electrode connected to the buffer node.

The second circuit unit may include an inverting circuit that inverts a voltage of the first control node and applies the inverted voltage to the second control node.

The inverter circuit may include a first Qb logic generator and a second Qb logic generator.

The first Qb logic generator may include a fourth transistor having a first electrode connected to a high-potential voltage rail, a gate electrode connected to a first node, and a second electrode connected to the second control node .

The first Qb logic generator may be a fourth-1st transistor having a first electrode connected to the high potential voltage line, a gate electrode connected to the second control node of the previous signal sending unit, and a second electrode connected to connected to the first node.

The second Qb logic generator may be a fourth-qth transistor having a first electrode connected to the first node, a gate electrode connected to the buffer node, and a second electrode connected to the second control node and a fifth-qth transistor having a first electrode connected to the second control node, a gate electrode connected to the buffer node, and a second electrode connected to the low-potential voltage line.

The first Qb logic generator may further include a capacitor connected between the gate electrode and the second electrode of the fourth transistor.

All of the transistors in the display panel may include the data driver, the gate driver, and the sub-pixels implemented with oxide thin film transistors (oxide TFTs) containing an n-channel type oxide semiconductor.

A display device according to an embodiment of the present disclosure includes a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are arranged; a data driver configured to supply a data voltage of pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, the gate driver comprising: a plurality of signal sending units connected via a carry line to which a carry signal from a previous signal sending unit is applied, in are connected in cascade, wherein an nth (n is a positive integer) signal transmission unit comprises: a circuit unit configured to receive the carry signal from the previous signal transmission unit to charge voltages of a first control node and a second control node unload; and an output unit configured to output a gate signal and the carry signal based on potentials of the first control node and the second control node, the output unit comprising: a first pull-up transistor having a first electrode connected to a first high-potential voltage line a gate electrode connected to the first control node and a second electrode connected to a first output node; a first pull-down transistor having a first electrode connected to the first output node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from a next signal transmission unit, and a second electrode connected to a first low potential voltage line; a second pull-up A transistor having a first electrode connected to a second high-potential voltage line, a gate electrode connected to the first control node, and a second electrode connected to a second output node; and a second pull-down transistor having a first electrode connected to the second output node, a gate electrode connected to the second control node, a back gate electrode receiving the carry signal from the next signal transmission unit, and a second electrode connected to a second low potential voltage line.

The first and second pull-down transistors can be turned on by a charge voltage of the second control node to discharge the first output node to a low potential voltage line.

The first and second pull-down transistors can receive a carry signal of a gate low voltage from the next signal sending unit at the back gate electrode while being turned off when the second control node is discharged.

All of the transistors in the display panel may include the data driver, gate driver, and sub-pixels implemented with oxide thin film transistors (oxide TFTs) containing an n-channel type oxide semiconductor.

In the present disclosure, since transistors that control discharging of a gate driver are formed in a double gate structure, and a negative bias is applied to a back gate electrode when the transistors in the double gate structure are turned off are, a leakage current can be reduced and at the same time the number of transistors can be reduced.

In the present disclosure, power consumption and output characteristics can be improved by reducing leakage current.

In the present disclosure, since a separate transistor is not required for improving discharge characteristics, not only a path on which the leakage current can be generated can be reduced, but also a case size can be reduced.

The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will become apparent to those skilled in the art from the following description and appended claims.

character list

• 1 eine Ansicht, die ein Schieberegister eines Gate-Treibers gemäß einer ersten Ausführungsform der vorliegenden Offenbarung schematisch zeigt;
• 2 eine Ansicht, die den Gate-Treiber gemäß der ersten Ausführungsform der vorliegenden Offenbarung zeigt;
• 3 ein Wellenformdiagramm, das Eingangs-/Ausgangssignale und Spannungen von Steuerknoten des in 2 gezeigten Gate-Treibers darstellt;
• 4A bis 4C Ansichten zum vergleichenden Beschreiben eines Prinzips zum Verringern des Leckstroms eines zweiten Q-Logik-Generators;
• 5 eine Ansicht, die einen Gate-Treiber gemäß einer zweiten Ausführungsform der vorliegenden Offenbarung darstellt;
• 6 eine Ansicht, die ein Schieberegister eines Gate-Treibers gemäß einer dritten Ausführungsform der vorliegenden Offenbarung schematisch darstellt;
• 7 ein Schaltungsdiagramm, das den Gate-Treiber gemäß der dritten Ausführungsform der vorliegenden Offenbarung im Detail darstellt;
• 8 ein Wellenformdiagramm, das Eingangs-/Ausgangssignale und Spannungen von Steuerknoten des in 7 gezeigten Gate-Treibers darstellt;
• 9A bis 9C Ansichten zum vergleichenden Beschreiben eines Prinzips zum Verringern des Leckstroms einer Ausgabeeinheit;
• 10 eine Ansicht, die ein Simulationsergebnis unter Verwendung eines in 7 gezeigten EM-Treibers zeigt;
• 11 ein Blockdiagramm, das eine Anzeigevorrichtung gemäß der Ausführungsform der vorliegenden Offenbarung darstellt;
• 12 eine Ansicht, die eine Querschnittsstruktur einer in 11 gezeigten Anzeigetafel darstellt;
• 13 ein Schaltungsdiagramm, das eine Pixelschaltung darstellt, die auf die in 11 gezeigte Anzeigetafel angewendet wird. 11; und
• 14 ein Wellenformdiagramm, das ein Ansteuerverfahren der in 13 gezeigten Pixelschaltung darstellt.

The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings; show it:

• 1 12 is a view schematically showing a shift register of a gate driver according to a first embodiment of the present disclosure;
• 2 12 is a view showing the gate driver according to the first embodiment of the present disclosure;
• 3 is a waveform diagram showing input/output signals and voltages of control nodes of the in 2 gate driver shown;
• 4A until 4C views for comparatively describing a principle for reducing leakage current of a second Q-logic generator;
• 5 12 is a view illustrating a gate driver according to a second embodiment of the present disclosure;
• 6 12 is a view schematically showing a shift register of a gate driver according to a third embodiment of the present disclosure;
• 7 12 is a circuit diagram detailing the gate driver according to the third embodiment of the present disclosure;
• 8th is a waveform diagram showing input/output signals and voltages of control nodes of the in 7 gate driver shown;
• 9A until 9C views for comparatively describing a principle for reducing leakage current of an output unit;
• 10 a view showing a simulation result using an in 7 EM driver shown;
• 11 12 is a block diagram illustrating a display device according to the embodiment of the present disclosure;
• 12 a view showing a cross-sectional structure of an in 11 display panel shown;
• 13 a circuit diagram showing a pixel circuit based on the in 11 scoreboard shown is applied. 11; and
• 14 a waveform diagram showing a driving method of in 13 pixel circuit shown.

Exact description of exemplary embodiments

Advantages and features of the present disclosure and implementation methods thereof will be made clearer by the embodiments described below with reference to the accompanying drawings. The present disclosure is not intended to be limited to the embodiments set forth herein, but may be embodied in numerous different forms and. Rather, the present embodiments will complete the disclosure of the present disclosure and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the appended claims and their equivalents.

The shapes, sizes, ratios, angles, and numbers disclosed in the accompanying drawings for describing embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Like reference numbers refer to like elements throughout the specification. Further, in describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

The terms "comprise," "include," "have," "include," "consist of," "constitute of," and the like are generally intended to allow other components to be added unless the terms are used with the Term "only" used. Any references to the singular may include the plural unless expressly stated otherwise.

Components are designed to encompass a common range of errors, even if not specifically stated.

When the positional relationship between two components is described using terms such as "on," "above," "below," and "next to," one or more components may be positioned between the two components, unless the terms are used with the term " direct” or “immediately”.

The terms "first," "second," and the like can be used to distinguish components from one another, but the functions or structures of the components are not limited by atomic numbers or component names in front of the components.

The same reference numbers may refer to substantially the same elements throughout the present disclosure.

The following embodiments can be partially or fully connected or combined with one another and linked and operated in a variety of technical ways. The embodiments may be practiced independently or in conjunction with each other.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 12 is a view schematically illustrating a shift register of a gate driver according to a first embodiment of the present disclosure.

With reference to 1 The gate driver according to the first embodiment includes a shift register synchronized with a shift clock CLK to successively output pulses of a gate signal (hereinafter referred to as "gate pulses") SCOUT(n-2) to SCOUT(n+2 ) to issue. "SET" in 1 represents a set terminal and "RESET" in 1 represents a reset connection.

The shift register includes a plurality of signal sending units ST(n-2), ST(n-1), ST(n), ST(n+1) and ST(n+2) connected via a carry line to which a carry signal is sent. are connected in cascade.

A timing controller can adjust a width and multiple output of an output signal SCOUT of the gate driver using a start pulse VST input to the gate driver.

In general, a start signal VST is input to a first signal transmission unit. In 2 an n-2nd signal transmission unit ST(n-2) may be the first signal transmission unit receiving the start signal VST.

The signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1) and ST(n+2) each receive a start pulse or carry signals Cout(n-2), Cout(n -1), Cout(n), Cout(n+1) and Cout(n+2) output from a previous signal sending unit and receive the shift clock CLK. The activation of a first signal transmission unit ST(n-2) begins according to the start pulse VST and the other signal transmission units ST(n-1), ST(n), ST(n+1) and ST(n+2) each receive the carry signals Cout (n-2), Cout(n-1), Cout(n) and Cout(n+1) from the previous signal transmission unit and start driving. The shift clock CLK may be an N-phase clock (N is a positive integer greater than or equal to 2). For example, the shift clock CLK may be a four-phase clock CLK1, CLK2, CLK3, and CLK4. The phase difference between the four-phase clocks CLK1, CLK2, CLK3 and CLK4 can be 90 degrees.

The signal sending units ST(n-2) to ST(n+2) may output a carry signal Cout through second output nodes while outputting strobe pulses SCOUT(n-2) to SCOUT(n+2) through first output nodes, respectively.

2 12 is a view illustrating the gate driver according to the first embodiment of the present disclosure, and 3 is a waveform diagram showing input/output signals and voltages of control nodes of the in 2 gate driver shown. Here, an example is described in which the gate driver is implemented as a scan driver.

With reference to 2 The sense driver (gate driver) according to the embodiment may have a first control node that pulls up an output voltage (hereinafter referred to as "Q node"), a second control node that pulls down the output voltage (hereinafter referred to as "Qb node") ), a first circuit unit 61, a second circuit unit 62 and an output unit 63.

The first circuit unit 61 may include a first Q logic generator 61a and a second Q logic generator 61b. The first Q logic generator 61a charges the Q node Q and the second Q logic generator 61b discharges the first control node.

The first Q logic generator 61a comprises a one-1st transistor T1, a one-2nd transistor T1A and a one-3rd transistor T3q.

The one-1st transistor T1 is turned on by an N-2nd carry signal C(n-2) from the previous signal sending unit, and supplies a voltage of the N-2nd carry signal C(n-2) to a buffer node Qh. The one-1st transistor T1 includes a first electrode and a gate electrode receiving the N-2nd carry signal from the previous signal transmission unit, and a second electrode connected to a buffer node.

The one-2nd transistor T1A is turned on by the N-2nd carry signal C(n-2) and charges the Q node Q based on the N-2nd carry signal. The one-2nd transistor T1A includes a first electrode connected to the second electrode of the one-1st transistor T1 or the buffer node Qh, a gate electrode connected to the N-2nd carry signal C(n -2) and a second electrode connected to the Q node Q.

The one-3rd transistor T3q is turned on by the Q node Q and sends a high potential voltage of a high potential voltage line GVDD to the buffer node Qh. The one-3rd transistor T3q includes a first electrode connected to the high potential voltage line GVDD, a gate electrode connected to the Q node Q, and a second electrode connected to the buffer node Qh.

The second Q-logic generator 61b comprises a second-1st transistor T3, a second-2nd transistor T3A, a second-3rd transistor T3nB and a second-4th transistor T3nC.

The second 1st transistor T3 is turned on by the Qb node Qb and discharges the Q node Q to a third low potential voltage of a third low potential voltage line GVSS2 together with the second 2nd transistor T3A.

When the second 1st transistor T3 is turned off by the Qb node Qb, a negative bias is applied to a back gate electrode by an N+2nd carry signal C(n+2) from the next signal sending unit. Accordingly, a threshold voltage Vth of the second-1st transistor T3 can increase, and thus a leakage current can be reduced. The second 1st transistor T3 comprises a first electrode connected to a first control node Qb, a gate electrode connected to a second control node Qb, a back gate electrode to which the N+2- th carry signal C(n+2) is applied, and a second electrode connected to a first electrode of the second-2nd transistor T3A.

The second 2nd transistor T3A is turned on by the second control node Qb and discharges the first control node Q together with the second 1st transistor T3 to a third low potential voltage of the third low potential voltage line GVSS2.

When the second-2nd transistor T3A is turned off by the Qb node Qb, the negative bias is applied to the back gate electrode by the N+2nd carry signal C(n+2) from the next signal sending unit. accordingly Accordingly, a threshold voltage Vth of the second-2nd transistor T3A can increase, and thus the leakage current can be reduced. The second 2nd transistor T3A includes the first electrode connected to the second electrode of the second 1st transistor T3, a gate electrode connected to the Qb node Qb, a back gate electrode , to which the N+2-th carry signal C(n+2) is applied, and a second electrode connected to the third low-potential voltage line GVSS2.

The second-3rd transistor T3nB is turned on by the start pulse VST and discharges the Q node Q together with the second-4th transistor T3nC to the third low-potential voltage of the third low-potential voltage line GVSS2. The second-3rd transistor T3nB includes a first electrode connected to the Q node Q, a gate electrode to which the start pulse VST is applied, and a second electrode connected to a first electrode of the second-4th transistor T3nB -th transistor T3nC is connected.

The second-4th transistor T3nC is turned on by the start pulse VST and discharges the first control node Q together with the second-3rd transistor T3nB to the second low-potential voltage of the third low-potential voltage line GVSS2. The second-4th transistor T3nC includes the first electrode connected to the second electrode of the second-3rd transistor T3nB, a gate electrode to which the start pulse VST is applied, and a second electrode connected to the third low-potential voltage line GVSS2.

The second circuit unit 62 comprises a three-1st transistor T4, a three-2nd transistor T41, a three-3rd transistor T4q, a three-4th transistor T5q and a three-5th transistor T5.

The third 1st transistor T4 is turned on by a voltage of a first node n1 and supplies the high potential voltage to the Qb node Qb. The third 1st transistor T4 includes a first electrode connected to the high-potential voltage line to which the high-potential voltage is applied, a gate electrode connected to the first node n1, and a second electrode connected to the second control node is connected. The first capacitor C1 is connected between the gate electrode and the second electrode of the fourth transistor T4.

The third 2nd transistor T41 is turned on by the high potential voltage and supplies the high potential voltage to the first node n1. The third 2nd transistor T41 includes a first electrode and a gate electrode connected to the high potential voltage line and a second electrode connected to the first node n1.

The third-3rd transistor T4q is turned on by a voltage of the Q node Q and discharges the first node n1 to a second low-potential voltage. The third-3rd transistor T4q includes a first electrode connected to the first node n1, a gate electrode connected to the Q node, and a second electrode connected to a second low-potential voltage line GVSS1.

The third-fourth transistor T5q is turned on by the Q node Q voltage and discharges the Qb node Qb to a third low potential voltage. The third-fourth transistor T5q includes a first electrode connected to the Qb node Qb, a gate electrode connected to the Q node Q, and a second electrode connected to the third low potential voltage line GVSS2 is.

The third-fifth transistor T5 is turned on by the voltage of the carry signal C(n-2) from the previous signal sending unit, and discharges the Qb node Qb to the third low-potential voltage. The third-5th transistor T5 comprises a first electrode connected to the Qb node Qb, a gate electrode to which the carry signal C(n-2) from the previous signal transmission unit is applied, and a second electrode, which is connected to the third low-potential voltage line GVSS2.

The output unit 63 may output the scan signal SCOUT(n) to the first output node and output a carry signal COUT(n) based on potentials of the Q node Q and the Qb node Qb to the second output node. The output unit 63 may include a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6cr, and a second pull-down transistor T7cr.

The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of the Q node Q and the Qb node Qb to output the scan signal SCOUT(n). The first pull-up transistor T6 includes a gate electrode connected to the Q node Q, a first electrode to which a clock signal SCCLK(n) is applied, and a second electrode connected to the first output node is. The second capacitor C2 is connected between the gate electrode and the second electrode of the first pull-up transistor T6. The first pull-down transistor T7 is connected to the first pull-up transistor T6, where the first output node is in between. The first pull-down transistor T7 includes a gate electrode connected to the Qb node Qb, a first electrode connected to the first output node, and a second electrode connected to a first low-potential voltage line GVSSO.

The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of the Q node Q and the Qb node Qb to output the carry signal COUT(n). The second pull-up transistor T6cr includes a gate electrode connected to the Q node Q, a first electrode to which a clock signal SC_CRCLK(n) is applied, and a second electrode connected to the second output node is. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node in between. The second pull-down transistor T7cr includes a gate electrode connected to the Qb node Qb, a first electrode connected to the second output node, and a second electrode connected to the third low-potential voltage line GVSS2.

A structural advantage of the second Q logic generator applied to the scan driver according to the embodiment will be described.

4A until 4C 12 are views for comparatively describing a principle for reducing a leakage current of the second Q logic generator.

With reference to 4A the second 1st transistor T3 and the second 1st transistor T3A of the second Q-logic generator according to the embodiment are in a double gate structure using an LS metal layer which is a light blocking layer of a coplanar element, implemented as a back gate electrode for receiving the negative bias, ie, the carry signal C(n+2) of a gate low voltage, from a next signal transmission unit on the back gate electrode during turn-off in discharging the Qb node Qb, and the threshold voltage Vth increases due to the negative bias and accordingly the leakage current is reduced.

like it in 4B 1, a circuit for comparison with the second Q logic generator of the embodiment is composed of, in addition to the two-1st transistor T3 and the two-2nd transistor T3nA, a two-1bth transistor T3n and a two- 2b-th transistor T3nA is formed in order to improve the discharge characteristics, and thus even if the second-1st transistor T3, the second-1b-th transistor T3n, the second-2nd transistor T3A and the second- 2b-th transistor T3nA can be turned off when the Qb node Qb is discharged because a gate-source voltage Vgs of both the second 1-th transistor T3A and the second 2b-th transistor T3nA becomes less than 0 when the threshold voltage Vth is shifted to a negative polarity and thus Vth is less than 0, the leakage current is generated in the low-potential voltage line GVSS2, and accordingly the power consumption increases.

In this case, in the circuit of the comparative example, as much leakage current as a threshold voltage, i.e. H. Vth(Δ), is generated, but in the circuit of the embodiment, as much leakage current as Vth×0.42 is generated and is thus reduced. The leakage current generated in the circuit of the embodiment is reduced due to an effect of the double gate structure, and is reduced in proportion to a capacitance ratio (0.42) of an upper gate and a lower gate. The capacitance ratio of the top gate and the bottom gate may vary according to various design parameters such as a length, a thickness, a width, and the like of the top gate and the bottom gate, respectively.

In this case, the leakage current is reduced in proportion to the capacitance ratio of the upper gate and the lower gate, and thus it can be effective only when an upper gate capacitance is smaller than a lower gate capacitance.

In the embodiment, by applying signals applied to the second 1b-th transistor T3n and the second 2b-th transistor T3nA of the comparative example to the back gate electrodes of the second 1-th transistor T3 and the second-2nd transistor T3A, the second-1st transistor T3 and the second-2nd transistor T3A are adapted to also serve as the second-1b-th transistor T3n and the second-2b-th transistor T3nA.

In the circuit of the embodiment in 4A can, since the transistors T3n and T3nA compared to the circuit of the comparative example in 4B are removed, a leakage current generation path decreases, and a case size is reduced by the decrease. In this case, the circuit of the embodiment requires an increase in the size of the transistor in order to maintain a drooping characteristic that is the same as that of the circuit of the comparative example, but an amount of leakage current is reduced and thus there is an advantage in improving the power consumption and the improvement of an issue.

like it in 4C 1, when Vth is -2V, since the leakage current is generated in the low potential voltage line GVSS2, a difference occurs between a target voltage of the low potential voltage line in the circuit of the comparative example and an actual voltage. On the other hand, there is no difference between the target voltage of the low potential voltage line in the circuit of the embodiment and the actual voltage.

That is, it can be seen that the power consumption is improved and the output is stabilized in the circuit of the embodiment.

5 12 is a view illustrating a gate driver according to a second embodiment of the present disclosure.

With reference to 5 For example, the gate driver according to the second embodiment may include a first control node (hereinafter referred to as “Q node”), a second control node (hereinafter referred to as “Qb node”), a circuit unit 70 and an output unit 73 .

The circuit unit 70 may receive a carry signal from a previous signal sending unit to charge or discharge voltages of the first control node and the second control node.

The output unit 73 may output an emission control signal EMOUT to a first output node and output a carry signal COUT(n) to a second output node based on potentials of the Q node Q and the Qb node Qb. The output unit 73 may include a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6cr, and a second pull-down transistor T7cr.

The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of the Q node Q and the Qb node Qb to output the emission control signal EMOUT. The first pull-up transistor T6 includes a gate electrode connected to the Q node Q, a first electrode connected to a first high potential voltage line GVDD0 to which a first high potential voltage is applied, and a second Electrode connected to the first output node. The first pull-down transistor T7 is connected to the first pull-up transistor T6 with the first output node in between. The first pull-down transistor T7 includes a gate electrode connected to the second control node Qb, a first electrode connected to the first output node, and a second electrode connected to a first low-potential voltage line GVSS0 to which a first low-potential voltage is applied.

The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of the Q node Q and the Qb node Qb to output the carry signal COUT(n). The second pull-up transistor T6cr includes a gate electrode connected to the Q node Q, a first electrode connected to a second high-potential voltage line GVDD 1 to which a second high-potential voltage is applied, and a second electrode , which is connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node in between. The second pull-down transistor T7cr includes a gate electrode connected to the Qb node Qb, a first electrode connected to the second output node, and a second electrode connected to a second low-potential voltage line GVSS1. to which a second low-potential voltage is applied.

6 12 is a view schematically illustrating a shift register of a gate driver according to a third embodiment of the present disclosure.

With reference to 6 the gate driver according to the embodiment includes a shift register synchronized with a shift clock CLK to successively output pulses of a gate signal (hereinafter referred to as “EM pulses”) EMOUT(n-2) to EMOUT(n+2) to spend

The shift register comprises a plurality of signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1) and ST(n+2) which are transmitted via a carry line to which a carry signal is applied. are connected in cascade.

A timing controller 130 (see 11 ) can adjust a width and multiple output of an output signal EMOUT of the gate driver 120 using a start pulse VST input to the gate driver 120.

A start signal VST is generally input to a first signal transmission unit. In 6 an n-2nd signal transmission unit ST(n-2) may be the first signal transmission unit receiving the start signal VST.

The signal transmission units ST(n-2), ST(n-1), ST(n), ST(n+1) and ST(n+2) each receive a start pulse or carry signals Cout(n-2), Cout(n -1), Cout(n), Cout(n+1) and Cout(n+2) output from a previous signal sending unit and receive the shift clock CLK. The activation of a first signal transmission unit ST(n-2) begins according to the start pulse VST and the other signal transmission units ST(n-1), ST(n), ST(n+1) and ST(n+2) each receive the carry signals Cout (n-2), Cout(n-1), Cout(n) and Cout(n+1) from the previous signal sending unit to start driving. The shift clock CLK may be an N-phase clock (N is a positive integer greater than or equal to 2). For example, the shift clock CLK can be a two-phase clock CLK1 and CLK2. The phases of the two-phase shift clocks CLK1 and CLK2 are opposite to each other.

The signal transmission units ST(n-2) to ST(n+2) can output a carry signal Cout via second output nodes while outputting EM pulses EMOUT(n-2) to EMOUT(n+2) via the first output node, respectively.

7 12 is a circuit diagram detailing the gate driver according to the third embodiment of the present disclosure. one inside 7 The circuit shown is a circuit of an nth (n is a positive integer) signal transmission unit ST(n). Other signal transmission units can be implemented with circuits that are essentially the same as the nth signal transmission unit ST(n). 8th is a waveform diagram showing input/output signals and voltages of control nodes of the in 7 gate driver shown. Here, an example in which the gate driver is implemented as an EM driver will be described.

With reference to 7 and 8th The EM driver according to the embodiment may include a first control node (hereinafter referred to as “Q node”), a second control node (hereinafter referred to as “Qb node”), a first circuit unit 71, a second circuit unit 72, and an output unit 73 include.

The first circuit unit 71 serves to control charging and discharging of the Q node Q and the Qb node Qb(n). When a shift clock EMCLK has a voltage greater than or equal to a gate-on voltage VGH, the first circuit unit 71 supplies a voltage of an n-1th carry signal C(n-1) from an n-1th signal sending unit ST (n-1), which is a previous signal sending unit, to a first control node Q to charge the first control node Q. This first circuit unit 71 includes first through third transistors T1, T1A and T3q.

The first transistor T1 is turned on to supply the voltage of the carry signal C(n-1) to a buffer node Qh when the shift clock EMCLK is the gate-on voltage VGH. The first transistor T1 comprises a first electrode connected to a line for the n-1th carry signal C(n-1), a gate electrode to which the shift clock EMCLK is applied, and a second electrode connected to connected to buffer node Qh.

The second transistor T1A is turned on to supply a voltage of the buffer node Qh to the first control node Q to charge the first control node Q when the shift clock EMCLK is the gate-on voltage VGH. The second transistor T1A includes a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock EMCLK is applied, and a second electrode connected to the first control node Qh.

The first and second transistors T1 and T1A are connected in series. The first and second transistors T1 and T1A are connected in series between the n-1th carry signal line C(n-1) and the buffer node Qh.

The third transistor T3q is turned on to supply the second high-potential voltage to the buffer node Qh via a second high-potential voltage line GVDD1 when the first control node Q is charged. The second high-potential voltage is supplied to the buffer node Qh via the second high-potential voltage line GVDD1. The third transistor T3q includes a first electrode connected to the second high-potential voltage line GVDD1, a gate electrode connected to the first control node Q, and a second electrode connected to the buffer node Qh.

The second circuit unit 72 includes an inverting circuit that inverts a voltage of the first control node Q and applies the inverted voltage to the second control node Qb(n). The inverter circuit of the second circuit unit 72 includes a first Qb logic generator and a second Qb logic generator.

The first Qb logic generator includes several transistors T4 and T41. The second Qb logic generator includes multiple transistors T4q and T5q, and multiple transistors T4q and T5q are connected in series.

The first Qb logic generator switches a current path between the second high potential voltage line GVDD1 and the second control node Qb(n) according to a voltage of a Qb node Qb(n-1) from the n-1th signal transmission unit ST(n-1).

A fourth transistor T4 is turned on to charge the Qb node Qb(n) to the gate-on voltage VGH by connecting the second high-potential voltage line GVDD1 to the Qb node Qb(n) when a first node voltage n1 is the gate on voltage VGH. The fourth transistor T4 includes a first electrode connected to the second high-potential voltage line GVDD1, a gate electrode connected to the first node n1, and a second electrode connected to the Qb node Qb(n). A first capacitor C1 is connected between the gate electrode and the second electrode of the fourth transistor T4. When the fourth transistor T4 is turned on by the first capacitor C1, the voltage of the first node n1 can be boosted.

A fourth-1 transistor T41 is turned on when the voltage of the Qb node Qb(n-1) of the n-1th signal transmission unit ST(n-1) is the gate-on voltage VGH to the first node n1 to the gate-on voltage VGH by supplying the second high-potential voltage to the first node n1. The fourth-1st transistor T41 includes a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the Qb node Q(n-1) of the n-1th signal sending unit ST(n- 1) and a second electrode connected to the first node n1.

The second Qb logic generator is turned on to discharge the Qb node Qb(n) when the voltage of the Q node Q and the voltage of the previous carry signal C(n-1) resulting from the n-1 th signal transmission unit ST(n-1) is input, the gate-on voltage are VGH.

A fourth-qth transistor T4q is turned on to connect the first node n1 to the Qb node Qb(n) when the voltage of the buffer node Qh is the gate-on voltage VGH. The fourth-qth transistor T4q includes a first electrode connected to the first node n1, a gate electrode connected to the buffer node Qh, and a second electrode connected to the Qb node Qb(n) connected is.

A fifth-qth transistor T5q is turned on to discharge the voltage of the Qb node Qb(n) to a second low-potential voltage by connecting the Qb node Qb(n) to a second low-potential voltage line GVSS1 when the voltage of the buffer node Qh is the gate-on voltage VGH. The fifth-qth transistor T5q includes a first electrode connected to the Qb node Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low-potential voltage line GVSS1 connected is.

The output unit 73 may output an emission control signal EMOUT to the first output node and output a carry signal COUT(n) to the second output node based on potentials of the Q node Q and the Qb node Qb(n). The output unit 73 may include a first pull-up transistor T6, a first pull-down transistor T7, a second pull-up transistor T6cr, and a second pull-down transistor T7cr.

The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of the Q node Q and the Qb node Qb(n) to output the emission control signal EMOUT. The first pull-up transistor T6 includes a gate electrode connected to the first control node Q, a first electrode connected to a first high-potential voltage line GVDD to which a first high-potential voltage is applied, and a second electrode connected to the first high-potential voltage line GVDD connected to the first output node. The second capacitor C2 is connected between the gate electrode and the second electrode of the first pull-up transistor T6. The first pull-down transistor T7 is connected to the first pull-up transistor T6 with the first output node in between. The first pull-down transistor T7 includes a gate electrode connected to a second control node Qb(n), a first electrode connected to the first output node, a back-gate electrode receiving the carry signal from a previous signal transmission unit, and a second electrode connected to a first low-potential voltage line GVSS0 to which a first low-potential voltage is applied.

The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of the Q node Q and the Qb node Qb(n) to output the carry signal COUT(n). The second pull-up transistor T6cr includes a gate electrode connected to the Q node Q, a first electrode connected to the second high-potential voltage line GVDD1 to which the second high-potential voltage is applied, and a second electrode, which is connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node in between. The second pull-down transistor T7cr includes a gate electrode connected to the Qb node Qb(n), a first electrode connected to the second output node den, a back gate electrode which receives the carry-over signal from a previous signal transmission unit, and a second electrode which is connected to the second low-potential voltage line GVSS1m to which the second low-potential voltage is applied.

A structural advantage of the output unit applied to the EM driver according to the embodiment will be described.

9A until 9C 12 are views for comparatively describing a principle of reducing leakage current of an output unit.

With reference to 9A the first pull-down transistor T7 and the second pull-down transistor T7cr of the output unit according to the embodiment are in a double gate structure using an LS metal layer, which is a light blocking layer of a coplanar element, as a back gate Electrode for receiving the negative bias, ie a carry signal C(n-2) with a gate low voltage, from the scan driver on the back gate electrode during turn-off when the Qb node Qb(n) is discharged and implemented a threshold voltage Vth of each of the first pull-down transistor T7 and the second pull-down transistor T7cr increases due to the negative bias and accordingly the leakage current is reduced.

like it in 9B As shown in FIG. Transistor T7cr is turned off when the second control node is discharged and a low voltage level carry signal SC_C(n-2) is applied to the second-1st pull-down transistor T8cr since the threshold voltage is shifted to a negative polarity and the carry signal SC_C (n-2) of the low voltage level leaks as much as a threshold voltage Δ, a leakage current as large as the threshold voltage Δ can also be generated from a gate-source voltage Vgs of the two-1st pull-down transistor T8cr and the power consumption increases accordingly.

In this case, in the circuit of the comparative example, as much leakage current as a threshold voltage, i.e. H. Vth(Δ), is generated, but in the circuit of the embodiment, as much leakage current as Vth × 0.42 is generated and is thus reduced. The leakage current generated in the circuit of the embodiment is reduced due to an effect of the double gate structure, and is reduced in proportion to a capacitance ratio (0.42) of an upper gate and a lower gate. The capacitance ratio of the top gate and the bottom gate may vary according to various design parameters such as a length, a thickness, a width, and the like of the top gate and the bottom gate, respectively.

In this case, the leakage current is reduced in proportion to the capacitance ratio of the upper gate and the lower gate, and thus can be effective only when an upper gate capacitance is smaller than a lower gate capacitance.

In the embodiment, the pull-down transistor T7 and the second pull-down transistor T7cr are activated by applying signals applied to a one-1st pull-down transistor T8 and a two-1st pull-down transistor T8. Transistor T8cr of the comparative example designed to back gate electrodes of the first pull-down transistor T7 and the second pull-down transistor T7cr, also as the one-1st pull-down transistor T8 and the two-1- te pull-down transistor T8cr to serve.

Since the transistors T8 and T8cr in the circuit of the embodiment in 9A compared to the circuit of the comparative example in FIG 9B are removed, a leakage current generation path can decrease and a case is reduced by the decrease. In this case, the circuit of the embodiment requires a size increase of the transistor in order to maintain a drooping characteristic equal to that of the circuit of the comparative example, but an amount of leakage current is reduced and thus there is an advantage in improving power consumption and improving a Output.

like it in 9C 1, since the leakage current is generated toward the output node from which the carry signal COUT(n) is output, a difference occurs between a target voltage of the output node and an actual voltage in the circuit of the comparative example. On the other hand, in the circuit of the embodiment, there is no difference between the target voltage of the output node and the actual voltage.

10 is a view showing a simulation result using the in 7 shown EM driver.

With reference to 10 A result of simulation using the EM driver according to the embodiment is shown. It can be seen that the leakage current in the low potential voltage line is reduced more in the circuit of the embodiment than in the circuit of the comparative example. In addition, it can be seen that the leakage current at the output node from which the carry signal is output is also reduced more in the circuit of the embodiment than in the circuit of the comparative example.

11 12 is a block diagram illustrating a display device according to an embodiment of the present disclosure, and 12 Fig. 12 is a diagram showing a cross-sectional structure of Figs 11 shown scoreboard.

With reference to 11 and 12 For example, the display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

The display panel 100 may be a display panel having a rectangular structure with a length in an X-axis direction, a width in a Y-axis direction, and a thickness in a Z-axis direction. The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power lines may include a power line to which a pixel drive voltage ELVDD is applied, a power line to which an initialization voltage Vinit is applied, a power line to which a reference voltage Vref is applied, and a power line to which a low-potential power voltage ELVSS is applied. These power lines are commonly connected to the pixels.

The pixel array AA includes multiple pixel rows L1 through Ln. Each of the pixel lines L1 to Ln includes a line of pixels arranged along a line direction X in the pixel array AA of the display panel 100 . Pixels arranged in a pixel row share the gate lines 103. Pixels arranged in a column direction Y along a data line direction share the same data line 102. A horizontal period 1H is a time obtained by dividing a frame period is obtained by the total number of pixel lines L1 to Ln.

The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on a screen and an actual background is seen.

The billboard 100 can be implemented as a flexible billboard. The flexible scoreboard can be made of a plastic OLED panel. An organic thin film can be arranged on a back plate of the plastic OLED panel, and the pixel array AA and the light-emitting element can be formed on the organic thin film.

In order to implement color, each of the pixels 101 may be divided into a red sub-pixel (hereinafter referred to as “R sub-pixel”), a green sub-pixel (hereinafter referred to as “G sub-pixel”), and a blue sub-pixel (hereinafter referred to as “B -sub-pixel") be subdivided. Each of the pixels may also include a white sub-pixel. Each of the sub-pixels includes a pixel circuit. The pixel circuit is connected to the data line, the gate line and the power line.

The pixels can be arranged as true color pixels and pentil pixels. The pentil pixel can realize a higher resolution than the true color pixel by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color representation in each pixel with a light color emitted from a neighboring pixel.

Touch sensors may be placed on display panel 100 . Touch input can be captured using separate touch sensors or can be captured by pixels. The touch sensors may be implemented as an on-cell type or add-on type on the screen of the display panel, or implemented as an in-cell type of touch sensors embedded in the pixel array AA.

like it in 12 As shown, the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10 when viewed from a cross-sectional structure.

The circuit layer 12 may include a pixel circuit connected to wirings such as a data line, a gate line, and a power line, a gate driver (GIP) connected to the gate lines, and the like. The wiring and Circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers separated by the insulating layer therebetween, and an active layer containing a semiconductor material.

The light-emitting element layer 14 may include a light-emitting element EL that is driven by a pixel circuit. The light-emitting element EL may include a red light-emitting element (R element), a green light-emitting element (G element), and a blue light-emitting element (B element). The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a protective layer comprising an organic film and a passivation film.

Encapsulation layer 16 covers light emitting element layer 14 to seal circuit layer 12 and light emitting element layer 14 . The encapsulation layer 16 may have a multilayer insulating structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, a movement path of moisture or oxygen becomes longer compared to a single layer, so that penetration of moisture and oxygen affecting the light-emitting element layer 14 is effectively blocked can.

A touch-sensing layer may be disposed on encapsulation layer 16 . The touch-sensing layer may include capacitive-type touch sensors that detect touch input based on a capacitance change before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating layers that form the capacitance of the touch sensors. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate can improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12. The polarizing plate can be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are connected, or a circular polarizing plate. A cover glass can be glued to the polarizing plate.

The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16 . The color filter layer may include red, green and blue color filters and a black matrix pattern. The color filter layer can replace the polarizing plate and increase color purity by absorbing part of the wavelength of light reflected from the circuit layer and touch sensor layer. In this embodiment, by applying the color filter layer 20, which has a higher light transmittance than the polarizing plate, to the display panel, the light transmittance of the display panel 100 can be improved, and the thickness and flexibility of the display panel 100 can be improved. A cover glass can be glued to the color filter layer.

The power supply 140 generates direct current necessary to drive the pixel array AA and the display panel driver of the display panel 100 using a DC-DC converter. The DC-to-DC converter may include a charge pump, a regulator, a down-converter, a boost-converter, and the like. The power supply 140 can adjust an input DC voltage from a host system (not shown), thereby supplying DC voltages such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, a pixel drive voltage ELVDD, a pixel generate low-potential power-supply voltage ELVSS, a reference voltage Vref, an initial voltage Vinit, an anode voltage Vano, and the like. The gamma reference voltage VGMA is supplied to a data driver 110 . Gate on voltages VGH and VEH and gate off voltages VGL and VEL are supplied to a gate driver 120 . The pixel drive voltage ELVDD and the pixel low potential power supply voltage ELVSS, a reference voltage Vref, an initial voltage Vinit, an anode voltage Vano, and the like are commonly supplied to the pixels.

The panel driver writes pixel data (digital data) of an input image into the pixels of the panel 100 under the control of a timing controller (TCON) 130.

The panel driver includes the data driver 110 and the gate driver 120. A panel driver may further include a demultiplexer arrangement 112 disposed between a data driver 110 and data lines 102. FIG.

The demultiplexer array 112 sequentially provides data voltages output from channels of the data driver 110 to the data lines 102 using multiple demultiplexers (DEMUXs). If the demultiplexers are arranged between output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 can be reduced. The demultiplexer arrangement 112 can be omitted.

The display panel driver may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is in 1 omitted. The touch sensor driver may be integrated into a driver integrated circuit (driver IC). In a mobile or portable device, the timing controller 130, power supply 140, data driver 110, touch sensor driver, and the like may be integrated into a driver integrated circuit (IC).

A panel driver may operate under the control of a timing controller (TCON) 130 in a low speed drive mode. The low-speed drive mode can be set to reduce power consumption of a display device when there is no change in an input image for a preset number of frames in the analysis of the input image. In the low-speed drive mode, power consumption of the panel driver and a panel 100 can be reduced by reducing a refresh rate of pixels when a still image is input for a predetermined time or longer. A low-speed drive mode is not limited to a case where a still image is input. For example, when the display device is operating in a standby mode or when no user command or input image is input to a panel driver for a predetermined time or longer, the panel driver may operate in the low-speed drive mode.

The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage every frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided by a voltage divider circuit for respective gray levels. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the data driver 110 DAC. The data voltage Vdata is output through the output buffer AMP in each of the data driver 110 channels.

The gate driver 120 may be implemented as a gate-in-panel (GIP) circuit formed directly on a circuit layer 12 of the display panel 100 together with the TFT array of the pixel array AA. The gate-in-panel (GIP) circuit may be arranged on a border area BZ, which is a non-display area of the display panel 100, or distributed in the pixel array on which an input image is displayed. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 can sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include sample pulses, emission control pulses (hereinafter referred to as “EM pulses”), initial pulses, and detection pulses.

The shift register of the gate driver 120 outputs a pulse of the gate signal in response to a start pulse and a shift clock from the timing controller 130 and shifts the pulse according to the shift clock timing.

In this case, the gate driver 120 can be implemented as a gate driver capable of reducing a leakage current while reducing the number of transistors, as shown in FIG 1 , 3 , 6 and 8th is shown. In the present invention, all the transistors in the display panel including the data driver, the gate driver and the sub-pixels can be implemented with oxide thin film transistors (oxide TFTs) containing an n-channel type oxide semiconductor.

The timing controller 130 receives from a host system (not shown) digital video data DATA of an input image and a timing signal synchronized therewith. The clock signal includes a vertical sync signal Vsync, a horizontal sync signal Hsync, a master clock CLK, a data enable signal DE, and the like. Since a vertical period and a horizontal period can be known by counting the data enable signal DE, the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync can be omitted. The data enable signal DE has a cycle of one horizontal period (1H).

A host system can be a television system (TV system), a tablet computer, a notebook A computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100 and send the image signal to a timing controller 130 along with the timing signal.

The timing controller 130 multiplies an input frame frequency by i and controls the operation timing of the panel drive circuit with a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC scheme (scheme of the Committee for national television standards) and 50 Hz in the PAL (Phase Alternating Lines) scheme. The timing controller 130 may decrease a driving frequency of the panel driver by dropping a frame frequency to a frequency between 1 Hz and 30 Hz to decrease a refresh rate of pixels in the low-speed driving mode.

Based on the timing signals Vsync, Hsync and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer arrangement 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls an operational timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, a touch sensor driver and a gate driver 120.

The voltage level of the gate timing control signal output from the timing controller 130 can be converted into the gate on voltages VGH and VEH and the gate off voltages VGL and VEL by a level shifter (not shown) and then to the Gate driver 120 are provided. That is, the level shifter converts a low-level voltage of the gate timing control signal into gate-off voltages VGL and VEL, and converts a high-level voltage of the gate timing control signal into gate-on voltages VGH and VEH. The gate timing control signal includes the start pulse and the shift clock.

Due to process variations and device characteristic variations caused in a manufacturing process of the display panel 100, there may be a difference in electrical characteristics of the driving element between pixels, and this difference may increase as the driving time of the pixels elapses. An internal compensation technology or an external compensation technology can be applied to an organic light emitting diode display to compensate for the variations in electrical characteristics of a driving element between pixels. The internal compensation technology samples a threshold voltage of the driver for each sub-pixel using an internal compensation circuit implemented in each pixel circuit to compensate a gate-source voltage Vgs of the driver as much as the threshold voltage. The external compensation technology detects in real time a current or a voltage of the driver, which changes according to the electric characteristics of the driver, using an external compensation circuit. The external compensation technology compensates for the variations (or changes) in the electrical properties of the drive element in each pixel in real time by capturing the pixel data (digital data) of the input image as much as the variations (or changes) in the electrical properties of the drive element recorded for each pixel become, be modulated. The panel driver can drive the pixels using external compensation technology and/or internal compensation technology. A pixel circuit of the present disclosure may be implemented as a pixel circuit to which an internal compensation circuit is applied.

13 is a circuit diagram showing a pixel circuit based on an in 11 scoreboard shown is applied, and 14 is a waveform diagram showing a driving method of FIG 13 pixel circuit shown.

With reference to 13 and 14 For example, the pixel circuit may include a light-emitting element EL, a driving element DT that drives the light-emitting element EL, a plurality of switching elements MO1, MO2, MO3, and MO4, and a capacitor Cst.

This pixel circuit is provided with a first power line PL1 to which a pixel drive voltage EVDD is applied, a second power line PL2 to which a low-potential power voltage EVSS is applied, a third power line PL3 to which an initialization voltage Vinit is applied, a fourth power line PL4 to which a reference voltage Vref is applied, a data line DL to which a data voltage Vdata is applied, and gate lines to which gate signals INIT(n), SENSE(n), SCAN(n) and EM(n) are applied, tied together. the gate Signals INIT(n), SENSE(n), SCAN(n) and EM(n) can be generated by the gate driver according to the embodiment and applied to the pixel circuit via the gate lines.

The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode electrode of the light-emitting element EL is connected to a third node n3, and the cathode electrode is connected to a second power line PL2 to which a low-potential power voltage EVSS is applied. When a voltage is applied to the anode and cathode electrodes of the light-emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer (EML) and form an exciton, which thereby emits visible light in the emission layer (EML).

An organic light emitting diode used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. The organic light emitting diode with the tandem structure can improve the luminance and lifetime of the pixel.

The driving element DT generates a current according to a gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

A first switching element M01 is turned on according to a gate-on voltage VGH of a scan pulse SCAN(n) to apply the data voltage to the second node n2. The first switching element M01 includes a first electrode connected to the data line DL to which the data voltage is applied, a gate electrode to which the scanning pulse SCAN(n) is applied, and a second electrode connected to the second node n2 is connected.

A second switching element MO2 is turned on according to a gate-on voltage VGH of an initialization pulse INIT(n) to apply the initialization voltage to the second node n2. The second switching element M02 includes a first electrode connected to the third power line PL3 to which the initialization voltage is applied, a gate electrode to which the initialization pulse INIT(n) is applied, and a second electrode connected to the second Node n2 is connected.

A third switching element MO3 is turned on according to a gate-on voltage VGH of a sense pulse SENSE(n) to apply the reference voltage to the third node n3. The third switching element M03 includes a first electrode connected to the third node n3, a gate electrode to which the detection pulse is applied, and a second electrode connected to the fourth power line PL4 to which the reference voltage is applied .

A fourth switching element MO4 is turned on according to a gate-on voltage VGH of an emission control pulse EM(n) to apply the pixel drive voltage to the first node n1. The fourth switching element M04 includes a first electrode connected to the first power line to which the pixel drive voltage is applied, a gate electrode to which the emission control pulse is applied, and a second electrode connected to the first node n1.

A capacitor Cst is connected between the second node n2 and the third node n3. In the present invention, the first and second high-potential voltage lines may be collectively referred to as a high-potential voltage line, and the first, second, and third low-potential voltage lines may collectively be referred to as a low-potential voltage line.

like it in 14 As shown, the pixel circuit can be driven in the order of initialization operation Ti, detection operation Ts, data write operation Tw, and light emission operation Tem. In the detection operation Ts, a threshold voltage Vth of the driving element DT is detected and stored in the capacitor Cst. In the data write operation Tw, the data voltage Vdata of the pixel data is applied to the second node n2. In the light emitting operation Tem, the light emitting element EL can emit light having a luminance corresponding to a gray level value of the pixel data.

Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in various forms without departing from the technical concept of the present disclosure. Therefore, in the present Revelation The embodiments disclosed in the above are provided for illustration purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited to this. Therefore, it is to be understood that the embodiments described above are in all aspects illustrative and not limiting of the present disclosure. The scope of the present disclosure should be construed based on the following claims, and all technical concepts in the equivalent scope thereof should be construed as falling within the scope of the present disclosure.

Claims (14)

Gate driver comprising a plurality of signal sending units (ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2)) connected via a carry line to which a carry signal (Cout(n)) is applied from a previous signal sending unit are connected in cascade, wherein an nth signal sending unit (ST(n)), where n is a positive integer, comprises: a first circuit unit (61, 71) including a first Q logic generator (61a) adapted to receive the carry signal from the previous signal sending unit to load a first control node (Q), and a second Q logic a logic generator (61b) configured to discharge the first control node (Q); a second circuit unit (62, 72) configured to discharge a second control node (Qb) according to a voltage of the first control node (Q); and an output unit (63) designed to output the carry signal (Cout(n)) and a gate signal (SCOUT(n)) based on potentials of the first control node (Q) and the second control node (Qb), wherein the second Q-logic generator (61b) comprises: a second 1st transistor (T3) having a first electrode connected to said first control node (Qb), a gate electrode connected to said second control node (Qb), a back gate electrode connected to receives the carry signal (Cout(n)) from a next signal sending unit, and a second electrode connected to a buffer node (Qh); and a second 2nd transistor (T3A) having a first electrode connected to the buffer node (Qh), a gate electrode connected to the second control node (Qb), a back gate electrode connecting the receiving carry signal (Cout(n)) from the next signal sending unit, and a second electrode connected to a low potential voltage line (GVSS2). gate driver after claim 1 , wherein the second-1st and second-2nd transistors (T3, T3A) are turned on by a charge voltage of the second control node (Qb) to discharge the first control node (Q) to a low potential voltage, and a carry signal ( C(n+2)) receive a gate low voltage from the next signal sending unit on the back gate electrode while they are turned off when the second control node (Qb) is discharged. gate driver after claim 1 or 2 , the second Q-logic generator further comprising: a second-3rd transistor (T3nB) having a first electrode connected to the first control node (Q), a gate electrode receiving a start signal (VST). , and a second electrode connected to the buffer node (Qh); and a second-4th transistor (T3nC) having a first electrode connected to the buffer node (Qh), a gate electrode receiving the start signal (VST) and a second electrode connected to the low potential voltage line (GVSS2 ) connected is. gate driver after claim 3 wherein the first Q-logic generator (61a) comprises: a one-1st transistor (T1) having a first electrode and a gate electrode receiving the carry signal (C(n-2)) from the previous signal sending unit , and a second electrode connected to the buffer node (Qh); a one-2nd transistor (T1A) having a first electrode connected to the buffer node (Qh), a gate electrode receiving the carry signal (C(n-2)) from the previous signal sending unit, and a second electrode connected to the first control node (Q); and a one-3rd transistor (T3q) having a first electrode connected to a high potential voltage line (GVDD) to which a high potential voltage is applied, a gate electrode connected to the first control node (Q), and a second electrode connected to the buffer node (Qh). gate driver after claim 4 , wherein the second circuit unit (62) comprises: a three-1st transistor (T4) having a first electrode connected to the high potential voltage line (GVDD), a gate electrode connected to a first node (n1). , and a second electrode connected to the second control node (Qb); a third-2nd transistor (T41) having a first electrode and a gate electrode connected to said high potential voltage line (GVDD) and a second electrode connected to said first node (n1); a third-3rd transistor (T4q) with a first electrode connected to the first node (n1), a gate electrode connected to the first control node (Q) and a second electrode to which a low potential voltage (GVSS 1) is applied; a third-fourth transistor (T5q) having a first electrode connected to the second control node (Qb), a gate electrode connected to the first control node (Q) and a second electrode to which the low potential voltage (GVSS2) is applied; and a third-fifth transistor (T5) having a first electrode connected to the second control node (Qb), a gate electrode to which the carry signal (C(n-2)) from the previous signal sending unit is applied , and a second electrode to which the low potential voltage (GVSS2) is applied. gate driver after claim 5 , wherein the output unit (63) comprises: a first pull-up transistor (T6) having a first electrode to which a first clock signal (SCCLK(n)) is applied, a gate electrode connected to the first control node (Q ) is connected, and a second electrode connected to a first output node; a first pull-down transistor (T7) having a first electrode connected to the first output node, a gate electrode connected to the second control node (Qb), and a second electrode to which a first low-potential voltage is applied is; a second pull-up transistor (T6cr) having a first electrode to which a second clock signal (SC_CRCLK(n)) is applied, a gate electrode connected to the first control node (Q) and a second electrode, connected to a second output node; and a second pull-down transistor (T7cr) having a first electrode connected to the second output node, a gate electrode connected to the second control node (Qb), and a second electrode to which a second low-potential voltage is applied is created. A gate driver as claimed in any preceding claim, wherein the second circuit unit (72) comprises an inverter circuit which inverts a voltage of the first control node (Q) and applies the inverted voltage to the second control node (Qb). gate driver after claim 7 , wherein the inverter circuit includes a first Qb logic generator and a second Qb logic generator, the first Qb logic generator having a fourth transistor (T4) having a first electrode connected to a high-potential voltage line (GVDD1), a gate electrode connected to a first node (n1) and a second electrode connected to the second control node (Qb); and a fourth-1st transistor (T41) having a first electrode connected to the high potential voltage line (GVDD 1), a gate electrode connected to the second control node (Qb) of the previous signal transmission unit, and a second electrode connected to the first node (n1), and wherein the second Qb logic generator comprises a fourth q-transistor (T4q) having a first electrode connected to the first node (n1), a gate - an electrode connected to the buffer node (Qh) and a second electrode connected to the second control node (Qb); and a fifth q-transistor (T5q) having a first electrode connected to the second control node (Qb), a gate electrode connected to the buffer node (Qh), and a second electrode connected to the low potential voltage line ( GVSS1) is connected having. gate driver after claim 8 , wherein the first Qb logic generator further comprises a capacitor (C1) connected between the gate electrode and the second electrode of the fourth transistor (T4). Gate driver comprising a plurality of signal sending units (ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2)) connected via a carry line at which a carry signal (Cout(n)) is applied from a previous signal sending unit, are connected in cascade, wherein an nth signal sending unit (ST(n)), where n is a positive integer, comprises: a circuit unit (70) which is adapted to receive the carry signal from the previous signal sending unit (ST(n)) to charge or discharge voltages of a first control node (Q) and a second control node (Qb); and an output unit (73) configured to output a gate signal (EMout) and the carry signal (Cout(n)) based on potentials of the first control node (Q) and the second control node (Qb), the output unit ( 73) comprises: a first pull-up transistor (T6) having a first electrode connected to a first high potential voltage line (GVDD0), a gate electrode connected to the first control node (Q) and a second electrode connected to a first output node; a first pull-down transistor (T7) having a first electrode connected to the first output node, a gate electrode connected to the second control node (Qb), a back gate electrode outputting the carry signal a previous signal sending unit receiving, and a second electrode connected to a first low potential voltage line (GVSS0); a second pull-up transistor (T6cr) having a first electrode connected to a second high potential voltage line (GVDD1), a gate electrode connected to the first control node (Q) and a second electrode connected to a second output node is connected; and a second pull-down transistor (T7cr) having a first electrode connected to the second output node, a gate electrode connected to the second control node (Qb), a back gate electrode connecting the carry signal received from the next signal sending unit, and a second electrode connected to a second low potential voltage line (GVSS1). gate driver after claim 10 , wherein the first and second pull-down transistors (T7, T7cr) are turned on by a charge voltage of the second control node (Qb) to discharge the first output node to a low potential voltage, and a carry signal with a gate low voltage from the next To receive signal sending unit at the back gate electrode while they are turned off when the second control node (Qb) is discharged. gate driver after claim 10 or 11 , wherein the circuit unit (70) comprises a first circuit unit (71) which is adapted to receive the carry signal from the previous signal transmission unit in order to charge the first control node, the first circuit unit (71) comprising: a first transistor (T1 ) having a first electrode receiving the carry signal (C(n-1)) from the previous signal sending unit, a gate electrode to which a clock signal (EMCLK) is applied, and a second electrode connected to a buffer node (Qh) connected is; a second transistor (T1A) having a first electrode connected to the buffer node (Qh), a gate electrode to which the clock signal (EMCLK) is applied and a second electrode connected to the first control node (Q). is; and a third transistor (T3q) having a first electrode connected to the second high potential voltage line (GVDD1) to which a second high potential voltage is applied, a gate electrode connected to the first control node (Q) and a second Electrode connected to buffer node (Qh). gate driver after claim 12 , wherein the circuit unit (70) comprises a second circuit unit (72) configured to discharge the second control node (Qb) according to a voltage of the first control node, the second circuit unit (72) comprising: a fourth transistor (T4) a first electrode connected to the second high potential voltage line (GVDD1), a gate electrode connected to a first node (n1) and a second electrode connected to the second control node (Qb); a fifth transistor (T41) having a first electrode connected to the second high-potential voltage line (GVDD1), a gate electrode to which a voltage of the second control node (Qb) from the previous signal transmission unit is applied, and a second electrode which connected to the first node (n1); a sixth transistor (T4q) having a first electrode connected to the first node (n1), a gate electrode connected to the buffer node (Qh) and a second electrode connected to the second control node (Qb) connected is; and a seventh transistor (T5q) having a first electrode connected to the second control node (Qb), a gate electrode connected to the buffer node (Qh), and a second electrode connected to the second low potential voltage line (GVSS 1) is connected to which a second low-potential voltage is applied. Display device comprising: a display panel (100) on which multiple data lines (102), multiple gate lines (103) crossing the data lines (102), multiple power lines to which different constant voltages (ELVDD, Vinit, Vref, ELVSS) are applied, and a plurality of sub-pixels (R, B, G) are arranged; a data driver configured to supply a data voltage of pixel data to the data lines (102); and a gate driver according to any one of the preceding claims, arranged to supply a gate signal to the gate lines (103).

Images