DE102021106311A1 - INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THEM - Google Patents

Abstract

One method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region over the substrate. An etch stop layer is selectively formed over the dielectric cap such that the etch stop layer exposes the source/drain contact. An interlayer dielectric is formed over the etch stop layer and the source/drain contact. A source/drain via is formed in the ILD and connected to the source/drain contact.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority from U.S. Provisional Patent Application No. 63/084,999 , filed September 29, 2020, which is incorporated herein by reference.

BACKGROUND ART

Technological advances in IC materials and design have produced generations of ICs in which each generation has smaller and more complex circuitry than the previous generation. As ICs have evolved, functional density (that is, the number of interconnected devices per chip area) has typically increased while geometric size (that is, the smallest component (or line) that can be created using a manufacturing process) has decreased Has. This downsizing process typically provides benefits by increasing production efficiency and reducing associated costs.

character list

• Die 1 - 16B stellen perspektivische Ansichten und Querschnittsansichten von Zwischenstadien der Bildung einer integrierten Schaltungsstruktur im Einklang mit einigen Ausführungsformen der vorliegenden Offenbarung dar.
• Die 17 - 18B stellen beispielhafte Querschnittsansichten verschiedener Stadien zur Herstellung einer integrierten Schaltungsstruktur im Einklang mit einigen anderen Ausführungsformen der vorliegenden Offenbarung dar.
• Die 19 - 21 stellen beispielhafte Querschnittsansichten verschiedener Stadien zur Herstellung einer integrierten Schaltungsstruktur im Einklang mit einigen anderen Ausführungsformen der vorliegenden Offenbarung dar.
• Die 22 - 25 stellen beispielhafte Querschnittsansichten verschiedener Stadien zur Herstellung einer integrierten Schaltungsstruktur im Einklang mit einigen anderen Ausführungsformen der vorliegenden Offenbarung dar.
• Die 26 - 43B stellen perspektivischen Ansichten und Querschnittsansichten von Zwischenstadien der Bildung einer integrierten Schaltungsstruktur im Einklang mit einigen Ausführungsformen der vorliegenden Offenbarung dar.
• Die 44A und44B sind Querschnittsansichten integrierter Schaltungsstrukturen im Einklang mit einigen Ausführungsformen.
• Die 45 - 48 stellen beispielhafte Querschnittsansichten verschiedener Stadien zur Herstellung einer integrierten Schaltungsstruktur im Einklang mit einigen anderen Ausführungsformen der vorliegenden Offenbarung dar.

Aspects of the present disclosure are best understood by considering the following detailed description when taken in connection with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily exaggerated or minimized for the sake of clarity of explanation.

• the 1 - 16B 12 illustrate perspective and cross-sectional views of intermediate stages in the formation of an integrated circuit structure consistent with some embodiments of the present disclosure.
• the 17 - 18B 12 illustrate exemplary cross-sectional views of various stages in fabricating an integrated circuit structure consistent with some other embodiments of the present disclosure.
• the 19 - 21 12 illustrate exemplary cross-sectional views of various stages in fabricating an integrated circuit structure consistent with some other embodiments of the present disclosure.
• the 22 - 25 12 illustrate exemplary cross-sectional views of various stages in fabricating an integrated circuit structure consistent with some other embodiments of the present disclosure.
• the 26 - 43B 12 illustrate perspective and cross-sectional views of intermediate stages in the formation of an integrated circuit structure consistent with some embodiments of the present disclosure.
• the 44A and 44B 12 are cross-sectional views of integrated circuit structures consistent with some embodiments.
• the 45 - 48 12 illustrate exemplary cross-sectional views of various stages in fabricating an integrated circuit structure consistent with some other embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples, which should in no way be interpreted as a restriction. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact with one another, but may also include embodiments in which additional features are so formed between the first Feature and the second feature can be formed that the first and the second feature can not be in direct contact with each other. In addition, the present disclosure may repeat reference numerals and/or indicia throughout the various examples. This repetition is for the purpose of simplicity and clarity, and does not by itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, terms of spatial relationships such as "beneath", "beneath", "low", "above", "upper" and the like may be used herein for the purpose of simplifying the description of the relationship of an element or feature depicted in the figures to (an) other element(s) or characteristic(s). The terms of spatial relationships are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be displayed in other orientations (rotated 90 degrees or in other orientations). be ordered, and thus the terms of spatial relationships used herein can also be construed accordingly.

As used herein, the terms "about," "about," "approximately," or "substantially" mean typically within 20 percent, or within 10 percent, or within 5 percent of a specified value or range. Numerical references herein are approximate, meaning that the term "around," "about," "approximately," or "substantially" may be inferred unless expressly stated.

The present disclosure relates to integrated circuit structures and methods of forming the same in general, and more particularly to the fabrication of transistors (e.g., fin field effect transistors (FinFET), all around gate transistors (GAA transistors)) and source/drain vias via source/ drain contacts of the transistors. It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multiple gate devices may include a p-type metal oxide semiconductor device or an n-type metal oxide semiconductor device, among others. Certain examples may be presented herein and referred to as FinFETs due to their fin-like structure. A FinFET has a gate structure formed on three sides of a channel region (eg, wrapped around a top portion of a channel region in a semiconductor fin). Additionally, embodiments of a type of multi-gate transistor referred to as an all-around gate (GAA) device are presented herein. A GAA device includes any device whose gate structure, or portions thereof, is formed on 4 sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein may also have embodiments having channel regions arranged in one or more nanosheet channels, nanowire channels, and/or other suitable channel configurations.

After front-end-of-line (FEOL) processing for transistor fabrication is complete, source/drain contacts are formed over source/drain regions of the transistors. Then source/drain vias are formed over the source/drain contacts to electrically connect the source/drain contacts to subsequently formed interconnect metal lines. The formation of the source/drain vias may include depositing an interlayer dielectric (ILD) layer over the source/drain contacts, forming via openings extending through the ILD layer using an anisotropic etch, and then depositing one or more metal layers in the via openings to serve as the source/drain vias. To avoid over-etching the dielectric materials near the source/drain contacts during the anisotropic etch process, an additional etch stop layer may be selectively formed over the dielectric materials prior to forming the ILD layer. The selectively formed ESL has a different etch selectivity than the ILD layer, allowing the selectively formed ESL to slow down or even stop the etch process for forming the via openings, which in turn prevents over-etching of the dielectric materials underneath the ESL and thus leads to a reduced risk of leakage currents.

the 1 - 16B 10 illustrate perspective and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 100 in accordance with some embodiments of the present disclosure. In accordance with some example embodiments, the transistors formed may include a p-type transistor (such as a p-type FinFET) and an n-type Transistor (such as an n-FinFET) have. Similar reference numbers are used to identify similar elements throughout the various views and illustrative embodiments. It is understood that additional operations before, during and after the in the 1-16B process(es) shown may be provided, and that some of the operations described below may be substituted or eliminated for additional embodiments of the method. The order of operations/processes may be interchangeable.

1 FIG. 12 illustrates a perspective view of a structure. The structure includes a substrate 12. FIG. The substrate 12 may be a semiconductor substrate (also referred to as a wafer in some embodiments), which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. In accordance with some embodiments of the present disclosure, the substrate 12 comprises a bulk silicon substrate and a silicon germanium (SiGe) epitaxial layer or a germanium layer (which does not contain silicon) over the bulk silicon substrate. The substrate 12 may be doped with a p or an n impurity. Isolation regions 14, such as shallow trench isolation regions ture (STI regions) may be formed such that they extend into the substrate 12 . The portions of substrate 12 between adjacent isolation regions 14 are referred to as semiconductor strips 102 .

The isolation regions 14 may include an oxide isolation layer (not shown). The oxide separating layer may be formed by thermally oxidizing a surface layer of the substrate 12 from a thermal oxide. The oxide separation layer may also be a deposited silicon oxide layer, for example formed using atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The isolation regions 14 may also include a dielectric material over the oxide barrier layer, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

Referring to 2 the isolation regions 14 are recessed such that the top portions of the semiconductor strips 102 protrude higher than the top surfaces of the adjacent isolation regions 14 to form protruding fins 104. The etch can be performed using a dry etch process using NH ₃ and NF ₃ as the etching gases. Plasma can be generated during the etching process. Argon can also be used. Consistent with alternative embodiments of the present disclosure, the recessing of the isolation regions 14 is performed using a wet etch process. For example, the etchant chemistry may contain diluted HF.

In the example embodiments presented above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, such as double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithographic and self-aligned processes, thereby enabling the creation of structures having, for example, pitch dimensions that are smaller than those that would otherwise be achievable using a single, direct photolithographic process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along with the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers, or mandrels, can then be used to pattern the fins.

The materials of the protruding fins 104 can also be replaced with materials different from that of the substrate 12 . For example, if the protruding fins 104 are to serve as n-type transistors, the protruding fins 104 may be made of Si, SiP, SiC, SiPC, or a Group III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs or the like. On the other hand, if the protruding fins 104 are to serve as p-type transistors, the protruding fins 104 may be formed of Si, SiGe, SiGeB, Ge, or a group III-V compound semiconductor such as InSb, GaSb, InGaSb, or the like.

Referring to the 3A and 3B For example, dummy gate structures 106 have been formed on the top surfaces and sidewalls of the protruding fins 104. FIG. 3B represents a cross-sectional view obtained from a vertical plane containing the line B - B in 3A The formation of the dummy gate structures 106 includes the sequential deposition of a gate dielectric layer and a dummy gate electrode layer across the fins 104, followed by patterning of the gate dielectric layer and the dummy gate electrode layer . As a result of the patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 over the gate dielectric layer 108 . Gate dielectric layers 108 may be any acceptable dielectric layer such as silicon oxide, silicon nitride, the like, or a combination thereof, and may be formed using any acceptable process such as thermal oxidation, a spin coating process, CVD, or the like will. The dummy gate electrodes 110 can be any acceptable electrode layer including, for example, polysilicon, metal, the like, or a combination thereof. The gate electrode layer can be deposited using any acceptable deposition process, such as CVD, plasma enhanced CVD (PECVD), or the like. Each of the dummy gate structures 106 traverses a single or a plurality of the salient fins 104. The dummy gate structures 106 may also have longitudinal directions that extend perpendicular to the longitudinal directions of the respective salient fins 104.

A mask pattern may be formed over the dummy gate electrode layer to aid patterning. In some versions 1, a hard mask structure has lower masks 112 over a cap layer of polysilicon and upper masks 114 over the lower masks 112. The hard mask structure is made of one or more layers of SiO ₂ , SiCN, SiON, Al ₂ O ₃ , SiN or other suitable materials. In certain embodiments, bottom masks 112 include silicon oxide and top masks 114 include silicon nitride. By using the mask pattern as an etch mask, the dummy electrode layer is patterned into dummy gate electrodes 110 and the gate cap dielectric layer is patterned into gate dielectric layers 108 .

As in 4 1, gate spacers 116 are formed on sidewalls of dummy gate structures 106 next. In some embodiments of the gate spacer formation processes, a layer of spacer material is deposited on substrate 12 . The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers 116 . In some embodiments, the spacer material layer comprises multiple layers, such as a first spacer layer 118 and a second spacer layer 120 formed over the first spacer layer 118 . The first and second spacer layers 118 and 120 are each made of a suitable material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. By way of example but not limitation, the first and second spacer layers 118 and 120 may be formed by sequentially depositing two different dielectric materials over the dummy gate structures 106 using processes such as a CVD process subatmospheric CVD (SACVC) process, a flowable CVD process, an ALD process, a PVD process and/or other suitable process can be used. An anisotropic etch process is then performed on the deposited spacer layers 118 and 120 to expose portions of the fins 104 not covered by the dummy gate structures 106 (e.g., in source/drain regions of the fins 104). Portions of spacer layers 116 and 118 directly over dummy gate structures 106 may be removed by this anisotropic etch process. Portions of spacer layers 118 and 120 on sidewalls of dummy gate structures 106 may be left, thereby forming gate sidewall spacers, which will be referred to as gate spacers 116 for convenience. In some embodiments, the first spacer layer 118 is formed from silicon oxide, which has a lower dielectric constant than silicon nitride, and the second spacer layer 120 is formed from silicon nitride, which has higher etch resistance to subsequent etch processing (e.g., etching source/drain recesses in the fin 104) comprises silicon oxide. In some embodiments, the gate sidewall spacers 116 may be used to level subsequently formed doped regions, such as source/drain regions. Gate spacers 116 may also be used to design or modify the source/drain region profile.

After the formation of the gate sidewall spacers 116 is complete, source/drain structures 122 are formed at source/drain regions of the fin 104 that are not covered by the dummy gate structures 106 and the gate sidewall spacers 116 . The resulting structure is in 5 shown. In some embodiments, the formation of source/drain structures 122 includes recessing source/drain regions of fin 104, followed by epitaxially growing semiconductor materials in the recessed source/drain regions of fin 104.

The source/drain regions of the fin 104 can be deepened by using appropriate selective etch processing that attacks the semiconductor fin 104 while barely attacking the gate spacers 116 and the top masks 114 of the dummy gate structures 106 . For example, deepening the semiconductor fin 104 can be done by chemical dry etching with a plasma source and an etching gas. The plasma source can be an inductively coupled plasma etch (ICR etch), a transformer coupled plasma etch (TCP etch), electron cyclotron resonance etch (ECR etch), reactive ion etch (RIE), or the like, and the etchant gas can be fluorine, chlorine, Bromine, combinations thereof, or the like, which etches the semiconductor fin 104 at a faster etch rate than it etches the gate spacers 116 and the top masks 114 of the dummy gate structures 106 . In some other embodiments, deepening the semiconductor fin 104 may be performed by a wet chemical etch, such as mixed ammonia peroxide (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the semiconductor fin 104 at a faster etch rate , as it etches the gate spacers 116 and the top masks 114 of the dummy gate structures 106 . In some other embodiments, deepening the semiconductor fin 104 may be through a combination of a chemical drench eck etch and a wet chemical etch.

Once recesses have been created in the source/drain regions of fin 104, epitaxial source/drain structures 122 are formed in the source/drain recesses in fin 104 using one or more epitaxial or epitaxial processes ( Epi-processes may be used, which provide one or more epitaxial materials on the semiconductor fin 104. During the epitaxial growth process, the gate spacers 116 confine the one or more epitaxial materials to the source/drain regions in the fin 104. In some embodiments, the lattice constants of the epitaxial structures 122 differ from the lattice constant of the semiconductor fin 104 such that the Channel region in the fin 104 and between the epitaxial structures 122 can be stressed or strained by the epitaxial structures 122 to improve the carrier mobility of the semiconductor device and increase the performance of the device. The epitaxial processes include CVD deposition methods (e.g., PECVD, vapor phase epitaxy (VPE), and/or ultra high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors that interact with the composition of the underlying fin 104 .

In some embodiments, the source/drain epitaxial structures 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures 122 may be doped in-situ during the epitaxial processes by introducing dopant species such as: p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and/or other suitable dopants or combinations thereof. If the source/drain epitaxial structures 122 are not doped in situ, an implantation process (ie, a junction implantation process) is performed to dope the source/drain epitaxial structures 122 . In some example embodiments, the source/drain epitaxial structures 122 in an n-type transistor include SiP, while those in a p-type transistor include GeSnB and/or SiGeSnB. In embodiments with different device types, a mask, such as photoresist, may be formed over n-device areas while exposing p-device areas, and p-epitaxial structures may be formed on the exposed fins 104 in the p-device areas. Then the mask can be removed. As a result, a mask, such as photoresist, may be formed over the p-device area while exposing the n-device areas, and n-epitaxial structures may be formed on the exposed fins 104 in the n-device area. Then the mask can be removed.

Once the source/drain epitaxial structures 122 have been formed, an annealing process may be performed to activate the p-type dopants or the n-type dopants in the source/drain epitaxial structures 122 . The annealing process may be, for example, a rapid thermal anneal (RTA) process, a laser anneal, a millisecond thermal anneal (MSA) process, or the like.

Next will be in 6 an interlayer dielectric (ILD) layer 126 is formed on substrate 12 . In some embodiments, prior to forming the ILD layer 126, a contact etch stop layer (CESL) is also formed. In some examples, the CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other suitable materials that have a different etch selectivity than the ILD layer 126. The CESL may be formed by a plasma enhanced chemical vapor deposition (PECVD) process and/or others suitable deposition or oxidation processes are formed. In some embodiments, the ILD layer 126 includes materials such as tetraethyl orthosilicate formed oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as boron phosphorus silicate glass (BPSG), fused silica glass (FSG), phosphorus silicate glass (PSG), boron doped Silicon Glass (BSG) and/or other suitable dielectric materials that have a different etch selectivity than CESL 124. ILD layer 126 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 126 is formed, the wafer may be subjected to a high thermal budget process to anneal the ILD layer 126 .

In some examples, after forming the ILD layer 126, a planarization process may be performed to remove excess ILD layer 126 materials. For example, a planarization process includes a chemical-mechanical planarization (CMP) process that removes portions of the ILD layer 126 (and the CESL, if present) disposed over the dummy gate structures 106 . In some embodiments, the CMP process also removes the hard mask layers 112, 114 (as in 5 shown), and exposes the dummy gate electrodes 110.

As in 7 shown, the remaining dummy gate structures 106 (see Fig 6 ) are removed, leaving gate trenches GT1 between respective gate sidewall spacers 116 . The dummy gate structures 106 are etched using a selective etch process (e.g., selective dry etch, selective wet etch, or a combination thereof) that etches materials in the dummy gate structures 106 at a faster etch rate than other materials (e.g., removes the gate sidewall spacers 116 which etches the CESL and/or the ILD layer 126).

After that, replacement gate structures 130 are respectively formed in the gate trenches GT1, as in FIG 8th shown. Gate structures 130 may be the final gates of FinFETs. The final gate structures can each be a high-K metal gate stack, although other compositions are possible. In some embodiments, each of the gate structures 130 forms the gate in conjunction with the three sides of the channel region provided by the fin 104. In other words, each of the gate structures 130 wraps around the fin 104 on three sides. In various embodiments, the high-k metal gate structure 130 includes a gate dielectric layer 132 lining the gate trench GT1, a work function metal layer 134 formed over the gate dielectric layer 132, and a fill metal 136 , which is formed over the work function metal layer 134 and fills a remainder of the gate trenches GT1. Gate dielectric layer 132 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer overlying the interface layer. The high-k gate dielectrics used and described herein include dielectric materials having a high dielectric constant, which is higher than, for example, thermal silicon oxide (˜3.9). The work function metal layer 134 and/or fill metal 136 used within the high-k metal gate structures 130 may include a metal, metal alloy, or metal silicides. The formation of the high-k metal gate structures 130 may include multiple deposition processes to form various gate materials and one or more liner layers, and one or more CMP processes to remove excess gate materials.

In some embodiments, the interface layer of gate dielectric layer 132 may include a dielectric material such as silicon oxide (SiO 2 ), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or any other suitable method. The high-k dielectric layer of gate dielectric layer 132 may include hafnium oxide (HfO 2 ). Alternatively, gate dielectric layer 132 may include other high-k dielectrics such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium Zirconium Oxide (HfZrO), Lanthanum Oxide (LaO), Zirconium Oxide (ZrO), Titanium Oxide (TiO), Tantalum Oxide (Ta2O5), Yttrium Oxide (Y2O3), Strontium Titanium Oxide (SrTiO ₃ , STO), Barium Titanium Oxide (BaTiO ₃ , BTO), Barium zirconia (BaZrO), hafnium lanthana (HfLaO), lanthanum silica (LaSiO), alumina silica (AlSiO), alumina (Al ₂ O ₃ ), silicon nitride (Si ₃ N4 ₎ , oxynitrides (SiON), and combinations thereof , contain.

The work function metal layer 134 may contain work function metals to provide an appropriate work function for the high-k metal gate structures 130 . For an n-type FinFET, work-function metal layer 134 may include one or more n-type work-function metals (N-metals). The n-work function metals can be, for example, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), carbonitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., but not limited to hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 134 may include one or more p-type work function metals (P-metals). The p-workfunction metals can be, for example, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), and conductive metal oxides /or include, but are not limited to, other suitable materials.

For example, in some embodiments, the fill metal 136 may include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials to this.

Reference is now made to 9 . An etch back process is performed to etch back the replacement gate structures 130 , thereby forming recesses R1 over the etched back gate structures 130 . Since the materials of the replacement gate structures 130 have a different etch selectivity than the gate spacers 116, in some embodiments, a selective etch process may be performed to etch back the replacement gate structures 130 to provide the replacement gate structures 130 lower. Consequently, the top surfaces of replacement gate structures 130 may be located at a lower level than the top surfaces of gate spacers 116.

Subsequently, a capping dielectric layer 140 is deposited over the substrate 12 until the wells R1 are crowded, as shown in FIG 10 shown. The dielectric cap layer 140 includes SiN _x , Al _x O _y , AlON, SiO x Cy, SiC _x N _y , boron nitride (BN), boron carbonitride (BNC), combinations thereof, or the like, and is plasma enhanced by a suitable deposition technique such as CVD CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma enhanced ALD (PEALD), combinations thereof, or the like. Thereafter, a CMP process is performed to remove the cap layer outside of the recesses R1 , leaving only portions of the dielectric cap layer 140 in the recesses R1 to serve as the dielectric caps 142 . The resulting structure is in 11 shown. The dielectric cap 142 is placed in direct contact with the replacement gate structures 130, as in FIG 11 shown.

Referring to 12 , source/drain contacts 144 are formed that extend through the ILD layer 126 (and the CESL, if present) (see FIG 11 ). Forming the source/drain contacts 144 includes, for example but not limitation, performing one or more etch processes to form contact openings that extend through the ILD layer 126 (and the CESL, if present) to the exposing source/drain epitaxial structures 122, depositing one or more metallic materials overfilling the contact openings, and then performing a CMP process to remove excess metallic materials outside of the contact openings. In some embodiments, the one or more etch processes include a selective etch that etches ILD layer 126 at a faster etch rate than it etches dielectric caps 142 and gate spacers 116 . Consequently, the selective etch is performed using the dielectric caps 142 and the gate spacers 116 as an etch mask such that the contact openings and thus the source/drain contacts 144 are formed self-aligned to the source/drain epitaxial structures 122 without the an additional photolithographic process is used. Because the dielectric caps 142 allow the source/drain contacts 144 to be formed in a self-aligned manner, they may be referred to as self-aligned contact caps (SAC caps) 142 .

Once the self-aligned source/drain contacts 144 have been formed, as in FIG 13 1, an etch stop layer (ESL) 146 is formed selectively over the dielectric materials (e.g., the SAC caps 142 and the gate spacers 116). In some embodiments, the ESL 146 is formed by a selective atomic layer deposition (ALD) process, which exhibits a faster deposition rate on dielectric surfaces than on metallic surfaces. The selective ALD process involves providing alternating pulses of a metallic precursor and a hydroxyl precursor into a reaction chamber. Pulses of the reactants saturate the surface in a self-limiting manner.

An example selective ALD process in which the ESL 146 is formed includes the following operations. The structure of 12 is loaded into a reaction chamber. A pulse of precursor is then injected into the reaction chamber loaded with the structure for a first period of time. In this case, the precursor contains a chemical selected from the group consisting of H ₂ O, H ₂ O ₂ and/or O ₃ . For example, the precursor includes hydroxyl precursors.

When the hydroxyl precursor is injected into the reaction chamber, a chemisorption layer of the hydroxyl precursor forms selectively on the exposed surfaces of the dielectric materials (e.g., the SAC caps 142 and the gate spacers 116), but does not form on exposed surfaces of the metallic materials ( for example the source/drain contacts 144). Subsequently, the residual hydroxyl precursor is discharged from the reaction chamber for a second period of time. In order to more efficiently unload residual hydroxyl precursor from the reaction chamber, purge gas may be injected into the reaction chamber during this purge period, which purge gas may include an inert gas such as N 2 , Ar, He or similar inert gases.

After the residual hydroxyl precursor is discharged from the reaction chamber, a pulse of metallic precursor is injected into the reaction chamber for a third period of time. In this case, the metallic precursor has a high reaction probability with the chemisorption layer of the hydroxyl precursor. Some examples of the metallic precursor include a tetrachloro transition metal complex. In some embodiments, the tetrachloro-transition metal complex contains a chemical selected from the group consisting of ZrCl ₄ , HfCl ₄ , AlCl ₄ and TiCl ₄ . The metallic precursor reacts with the chemisorption layer of the hydroxyl precursor. As a result, an atomic layer is formed from several ESL 146 forms on the exposed surfaces of the dielectric materials (e.g., the SAC caps 142 and the gate spacers 116), but does not form on the exposed surfaces of the metallic materials (e.g., the source/drain contacts 144). In 13 ESL 146 is a high-k dielectric layer containing a metal oxide. In some embodiments, the metal oxide includes zirconia, hafnia, alumina, titania, and/or other suitable materials. In some other embodiments, the ESLs 146 may be made of SiO ₂ , SiN _x , Al _x O _y , AlON, SiO _x Cy, SiC _x N _y , boron nitride (BN), boron carbonitride (BNC), or other suitable materials.

Subsequently, the remaining metallic precursor is discharged from the reaction chamber for a fourth period of time. During this fourth purge period, an inert gas, such as N 2 , Ar, He, or the like, may be injected into the reaction chamber to more efficiently discharge residual metal precursor from the reaction chamber.

In some embodiments, the selective ALD process includes a series of selective ALD cycles, that is, the first through fourth periods, as described above, during which the hydroxyl precursor and the metallic precursor are alternately injected into the reaction chamber and thereafter discharged from the reaction chamber , are collectively considered a deposition or film formation cycle. By repeating this cycle multiple times, the ESLs 146 having a desired thickness are formed. The ESL 146 may have a thickness T1 of about 3 nm to about 10 nm. If the thickness T1 is less than about 3 nm, the ESL 146 may be too thin to slow or stop a subsequent etch process; if the thickness T1 is greater than about 10 nm, the integrated circuit structure may have a high parasitic capacitance. In some embodiments, a CMP process is optionally performed to planarize the ESL 146 after the selective ALD process is complete.

Referring to 14 another ILD layer 148 is formed over the ESL 146 . In some embodiments, the ILD layer 148 includes materials such as tetraethyl orthosilicate formed oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as boron phosphorus silicate glass (BPSG), fused silica glass (FSG), phosphorus silicate glass (PSG), boron doped Silicon Glass (BSG), SiOC, SiCH _x , and/or other suitable dielectric materials that have a different etch selectivity than ESL 146. In certain embodiments, ILD layer 148 is formed of silicon oxide (SiO _x ). The ILD layer 148 can be deposited by a PECVD process or other suitable deposition technique. In some embodiments, the ESL 146 has a sufficient etch selectivity (eg, about 7 times higher to about 10 times higher or more) with respect to the ILD layer 148 in a subsequent via etch process. In other words, in the subsequent via etch process, an etch rate of the ILD layer 148 is about seven to about ten times or more than an etch rate of the ESL 146. That is, the subsequent via etch process etches the ILD layer 148 at more than about 7 times faster Etch rate as he etches the ESL 146. Thus, the ESL 146 can perform the etch process to form the via openings (see the 15A and 15B) slow down or stop, which in turn prevents overetching of the dielectric materials near the source/drain contacts 144.

Referring to 15A For example, the ILD layer 148 is patterned to form via openings O1 that extend through the ILD layer 148 using an etch process ET1 (also referred to as a via etch process). The etch period of the via etch process ET1 is controlled to break through the ILD layer 148 . As a result of the etch process ET1, the source/drain contacts 144 are exposed at the bottoms of the via openings O1.

In some embodiments, before the via etch process ET1, a photolithographic process is performed to define expected structures in the top view of the via openings O1. For example, the photolithography process may include spin coating a photoresist layer over the ILD layer 148, as in FIG 14 shown, followed by performing a post-exposure baking process and developing the photoresist layer to form a patterned mask with the structures of the via openings O1 in plan view. In some embodiments, patterning the photoresist to form the patterned mask may be performed using an Electron Beam (E-Beam) lithography process or an Extreme Ultraviolet Radiation (EUV) lithography process.

In some embodiments, the via etch process ET1 is an anisotropic selective etch process, such as a plasma etch. In the example of plasma etching, the semiconductor substrate 12, which has the 14 illustrated structure, loaded into a plasma tool and for a time sufficient to etch through the ILD layer 148, a plasma environment created by RF (radio frequency) or microwave energy in a gaseous mixture of a fluorine-containing gas, such as C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , CHF ₃ or a similar type of gas, an inert gas such as argon or helium, an optional weak oxidizer such as O ₂ or CO or a similar type of oxidizing agent, is exposed. A plasma generator in a gaseous mixture containing C ₄ F ₆ , CF ₄ , CHF ₃ , O ₂ and argon can be used to etch through the ILD layer 148 . The chemistries described above allow the ILD layer 148 to be selectively etched at a faster etch rate than that at which the ESL 146 is etched. In the anisotropic selective etch process ET1, the etch rate of the ILD layer 148 is about seven to about ten times or more than an etch rate of the ESL 146, for example.

In some embodiments, there may be some misalignment (or overlay error) between via openings O1 and source/drain contacts 144 due to process variations. Or, the size (or width) of via openings O1 may be larger than the size (or width) of source/drain contacts 144 in some embodiments. In either of these cases, via openings O1 may expose ESL 146 . However, due to the etch selectivity between the ILD layer 148 and the ESL 146, the ESL 146 may slow or stop the etch process for forming the via openings O1, which in turn may over-etch the dielectric materials (e.g., the gate sidewall spacers 116 and/or the dielectric caps 142) and reduces the risk of leakage currents.

In some embodiments, the above etchants and etch conditions of the via etch process ET1 are chosen such that the ESL 146 (e.g., a metal-containing dielectric) has a slower etch rate than the ILD layer 148 (e.g., SiO _x ). In this way, the ESL 146 can act as a detectable etch endpoint, which in turn prevents the ESL 146 from being punctured or punctured and thus prevents the dielectric materials covered by the ESL 146 from being over-etched. In other words, the via etch process ET1 is tuned to etch silicon oxide at a faster etch rate than a metal-containing dielectric or silicon nitride is etched.

In some embodiments, ILD layer 148 includes silicon oxide and ESL 146 includes a metal-containing dielectric. The via etch process ET1 may include a suitable wet etch, dry etch (plasma etch), and/or other processes. For example, a dry etch process may use chlorine-containing gases, fluorine-containing gases, other etching gases, or a combination thereof. The wet etch solutions may include NH ₄ OH, HF (hydrofluoric acid) or diluted HF, deionized water, TMAH (tetramethylammonium hydroxide), other suitable wet etch solutions, or combinations thereof. In this way, the etch rate of the metal-based dielectric remains low in the via etch process ET1, which in turn makes it possible to etch silicon oxide (e.g., the ILD material) at a faster etch rate than that at which metal-based dielectric (e.g., the ESL 146) etches will.

In some embodiments, ILD layer 148 includes silicon oxide and ESL 146 includes silicon nitride. It has been observed that the etch rate of silicon nitride increases when the etch plasma is generated from a gaseous mixture containing a hydrogen (H ₂ ) gas. Thus, in accordance with some embodiments of the present disclosure, the via etch process ET1 is performed using a hydrogen-free gaseous mixture to reduce the silicon nitride etch rate. In other words, in the via etching process ET1, the plasma is generated in a gaseous mixture without hydrogen gas (H2 gas). In this way, the etch rate for silicon nitride in the via etch process ET1 remains low, which in turn makes it possible to etch silicon oxide (e.g. the ILD material) at a faster etch rate than that at which silicon nitride (e.g. the ESL 146) is etched.

In some embodiments, such as in 15A shown, the via openings O2 have tapered sidewall profiles due to the anisotropic etch characteristic of the etch process ET1. In some other embodiments, however, the etching conditions of the etching process ET1 can be fine-tuned such that it is possible to form via openings O1 with vertical sidewall profiles, as in FIG 15B shown.

Referring to 16A Source/drain vias 150 are then formed in via openings O1 to make physical and electrical connection to source/drain contacts 144 . By way of example but not limitation, the source/drain vias 150 are formed by depositing one or more metal ical materials is used, which overfills the via openings O1, followed by a CMP process to remove excess metallic materials outside the via openings O1. As a result of the CMP process, source/drain vias 150 have top surfaces that are substantially coplanar with ILD layer 148 . The source/drain vias 150 may include metallic materials such as copper, aluminum, tungsten, combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the source/drain vias 150 may further include one or more barrier/adhesion layers (not shown) to protect the ILD layer 148 and/or the ESL 146 from metal (e.g., copper) diffusion. The one or more barrier/adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like.

As in the 16A and 16B As shown, source/drain vias 150 may be aligned with or misaligned with source/drain contacts 144 due to lithography overlay errors. Source/drain vias 150 adopt the geometry of via openings O1. In other words, the sidewalls of the source/drain vias 150 extend linearly through the ILD layer 148 and have steps (or notched corners) formed at the interface between the ILD 148 and the ESL 146 . For example, ILD layer 148 has a stepped bottom surface with a top step contacting etch stop layer 146 and a bottom step contacting source/drain contact 144 . More specifically, a source/drain via 150 forms a first linear interface 1501 to the ILD layer 148 and a second linear interface 1502 to the ESL 146. The first linear interface 1501 and the second linear interface 1502 are non-coincident, and the first linear Interface 1501 and the second linear interface 1502 are misaligned with each other. In some embodiments, the first linear interface 1501 is more inclined than the second linear interface 1502 . That is, the etch stop layer 146 is spaced one step above the source/drain contact 144 .

In some embodiments, as in 16A As shown, source/drain vias 150 have a tapered sidewall profile due to the anisotropic etch characteristic of etch process ET1. However, in some other embodiments, the etch conditions of the etch process ET1 can be fine-tuned to allow the via openings O1, and thus the source/drain vias 150, to have a vertical sidewall profile, as in FIG 16B shown.

the 17 - 18B 12 illustrate exemplary cross-sectional views of various stages of fabricating an integrated circuit structure 100 consistent with some other embodiments of the present disclosure. It should be understood that additional operations before, during, and after the processes illustrated in FIGS 17 - 18B process(es) shown may be provided and that some of the operations described below may be substituted or omitted for additional embodiments of the method. The order of operations/processes may be interchangeable. The same or similar assemblies, materials, processes and/or operations as set forth in 1 - 18B may be used in the following embodiments, and the detailed explanation thereof again may be omitted.

After the structure as in 8th 1, an etch back process is performed to etch back the replacement gate structures 130 and the gate spacers 116, thereby forming recesses R1' over the etched back gate structures 130 and the etched back gate spacers 116. FIG. Since the materials of the replacement gate structures 130 have a different etch selectivity than the gate spacers 116, in some embodiments a first selective etch process may be performed to etch back the replacement gate structures 130 such that the replacement gate structures 130 can be made lower. A second selective etch process is then performed to make the gate spacers 116 lower. Consequently, the top surfaces of the replacement gate structures 130 may be located at a lower level than the top surfaces of the gate spacers 116. For example, in the illustrated embodiments, such as FIG 17 As shown, the replacement gate structures 130 have top surfaces that are lower than the top surfaces of the gate spacers 116. However, in some other embodiments, the top surfaces of the replacement gate structures 130 may be level with or even higher as the top surfaces of gate spacers 116 .

In some embodiments, metal caps 138 are each atop by a suitable process such as CVD or ALD the replacement gate structures 130 are formed. In some embodiments, the metal caps 138 on the replacement gate structures 130 are formed using a bottom-up approach. For example, the metal caps 138 are selectively grown on the metal surface, such as the work function metal layer 134 and the fill metal 136, leaving the sidewalls of the gate spacers 116 substantially free of the grown metal caps 138. FIG. By way of example but not limitation, the metal caps 138 may be substantially fluorine-free tungsten (FFW) films, having a fluorine impurity content of less than 5 atomic percent and a chlorine impurity content of greater than 3 atomic percent. The FFW films or the FFW-containing films can be formed by ALD or CVD using one or more non-fluorine based tungsten precursors such as, but not limited to, tungsten pentachloride (WCl ₅ ) or tungsten hexachloride (WCl ₆ ). In some embodiments, portions of the metal caps 138 may flow over the gate dielectric layer 132 such that the metal caps 138 may also cover the exposed surface of the gate dielectric layers 132 . Since the metal caps 138 are formed from the bottom up, their formation can be simplified, for example by reducing repeated etch back processes used to remove unwanted metallic material resulting from conformal growth.

The structure of 17 then becomes the in the 10 - 16A subjected to the processes shown to complete the formation of the source/drain vias 150 as shown in FIG 18A shown. In some embodiments, as in 18A As shown, source/drain vias 150 have a tapered sidewall profile due to the anisotropic etch characteristic of etch process ET1. However, in some other embodiments, the etch conditions of the etch process ET1 can be fine-tuned to allow the via openings O1, and thus the source/drain vias 150, to have a vertical sidewall profile, as in FIG 18B shown.

The formation of the ESL 146 is not limited to the in 13 shown processes limited. In some other embodiments, the ESL 146 is formed with the support of a barrier layer. the 19 - 21 12 illustrate exemplary cross-sectional views of various stages in fabricating an integrated circuit structure 100 consistent with some other embodiments of the present disclosure 12 Once the structure shown has been formed, barrier layers 152 are formed over metals (in this case, for example, the source/drain contacts 144), respectively. In some embodiments, the barrier layers 152 are polymer, benzotriazole (BTA), or a self-assembled monolayer (SAM).

In some embodiments, the barrier layers 152 are made of BTA. The structure of 12 may be placed in a deposition chamber, and BTA (vaporized or liquid) and reactant gases are introduced into the deposition chamber. Due to material properties, BTA molecules have a tendency not to adhere to the surface of dielectric materials (e.g., the SAC caps and gate spacers 116) and have a tendency to stick to the surfaces of metals (in this case, for example, the source/drain contacts 144). Thus, the barrier layers 152 form over the source/drain contacts 144, respectively.

In some other embodiments, the barrier layers 152 are made of SAM. The SAM contains silane type or thiol type inhibitor. In some embodiments, the silane-type inhibitor can be octadecyltrichlorosilane (CH ₃ (CH ₂ ) ₁₇ SiCl ₃ ), trichloro(iH,1H,2H,2H-perfluorooctyl)silane (CF ₃ (CF ₂ ) ₅ (CH ₂ ) ₂ SiCl ₃ ), dimethyldichlorosilane ((CH ₃ ) ₂ SiCl ₂ )/ (dimethylamino)trimethylsilane ((CH ₃ ) ₂ NSi(CH ₃ ) ₃ ), 1-(trimethylsilyl)pyrrolidine ((CH ₃ ) ₃ Si-NC ₄ H ₈ ), hexamethyldisilazane ([(CH ₃ ) ₃ Si] ₂ NH) or bis(dimethylamino)dimethylsilane ([(CH ₃ ) ₂ N] ₂ Si(CH ₃ ) ₂ ). In some other embodiments, the thiol-type inhibitor is alkanethiol, propanethiol, butanethiol, hexanethiol, heptanethiol, octadecanethiol, nonanethiol, or dodecanethiol. In some embodiments, the thiol-type inhibitor forms selectively on a metal layer but not on a dielectric layer.

In some embodiments in which the barrier layers 152 are self-assembling monolayers (SAM), the molecules of the barrier layers 152 each have a first protruding end portion (e.g., a head group) and a second protruding end portion (e.g., an end group) which are attached to opposite sides of an optional middle section (molecular chain). The first protruding end portion has a group that selectively attaches to hydroxyl-terminated faces (ie, -OH-terminated faces, such as _silica faces) while not attaching to hydrogen-terminated faces (such as for example silicon nitride surfaces which have an H-termination). The second projecting end portion includes a metal oxide deposition inhibitor group. The optional middle section can contain an alkyl chain. The van der Waals interactions between these chains cause the self-assembled monolayers to self-assemble. In some embodiments where the barrier layers 152 contain alkanethiols (X-(CH ₂ ) _n -SH), the head group may be bonded to a surface of a metallic material. Thus, the barrier layers 152 can selectively form (grow) on a metal layer but not on a dielectric layer.

Referring to 20 For example, a deposition process (e.g., an ALD process) is used to form the ESL 146 over the dielectric materials (e.g., the SAC caps 142 and the gate spacers 116). Due to the material properties, precursors to the ALD process have a tendency not to adhere to the surface of the barrier layers 152 . Thus, during the ALD process, the ESLs 146 form over the SAC caps 142 and the gate spacers 116 while leaving the top surfaces of the barrier layers 152 uncovered.

In the following reference is made to 21 . The barrier layers 152 (refer to Fig 20 ) are removed to expose the top surfaces of the source/drain contacts 144. FIG. In some embodiments where the barrier layers 152 are removed by baking, the baking temperature may range from about 1°C to about 60°C to break the CH bonding of the barrier layers 152 . Then, the disassembled portion of the barrier layers 152 can be washed away with a dilute acidic solution, such as H ₃ PO ₄ , HCl, or other suitable solutions. In some other embodiments in which the barrier layers 152 are removed by etching, the etchants may include CF ₃ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, NF ₃ , or other suitable substances. The structure of 21 then becomes the in the 14 - 16A (or FIGS. 14-15B and 16B) to complete the formation of the source/drain vias 150. FIG.

the 22 - 25 12 illustrate exemplary cross-sectional views of various stages of fabricating an integrated circuit structure 100a consistent with some other embodiments of the present disclosure. It should be understood that additional operations before, during, and after the processes illustrated in FIGS 22 - 25 process(es) shown may be provided and that some of the operations described below may be substituted or omitted for additional embodiments of the method. The order of operations/processes may be interchangeable. The same or similar assemblies, materials, processes and/or operations as set forth in 1 - 16B may be used in the following embodiments, and detailed explanation thereof again may be omitted.

After the in 14 Once the structure shown has been formed, the ILD layer 148 is patterned to form gate contact openings O2 which extend through the ILD layer 148, the ESL 146 and the dielectric cap 142 to the replacement gate structures 130. FIG. The resulting structure is in 22 shown. The ILD layer 148 can be patterned using appropriate photolithography and etching techniques.

Next, as in 23 As shown, a patterned mask layer M4 is formed over the substrate 12 to fill the gate contact openings O2. The patterned mask layer M4 has an opening O3 vertically above a source/drain contact 144. FIG. In some embodiments, the patterned mask layer M4 may be a photoresist mask formed by a suitable photolithographic process. For example, the photolithography process can spin-coat a photoresist layer over the in 22 structure shown, followed by performing a post exposure bake process and developing the photoresist layer to form the patterned mask layer M4. In some embodiments, patterning the photoresist to form the patterned mask feature may be performed using an Electron Beam (E-Beam) lithography process or an Extreme Ultraviolet Radiation (EUV) lithography process.

Referring to 24 With the patterned mask layer M4 in place, a via etch process ET2 is performed to form a via opening O4 extending through the ILD layer 148 . The etch duration of the via etch process ET2 is controlled such that the ILD layer 148 is broken down. As a result of the etch process ET2, the source/drain contacts 144 are exposed at the bottoms of the via openings O4. Details regarding the via etch process ET2 were previously discussed in relation to the via etch process ET1, and thus will not be repeated here for the sake of brevity.

Referring to 25 the patterned mask layer M4 (refer to Fig 24 ) removed by ashing and/or wet stripping from the gate contact openings O2 before a butt contact (or butt via) 154 is formed to fill via opening O4 and gate contact opening O2, and a gate contact 156 is formed to fill another gate contact opening O2. The resulting structure is in 25 shown. Details regarding materials and manufacturing processes relating to butt contact 154 and gate contact 156 are similar to those relating to source/drain vias 150, and thus will not be repeated here for the sake of brevity.

In 25 the ILD layer 148 has a bottom surface 1481 which is arranged lower than a top surface 1461 of the ESL 146. Furthermore, the top surface 1461 of the ESL 146 is also arranged higher than a top surface of the source/drain contact 144. The ILD layer 148 is also placed in contact with sidewalls 1462 of the ESL 146 . Furthermore, the ILD layer 148 is also placed in contact with some of the source/drain contacts 144 .

Bump contact 154 adopts the geometry of via openings O2 and O4. In other words, sidewalls of the butt contact extend linearly through the ILD layer 148 and have steps (or notched corners) formed at the interface between the ILD layer 148 and the ESL 146 . For example, ILD layer 148 has a stepped bottom surface with a top step contacting top surface 1461 of etch stop layer 146 and a bottom step contacting a top surface (ie, surface 1481) of the source/drain Contacts 144 contacted, on. More specifically, butt contact 154 forms a first linear interface 1541 to ILD layer 148 and a second linear interface 1542 to ESL 146. First linear interface 1541 and second linear interface 1542 are not coincident, and first linear interface 1541 and second linear interface 1542 are misaligned with each other. In some embodiments, the first linear interface 1541 is more inclined than the second linear interface 1542. Furthermore, the second linear interface 1542 is substantially aligned with a sidewall 1441 of the source/drain contact 144, which is connected to the butt contact 154. Furthermore, butt contact 154 has a greater thickness over gate structure 130 than over source/drain contact 144 .

the 26 - 43B 10 illustrate perspective and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 200, consistent with some embodiments of the present disclosure n-type transistor (such as an n-FAA FET). Similar reference numbers are used to identify similar elements throughout the various views and illustrative embodiments. It is understood that additional operations before, during and after the in the 26 - 43B process(es) shown may be provided, and that some of the operations described below may be substituted or eliminated for additional embodiments of the method. The order of operations/processes may be interchangeable.

the 26 , 27 , 28 , 29A , 30A , 31A and 32A 12 are perspective views of some embodiments of the integrated circuit structure 200 at intermediate stages during manufacture. the 29B , 30B , 31B , 32B , 33 - 35 , 36A , 37 - 43B 12 are cross-sectional views of some embodiments of the integrated circuit structure 200 at intermediate stages during fabrication along a first cut (e.g., cut X-X in 29A) , which runs along a longitudinal direction of the channel and perpendicular to a top surface of the substrate. 36B Figure 12 is a cross-sectional view of some embodiments of the integrated circuit structure 200 at intermediate stages during fabrication along a second cut (e.g., cut Y - Y in 29A) , which runs in the gate region and perpendicular to the longitudinal direction of the channel.

Referring to 26 An epitaxial stack 220 has been formed over substrate 210. FIG. In some embodiments, the substrate 210 may include silicon (Si). Alternatively, the substrate 210 may be germanium (Ge), silicon germanium (SiGe), a Group III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and/or or GaInAsP; or a combination thereof) or other suitable semiconductor materials. In some embodiments, the substrate 210 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. As a further alternative, the substrate 210 may include a buried dielectric layer, such as a buried oxide (BOX) layer, including but not limited to those formed wafer-thin by a process referred to as separation by implantation of oxygen (SIMOX). Bonding, SEG or other suitable method.

The epitaxial stack 220 comprises epitaxial layers 222 of a first composition between which are disposed epitaxial layers 224 of a second composition. the first and second compositions may differ from each other. In some embodiments, epitaxial layers 222 are SiGe and epitaxial layers 224 are silicon (Si). However, other embodiments are possible, for example those providing a first composition and a second composition having different oxidation rates and/or etch selectivity. In some embodiments, epitaxial layers 222 include SiGe, and in those cases where epitaxial layers 224 include Si, the Si oxidation rate of epitaxial layers 224 is less than the SiGe oxidation rate of epitaxial layers 222.

The epitaxial layers 224 or portions thereof may form one or more nanosheet channels of the multi-gate transistor. The term nanosheet is used herein to denote any section of material with nanoscale or even microscale dimensions that has an elongated shape regardless of the cross-sectional shape of that section. Thus, this term designates longitudinally extended material sections both with a circular and essentially circular cross-section as well as radial or rod-shaped material sections which have, for example, a cylindrically shaped or essentially rectangular cross-section. The use of the epitaxial layers 224 to define one or more channels of a device is discussed in more detail below.

It is noted that three layers of the epitaxial layers 222 and three layers of the epitaxial layers 224 are arranged alternately as shown in FIG 26 provided, however, is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers can be formed in epitaxial stack 220; the number of layers depending on the desired number of channel layers for the transistor. In some embodiments, a number of epitaxial layers 224 is between 2 and 10.

As described in more detail below, the epitaxial layers 224 may serve as one or more channel regions for a subsequently formed multi-gate device, and their thickness is chosen based on device performance considerations. The epitaxial layers 222 in the channel region(s) may eventually be removed, and serve to define a vertical spacing between adjacent channel regions for a subsequently formed multi-gate device, with their thickness chosen based on device performance considerations . Accordingly, the epitaxial layers 222 may also be referred to as sacrificial layers and the epitaxial layers 224 may also be referred to as channel layers.

As an example, the epitaxial growth of the layers of the stack 220 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layers, such as epitaxial layers 224, include the same material as substrate 210. In some embodiments, epitaxial growth layers 222 and 224 include a different material than substrate 210. As noted above, at least in some For example, epitaxial layers 222 comprise an epitaxially grown silicon germanium (SiGe) layer and epitaxial layers 224 comprise an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, epitaxial layers 222 and 224 may each include other materials, such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and/or GaInAsP, or combinations thereof. As discussed above, the materials of the epitaxial layers 222 and 224 can be chosen based on providing different oxidation and/or etch selectivity properties. In some embodiments, epitaxial layers 222 and 224 are substantially dopant-free (that is, have an extrinsic dopant concentration of about 0 cm -3 to about 1X1018 cm -3 ) with, for example, no intentional doping during the epitaxial growth process will.

Referring to 27 a plurality of semiconductor fins 230 extending away from the substrate 210 is formed. In various embodiments, each of the fins 230 includes a substrate portion 212 formed from the substrate 210 and portions of each of the epitaxial layers of the epitaxial stack including the epitaxial layers 222 and 224 . The fins 230 may be fabricated using any suitable process, such as double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithographic and self-aligned processes, enabling the creation of structures that can be example, have spacing dimensions that are smaller than those that would otherwise be achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along with the patterned sacrificial layer using a self-aligned process. Then the sacrificial layer is removed and the remaining spacers, or mandrels, can now be used to pattern the fins 230 by etching the original epitaxial stack 220. FIG. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

In the illustrated embodiment according to 26 and 27 A hard mask (HM) layer 910 is formed over the epitaxial stack 220 before the fins 230 are patterned. In some embodiments, the HM layer has an oxide layer 912 (e.g., a pad oxide layer that may include SiO 2 ) and a nitride layer (e.g., a pad nitride layer that may include Si ₃ N _4\ ) formed over the oxide layer. Oxide layer 912 may serve as an adhesion layer between epitaxial stack 220 and nitride layer 914 , and may serve as an etch stop layer for etching nitride layer 914 . In some examples, the HM oxide layer 912 includes thermally grown oxide, chemical vapor deposited (CVD) deposited oxide, and/or atomic layer deposition (ALD) deposited oxide. In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and/or other suitable techniques.

The fins 230 can then be fabricated using suitable processes such as photolithography and etching processes. The photolithography process may include forming a photoresist layer (not shown) over the HM layer 910, exposing the photoresist into a pattern, performing post exposure bake processes, and developing the photoresist to form a patterned mask comprising the photoresist. In some embodiments, patterning the photoresist to form the patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet radiation (EUV) lithography process having a wavelength of about 1-200 nm, for example . The patterned mask can then be used to protect portions of the substrate 210 and layers formed thereon while an etch process forms trenches 202 in unprotected areas through the HM layer 910, through the epitaxial stack 220, and into the substrate 210, creating the Plurality of extending fins 230 remains. The trenches 202 may be etched using a dry etch (e.g., reactive ion etch), a wet etch, and/or a combination thereof. Numerous other embodiments of methods for forming the fins on the substrate may also be used, such as defining the fin region (e.g., through a mask or isolation regions) and epitaxially growing the epitaxial stack 220 in the shape of the fins 230.

As in 28 1, isolation regions 240 are formed between fins 230 next. Details regarding materials and processes relating to isolation regions 240 are similar to those for isolation regions 14 previously discussed, and thus will not be repeated here for the sake of brevity.

In the following reference is made to the 29A and 29B . Dummy gate structures 250 are formed over substrate 210 and are at least partially disposed over fins 230 . The portions of the fins 230 that are located under the dummy gate structures 250 may be referred to as the channel region. The dummy gate structures 250 may also define source/drain (S/D) regions of the fins 230, for example the regions of the fins 230 adjacent to, and on opposite sides of, the channel regions.

The process of forming the dummy gates first forms a dummy gate dielectric layer 252 over the fins 230. Subsequently, a dummy gate electrode layer 254 and a hard mask comprising multiple layers 256 and 258 (e.g., an oxide layer 256 and a nitride layer 258 ) formed over the dummy gate dielectric layer 252 . Then the hard mask is patterned, followed by patterning of the dummy gate electrode layer 252 by using the patterned hard mask as an etch mask. In some embodiments, the dummy gate dielectric layer 252 is removed from the S/D regions of the fins 230 after the dummy gate electrode layer 254 is patterned. The etching process may include a wet etch, a dry etch, and/or a combination thereof. The etch process is chosen to substantially selectively etch dummy gate dielectric layer 252 without etching fins 230, dummy gate electrode layer 254, oxide mask layer 256, and nitride mask layer 258. FIG. Materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those previously discussed dummy gate dielectric layer 108 and dummy gate electrode layer 110, and thus will not be repeated here for the sake of brevity.

After formation of dummy gate structures 250 is complete, gate spacers 260 are formed on sidewalls of dummy gate structures 250 . For example, a spacer material layer is deposited on substrate 210 . The spacer material layer may be a conformal layer which is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, a spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structures 250 . Spacer material layer 260 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitrides, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. In some embodiments, the spacer material layer 260 includes multiple layers, such as a first spacer layer 262 and a second spacer layer 264 formed over the first spacer layer 262 (shown in FIG 29B) , on. As an example, the spacer material layer 260 may be formed by depositing a dielectric material over the gate structures 250 using appropriate deposition processes. An anisotropic etch process is then performed on the deposited spacer layer 260 to expose portions of the fins 230 not covered by the dummy gate structures 250 (eg, in source/drain regions of the fins 230). Portions of the spacer layer directly over the dummy gate structure 250 may be completely removed by this anisotropic etch process. Portions of the spacer layer on sidewalls of the dummy gate structure 250 may be left, thereby forming gate sidewall spacers, which will be referred to as the gate spacers 260 for convenience. It is noted that the gate spacers 260 in the cross-sectional view of FIG 29B Although multi-layer structures, these are shown in the perspective view of FIG 29A however, are shown as single layer structures.

Next, as in the 30A and 30B As illustrated, exposed portions of the semiconductor fins 230 that extend laterally beyond the gate spacers 260 (e.g., in source/drain regions of the fins 230) are etched using, for example, an anisotropic etch process that includes the dummy Gate structure 250 and gate spacers 260 are used as an etch mask, creating indentations R2 into semiconductor fins 230 and between the corresponding dummy gate structures 250. After the anisotropic etch, end faces of the epitaxial layers 222 and channel layers 224 are aligned with the respective outermost sidewalls of the gate spacers 260 due to the anisotropic etch. In some embodiments, the anisotropic etch may be performed by a dry chemical etch using a plasma source and a reactive gas. The plasma source may be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, or the like, and the reaction gas may be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), a chlorine-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), the like, or combinations thereof.

Next are the epitaxial layers 222 in FIGS 31A and 31B have been recessed laterally or horizontally using appropriate etching techniques, thereby creating lateral recesses R3 each vertically between corresponding channel layers 224. This operation can be performed by using a selective etching process. By way of example but not limitation, the epitaxial layers 222 are SiGe and the channel layers 224 are silicon, enabling the epitaxial layers 222 to be selectively etched. In some embodiments, the selective wet etch includes an APM (e.g., ammonium hydroxide-hydrogen peroxide) etch, which etches SiGe at a faster etch rate than it etches Si. In some embodiments, the selective etch includes SiGe oxidation followed by SiGeO _x removal. For example, oxidation by O ₃ can provide clean, and then remove SiGeO _x by an etchant such as NH ₄ OH, which selectively etches SiGeO _x at a faster etch rate than it etches Si. In addition, the channel layers 224 are not significantly etched by the process of laterally recessing the epitaxial layers 222 since the oxidation rate of Si is much slower (sometimes 30 times slower) than the oxidation rate of SiGe. Consequently, channel layers 224 extend laterally beyond opposite end faces of epitaxial layers 222 .

In the 32A and 32B an inner spacer material layer 270 has been formed to encircle the recesses R3 defined by the above with reference to FIG 32A and 32B discussed lateral etching of the epitaxial layers are left to fill. The inner spacer material layer 270 may be a low k dielectric material such as SiO 2 , SiN, SiCN or SiOCN and may be formed by a suitable deposition process such as ALD. After the deposition of the inner spacer material layer 270, an anisotropic etch process may be performed to trim the deposited inner spacer material 270 such that only portions of the deposited inner spacer material 270 that fill the recesses R3 are left by the lateral etching of the epitaxial layers 222. After the trimming process, the remaining portions of the applied inner spacer material are referred to as inner spacers 270 for convenience. The inner spacers 270 serve to isolate metal gates from the source/drain regions formed in subsequent processing. In the example of 32A and 32B sidewalls of inner spacers 270 are aligned with sidewalls of channel layers 224 .

In 33 the epitaxial source/drain structures 280 have been formed over the source/drain regions S/D of the semiconductor fins 230. FIG. The source/drain epitaxial structures 280 may be formed by performing an epitaxial growth process that provides an epitaxial material on the fins 230 . During the epitaxial growth process, the dummy gate structures 250, the gate sidewall spacers 60 and the inner spacers 270 confine the source/drain epitaxial structures 280 to the source/drain regions S/D. Details regarding materials and processes relating to the GAA-FET source/drain epitaxial structures 280 are similar to those of the FinFET epitaxial source/drain structures 122 discussed previously, and thus will not be repeated here for the sake of brevity.

In 34 An interlayer dielectric (ILD) layer 310 has been formed on substrate 210 . In some embodiments, prior to forming the ILD layer 310, a contact etch stop layer (CESL) is also formed. Details regarding materials and processes related to the CESL and the ILD layer are similar to those of the CESL and the ILD layer 126 and thus are not repeated here for the sake of brevity. In some examples, after depositing the ILD layer 310, a planarization process may be performed to remove excess ILD layer 310 materials. For example, a planarization process includes a chemical-mechanical planarization (CMP) process that removes portions of the ILD layer 310 (and the CESL, if present) disposed over the dummy gate structures 250 and a top surface of the integrated circuit structure 200 is planarized. In some embodiments, the CMP process also removes the hard mask layers 256, 258 (as in 33 shown) and exposes the dummy gate electrode layer 254 .

After that, first the dummy gate structures 250 (as in 34 shown) and then the epitaxial layers (i.e. the sacrificial layers) 222 removed (as in FIG 34 shown). The resulting structure is in 35 shown. In some embodiments, the dummy gate structures 250 are etched using a selective etch process (e.g., selective dry etch, selective wet etch, or a combination thereof) that etches the materials in the dummy gate structures 250 at a faster etch rate than others Materials (e.g., the gate sidewall spacers 260 and/or the ILD layer 310) are etched, thereby creating gate trenches GT2 between the respective gate sidewall spacers 260, exposing the epitaxial layers 222 in the gate trenches GT2. Next, the epitaxial layers 222 in the gate trenches GT2 are removed using another selective etch process that etches the epitaxial layers 222 at a faster etch rate than it etches the channel layers 224, creating openings O5 between adjacent epitaxial layers (the is called the channel layers) 224 form. In this way, the epitaxial layers 224 become nanosheets that are exposed over the substrate 210 and between the source/drain epitaxial structures 280 . This process is also referred to as a channel release process. In this intermediate processing operation, the openings O5 between the epitaxial layers (ie, nanosheets) 224 may be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the epitaxial layers 224 may instead be referred to as nanowires, nanodiscs, and nanorings, depending on their geometry. For example, in some other embodiments, the epitaxial layers 224 may be trimmed to have a substantially rounded shape (ie, a cylindrical shape) due to the selective etch process to completely remove the epitaxial layers 222 . In this case, the resulting epitaxial layers 224 can be referred to as nanowires.

In some embodiments, the epitaxial layers 222 are removed using a selective wet etch process. In some embodiments, epitaxial layers 222 are SiGe and epitaxial layers 224 are silicon, allowing for selective removal of epitaxial layers 222 . In some embodiments, the selective wet etch includes an APM Etching (for example with a mixture of ammonium hydroxide and hydrogen peroxide). In some embodiments, the selective removal includes a SiGe oxidation followed by a SiGeO _x removal. For example, oxidation can be provided by O ₃ Clean, and then SiGeO _x removed by an etchant, such as NH ₄ OH, which selectively etches SiGeO _x at a faster etch rate than it etches Si. In addition, the channel layers 224 are not significantly etched by the channel release process since the oxidation rate of Si is much slower (sometimes 30 times slower) than the oxidation rate of SiGe. It should be noted that both the channel release operation and the previous operation of laterally recessing the sacrificial layers (the one shown in Figs 31A and 31B process shown) use a selective etch process that etches SiGe at a faster etch rate than it etches Si, allowing these two processes to use the same etchant chemistry in some embodiments. In this case, the etching time of the channel release process is longer than the etching time of the previous process of laterally recessing the sacrificial layers in order to completely remove the SiGe sacrificial layers.

In the 36A and 36B For example, replacement gate structures 320 have been respectively formed in the gate trenches GT2 so as to surround each of the epitaxial layers 224 exposed in the gate trenches GT2. Gate structure 320 may be the final gate of a GAA-FET. The final gate structure can be a high-k metal gate stack, although other compositions are possible. In some embodiments, each of the gate structures 320 forms the gate associated with the multiple channels provided by the plurality of epitaxial layers 224. For example, high-k metal gate structures 320 are formed within the openings O ₅ exposed by the release of the epitaxial layers 224 have been provided (as in 36A shown). In various embodiments, high-k metal gate structure 320 includes a gate dielectric layer 322 formed around epitaxial layers 224, a work function metal layer 324 formed around gate dielectric layer 322, and a fill metal 326 formed around the work function metal layer 324 is formed and fills a remainder of the gate trenches GT2. The gate dielectric layer 322 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer over the interface layer. The high-k gate dielectrics used and described herein include dielectric materials having a high dielectric constant greater than, for example, thermal silicon oxide (˜3.9). The work function metal layer 324 and/or the fill metal layer 326 used within the high-k metal gate structures 320 may include a metal, metal alloy, or metal silicides. The formation of the high-k metal gate structures 320 may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate materials. As in a cross-sectional view of 36B 1, cut along a longitudinal axis of a high-k metal gate structure 320, the high-k metal gate structure 320 surrounds each of the epitaxial layers 224, and is therefore considered a gate of a GAA-FET designated. Details regarding materials and processes related to GAA-FET gate structures 320 are similar to those of FinFET gate structures 130, and thus are not repeated here for the sake of brevity.

In 37 an etch-back process is performed to etch back the replacement gate structures 320 , resulting in depressions over the etch-back gate structures 320 . Because the materials of the replacement gate structures 320 have a different etch selectivity than the gate spacers 260, in some embodiments, the top surfaces of the replacement gate structures 320 may be located at a lower level than the top surfaces of the gate spacers 260 .

In 38 dielectric caps 340 have been formed over metal caps 330. FIG. Details regarding materials and processes relating to dielectric caps 340 are similar to those of dielectric caps 142 previously discussed, and thus will not be repeated here for the sake of brevity.

In 39 Source/drain contacts 350 have been formed which extend through the ILD layer 310 (and the CESL layer, if present). Forming source/drain contacts 350 includes, for example but not limitation, performing one or more etch processes to form contact openings that extend through ILD layer 310 to expose source/drain epitaxial structures 280 , depositing one or more metallic materials to overfill the contact openings, and then performing a CMP process to remove excess metallic materials outside of the contact openings. In some embodiments, the one or more etch processes include the selective etch that etches the ILD layer 310 at a faster etch rate than it does the dielectric caps 340 and the gate spacers 260 etches. Consequently, the selective etch is performed using the dielectric caps 340 and the gate spacers 260 as an etch mask so that the contact openings, and thus the source/drain contacts 350, are formed self-aligned to the source/drain epitaxial structures 280. without using an additional photolithography process. In this case, the dielectric caps 340 that enable the formation of the self-aligned contacts 350 may be referred to as SAC caps 340. FIG.

Once the self-aligned source/drain contacts 350 have been formed, as shown in FIG 40 1, etch stop layers (ESL) 360 are formed selectively over the dielectric materials (e.g., SAC caps 340 and gate spacers 260). Details regarding materials and processes relating to ESL 360 are similar to those of ESL 146 previously discussed, and thus will not be repeated here for the sake of brevity.

Subsequently, another ILD layer 370 is deposited over the ESL 360 as shown in FIG 41 shown. In some embodiments, the ILD layer 370 is silicon oxide (SiOx). Details regarding materials and processes related to the ESL 360 are similar to those of the ILD layer 148 previously discussed, and thus will not be repeated here for the sake of brevity.

Referring to 42A For example, the ILD layer 370 is patterned to form via openings 06 that extend through the ILD layer 370 using an etch process ET3 (also referred to as a via etch process). The etch duration of the via etch process ET3 is controlled such that the ILD layer 370 is broken down. As a result of the etch process ET3, the source/drain contacts 350 are exposed at the bottoms of the via openings O6. Details regarding the via etch process ET3 were previously discussed in relation to the via etch process ET1, and thus will not be repeated here for the sake of brevity.

In some embodiments, which in 42A 1, the via openings O6 have tapered sidewall profiles due to the anisotropic etch characteristic of the etch process ET3. However, in some other embodiments, the etch conditions of the etch process ET3 can be fine-tuned to allow the via openings O6 to have a vertical sidewall profile, as in FIG 42B shown.

Referring to 43A Source/drain vias 380 are then formed in via openings O6 to provide physical and electrical connection to source/drain contacts 350. FIG. Details regarding materials and processes relating to source/drain vias 380 are similar to those of source/drain vias 150 previously discussed, and thus will not be repeated here for the sake of brevity. In some embodiments, as in 43A As shown, source/drain vias 380 have a tapered sidewall profile due to the anisotropic etch characteristic of etch process ET3. However, in some other embodiments, the etch conditions of the etch process ET3 can be fine-tuned to allow the via openings O6, and thus the source/drain vias 380, to have a vertical sidewall profile, as shown in FIG 43B shown.

the 44A and 44B 12 are cross-sectional views of integrated circuit structures 200 consistent with some embodiments. In the 44A and 44B are also the gate spacers 260 during the in 37 been etched back using the process shown. Details regarding the etch process of the gate spacers 260 were previously discussed in relation to the etch of the gate spacers 116, and thus will not be repeated here for the sake of brevity. Furthermore, metal caps 330 are selectively formed on top of each of the replacement gate structures 320 by a suitable process such as CVD or ALD, for example. For example, but not by way of limitation, the metal caps 330 may be substantially fluorine-free tungsten (FFW) films, having a fluorine impurity content of less than 5 atomic percent and a chlorine impurity content of greater than 3 atomic percent. Details regarding the process of FFW formation were previously discussed in relation to the metal caps 138, and thus will not be repeated here for the sake of brevity.

the 45 - 48 12 illustrate exemplary cross-sectional views of various stages of manufacturing an integrated circuit structure 200a consistent with some other embodiments of the present disclosure. It should be understood that additional operations before, during, and after the processes illustrated in FIGS 45 - 48 process(es) shown may be provided and that some of the operations described below may be substituted or omitted for additional embodiments of the method. The order of operations/processes may be interchangeable. The same or similar assemblies, materials, processes and/or operations, wel che in the 26 - 43B may be used in the following embodiments, and thus the detailed explanation thereof again may be omitted.

After the in 41 Once the structure shown has been formed, the ILD layer 370 is patterned to form gate contact openings O7 which extend through the ILD layer 370, the ESL 360 and the dielectric cap 340 to the replacement gate structures 320. FIG. The resulting structure is in 45 shown. The ILD layer 148 can be patterned using appropriate photolithography and etching techniques.

Next, as in 46 As shown, a patterned mask layer M5 is formed over substrate 12 to fill gate contact openings O7. The patterned mask layer M5 has an opening O8 vertically above a source/drain contact 350. FIG.

Referring to 47 with the patterned mask layer M5 in place, a via etch process ET4 is performed to form a via opening O9 extending through the ILD layer 370. FIG. The etch duration of the via etch process ET4 is controlled such that the ILD layer 370 is broken down. As a result of the etching process ET4, the source/drain contacts 350 at the bottoms of the via openings 09 are exposed. Details regarding the via etch process ET4 were previously discussed in relation to the via etch process ET1, and thus will not be repeated here for the sake of brevity.

Referring to 48 the patterned mask layer M5 (refer to Fig 47 ) is removed from gate contact openings O7 by ashing and/or wet stripping before forming butt contact 390 to fill via opening O9 and gate contact opening O7 and forming gate contact 395 to fill another gate contact opening to fill O7. The resulting structure is in 48 shown. Details regarding materials and manufacturing processes relating to butt contact 390 and gate contact 395 are similar to those relating to source/drain vias 150, and thus will not be repeated here for the sake of brevity.

Based on the above discussions, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional benefits, and not all benefits are necessarily disclosed herein, and no particular benefit is required for all embodiments. An advantage is that the risk of leakage currents (e.g. leakage current from a source/drain via to a gate contact and/or gate structure) due to the etch stop layer can be reduced. Another advantage is that a patterning process for forming the etch stop layer can be omitted. Yet another advantage is that resistive-capacitance (RC) delay can be improved due to a long distance from source/drain via to a gate contact.

In accordance with some embodiments, a method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region near the gate structure and over the substrate. An etch stop layer is selectively formed over the dielectric cap without overlapping the source/drain contact. An interlayer dielectric is deposited over the etch stop layer and the source/drain contact. A source/drain via is formed that extends through the ILD and the source/drain contact.

In accordance with some embodiments, a device includes a source/drain contact, an etch stop layer, an interlayer dielectric (ILD) layer, and a source/drain via. The source/drain contact is arranged over a source/drain region of a transistor. The etch stop layer is arranged over a gate structure of the transistor. The etch stop layer has a stepped spacing over the source/drain contact and a sidewall substantially aligned with a sidewall of the source/drain contact. The ILD layer is arranged over the etch stop layer. The source/drain via extends through the ILD layer and the etch stop layer to the source/drain contact.

In accordance with some embodiments, a device includes first and second source/drain contacts, an etch stop layer, an interlayer dielectric (ILD) layer, and a via structure. The first and second source/drain contacts are disposed over first and second source/drain regions, respectively, of a transistor. The etch stop layer is arranged over a gate structure of the transistor. The ILD layer is disposed over the etch stop layer and has a stepped bottom surface having a bottom step in contact with a top surface of the first source/drain region and a top step in contact with a top surface of the etch stop layer. The via structure extends through the ILD layer and the etch stop layer to the gate structure.

The foregoing sets forth features of various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and/or obtain the same advantages of the embodiments presented herein. It should further be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and reconfigurations without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63/084999 [0001]

Claims (20)

Method comprising: forming a gate structure over a substrate; forming a dielectric cap over the gate structure; forming a source/drain contact over a source/drain region adjacent the gate structure and over the substrate; selectively forming an etch stop layer over the dielectric cap without overlapping the source/drain contact; depositing an interlayer dielectric (ILD) layer over the etch stop layer and the source/drain contact; and Forming a source/drain via extending through the ILD layer to the source/drain contact. procedure after claim 1 , wherein the selective formation of the etch stop layer is performed using a selective atomic layer deposition process. procedure after claim 1 or 2 wherein selectively forming the etch stop layer comprises: forming a barrier layer over the source/drain contact such that the barrier layer exposes the dielectric cap; depositing the etch stop layer over the dielectric cap; and removing the barrier layer after depositing the etch stop layer. procedure after claim 3 , where the barrier layer is polymer, benzotriazole (BTA) or a self-assembled monolayer (SAM). The method of any preceding claim, further comprising etching back the gate structure prior to forming the dielectric cap. The method of any preceding claim, wherein the forming of the ILD layer is such that the ILD layer has a stepped bottom surface with a top step contacting the etch stop layer and a bottom step contacting the source/drain contact , having. The method of any preceding claim, wherein forming the source/drain via in the ILD layer includes performing an etch process to form an opening extending through the ILD layer to expose the source/drain contact. wherein the etch process etches the ILD layer at a faster etch rate than it etches the etch stop layer. procedure after claim 7 , wherein the etching process is performed such that the opening further exposes the etch stop layer. A method according to any one of the preceding claims, wherein the etch stop layer, the dielectric cap and the ILD layer contain different materials. The method of any preceding claim, wherein the etch stop layer is formed such that a thickness of the etch stop layer is in a range from about 3 nm to about 10 nm. Device comprising: a source/drain contact over a source/drain region of a transistor; an etch stop layer over a gate structure of the transistor, the etch stop layer having a step spacing over the source/drain contact and a sidewall substantially aligned with a sidewall of the source/drain contact; an interlayer dielectric (ILD) layer over the etch stop layer; and a source/drain via extending through the ILD layer to the source/drain contact. device after claim 11 wherein the source/drain via is disposed in contact with a top surface of the etch stop layer. device after claim 11 or 12 , further comprising a gate spacer between the source/drain contact and the gate structure, wherein the etch stop layer is further disposed over the gate spacer. Device according to any of the preceding Claims 11 until 13 , further comprising a dielectric cap between the etch stop layer and the gate structure. Device according to any of the preceding Claims 11 until 14 wherein the source/drain via has a notched corner in contact with the etch stop layer. Device according to any of the preceding Claims 11 until 15 wherein the source/drain via has a first linear interface with the ILD and a second linear interface with the ESL, and wherein the first and second linear interfaces are misaligned with one another. device after Claim 16 , where the first linear interface is more inclined than the second linear interface. Device comprising: first and second source/drain contacts disposed over first and second source/drain regions, respectively, of a transistor; an etch stop layer over a gate structure of the transistor; an interlayer dielectric (ILD) layer over the etch stop layer and having a stepped bottom surface having a bottom step in contact with a top surface of the first source/drain contact and a top step in contact with a top surface of the etch stop layer; and a via structure extending through the ILD layer and the etch stop layer to the gate structure. device after Claim 18 , wherein the via structure is further in contact with the second source/drain contact. device after Claim 18 or 19 , wherein the via structure has a greater thickness over the gate structure than over the second source/drain contact.

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