DE102020131432A1 - SOURCE / DRAIN CONTACT STRUCTURE - Google Patents

Abstract

A semiconductor device according to the present disclosure includes a first interconnection structure, a first transistor over the first interconnection structure, a second transistor over the first transistor, and a second interconnection structure over the second transistor. The first transistor has first nanostructures and a first source region which adjoins the first nanostructures. The second transistor has second nanostructures and a second source region which adjoins the second nanostructures. The first source region is coupled to a first power supply rail in the first connection structure and the second source region is coupled to a second power supply rail in the second connection structure.

Description

PRIORITY DATA

This application claims priority to U.S. Provisional Patent Application No. 63 / 028,770 entitled “SOURCE / DRAIN CONTACT STRUCTURE” (attorney's file number 2020-1124 / 24061.4212PV01), the entire disclosure of which is hereby incorporated by reference into the present application.

BACKGROUND

The semiconductor integrated circuit (IC) industry has grown exponentially. Advances in technology in IC materials and designs have produced generations of ICs, with each generation having smaller and more complex circuits than the previous generation. As IC development has continued, functional density (i.e., the number of interconnected components per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process generally offers advantages in improving production efficiency and lowering associated costs. This downsizing has also increased the complexity of processing and manufacturing ICs.

For example, with the advancement of IC technologies in the direction of smaller technology nodes, multigate devices were introduced to improve gate control by increasing gate-channel coupling, reducing current when switched off, and reducing short-channel effects (SCEs) . A multigate device generally refers to a device having a gate structure, or a portion thereof, disposed over more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC and multi-bridge channel) transistors are examples of multi-gate devices that have become popular and promising candidates for high power, low leakage current applications. A FinFET has a raised channel that is enclosed by a gate on more than one side (for example, the gate encloses a top and side walls of a “fin” of semiconductor material that extends from a substrate). An MBC transistor has a gate structure that can extend partially or completely around a channel region in order to provide access to the channel region on two or more sides. Since its gate structure surrounds the channel areas, an MBC transistor is sometimes referred to as a surrounding gate transistor (SGT) or a gate-all-around transistor (GAA transistor) . The channel region of an MBC transistor can be formed from nanowires, nanofoils, other nanostructures and / or other suitable structures.

The implementation of multigate transistors reduces device dimensions and increases device packaging density, which is a challenge in forming the power and signal routing. While existing source / drain contact structures are generally sufficient for their intended purposes, they are not satisfactory in all aspects.

Figure list

• 1 veranschaulicht ein Flussdiagramm eines Verfahrens zum Ausbilden einer Halbleitervorrichtung, die eine rückseitige Stromversorgungsschiene aufweist, gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 2-10, 11A-17A und 11B-17B veranschaulichen unvollständige Querschnittsansichten eines Werkstücks während eines Herstellungsprozesses gemäß dem Verfahren aus 1 gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 18 veranschaulicht ein Flussdiagramm eines Verfahrens zum Ausbilden einer Halbleitervorrichtung, die eine rückseitige Stromversorgungsschiene aufweist, gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 19-28, 29A-35A und 29B-35B veranschaulichen unvollständige Querschnittsansichten eines Werkstücks während eines Herstellungsprozesses gemäß dem Verfahren aus 18 gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 36 veranschaulicht ein Flussdiagramm eines Verfahrens zum Ausbilden einer Halbleitervorrichtung, die eine rückseitige Stromversorgungsschiene aufweist, gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 37-44, 45A-50A und 45B-50B veranschaulichen unvollständige Querschnittsansichten eines Werkstücks während eines Herstellungsprozesses gemäß dem Verfahren aus 36 gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 51A und 5B veranschaulichen unvollständige Querschnittsansichten einer Halbleitervorrichtung gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 52 veranschaulicht ein Flussdiagramm eines Verfahrens zum Ausbilden einer gemeinsamen Gate-Struktur gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.
• 53-57 veranschaulichen unvollständige Querschnittsansichten eines Werkstücks in verschiedenen Stadien des Verfahrens aus 52 gemäß einem oder mehreren Aspekten der vorliegenden Offenbarung.

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It is emphasized that, in accordance with common industry practice, various features are not drawn to scale and are used for illustration purposes only. Indeed, for clarity of discussion, the dimensions of the various features can be arbitrarily enlarged or reduced.

• 1 FIG. 11 illustrates a flow diagram of a method of forming a semiconductor device having a back power supply rail according to one or more of several aspects of the present disclosure.
• 2-10 , 11A-17A and 11B-17B FIG. 10 illustrates incomplete cross-sectional views of a workpiece during a manufacturing process according to the method of FIG 1 according to one or more aspects of the present disclosure.
• 18th FIG. 11 illustrates a flow diagram of a method of forming a semiconductor device having a rear power supply rail, in accordance with one or more aspects of the present disclosure.
• 19-28 , 29A-35A and 29B-35B FIG. 10 illustrates incomplete cross-sectional views of a workpiece during a manufacturing process according to the method of FIG 18th according to one or more aspects of the present disclosure.
• 36 FIG. 11 illustrates a flow diagram of a method of forming a semiconductor device having a rear power supply rail, in accordance with one or more aspects of the present disclosure.
• 37-44 , 45A-50A and 45B-50B FIG. 10 illustrates incomplete cross-sectional views of a workpiece during a manufacturing process according to the method of FIG 36 according to one or more aspects of the present disclosure.
• 51A and 5B 12 illustrate fragmentary cross-sectional views of a semiconductor device in accordance with one or more aspects of the present disclosure.
• 52 FIG. 11 illustrates a flow diagram of a method of forming a common gate structure in accordance with one or more aspects of the present disclosure.
• 53-57 illustrate incomplete cross-sectional views of a workpiece at various stages of the process 52 according to one or more aspects of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing different features of the provided article. In order to simplify the present disclosure, specific examples of components and arrangements are described below. These are of course only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features are so between the first and the second feature can be formed that the first and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not per se provide any relationship between the various embodiments and / or configurations discussed.

Spatially relative terms such as “below”, “below”, “lower”, “above”, “upper / r / s” and the like can be used in the present case to simplify the description and to relate an element or feature to describe one or more other elements or features as illustrated in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device during use or operation. The object may be oriented differently (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly.

When describing a number or a range of numbers with “approximately”, “approximately” and the like, the term is also intended to encompass numbers which, taking into account variations that generally occur during manufacture, are within a realistic range, as would be done by a person skilled in the art is understood. For example, the number or range of numbers comprises a realistic range containing the number described, for example within ± 10% of the number described, based on known manufacturing tolerances associated with the manufacture of a feature that has a property that is associated with the Number is connected. For example, a material layer having a thickness of “approximately 5 nm” may include a dimensional range of 4.25 nm to 5.75 nm, it being known to those skilled in the art that manufacturing tolerances associated with the deposition of the material layer are ± 15%. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not per se provide any relationship between the various embodiments and / or configurations discussed.

The high packing density achieved through the use of MBC transistors creates challenges in forming satisfactory power and signal routing structures and features. To address these challenges, the present disclosure provides embodiments that use different combinations of contact structure plans to achieve flexibility and density in power and signal routing. For example, when a second MBC transistor is disposed over a first MBC transistor, contact structures in accordance with the present disclosure include double interconnect structures, hybrid fins with embedded conductive features, and staggered stacking of devices. In the "double connection structures", a source feature of the first MBC transistor is coupled by a rear source contact to a power supply rail in a first connection structure and a source feature of the second MBC transistor is coupled to a power supply rail in a second connection structure above the second MBC -Transistor coupled. In the case of the “hybrid fins with embedded conductive features”, a conductive feature is embedded in each of the hybrid fins in order to provide contact modules that can be used as conduction paths Serve connection structures. In “staggered device stacking,” the source / drain regions of the first MBC transistor and the second MBC transistor are offset from one another to increase the spacing between vias and drain features.

The various aspects of the present disclosure will now be described in greater detail with reference to the figures. In this regard are 1 , 18th and 36 Flowcharts showing procedures 100 , 300 and 500 for forming a semiconductor device from a workpiece in accordance with embodiments of the present disclosure. The proceedings 100 , 300 and 500 are only examples and are not intended to limit the present disclosure to what is included in the methods 100 , 300 and 500 is explicitly illustrated. Additional steps can be taken before, during, and after the procedure 100 , 300 and 500 and some of the steps described may be replaced, omitted, or postponed for additional embodiments of the methods. For the sake of simplicity, not all steps are described in detail here. The proceedings 100 , 300 and 500 are referred to below in conjunction with 2-10 , 11A-17A , 11B-17B , 19-28 , 29A-35A , 29B-35B , 37-44 , 45A-50A and 45B-50B described which incomplete cross-sectional views of the workpiece in various manufacturing stages according to embodiments of the method 100 , 300 and 500 are. To better illustrate various aspects of the present disclosure, all figures ending with the capital letter A illustrate an incomplete cross-sectional view of a source region, and all figures ending with the capital letter B illustrate an incomplete cross-sectional view of a drain region. The present disclosure also provides a method 600 ready to form a common gate structure that activates two vertically aligned MBC transistors. This in 52 illustrated procedures 600 is used in conjunction with cross-sectional views in 53-57 described. The procedure 600 can with at least the procedure 100 and 300 be used.

Referring to 1 and 2 includes the procedure 100 one block 102 in which a workpiece 200 provided. It is noted that since from the workpiece 200 a semiconductor device is manufactured, the workpiece 200 Depending on the context, also as a semiconductor device 200 can be designated. The workpiece 200 can be a substrate 202 exhibit. Although this is not explicitly shown in the figures, the substrate 202 can, however, have an n-well region and a p-well region for producing transistors of different conductivity types. In one embodiment, the substrate 202 be a substrate made of silicon (Si). In some other embodiments, the substrate 202 contain other semiconductors such as germanium (Ge), silicon germanium (SiGe) or a III-V semiconductor material. Exemplary III-V semiconductor materials can include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide ( ) contain. The substrate 202 may also include an insulating layer such as a silicon oxide layer to have a silicon-on-insulator (SOI) structure. If any, all n-wells and all p-wells are in the substrate 202 formed and have a doping profile. An n-well can have a doping profile of an n-dopant such as phosphorus (P) or arsenic (As). A p-well can have a doping profile of a p-type dopant such as boron (B). The doping in the n-well and the p-well can be formed using ion implantation or thermal diffusion and can be formed as a portion of the substrate 202 to be viewed as. For the avoidance of doubt: the X-direction, the Y-direction and the Z-direction are perpendicular to each other.

As in 2 is shown, has the workpiece 200 also a first batch 204 on that above the substrate 202 is arranged. The first batch 204 has a plurality of channel layers 208 on that with a variety of sacrificial layers 206 is arranged alternately. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. In some implementations, these are channel layers 208 formed from silicon (Si) and the sacrificial layers 206 made of silicon germanium (SiGe). In these implementations, the additional germanium content in the sacrificial layers enables 206 selective removal or deepening of the sacrificial layers 206 without significant damage to the channel layers 208 . In some embodiments, the sacrificial layers are 206 and the channel layers 208 Epitaxial layers and can be deposited using an epitaxial process. Suitable epitaxial processes include gas phase epitaxy (VPE), chemical vapor deposition in ultra-high vacuum (UHV-CVD), molecular beam epitaxy (MBE) and / or other suitable processes. As in 2 shown are the sacrificial layers 206 and the channel layers 208 deposited alternately one after the other to the first pile 204 to train. It is noted that as in 2 illustrates three (3) layers of the sacrificial layers 206 and three (3) layers of the channel layers 208 are arranged alternately and vertically, which is for illustrative purposes only and is not intended to be more restrictive than what is expressly stated in the claims is specified. It can be seen that any number of sacrificial layers 206 and channel layers 208 in the first batch 204 can be formed. The number of layers depends on the number of channel elements desired for the device 200 away. In some embodiments, the number of channel layers is within 208 between 2 and 10.

Referring to 1 and 3 includes the procedure 100 one block 104 in which a first fin-shaped structure 209 from the first batch 204 is trained. In some embodiments, the first batch 204 and a portion of the substrate 202 structured around the first fin-shaped structure 209 to train. A hard mask layer can be placed over the first stack for structuring purposes 204 to be deposited. The hard mask layer can be a single layer or a multiple layer. In one embodiment, the hard mask layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. As in 3 As shown, the first fin-shaped structure extends 209 vertically in the Z-direction from the substrate 202 and along in the Y direction. The first fin-shaped structure 209 has a base portion 209B that comes from the substrate 202 is formed, and a stacking portion 209S that from the first batch 204 is trained on. The first fin-shaped structure 209 can be structured using appropriate processes including double structuring or multiple structuring processes. In general, double structuring or multiple structuring processes combine photolithography and self-aligning processes, whereby structure patterns can be generated that, for example, have distances that are smaller than those that can otherwise be achieved with a single direct photolithography process. For example, in one embodiment, a layer of material is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned layer of material using a self-aligned process. The layer of material is then removed and the remaining spacers or mandrels can then be used to create the first fin-shaped structure 209 by etching the first stack 204 and the substrate 202 to structure. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some in 3 implementations shown may after the first fin-shaped structure 209 was formed, a first liner 210 conformal over the workpiece 200 to be deposited. The first lining 210 may contain silicon nitride and may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Referring to 1 and 4th includes the procedure 100 one block 106 , in which an isolation feature 214 is trained. The isolation feature 214 can also be used as a shallow trench isolation (STI) feature 214 are designated. In an exemplary process, a dielectric material is used for the isolation feature 214 using CVD, vacuum CVD (SACVD), flowable CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating, and / or any other suitable process over the first liner 210 deposited. The deposited dielectric material is then planarized and recessed until the first fin-shaped structure 209 about the isolation feature 214 increases. That is, after deepening the isolation feature 214 is the base section 209B the first fin-shaped structure 209 from the isolation feature 214 surround. The dielectric material for the isolation feature 214 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. After the isolation feature 214 has been deepened, becomes the first lining 210 selectively recessed until the stacking section 209S the first fin-shaped structure 209 exposed.

Referring to 1 and 5 includes the procedure 100 one block 108 in which a sacrificial spacer layer 216 above the first fin-shaped structure 209 and the isolation feature 214 is deposited. In some embodiments, the sacrificial spacer layer can be 216 Containing silicon oxide and conforming above the workpiece 200 to be deposited. The sacrificial spacer layer 216 is on and along upper surfaces of the isolation feature 214 as well as the top surface and the side walls of the stacking section 209S arranged.

Referring to 1 and 6th includes the procedure 100 one block 110 in which a first dielectric layer 218 over the sacrificial spacer layer 216 is deposited. The first dielectric layer 218 may include silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, or a dielectric material that allows selective etching of the sacrificial spacer layer 216 enables. The first dielectric layer 218 can be deposited using CVD. Although this is not explicitly shown in the figures, a planarization process such as a chemical-mechanical polishing process (CMP process) can, however, be carried out on the workpiece 200 carried out to the top surface of the stacking section 209S to expose. The planarization process also lays down top surfaces of the sacrificial spacer layer 216 free.

Referring to 1 and 7th includes the procedure 100 one block 112 in which the sacrificial spacer layer 216 is selectively etched back to the stack portion 209S the first fin-shaped structure 209 to release. As in 7th shown are at block 112 vertical portions of the sacrificial spacer layer 216 extending along side walls of the stacking section 209S extends, selectively removed without the stacking section 209S and the first dielectric layer 218 substantial damage. In one embodiment in which the sacrificial spacer layer 216 is formed from silicon oxide and the first dielectric layer 218 is formed from silicon nitride, the sacrificial spacer layer 216 possibly selectively use diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). In the present case, BHF contains hydrofluoric acid and ammonium fluoride. After completing the operations from block 112 are hybrid fins 217 on both sides of the stacking section 209S formed, wherein they are longitudinally parallel to the stack portion 209S extend. Each of the hybrid fins 217 exhibits the sacrificial spacer layer 216 and the first dielectric layer 218 over the sacrificial spacer layer 216 on.

Referring to 1 and 8th includes the procedure 100 one block 114 in which a dummy gate stack 222 above the stacking section 209S and the hybrid fins 217 is trained. In some embodiments, a gate replacement (or gate last process - gate last process) is used in which the dummy gate stack 222 serves as a placeholder for a functional gate structure. Other processes and configurations are possible. To the dummy gate stack 222 To form a dummy dielectric layer, a dummy gate electrode layer, and an on-gate hard mask layer over the workpiece 200 deposited. The deposition of these layers can include the use of low pressure CVD (LPCVD), CVD, plasma enhanced CVD (PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof. The dummy dielectric layer can contain silicon oxide, the dummy gate electrode layer can contain polysilicon, and the on-gate hard mask layer can be a multilayer containing silicon oxide and silicon nitride. The on-gate hard mask layer is patterned using photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), softbake, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof include. The etching process can include dry etching (e.g., RIE etching), wet etching, and / or other etching processes. Thereafter, using the patterned on-gate hard mask as an etch mask, the dummy dielectric layer and the dummy gate electrode layer are etched around the dummy gate stack 222 to train. As in 8th shown becomes the dummy gate stack 222 above the isolation feature 214 , the hybrid fins 217 and a portion of the first fin-shaped structures 209 educated. The dummy gate stack 222 extends longitudinally in the X direction in such a way that it forms the first fin-shaped structure 209 encloses. The section of the first fin-shaped structure 209 that is under the dummy gate stack 222 is a canal area. The channel area and the dummy gate stack 222 also define source / drain regions from the dummy gate stack 222 not be overlapped vertically. The channel region is arranged in the Y direction between two source / drain regions.

Although this is not explicitly shown, operations at block 114 however, a gate spacer layer can be formed over the top surface and sidewalls of the dummy gate stack 222 include. In some embodiments, forming the gate spacer layer includes conformally depositing one or more dielectric layers over the workpiece 200 . In an exemplary process, the one or more dielectric layers are deposited using CVD, SACVD, or ALD. The one or more dielectric layers can include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof.

Referring to 1 and 9 includes the procedure 100 one block 116 , in the source / drain portions of the first fin-shaped structure 209 deepened to source / drain wells 224 to train. It is noted that the cross section in 9 a source region or a drain region of the first fin-shaped structure 209 intersects and the channel region of the first fin-shaped structure lies outside the cross-sectional plane. For illustration, structures in the canal area are also shown in 9 illustrated with dotted lines. In an exemplary process, the workpiece is 200 after the gate spacer layer has been deposited, the source / drain regions of the first fin-shaped structure are etched in an etching process 209 selectively deepened. The selective depression of the source / drain regions results in source / drain trenches 224 between the hybrid fins 217 . The etching process at Block 116 can be a dry etching process or a suitable etching process. An exemplary dry etching process can be an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g. CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and / or C ₂ F ₆ ), a chlorine-containing gas (e.g. Cl ₂ , CHCl ₃ , CCl ₄ and / or BCl ₃ ), a bromine-containing gas (e.g. HBr and / or CHBR ₃ ), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As in 9 shown lie side walls of the sacrificial layers 206 and the channel layers 208 in the channel area in the source / drain trenches 224 free.

Referring to 1 and 10 includes the procedure 100 one block 118 , in which inner spacer features 226 be formed. At block 118 become those in the source / drain trenches 224 exposed sacrificial layers 206 selectively and partially recessed to form interior spacer recesses with the exposed channel layers 208 remain essentially unetched. In one embodiment in which the channel layers 208 consist essentially of silicon (Si) and the sacrificial layers 206 consist essentially of silicon germanium (SiGe), the selective and partial deepening of the sacrificial layers 206 comprise a SiGe oxidation process followed by SiGe oxide removal. In this embodiment, the SiGe oxidation process can _{include use of ozone (O 3} ). In some other embodiments, the selective recess may be a selective isotropic etch process (e.g., a selective dry etch process or a selective wet etch process) and the extent to which the sacrificial layers 206 are deepened is controlled by the duration of the etching process. The selective dry etch process may include using one or more fluorine-based etchants such as fluorine gas or fluorocarbons. The selective wet etch process can include a hydrogen fluoride (HF) or NH ₄ OH etchant. After the inner spacer dimples are formed, an inner spacer material layer is placed over the workpiece 200 , including in the inner spacer recesses. The inner spacer material layer can contain silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess of the inner spacer material layer over the gate spacer layer and the sidewalls of the channel layers 208 remove, eliminating the inner spacer features 226 as in 10 shown. In some embodiments, the etch back process may be at block 118 be a dry etching process, the use of an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g. CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and / or C ₂ F ₆ ), a chlorine-containing gas (e.g. B. Cl ₂ , CHCl ₃ , CCl ₄ and / or BCl ₃ ), a bromine-containing gas (e.g. HBr and / or CHBR ₃ ), an iodine-containing gas (e.g. CF ₃ I), other suitable gases and / or plasmas and / or combinations thereof.

Referring to 1 , 11A and 11B includes the procedure 100 one block 120 , in which a first source characteristic 228S and a first drain feature 228D in the source / drain trenches 224 be formed. It should be noted that the source area 200S and the drain area 200D in 11A respectively. 11B are illustrated separately. The source area is similar 200S in 12A-17A shown and the drain area 200D in 12B-17B illustrated. In some embodiments, the first source feature 228S and the first drain feature 228D using an epitaxial process such as VPE, UHV-CVD, MBE and / or other suitable processes. The epitaxial growth process can use gaseous and / or liquid precursors that match the composition of the substrate 202 as well as the channel layers 208 to interact. The first source feature 228S and the first drain feature 228D are therefore with the channel layers 208 or coupled to the released channel. Depending on the conductivity type of the MBC transistor to be formed, the first source feature 228S and the first drain feature 228D n-source / drain features or p-source / drain features. Exemplary n-source / drain features can include Si, GaAs, GaAsP, SiP or another suitable material and can be doped in situ with the introduction of an n-dopant such as phosphorus (P), arsenic (As) during the epitaxial process or under Using an implantation process (ie, a transitional implantation process) to be doped ex situ. Exemplary p-source / drain features can include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or another suitable material and can be doped in situ with the introduction of a p-type dopant such as boron (B) during the epitaxial process or using a Implantation process (ie a transitional implantation process) are doped ex situ.

Referring to 1 , 12A and 12B includes the procedure 100 one block 122 in which the dummy gate stack 222 is replaced by a first gate structure (not shown). Operations at block 122 include deposition of a first contact etch stop layer (CESL) 230 , Deposition of a first interlayer dielectric layer (interlayer dielectric or ILD layer) 232, removal of the dummy gate stack 222 , selective removal of the sacrificial layers 206 to expose channel elements, formation of the first gate structure and planarization of the workpiece 200 to remove excess material. The first CESL 230 may include silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be produced by ALD, plasma enhanced chemical vapor deposition (PECVD) processes, and / or others suitable deposition or oxidation processes are formed. As in 12A and 12B is shown, the first CESL 230 on top surfaces of the first source feature 228S , the first drain features and the hybrid fins 217 to be deposited. The first ILD layer 232 can use materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide such as boron phosphorus silicate glass (BPSG), quartz glass (FSG - Fused Silica Glass), phosphorus silicate glass (PSG), boron-doped silicon glass (BSG - boron-doped silicon glass) and / or contain other suitable dielectric materials. The first ILD layer 232 can be deposited by a PECVD process or another suitable deposition technique. In some embodiments, the workpiece 200 after the formation of the first ILD layer 232 Annealed to the integrity of the first ILD layer 232 to improve. To remove excess material and the top surfaces of the dummy gate stack 222 To expose, a planarization process such as a chemical mechanical polishing (CMP) process can be performed.

After exposing the dummy gate stack 222 moves the block 122 with removal of the dummy gate stack 222 away. The removal of the dummy gate stack 222 may include one or more etch processes common to the material in the dummy gate stack 222 are selective. For example, removing the dummy gate stack 222 using a selective wet etch, a selective dry etch, or a combination thereof. After removing the dummy gate stack 222 become side walls of the channel layers 208 and sacrificial layers 206 in the channel area between the source area 200S and the drain area 200D is arranged, exposed. After that, the sacrificial layers 206 in the channel area selectively removed to the channel layers 208 to be released as channel elements. Since the dimensions of the channel elements are nanoscale, the channel elements can also be referred to as nanostructures in the present case. The selective removal of the sacrificial layers 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etch includes an APM etch (e.g., an ammonia-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by silicon germanium oxide removal. For example, the oxidation can be provided by an ozone purge and then silicon germanium oxide can be _{removed by an etchant such as NH 4} OH.

When the channel elements have been released, the first gate structure (its view through the first source feature 228S is hidden) deposited such that it encloses each of the channel elements in the channel region. The gate structure has an interface layer around and in contact with the channel elements, a gate dielectric layer over the interface layer, and a gate electrode layer over the gate dielectric layer. In some embodiments, the interface layer includes silicon oxide and can be formed in a pre-cleaning process. An exemplary pre-cleaning process may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The gate dielectric layer is then deposited over the interface layer using ALD, CVD and / or other suitable methods. The gate dielectric layer can be formed from high-k dielectric materials. As used and described herein, high-k dielectric materials include dielectric materials having a high dielectric constant, for example greater than that of thermal silicon oxide (about 3.9). The gate dielectric layer can contain hafnium oxide. Alternatively, the gate dielectric layer can contain other dielectrics with a high k value, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta ₂ O ₅ ), hafnium silicon _{oxide (HfSiO 4} ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₂ ) Lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO), yttrium oxide (Y ₂ O ₃ ), SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide ( LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HffaO), hafnium titanium oxide (HffiO), (Ba, Sr) TiO ₃ (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof or another suitable material.

The gate electrode layer is then deposited over the gate dielectric layer using ALD, PVD, CVD, electron beam evaporation, or other suitable methods. The gate electrode layer can have a single layer or, alternatively, a multilayer structure, such as various combinations of a metal layer with a selected work function to improve the performance of the device (work function metal layer), a lining layer, a wetting layer, an adhesive layer, a metal alloy or a metal silicide. For example, the gate electrode layer may be titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum (TiAl), aluminum (TaCarbon), tungsten (TaAlC), tantalum carbon nitride (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable ones Metal materials or a combination of which included. Know the semiconductor device 200 N-type transistors and p-type transistors, different gate electrode layers may also be formed separately for n-type transistors and p-type transistors, which may have different metal layers (e.g. to provide different n-type work function metal layers. Type and p-type).

Referring to 1 , 13A and 13B includes the procedure 100 one block 124 , in which a first drain contact 234 is trained. In an exemplary process, lithography processes are used to form a contact opening that has the first drain feature 228D exposed. To reduce contact resistance, a silicide layer can be placed on the first drain feature 228D be formed by placing a metal layer over the first drain feature 228 is deposited and an annealing process is performed to silicidation between the metal layer and the first drain feature 228 to effect. A suitable metal layer can contain titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) or tungsten (W). The silicide layer can contain titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi) or nickel silicide (NiSi). After the formation of the silicide layer, a metal filler layer can be deposited in the contact opening. The metal filling layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride ( TaN) included. A planarization process can follow to provide a planar top surface that sets the stage for subsequent processes.

Referring to 1 , 14A and 14B includes the procedure 100 one block 126 in which a second pile 240 on the workpiece 200 is bonded. In some embodiments, a cover layer is used 236 flat over the workpiece 200 deposited. In some implementations, the top layer includes 236 Silicon oxide and can also be used as a top oxide layer 236 are designated. Like the first batch 204 also contains the second batch 240 a variety of channel layers 208 that with a variety of sacrificial layers 206 is arranged alternately. In the in 14A and 14B Embodiments shown have the first stack 204 and the second batch 240 the same number of channel layers 208 and sacrificial layers. However, the present disclosure is not limited to the first stack 204 and the second batch 240 can have different configurations, for example different numbers of layers or different layer thicknesses. To make bonding easier, a base layer is used 238 on a bottom surface of the second stack 240 educated. The second stack and the base layer 238 can opposite the substrate 202 can be viewed as another substrate. In some implementations, the base layer contains 238 Silicon oxide and can also be used as a base oxide layer 238 are designated. For the avoidance of doubt, it is noted that the second stack is 240 which is separated into 14A and 14B is shown to be one and the same. In some embodiments, the second stack 240 by using the interface between the top layer 236 and the base layer 238 directly to the workpiece 200 be bonded. In an exemplary direct bonding process, both the top layer 236 as well as the base layer 238 purified using RCA SC-1 (ammonia, hydrogen peroxide and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide and water). The cleaned top layer 236 and base layer 238 are then put together and pressed together. The direct bonding can be strengthened by a tempering process.

Referring to 1 , 15A and 15B includes the procedure 100 one block 128 , in which operations from the blocks 104 , 108-122 on the second pile 240 be performed. Due to the similarity of the process steps, the processes are in block 128 summarized for the sake of simplicity. At block 104 becomes the second batch 240 structured to form a second fin-shaped structure (the view of which is hidden by other structures). Because the second fin-shaped structure through the top layer 236 and the base layer 238 is isolated, can block the operations 106 be omitted. At the blocks 108 , 110 and 112 become upper hybrid fins 242 formed on both sides of the second fin-shaped structure, extending parallel to the second fin-shaped structure. At block 114 For example, a counterpart dummy gate stack is formed over the channel region of the second fin-shaped structure to serve as a placeholder for a functional second gate structure. At block 116 the source / drain portion of the second fin-shaped structure is recessed, similar to the source / drain trenches 224 Form source / drain wells. At block 118 become the sacrificial layers 206 selectively and partially etched in the channel region to form internal spacer recesses, and internal spacer features are formed in such internal spacer recesses. At block 120 becomes a second source feature 244S and a second drain feature 244D formed in the source / drain recesses. At block 122 the dummy gate stack over the second fin-shaped structure is replaced by a second gate structure. The sacrificial layers 206 in the channel area are selectively removed to the channel layers 208 as channel elements, and the second gate structure encloses each of the channel elements. Before replacing the dummy gate stack, a second CESL 246 and a second ILD layer 248 one after the other over the upper hybrid fins 242 , the second source feature 244S and the second drain feature 244D deposited.

Referring to 1 , 16A and 16B includes the procedure 100 one block 130 , in which an upper source contact 250 , a second drain contact 252 , a first via 258 , a second via 260 and a third via 262 be formed. As in 17A is the top source contact 250 over and in contact with the second source feature 244S educated. Similar to the first drain contact 234 a contact opening is first made to the second source feature 244S Then, to expose a silicide layer on the second source feature 244S and a metal fill layer is deposited to fill the remainder of the contact opening. Similarly, a second drain contact is made 252 over and in contact with the second drain feature 244D educated. After the upper source contact has been formed 250 and the second drain contact 252 an etch stop layer (ESL) 254 and a third ILD layer 256 above the upper source contact 250 and the second drain contact 252 deposited in order to passivate them.

The formation of the first via 258 , the second via 260 and the third via 262 can form a via opening through at least the ESL 254 and the third ILD layer 256 and depositing a metal fill layer. The metal filling layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride ( TaN) included. In some embodiments, the first via 258 , the second via 260 and the third via 262 each have a liner between the metal filler layer and the adjacent dielectric material to improve electrical integrity. Such a lining can contain titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN) or tantalum nitride (TaN). Because the formation of the second via 260 requires the formation of a via opening that extends not only through the ESL 254 and the third ILD layer 256 , but also through the second ILD layer 248 , the second ILD 246 , the upper hybrid fin 242 , the base layer 238 and the top layer 236 extends, the via opening for the second via 260 not at the same time as via openings for the first via 258 and the third via 262 educated. In some other embodiments, the formation of the via opening for the second via 260 formed separately and etched in several etching stages.

Referring to 1 , 16A and 16B includes the procedure 100 one block 132 , in which an upper connection structure 270 is trained. The upper connection structure 270 has a first passivation layer 263 and conductive features in the first passivation layer 263 on. In the illustrated embodiments, the conductive features include a top power supply rail 264 , a first line 266 and a second line 268 . The upper power supply rail 264 is in direct contact with the first via 258 . In other words, the first via couples 258 the upper power supply rail 264 and the second source feature 244S electric. This is where the top power supply rail becomes 264 (or any other power supply rail) is referred to as such because it provides a positive supply voltage. In an exemplary process, the first passivation layer 263 above the workpiece 200 deposited, the first passivation layer 263 is then patterned and a conductive material is patterned over the first passivation layer 263 deposited. True, the upper connecting structure includes 270 in 16A and 16B only a single connection layer, the upper connection structure 270 however, may include more tie layers and may have all tie layers over the workpiece 200 include. As in 16B shown is the second via 260 in direct contact with the first line 266 and the third via 262 in direct contact with the second line 268 .

Referring to 1 , 17A and 17B includes the procedure 100 one block 134 , in which a rear source contact 274 is trained. Although this is in 17A and 17B not so illustrated, operations at block 134 however, can be performed while the workpiece 200 is bonded to a carrier substrate and turned upside down. In an exemplary process, the substrate is made 202 ground or planarized by a grinding process and / or a chemical-mechanical polishing process (CMP process) until the insulation feature 214 exposed. During a first structured hard mask the source area 200S covered, becomes the base section 209B in the drain area 200D selectively removed to the first drain feature 228D to expose. A first nitride liner 276 and a dielectric filler 282 can over the first drain feature 228D deposited in order to isolate this. In some cases the first nitride liner may be used 276 Contain silicon nitride, silicon oxynitride or silicon carbonitride and the dielectric filler 282 Contain silicon oxide. The first textured mask will be then removed and a second patterned mask is formed around the drain region 200D to cover. A rear contact opening is formed around the first source feature 228S to expose. A second nitride liner 277 is deposited over the rear contact opening and etched back to the first source feature 228S to expose. As in 17A illustrated are a back side silicide layer 272 and a rear source contact 274 formed in the rear contact opening. The back silicide layer 272 may contain titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi) or nickel silicide (NiSi). The rear source contact 274 can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride (TaN) contain.

Referring to 1 , 17A and 17B includes the procedure 100 one block 136 , in which a rear connection structure 290 is trained. In the illustrated embodiment, the rear connection structure 290 a first rear power supply rail 279 in a second passivation layer 278 on. The first rear power supply rail 279 is in direct contact with the rear source contact 274 . The result is the first rear power supply rail 279 with the first source characteristic 228S coupled and thereby through the first nitride liner 276 and the dielectric filler 282 from the first drain feature 228D isolated. As with the top power supply rail 264 becomes the first rear power supply rail here 279 referred to as such because it provides a positive supply voltage. In an exemplary process, the second passivation layer is used 278 over the exposed insulation feature 214 deposited, the second passivation layer 278 is then patterned and a conductive material is patterned over the second passivation layer 278 deposited.

It is now on 17A and 17B Referenced. After completing the operations of the procedure 100 are a first MBC transistor 10 and a second MBC transistor 20th above the first MBC transistor 10 educated. The first MBC transistor 10 has channel elements between the first source feature 228S and the first drain feature 228D are edged. A first gate structure (its view through the first source feature 228S is hidden) of the first MBC transistor 10 encloses each of its channel elements. The second MBC transistor 20th has channel elements interposed between the second source feature 244S and the second drain feature 244D are edged. A second gate structure (view it through the second source feature 244S and the second drain feature 244D is hidden) of the second MBC transistor 20th encloses each of its channel elements. The first source feature 228S is via the rear source contact 274 with the first rear power supply rail 279 coupled. The first rear power supply rail 279 is in the back connection structure 290 arranged. The second source feature 244S is via the upper source contact 250 and the first via 258 with the upper power supply rail 264 coupled. The upper power supply rail 264 is in the connection structure above 270 arranged. Both the first drain feature 228D as well as the second drain feature 244D is electrically with conductive features in the top interconnect structure 270 coupled, but from the rear connection structure 290 isolated. The first drain feature 228D is via the first drain contact 234 and the second via 260 with the first line 266 coupled. The second via 260 extends through the upper hybrid fin 242 in the Z direction. The second drain feature 244D is via the third via 262 with the second line 268 coupled.

Attention now turns to the procedure 300 . 18th Figure 11 illustrates a flow diagram of the method 300 in accordance with various aspects of the present disclosure. Throughout the present disclosure, like numerals indicate similar features in terms of composition and configuration. Provided similar details in connection with the procedure 100 may provide details of operations of the method 300 be simplified or omitted.

Referring to 18th and 19th includes the procedure 300 one block 302 in which a workpiece 200 provided. The workpiece 200 comprises a substrate 202 and a first batch 204 above the substrate 202 . As the substrate 202 and the first batch 204 described above, detailed descriptions thereof are omitted here.

Referring to 18th and 20th includes the procedure 300 one block 304 in which a first fin-shaped structure 209 from the first batch 204 is trained. Since operations in block 304 those from block 104 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th and 21 includes the procedure 300 one block 306 , in which an isolation feature 214 is trained. Since operations in block 306 those from block 106 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th and 22nd includes the procedure 300 one block 308 in which a sacrificial spacer layer 216 above the first fin-shaped structure 209 and the isolation feature 214 is deposited. Since operations in block 308 those from block 108 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th , 23 and 24 includes the procedure 100 one block 310 in which a second dielectric layer 2180 , a conductive layer 219 and a third dielectric layer 221 over the sacrificial spacer layer 216 to be deposited. The second dielectric layer 2180 can conform over the workpiece 200 including over the sacrificial spacer layer 216 to be deposited. As in 23 as shown, fills the second dielectric layer 2180 , different from the first dielectric layer 218 passing through sidewalls of the sacrificial spacer layer 216 defined trenches not completely. After conformal deposition of the second dielectric layer 2180 becomes a conductive layer 219 over the second dielectric layer 2180 deposited around the through sidewalls of the sacrificial spacer layer 216 to completely fill defined trenches. The conductive layer 219 may contain a conductive material such as titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta ) or tantalum nitride (TaN). The conductive layer 219 is then recessed until the top surface of the conductive layer 219 below that of the second dielectric layer 2180 lies. As a result, as in 24 illustrates isolated conductive features 219 on either side of the first fin-shaped structure 209 educated. The third dielectric layer 221 will then be on the conductive features 219 and the second dielectric layer 2180 deposited. As a result, there are the conductive characteristics 219 under the second dielectric layer 2180 and the third dielectric layer 221 buried or embedded in them. The second dielectric layer 2180 and the third dielectric layer 221 may include silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, or a dielectric material that allows selective etching of the sacrificial spacer layer 216 enables. The second dielectric layer 2180 and the third dielectric layer 221 can be deposited using CVD or ALD. Although this is not explicitly shown in the figures, a planarization process such as a chemical-mechanical polishing process (CMP process) can, however, be carried out on the workpiece 200 performed around the top surface of the first fin-shaped structure 209 to expose. The planarization process also lays down top surfaces of the sacrificial spacer layer 216 free.

Referring to 18th and 25th includes the procedure 300 one block 312 in which the sacrificial spacer layer 216 is selectively etched back to the stack portion 209S the first fin-shaped structure 209 to release. Since operations in block 312 those from block 112 are similar, detailed descriptions thereof are omitted for the sake of brevity. Regarding the procedure 300 are as a result of the operations from block 312 modular hybrid fins 2170 educated. The modular hybrid fins 2170 extend parallel to the first fin-shaped structure 209 . Any of the modular hybrid fins 2170 has a conductive feature embedded therein 219 on. As will be further described below, the hybrid modular fins 2170 serve as a contact module to provide guide paths if necessary. When modular hybrid fins are implemented, vias can have smaller aspect ratios because they can start and end at embedded conductive features in modular hybrid fins.

Referring to 18th and 26th includes the procedure 300 one block 314 in which a dummy gate stack 222 above the stacking section 209S and the modular hybrid fins 2170 is trained. Since operations in block 314 those from block 114 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th and 27 includes the procedure 300 one block 316 , in the source / drain portions of the first fin-shaped structure 209 deepened to source / drain wells 224 to train. Since operations in block 316 those from block 116 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th and 28 includes the procedure 300 one block 318 , in which inner spacer features 226 be formed. Since operations in block 318 those from block 118 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th , 29A and 29B includes the procedure 300 one block 320 , in which a first source characteristic 228S and a first drain feature 228D in the source / drain trenches 224 be formed. It should be noted that the source area 200S and the drain area 200D in 29A respectively. 29B are illustrated separately. The source area is similar 200S in 30A-35A shown and the drain area 200D in 30B-35B illustrated. Since operations in block 320 those from block 120 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th , 29A and 29B includes the procedure 300 one block 322 in which the dummy gate stack 222 is replaced by a first gate structure (the view of which is replaced by the first source feature 228S is hidden). Since operations in block 322 those from block 122 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th , 30A and 30B includes the procedure 300 one block 324 in which a first source contact 235 and a first drain contact 234 be formed. In an exemplary process, lithography processes are used to form contact openings that the first source feature 228S and the first drain feature 228D uncover. To reduce contact resistance, a silicide layer can be placed on the first source feature 228S and the first drain feature 228D be formed by placing a metal layer over the first source feature 228S and the first drain feature 228 is deposited and an annealing process is performed to silicidation between the metal layer and the first source feature 228S and between the metal layer and the first drain feature 228D to effect. A suitable metal layer can contain titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) or tungsten (W). The silicide layer can contain titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi) or nickel silicide (NiSi). After the formation of the silicide layer, a metal filler layer can be deposited in the contact opening. The metal filling layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride ( TaN) included. A planarization process can follow to provide a planar top surface that sets the stage for subsequent processes. It is noted that the dimension in the X direction and the position of the first source contact 235 are selected such that its sidewall is in contact with the adjacent conductive feature 219 is or is affiliated with this. In contrast, the dimension in the X direction and the position of the first drain contact 234 chosen so that its sidewall, or any part thereof, is separated from the adjacent conductive feature 219 is spaced.

Referring to 18th , 31A and 31B includes the procedure 300 one block 326 in which a second pile 240 on the workpiece 200 is bonded. Since operations in block 326 those from block 126 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 18th , 32A , 32B , 33A and 33B includes the procedure 300 one block 328 , in which operations from the blocks 304 , 308-322 on the second pile 240 be performed. Due to the similarity of the process steps, the processes are in block 328 summarized for the sake of simplicity. Referring to 32A and 32B will be in block 304 the second batch 240 structured around a second fin-shaped structure 2090 to train. As in 32A and 32B shown is the second fin-shaped structure 2090 vertical with the first fin-shaped structure 209 aligned. This is due to the vertical alignment between the second fin-shaped structure 2090 and the base section 209B proven. Because the second fin-shaped structure 2090 through the top layer 236 and the base layer 238 is isolated, can block the operations 306 be omitted. Still referring to 32A and 32B are in blocks 308 , 310 and 312 upper modular hybrid fins 2172 on either side of the second fin-shaped structure 2090 formed, wherein they are longitudinally parallel to the second fin-shaped structure 2090 extend. Any of the upper modular hybrid fins 2172 has upper conductive characteristics 239 on that in a fourth dielectric layer 241 and a fifth dielectric layer 243 are embedded. The top conductive features 239 and the conductive features 219 can have the same composition. The fourth dielectric layer 241 and the fifth dielectric layer 243 have the same composition as the second dielectric layer 2180 . As in 32A is shown a jumper via 237 designed to be a conductive feature 219 in a modular hybrid fin 2170 and a top conductive feature 239 in an upper modular hybrid fin 2172 to couple electrically. To the jumper vias 237 after cutting off the fourth dielectric layer 241 a via hole directly over the conductive feature to be connected 219 educated. The bridging vias 237 and the associated upper conductive feature 239 are formed at the same time when the upper conductive feature 239 is deposited.

Referring to 33A and 33B will be in block 314 a counterpart dummy gate stack is formed over the channel region of the second fin-shaped structure to serve as a placeholder for a functional second gate structure. At block 316 the source / drain portion of the second fin-shaped structure is recessed, similar to the source / drain trenches 224 Form source / drain wells. At block 318 become the sacrificial layers 206 selectively and partially etched in the channel region to form internal spacer recesses, and internal spacer features are formed in such internal spacer recesses. At block 320 becomes a second source feature 244S and a second drain feature 244D formed in the source / drain recesses. At block 322 For example, the dummy gate stack over the second fin-shaped structure is replaced by a second gate structure (not shown). The sacrificial layers 206 in the channel area are selectively removed to the channel layers 208 as channel elements, and the second gate structure encloses each of the channel elements. Before replacing the dummy gate stack, a second CESL 246 and a second ILD layer 248 one after the other over the upper modular hybrid fins 2172 , the second source feature 244S and the second drain feature 244D deposited.

Referring to 18th , 34A and 34B includes the procedure 300 one block 330 , in which an upper source contact 250 , a second drain contact 252 , a second via 260 and a third via 262 be formed. As in 34A is the top source contact 250 over and in contact with the second source feature 244S educated. First, a contact hole is made around the second source feature 244S Then, to expose a silicide layer on the second source feature 244S and a metal fill layer is deposited to fill the remainder of the contact opening. Similarly, a second drain contact is made 252 over and in contact with the second drain feature 244D educated. After the upper source contact has been formed 250 and the second drain contact 252 an etch stop layer (ESL) 254 and a third ILD layer 256 above the upper source contact 250 and the second drain contact 252 deposited in order to passivate them. It is noted that the dimension in the X direction and the position of the upper source contact 250 are selected such that its sidewall is in contact with the top conductive feature 239 is the one with the jumper via 237 is coupled, or merges with it. In contrast, the dimension in the X direction and the position of the second drain contact 252 chosen so that its sidewall, or any part thereof, is separated from the adjacent upper conductive feature 239 is spaced.

The formation of the second via 260 and the third via 262 can be the formation of a via opening through at least the ESL 254 and the third ILD layer 256 and depositing a metal fill layer. The metal filling layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride ( TaN) included. In some embodiments, the second via 260 and the third via 262 each have a liner between the metal filler layer and the adjacent dielectric material to improve electrical integrity. Such a lining can contain titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN) or tantalum nitride (TaN). Because the formation of the second via 260 requires the formation of a via opening that extends not only through the ESL 254 and the third ILD layer 256 , but also through the second ILD layer 248 , the second CESL 246 , the fourth dielectric layer 241 (the upper modular hybrid fin 2172 ), the base layer 238 and the top layer 236 extends, the via opening for the second via 260 not at the same time as the via opening for the third via 262 educated. In some other embodiments, the formation of the via opening for the second via 260 formed separately and etched in several etching stages. The second via 260 is of the second drain feature 244D and the adjacent top conductive feature 239 objected to and isolated from them. It is noted that in the procedure 300 no via over the top source contact 250 is trained.

Referring to 18th , 34A and 34B includes the procedure 300 one block 332 , in which an upper connection structure 270 is trained. The upper connection structure 270 has a first passivation layer 263 and conductive features in the first passivation layer 263 on. In the in 34A and 34B In the illustrated embodiments, the conductive features include a first line 266 and a second line 268 . In an exemplary process, the first passivation layer 263 above the workpiece 200 deposited, the first passivation layer 263 is then patterned and a conductive material is patterned over the first passivation layer 263 deposited. True, the upper connecting structure includes 270 in 35A and 35B only a single connection layer, the upper connection structure 270 however, may include more tie layers and may have all tie layers over the workpiece 200 include. As in 35B shown is the second via 260 in direct contact with the first line 266 and the third via 262 in direct contact with the second line 268 .

Referring to 18th , 35A and 35B includes the procedure 300 one block 334 , in which a first back through-hole 281 and a second rear via 283 be formed. Although this is in 35A and 35B not so illustrated, operations at block 334 however, can be done while the workpiece 200 to a carrier substrate bonded and turned upside down. In an exemplary process, the substrate is made 202 ground or planarized by a grinding process and / or a chemical-mechanical polishing process (CMP process) until the insulation feature 214 exposed. The base section 109B in the isolation feature 214 is removed and through a first nitride liner 276 and a dielectric filler 282 replaced, the first nitride liner 276 and the dielectric filler 282 serve as a dielectric plug for insulation. In some cases the first nitride liner may be used 276 Contain silicon nitride, silicon oxynitride or silicon carbonitride and the dielectric filler 282 Contain silicon oxide. Rear contact openings are made by the insulation feature 214 formed, creating the conductive features 219 in the modular hybrid fins 2170 be exposed. A metal fill layer is then deposited in the rear contact openings around the first rear via 281 and the second rear via 283 to train. An exemplary metal filler layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride (TaN) included. About the conductive feature 219 that with the first source contact 235 is in contact is the first back via 281 electrically to the first source contact 235 coupled. About the other conductive feature 219 , the bridging vias 237 and the upper conductive feature 239 , the one with the upper source contact 250 is in contact is the second back via 283 electrically to the top source contact 250 coupled.

Referring to 18th , 35A and 35B includes the procedure 300 one block 336 , in which a rear connection structure 290 is trained. In the illustrated embodiment, the rear connection structure 290 a second passivation layer 278 and a first rear power supply rail 279 and a second rear power supply rail 280 on. The first rear power supply rail 279 is in direct contact with the first back via 281 , and the second rear power supply rail 280 is in direct contact with the second rear via 283 . The result is the first rear power supply rail 279 with the first source characteristic 228S coupled and the second rear power supply rail 280 with the second source feature 244S coupled. As with the top power supply rail 264 become the first rear power supply rail here 279 and the second rear power supply rail 280 referred to as such because they provide a positive supply voltage. In an exemplary process, the second passivation layer is used 278 over the exposed insulation feature 214 deposited, the second passivation layer 278 is then patterned and a conductive material is patterned over the second passivation layer 278 deposited.

It is now on 35A and 35B Referenced. After completing the operations of the procedure 300 are a first MBC transistor 10 and a second MBC transistor 20th above the first MBC transistor 10 educated. The first MBC transistor 10 has channel elements between the first source feature 228S and the first drain feature 228D are edged. A first gate structure (its view through the first source feature 228S is hidden) of the first MBC transistor 10 encloses each of its channel elements. The second MBC transistor 20th has channel elements interposed between the second source feature 244S and the second drain feature 244D are edged. A second gate structure (view it through the second source feature 244S is hidden) of the second MBC transistor 20th encloses each of its channel elements. The first source feature 228S is about the first source contact 235 , a conductive characteristic 219 in a modular hybrid fin 2170 and the first back via 281 with the first rear power supply rail 279 coupled. The second source feature 244S is via the upper source contact 250 , an upper conductive feature 239 in an upper modular hybrid fin 2172 , the bridging vias 237 , a conductive characteristic 219 in a modular hybrid fin 2170 and the second rear via 283 to the second rear power supply rail 280 coupled. The first rear power supply rail 279 and the second rear power supply rail 280 are both in the back connection structure 290 arranged. Both the first drain feature 228D as well as the second drain feature 244D is electrically with conductive features in the top interconnect structure 270 coupled, but from the rear connection structure 290 isolated. The first drain feature 228D is via the first drain contact 234 and the second via 260 with the first line 266 coupled. The second via 260 extends through the fourth dielectric layer 241 an upper modular hybrid fin 2172 in the Z direction. The second drain feature 244D is via the second drain contact 252 and the third via 262 with the second line 268 coupled.

Attention now turns to the procedure 500 . 36 Figure 11 illustrates a flow diagram of the method 500 in accordance with various aspects of the present disclosure. Throughout the present disclosure, like numerals indicate similar features in terms of composition and configuration. Unless similar Details above in connection with the method 100 or the procedure 300 may provide details of operations of the method 500 be simplified or omitted.

Referring to 36 and 37 includes the procedure 500 one block 502 in which a workpiece 200 provided. Since operations in block 502 those from block 102 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 and 38 includes the procedure 500 one block 504 in which a first fin-shaped structure 209 from the first batch 204 is trained. Since operations in block 504 those from block 104 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 and 39 includes the procedure 500 one block 506 , in which buried power supply rails 211 be formed. In some embodiments, before the first liner 210 is etched back, a metal layer for the buried power supply rails 211 using organometallic CVD or PVD over the workpiece 200 deposited. The first liner and the deposited metal layer are recessed to create buried power supply rails 211 to train. The metal layer for the buried power supply rails 211 can tungsten (W), ruthenium (Ru), copper (Cu), aluminum ( A1 ), Silver (Ag), molybdenum (Mo), rhenium (Re), iridium (Ir), cobalt (Co) or nickel (Ni). In the illustrated embodiment, each of the buried power supply rails 211 a width W between about 40 nm and 80 nm and a height H between about 30 nm and about 50 nm. As in 39 shown, the stacking section 209S the first fin-shaped structure 209 after completing the block 506 be exposed. As in 39 shown include the buried power supply rails 211 a first buried power supply rail 211-1 and a second buried power supply rail 211-2 .

Referring to 36 and 40 includes the procedure 500 one block 508 , in which an isolation feature 214 is trained. In some embodiments, it is used to protect the buried power supply rails 211 a second lining before oxidation 213 over the buried power supply rails 211 deposited. The second lining 213 can with regard to the composition and design of the first lining 210 be similar to. As in 41 shown are the buried power supply rails 211 from the first liner 210 and the second liner 213 surround. The isolation feature 214 is then over the second liner 213 educated. As the training of the isolation feature 214 in connection with the proceedings 100 has been described, it is omitted here for the sake of brevity. After the isolation feature 214 is formed, the second liner will be 213 selectively recessed until the stacking section 209S the first fin-shaped structure 209 exposed.

Referring to 36 and 41 includes the procedure 500 one block 510 in which a sacrificial spacer layer 216 above the first fin-shaped structure 209 and the isolation feature 214 is deposited. Since operations in block 510 those from block 108 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 and 41 includes the procedure 500 one block 512 in which a first dielectric layer 218 over the sacrificial spacer layer 216 is deposited. Since operations in block 512 those from block 110 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 and 42 includes the procedure 500 one block 514 in which the sacrificial spacer layer 216 is selectively etched back to the stack portion 209S the first fin-shaped structure 209 to release. Since operations in block 514 those from block 112 are similar, detailed descriptions thereof are omitted for the sake of brevity. After completing the operations from block 514 are on both sides of the stacking section 209S Hybrid fins 217 educated. Each of the hybrid fins 217 exhibits the sacrificial spacer layer 216 and the first dielectric layer 218 over the sacrificial spacer layer 216 on.

Referring to 36 and 43 includes the procedure 500 one block 516 in which a dummy gate stack 222 above the stacking section 209S and the hybrid fins 217 is trained. Since operations in block 516 those from block 114 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 and 43 includes the procedure 500 one block 518 , in the source / drain portions of the first fin-shaped structure 209 deepened to source / drain wells 224 to train. Since operations in block 518 those from block 116 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 and 44 includes the procedure 500 one block 520 , by doing inner spacer features 226 be formed. Since operations in block 520 those from block 118 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 , 45A and 45B includes the procedure 500 one block 522 , in which a first source characteristic 228S and a first drain feature 228D in the source / drain trenches 224 be formed. Since operations in block 522 those from block 120 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 , 45A and 45B includes the procedure 500 one block 524 in which the dummy gate stack 222 is replaced by a first gate structure (the view of which is replaced by the first source feature 228S is hidden). Since operations in block 524 those from block 122 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 , 46A and 46B includes the procedure 500 one block 526 , in which a first drain contact 234 , a first source contact 235 and a fourth via 215 be formed. In an exemplary process, lithography processes are used to form contact openings that the first source feature 228S and the first drain feature 228D uncover. Additional lithography processes can be used to create a via opening for the fourth via 215 form, wherein the via opening is the first buried power supply rail 211-1 exposed. To reduce contact resistance, a silicide layer can be placed on the first source feature 228S and the first drain feature 228D be formed by placing a metal layer over the first source feature 228S and the first drain feature 228 is deposited and an annealing process is performed to silicidation between the metal layer and the first source feature 228S and between the metal layer and the first drain feature 228D to effect. A suitable metal layer here can contain titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) or tungsten (W). The silicide layer can contain titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi) or nickel silicide (NiSi). After the formation of the silicide layer, a metal filler layer can be deposited in the contact openings and the via openings. The metal filling layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride ( TaN) included. A planarization process can follow to remove excess material and the fourth via 215 , the first source contact 235 and the first drain contact 234 to train.

Referring to 36 , 47A and 47B includes the procedure 500 one block 528 in which a second pile 240 on the workpiece 200 is bonded. Since operations in block 528 those from block 126 are similar, detailed descriptions thereof are omitted for the sake of brevity.

Referring to 36 , 48A , 48B , 49A and 49B includes the procedure 500 one block 530 , in which operations from the blocks 504 , 510-524 on the second pile 240 be performed. Operations in block 530 are only summarized if such operations are similar to those described above. Referring to 48A and 48B will be in block 504 the second batch 240 structured around a third fin-shaped structure 2092 to train. Different from the second fin-shaped structure 2090 is the third fin-shaped structure 2092 not vertical with the first fin-shaped structure 209 aligned (their position through the base section 209B is marked). The third fin-shaped structure is measured from the respective center line 2092 intentionally by an offset D from the first fin-shaped structure 209 offset. In some cases, the offset D can be between about 5 nm and about 150 nm. In this regard, an offset of less than 5 nm falls within the range of general misalignment and may not be significant enough to be beneficial. The offset is less than 150nm, which is roughly the largest dimension of the hybrid fin 217 is equivalent to. If the offset is more than 150 nm, the benefits of reducing the parasitic capacitance may decrease over the intended one. Operations from block 506 are omitted as the buried power supply rails 211 are already trained. Because the third fin-shaped structure 2092 through the top layer 236 and the base layer 238 is isolated, can block operations 508 be omitted. Still referring to 48A and 48B are in blocks 510 , 512 and 514 upper hybrid fins 242 on either side of the third fin-shaped structure 2092 educated. At block 516 becomes a counterpart dummy gate stack over the channel region of the third fin-shaped structure 2092 designed to serve as a placeholder for a functional second gate structure. At block 518 becomes the source / drain portion of the third fin-shaped structure 2092 recessed to be similar to the source / drain trenches 224 Form source / drain wells. At block 520 become the sacrificial layers 206 selectively and partially etched in the channel region to form internal spacer recesses, and internal spacer features are formed in such internal spacer recesses. Referring to 49A and 49B will be in block 522 a second source feature 244S and a second drain feature 244D formed in the source / drain recesses. At block 524 the dummy gate stack over the second fin-shaped structure is replaced by a second gate structure. The sacrificial layers 206 in the channel area are selectively removed to the channel layers 208 as channel elements, and the second gate structure encloses each of the channel elements. Before replacing the dummy gate stack, a second CESL 246 and a second ILD layer 248 one after the other over the upper hybrid fins 242 , the second source feature 244S and the second drain feature 244D deposited as this in 49A and 49B is illustrated.

Referring to 36 , 50A and 50B includes the procedure 100 one block 532 , in which a fifth via 259 , an upper source contact 250 , a second drain contact 252 , a second via 260 and a third via 262 be formed. As in 50A is the top source contact 250 over and in contact with the second source feature 244S educated. Similar to the first drain contact 234 a contact opening is first made to the second source feature 244S to expose. Then a via opening is made for the fifth via 259 through the base layer 238 , the top layer 236 , a hybrid fin 217 , the isolation feature 214 and the second liner 213 formed around the second buried power supply rail 211-2 to expose. After the contact openings and the via opening are formed, a silicide layer is deposited on the second source feature 244S is formed and a metal fill layer is deposited to fill the remainder of the contact opening. The fifth via 259 serves to make the top source contact 250 and the second buried power supply rail 211-2 to pair. Similarly, a second drain contact is made 252 over and in contact with the second drain feature 244D educated. The top source contact 250 and the second drain contact 252 can be formed in the same process step. After the upper source contact has been formed 250 and the second drain contact 252 an etch stop layer (ESL) 254 and a third ILD layer 256 above the upper source contact 250 and the second drain contact 252 deposited in order to passivate them.

The formation of the second via 260 and the third via 262 can be the formation of through-hole openings through at least the ESL 254 and the third ILD layer 256 and depositing a metal fill layer. The metal filling layer can be titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride ( TaN) included. In some embodiments, the second via 260 and the third via 262 each have a liner between the metal filler layer and the adjacent dielectric material to improve electrical integrity. Such a lining can contain titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN) or tantalum nitride (TaN). Because the formation of the second via 260 requires the formation of a via opening that extends not only through the ESL 254 and the third ILD layer 256 , but also through the second ILD layer 248 , the second ILD 246 , the upper hybrid fin 242 , the base layer 238 and the top layer 236 extends, the via opening for the second via 260 not at the same time as the via opening for the third via 262 educated. In some other embodiments, the formation of the via opening for the second via 260 formed separately and etched in several etching stages.

Referring to 36 , 50A and 50B includes the procedure 500 one block 534 , in which an upper connection structure 270 is trained. The upper connection structure 270 has a first passivation layer 263 and conductive features in the first passivation layer 263 on. In the illustrated embodiments, the conductive features include a first line 266 and a second line 268 . In an exemplary process, the first passivation layer 263 above the workpiece 200 deposited, the first passivation layer 263 is then patterned and a conductive material is patterned over the first passivation layer 263 deposited. True, the upper connecting structure includes 270 in 50A and 50B only a single connection layer, the upper connection structure 270 however, may include more tie layers and may have all tie layers over the workpiece 200 include. As in 50B shown is the second via 260 in direct contact with the first line 266 and the third via 262 in direct contact with the second line 268 .

It is now on 50A and 50B Referenced. After completing the operations of the procedure 500 are a first MBC transistor 10 and a second MBC transistor 20th above the first MBC transistor 10 educated. The first MBC transistor 10 has channel elements between the first source feature 228S and the first drain feature 228D are edged. A first gate structure (its view through the first source feature 228S is hidden) of the first MBC transistor 10 encloses each of its channel elements. The second MBC transistor 20th has channel elements interposed between the second source feature 244S and the second drain feature 244D are edged. A second gate structure (view it through the second source feature 244S is hidden) of the second MBC transistor 20th encloses each of its channel elements. The first source feature 228S is about the first source contact 235 and the fourth via 215 with the first buried power supply rails 211-1 coupled. The second source feature 244S is via the upper source contact 250 and the fifth via 259 with the second buried power supply rails 211-2 coupled. Both the first drain feature 228D as well as the second drain feature 244D is electrically with conductive features in the top interconnect structure 270 coupled. The first drain feature 228D is via the first drain contact 234 and the second via 260 with the first line 266 coupled. The second via 260 extends through the upper hybrid fin 242 in the Z direction. The second drain feature 244D is via the third via 262 with the second line 268 coupled. Because the third fin-shaped structure 2092 in the X direction by the offset D from the first fin-shaped structure 209 shifted vertically are the distance between the fifth via 259 and the first source feature 228S and the distance between the second via 260 and the second drain feature 244D also enlarged by the offset D. These increased distances reduce parasitic capacitances and can improve the process window.

51A and 51B illustrate an alternative embodiment in which using the method 100 formed structures and using the process 500 trained structures are combined. According to the alternative embodiment is the semiconductor device 200 the in 17A and 17B semiconductor device shown 200 structurally similar, the channel elements of the second MBC transistor 20th are, however, by the offset D from the channel elements of the first MBC transistor 10 vertically offset. In this alternative embodiment, the distance is between the second via 260 and the second drain feature 244D increased by the offset D in order to reduce parasitic capacitances and to enlarge the process window.

As in 17A , 17B , 35A and 35B shown are in the proceedings 100 and 300 the channel elements of the first MBC transistor 10 vertically with the channel elements of the second MBC transistor 20th aligned. This vertical alignment enables a common gate structure to be formed with each of the channel elements in the first MBC transistor 10 and in the second MBC transistor 20th encloses. 52 illustrates a procedure 600 for forming a common gate structure when the channel elements of the first MBC transistor 10 vertically with the channel elements of the second MBC transistor 20th are aligned.

Referring to 52 and 53 includes the procedure 600 one block 602 in which a first MBC transistor 10 is added and the first MBC transistor 10 first channel elements 2080 and a gate structure 406 having each of the first channel elements 2080 encloses. In some embodiments, the first MBC transistor 10 the in 17A and 17B or 35A and 35B shown first MBC transistor 10 structurally be similar. The gate structure 406 has a first gate dielectric layer 402 and a first gate electrode layer 404 on. In some embodiments, there is an interface layer between each of the first channel elements 2080 and the first gate dielectric layer 402 arranged. The compositions and formation of the interface layer, the first gate dielectric layer 402 and the first gate electrode layer 404 are described above and are not repeated here. When the procedure 100 are applied as in 53 shown the first channel elements 2080 and at least a portion of the gate structure 406 between two hybrid fins 217 arranged, each of which is the sacrificial spacer layer 216 and a first dielectric layer 218 over the sacrificial spacer layer 216 having. When the procedure 300 is applied (not explicitly shown) are the first channel elements 2080 and at least a portion of the gate structure 406 between two modular hybrid fins 2170 each having a conductive feature embedded in a second dielectric layer and a third dielectric layer. The base section 209B is in the isolation feature 214 arranged.

Referring to 52 , 53 and 54 includes the procedure 600 one block 604 , in the second channel elements 2082 over the first channel elements 2080 be formed. In an exemplary process, a second fin-shaped structure is made 2090 from a second batch 240 educated. The second batch 240 , the sacrificial layers 206 and channel layers 208 is by direct bonding a cover layer 236 on the first MBC transistor 10 and a base layer 238 onto a bottom surface of the second stack 240 to the first MBC transistor 10 bonded. When the procedure 100 is applied is as in 53 shown the second fin-shaped structure 2090 between two upper hybrid fins 242 arranged, but spaced from these. When the procedure 300 is applied (not explicitly shown) is the second fin-shaped structure 2090 between two upper modular hybrid fins 2172 arranged, but by these spaced. After the second fin-shaped structure 2090 is formed, a dummy gate structure is formed over a channel region of the second fin-shaped structure, source / drain regions of the second fin-shaped structure are recessed to form source / drain recesses, and internal spacer features are formed, source / drain features are formed in the source / drain recesses. After the dummy gate structure has been removed, the sacrificial layers are made 206 selectively removed to as in 54 shown the channel layers 208 as second channel elements 2082 to release. The second channel elements 2082 are vertical with the first channel elements 2080 aligned.

Referring to 52 and 55 includes the procedure 600 one block 606 , in which an access opening 294 to the gate structure 406 is trained. Using an anisotropic etch, such as RIE or another suitable dry etch process, the access opening is created 294 through the base layer 238 and the top layer 236 formed, creating the gate structure 400 of the first MBC transistor 10 in the access opening 294 is exposed.

Referring to 52 and 56 includes the procedure 600 one block 608 in which the gate structure 406 is selectively removed to the first channel elements 2080 to expose. When the gate structure 406 in the access opening 294 exposed becomes the gate structure 406 in the access opening 294 selectively removed to the first channel elements 2080 to release, the first channel elements 2080 remain essentially undamaged. For some in 56 The illustrated embodiments may include a portion of the base layer 238 and the top layer 236 remain to be a dielectric channel feature 298 to train. In some other embodiments not explicitly shown, the dielectric channel feature is 298 may not exist. It is noted that in some implementations, a portion of the gate structure 406 between the top layer 236 and the hybrid fin 217 may be present. In other implementations where a gate cut dielectric feature is present, the gate structure resides 406 not between the top layer and the hybrid fin 217 .

Referring to 52 and 57 includes the procedure 600 one block 610 , in which a common gate structure 412 is formed such that it has each of the first channel elements 2080 and the second channel elements 2082 encloses. The common gate structure 412 has an interface layer, a common gate dielectric layer 408 over the interface layer and a common gate electrode layer 410 over the gate dielectric layer 408 on. The interface layer of the common gate structure 412 is around each of the first channel elements 2080 , the dielectric channel feature 298 and each of the second channel elements 2082 placed around and in contact with them. In some embodiments, the interface layer includes silicon oxide and can be formed in a pre-cleaning process. An exemplary pre-cleaning process may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The common gate dielectric layer 408 is then deposited over the interface layer using ALD, CVD, and / or other suitable methods. The common gate dielectric layer 408 can be formed from high-k dielectric materials. As used and described herein, high-k dielectric materials include dielectric materials having a high dielectric constant, for example greater than that of thermal silicon oxide (about 3.9). The common gate dielectric layer 408 may contain hafnium oxide. Alternatively, the common gate dielectric layer 408 Contain other high-k dielectrics such as titanium oxide (TiO ₂ ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta ₂ O ₅ ), hafnium silicon _{oxide (HfSiO 4} ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₂ ), lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO), yttrium oxide (Y ₂ O ₃ ), SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), Aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HffiO), (Ba, Sr) TiO ₃ (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof or another suitable material.

The common gate electrode layer 410 is then over the common gate dielectric layer using ALD, PVD, CVD, electron beam evaporation, or other suitable method 408 deposited. The common gate electrode layer 410 may comprise a single layer or, alternatively, a multilayer structure, such as various combinations of a metal layer with a selected work function to improve the performance of the device (work function metal layer), a lining layer, a wetting layer, an adhesive layer, a metal alloy or a metal silicide. For example, the common gate electrode layer 410 Titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum ( A1 ), Tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials, or a combination thereof. Know the semiconductor device 200 N-type transistors and p-type transistors, different common gate electrode layers may also be formed separately for n-type transistors and p-type transistors, which may include different metal layers (e.g. to provide different n-type work function metal layers -Type and p-type).

Embodiments of the present disclosure provide advantages. The present disclosure provides different contact structure plans that can be combined in different embodiments. The contact structure diagrams according to the present disclosure include, for example, dual interconnect structures, hybrid fins with embedded conductive features, and staggered stacking of devices. In the "double interconnection structures", a source feature of the first MBC transistor is coupled to a power supply rail in a first interconnection structure by a back source contact, and a source feature of the second MBC transistor (which is arranged above the first MBC transistor ) is coupled to a power rail in a second interconnection structure above the second MBC transistor. In the case of the “hybrid fins with embedded conductive features”, a conductive feature is embedded in each of the hybrid fins in order to provide contact modules that serve as conduction paths to connection structures. In “staggered device stacking,” the source / drain regions of the first MBC transistor and the second MBC transistor are staggered to increase the spacing between vias and drain features. These contact structure plans offer process flexibility and can improve device performance by reducing contact resistance or parasitic capacitances.

In an exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device has a first interconnection structure, a first transistor over the first interconnection structure, a second transistor over the first transistor, and a second interconnection structure over the second transistor. The first transistor has first nanostructures and a first source feature that is adjacent to the first nanostructures. The second transistor has second nanostructures and a second source feature that is adjacent to the second nanostructures. The first source feature is coupled to a first power supply rail in the first connection structure, and the second source feature is coupled to a second power supply rail in the second connection structure.

In some embodiments, the second nanostructures are vertically aligned with the first nanostructures. In some implementations, the first transistor further includes a first gate structure that encloses each of the first nanostructures and the first gate structure extends longitudinally in one direction, the second transistor further includes a second gate structure that encloses each of the second nanostructures, and the second gate structure extends longitudinally in the direction, and the second nanostructures are offset in the direction from the first nanostructures. In some embodiments, the semiconductor device may further include a gate structure that encloses each of the first nanostructures and each of the second nanostructures. In some embodiments, the first transistor further has a first drain feature and a first drain contact over and in contact with the first drain feature, and the first drain contact is through a first via to a first line in the second interconnect structure coupled. In some implementations, the second transistor further has a second drain feature and a second drain contact over and in contact with the second drain feature, and the second drain contact is through a second via to a second line in the second interconnect structure coupled. In some cases, the first source feature is coupled to the first power supply rail in the first connection structure via a rear source contact arranged directly below the first source feature.

In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device has a first interconnection structure, a first transistor over the first interconnection structure, a second transistor over the first transistor, and a second interconnection structure over the second transistor. The first transistor has first nanostructures and a first source feature that is adjacent to the first nanostructures. The second transistor has second nanostructures and a second source feature that is adjacent to the second nanostructures. The first source feature is coupled to a first power supply rail in the first connection structure, and the second source feature is coupled to a second power supply rail in the first connection structure.

In some embodiments, the first transistor further has a first drain feature and a first drain contact over and in contact with the first drain feature, and the first drain contact is through a first via coupled to a first line in the second connection structure. In some implementations, the second transistor further has a second drain feature and a second drain contact over and in contact with the second drain feature, and the second drain contact is through a second via to a second line in the second interconnect structure coupled. In some cases, the first nanostructures are arranged between a first hybrid fin and a second hybrid fin, the first hybrid fin having a first conductive feature embedded in a first dielectric feature and the second hybrid fin having a second conductive feature embedded in a second dielectric feature is embedded. In some embodiments, the first source feature is coupled to the first power supply rail in the first connection structure via the first conductive feature and the second source feature is coupled to the second power supply rail in the first connection structure via the second conductive feature. In some cases, the first transistor further has a first drain feature and a first drain contact over and in contact with the first drain feature. The first drain feature and the first drain contact are disposed between the first hybrid fin and the second hybrid fin. The first drain feature and the first drain contact are electrically isolated from the first conductive feature and the second conductive feature. In some embodiments, the second nanostructures are arranged between a third hybrid fin and a fourth hybrid fin, the third hybrid fin having a third conductive feature embedded in a first dielectric feature and the fourth hybrid fin having a fourth conductive feature embedded in a second dielectric feature is embedded. In some cases, the first transistor further includes a first drain feature and a first drain contact over and in contact with the first drain feature, the first drain contact being coupled to a first line in the second interconnect via a first via and the first via extends through the first dielectric feature and is electrically isolated from the third conductive feature.

In yet another exemplary aspect, the present disclosure is directed to a method. The method includes picking up a workpiece having a first substrate and a first stack over the first substrate, the first stack including a first plurality of channel layers alternating with a first plurality of sacrificial layers, forming a first fin-shaped structure therefrom first stack and a portion of the first substrate, the first fin-shaped structure having a first source region and a first drain region, forming a first hybrid fin and a second hybrid fin that extend parallel to the first fin-shaped structure, the first hybrid fin a first conductive feature embedded in a first dielectric feature and the second hybrid fin having a second conductive feature embedded in a second dielectric feature, forming a first source feature over the first source region and a first drain -Feature about de m first drain region, forming a first source contact in direct contact with the first source feature and the first conductive feature, forming a first drain contact in direct contact with the first drain feature, depositing a cover layer over the first source Contact and the first drain contact, bonding a second stack over the cover layer, the second stack comprising a second plurality of channel layers alternating with a second plurality of sacrificial layers, forming a second fin-shaped structure from the second stack, wherein the second fin-shaped structure has a second source region and a second drain region, forming a third hybrid fin and a fourth hybrid fin that extend parallel to the second fin-shaped structure, the third hybrid fin having a third conductive feature that leads to a third dielectric feature is embedded, and the fourth hybri dfinne has a fourth conductive feature embedded in a fourth dielectric feature, forming a second source feature over the second source region and a second drain feature over the second drain region, forming a second source contact in direct contact having the second source feature and the third conductive feature and forming a second drain contact in direct contact with the second drain feature.

In some embodiments, the method may further form a first via coupling the fourth conductive feature and the second conductive feature, forming a second via under and in contact with the first conductive feature, and forming a third via under and in contact with the second conductive feature Feature include. In some implementations, the method may further form a first connection structure over the second source contact and the second drain contact, the first connection structure including a first line and a second line, forming a fourth via that includes the first drain contact and the first line couples, and forming a fifth via coupling the second drain contact and the second line. In some implementations, the fourth via extends through the third dielectric feature and is electrically isolated from the third conductive feature. In some embodiments, the method may further include forming a second connection structure below the first substrate, wherein the second connection structure has a first power supply rail and a second power supply rail, the first power supply rail is coupled to the second via, and the second power supply rail is coupled to the third via.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand aspects of the present disclosure. Those of ordinary skill in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the presently presented embodiments. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and modifications therein without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN THE DESCRIPTION

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Patent literature cited

• US 63/028770 [0001]

Claims (20)

A semiconductor device comprising: a first connection structure; a first transistor over the first interconnect structure and comprising: first nanostructures and a first source feature adjacent to the first nanostructures; a second transistor over the first transistor and comprising: second nanostructures and a second source feature adjacent to the second nanostructures; and a second interconnection structure over the second transistor, wherein the first source feature is coupled to a first power supply rail in the first connection structure and the second source feature is coupled to a second power supply rail in the second connection structure. Semiconductor device according to Claim 1 wherein the second nanostructures are vertically aligned with the first nanostructures. Semiconductor device according to Claim 1 or 2 wherein the first transistor further comprises a first gate structure enclosing each of the first nanostructures, and the first gate structure extends longitudinally in one direction, wherein the second transistor further comprises a second gate structure that encompasses each of the second nanostructures and the second gate structure extends longitudinally in the direction wherein the second nanostructures are offset in the direction from the first nanostructures. A semiconductor device according to any preceding claim, further comprising: a gate structure enclosing each of the first nanostructures and each of the second nanostructures. Semiconductor device according to one of the preceding claims, wherein the first transistor further comprises a first drain feature and a first drain contact over and in contact with the first drain feature, wherein the first drain contact is coupled to a first line in the second connection structure via a first via. Semiconductor device according to one of the preceding claims, wherein the second transistor further comprises a second drain feature and a second drain contact over and in contact with the second drain feature, wherein the second drain contact is coupled to a second line in the second connection structure via a second via. The semiconductor device according to claim 1, wherein the first source feature is coupled to the first power supply rail in the first connection structure via a rear source contact arranged directly below the first source feature. A semiconductor device comprising: a first connection structure; a first transistor over the first interconnect structure and comprising: first nanostructures and a first source feature adjacent to the first nanostructures; a second transistor over the first transistor and comprising: second nanostructures and a second source feature adjacent to the second nanostructures; and a second interconnection structure over the second transistor, wherein the first source feature is coupled to a first power supply rail in the first connection structure and the second source feature is coupled to a second power supply rail in the first connection structure. Semiconductor device according to Claim 8 wherein the first transistor further comprises a first drain feature and a first drain contact over and in contact with the first drain feature, wherein the first drain contact is coupled to a first line in the second connection structure via a first via. Semiconductor device according to Claim 8 or 9 wherein the second transistor further comprises a second drain feature and a second drain contact over and in contact with the second drain feature, wherein the second drain contact is coupled to a second line in the second connection structure via a second via. Semiconductor device according to one of the preceding Claims 8 until 10 , wherein the first nanostructures are arranged between a first hybrid fin and a second hybrid fin, wherein the first hybrid fin comprises a first conductive feature that is embedded in a first dielectric feature, wherein the second hybrid fin comprises a second conductive feature that is embedded in a second dielectric Feature is embedded. Semiconductor device according to Claim 11 wherein the first source feature is coupled to the first power supply rail in the first interconnection structure via the first conductive feature, wherein the second source feature is coupled to the second power supply rail in the first interconnection structure via the second conductive feature. Semiconductor device according to Claim 11 or 12th wherein the first transistor further comprises a first drain feature and a first drain contact over and in contact with the first drain feature, the first drain feature and the first drain contact disposed between the first hybrid fin and the second hybrid fin wherein the first drain feature and the first drain contact are electrically isolated from the first conductive feature and the second conductive feature. Semiconductor device according to one of the preceding Claims 8 until 13th , wherein the second nanostructures are arranged between a third hybrid fin and a fourth hybrid fin, wherein the third hybrid fin comprises a third conductive feature that is embedded in a first dielectric feature, wherein the fourth hybrid fin comprises a fourth conductive feature that is embedded in a second dielectric Feature is embedded. Semiconductor device according to Claim 14 , wherein the first transistor further comprises a first drain feature and a first drain contact over and in contact with the first drain feature, wherein the first drain contact is coupled to a first line in the second connection structure via a first via, wherein the first via extends through the first dielectric feature and is electrically isolated from the third conductive feature. Method comprising: Receiving a workpiece comprising a first substrate and a first stack over the first substrate, the first stack including a first plurality of channel layers alternating with a first plurality of sacrificial layers; Forming a first fin-shaped structure from the first stack and a portion of the first substrate, the first fin-shaped structure including a first source region and a first drain region; Forming a first hybrid fin and a second hybrid fin that extend parallel to the first fin-shaped structure, wherein the first hybrid fin includes a first conductive feature embedded in a first dielectric feature and the second hybrid fin includes a second conductive feature shown in FIG a second dielectric feature is embedded; Forming a first source feature over the first source region and a first drain feature over the first drain region; Forming a first source contact in direct contact with the first source feature and the first conductive feature; Forming a first drain contact in direct contact with the first drain feature; Depositing a cap over the first source contact and the first drain contact; Bonding a second stack over the cover layer, the second stack including a second plurality of channel layers alternating with a second plurality of sacrificial layers; Forming a second fin-shaped structure from the second stack, the second fin-shaped structure including a second source region and a second drain region; Forming a third hybrid fin and a fourth hybrid fin that extend parallel to the second fin-shaped structure, wherein the third hybrid fin includes a third conductive feature embedded in a third dielectric feature, and the fourth hybrid fin includes a fourth conductive feature shown in FIG a fourth dielectric feature is embedded; Forming a second source feature over the second source region and a second drain feature over the second drain region; Forming a second source contact in direct contact with the second source feature and the third conductive feature; and Forming a second drain contact in direct contact with the second drain feature. Procedure according to Claim 16 further comprising: forming a first via coupling the fourth conductive feature and the second conductive feature; Forming a second via under and in contact with the first conductive feature; and forming a third via under and in contact with the second conductive feature. Procedure according to Claim 17 , further comprising: forming a first connection structure over the second source contact and the second drain contact, the first connection structure including a first line and a second line; Forming a fourth via coupling the first drain contact and the first line; and forming a fifth via coupling the second drain contact and the second line. Procedure according to Claim 18 wherein the fourth via extends through the third dielectric feature and is electrically isolated from the third conductive feature. Procedure according to Claim 18 or 19th , further comprising: forming a second connection structure below the first substrate, wherein the second connection structure comprises a first power supply rail and a second power supply rail, wherein the first power supply rail is coupled to the second via and the second power supply rail is coupled to the third via.

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