DE102020120097A1 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - Google Patents

Abstract

Photonic device manufacturing methods are provided. In embodiments, a filler material and / or a secondary waveguide are used to protect other internal structures such as grating couplers from stresses from subsequent processing steps. By using these structures at suitable times during the manufacturing process, damage and debris can be avoided, which could otherwise disrupt the manufacturing process of the device or its operation.

Description

PRIORITY CLAIM AND CROSS REFERENCE

This application claims priority of the preliminary filing on January 22, 2020 U.S. Patent Application 62 / 964,375 which is incorporated herein by reference.

BACKGROUND

Electrical signal transmission and signal processing are the most common techniques for signal transmission and signal processing. Optical signal transmission and signal processing have been used in more and more applications in recent years, particularly due to the use of fiber optic applications for signal transmission.

Figure list

• 1A-1B veranschaulicht das Anordnen einer ersten photonischen integrierten Schaltung gemäß einigen Ausführungsformen.
• 2 veranschaulicht das Bilden einer ersten Umverteilungsstruktur gemäß einigen Ausführungsformen.
• 3 veranschaulicht das Übertragen der Struktur auf ein zweites Trägersubstrat gemäß einigen Ausführungsformen.
• 4 veranschaulicht das Bilden einer zweiten Umverteilungsstruktur gemäß einigen Ausführungsformen.
• 5 veranschaulicht das Bilden von externen Kontakten gemäß einigen Ausführungsformen.
• 6 veranschaulicht das Bonden einer elektronischen integrierten Schaltung gemäß einigen Ausführungsformen.
• 7 veranschaulicht das Anordnen einer ersten Unterfüllung gemäß einigen Ausführungsformen.
• 8 veranschaulicht einen Vereinzelungsprozess gemäß einigen Ausführungsformen.
• 9 veranschaulicht das Anordnen einer optischen Faser gemäß einigen Ausführungsformen.
• 10A-10B veranschaulicht das Verkapseln der ersten photonischen integrierten Schaltung mit Halbleiter-Dies gemäß einigen Ausführungsformen.
• 11A-11B veranschaulicht das Bilden einer zweiten optischen Faser gemäß einigen Ausführungsformen.
• 12 veranschaulicht das Anbringen der Struktur an einem zweiten Trägersubstrat gemäß einigen Ausführungsformen.
• 13 veranschaulicht das Bilden einer zweiten Umverteilungsstruktur gemäß einigen Ausführungsformen.
• 14 veranschaulicht das Bilden von externen Kontakten gemäß einigen Ausführungsformen.
• 15 veranschaulicht das Binden der elektronischen integrierten Schaltung gemäß einigen Ausführungsformen.
• 16 veranschaulicht das Anordnen der optischen Faser gemäß einigen Ausführungsformen.
• 17 veranschaulicht das Verkapseln der ersten photonischen integrierten Schaltung mit der elektronischen integrierten Schaltung gemäß einigen Ausführungsformen.
• 18 veranschaulicht eine erste Hartmaske gemäß einigen Ausführungsformen.
• 19 veranschaulicht das Bilden einer Öffnung gemäß einigen Ausführungsformen.
• 20 veranschaulicht einen Verdünnungsprozess gemäß einigen Ausführungsformen.
• 21 veranschaulicht das Bilden einer zweiten Wellenleiter und einer ersten Umverteilungsstruktur gemäß einigen Ausführungsformen.
• 22 veranschaulicht eine vollständig ausgebildete Vorrichtung gemäß einigen Ausführungsformen.

Aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Indeed, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

• 1A-1B FIG. 11 illustrates arranging a first photonic integrated circuit in accordance with some embodiments.
• 2 illustrates forming a first redistribution structure in accordance with some embodiments.
• 3 illustrates the transfer of the structure to a second carrier substrate in accordance with some embodiments.
• 4th illustrates forming a second redistribution structure in accordance with some embodiments.
• 5 illustrates the formation of external contacts in accordance with some embodiments.
• 6th illustrates bonding of an electronic integrated circuit in accordance with some embodiments.
• 7th Figure 3 illustrates placing a first underfill in accordance with some embodiments.
• 8th illustrates a singulation process in accordance with some embodiments.
• 9 Figure 3 illustrates the placement of an optical fiber in accordance with some embodiments.
• 10A-10B FIG. 10 illustrates encapsulating the first photonic integrated circuit with semiconductor dies in accordance with some embodiments.
• 11A-11B illustrates forming a second optical fiber in accordance with some embodiments.
• 12th illustrates the attachment of the structure to a second carrier substrate in accordance with some embodiments.
• 13th illustrates forming a second redistribution structure in accordance with some embodiments.
• 14th illustrates the formation of external contacts in accordance with some embodiments.
• 15th illustrates bonding of the electronic integrated circuit in accordance with some embodiments.
• 16 Figure 3 illustrates the placement of the optical fiber in accordance with some embodiments.
• 17th illustrates encapsulation of the first photonic integrated circuit with the electronic integrated circuit in accordance with some embodiments.
• 18th illustrates a first hard mask in accordance with some embodiments.
• 19th illustrates forming an opening in accordance with some embodiments.
• 20th illustrates a dilution process in accordance with some embodiments.
• 21 illustrates forming a second waveguide and a first redistribution structure in accordance with some embodiments.
• 22nd Figure 3 illustrates a fully formed device in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure offers many different embodiments or examples of implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are of course only examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features are between the first and the second feature so that the first and second features may not be in direct contact. Furthermore, reference characters may be repeated in the various examples of the present disclosure. This repetition is for the purpose of simplicity and clarity and does not per se dictate a relationship between the various embodiments and / or configurations discussed herein.

Furthermore, for the sake of simplicity, spatially relative terms such as “below”, “below”, “downwards”, “above”, “above”, “upwards” and the like can be used here to describe the relationship of one element or feature to one or more others Describe any item or feature (s) as shown in the drawings. The spatially relative terms are intended to include various orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly.

Embodiments will now be described in terms of specific methods and processes used to protect sensitive components of photonic integrated circuits such as grating couplers and waveguides. However, the embodiments discussed herein are intended to be representative and are not intended to limit the embodiments in any way.

With reference now to 1A-1B , in which 1B a close up view of the dashed box 110 in 1A is presented a method of forming a pluggable, modularized device having a first carrier substrate 101 , a first layer of adhesive 103 over the first carrier substrate 101 and the formation of through insulator vias (TIVs) 107 over the first layer of adhesive 103 having. The first carrier substrate 101 contains, for example, silicon-based materials such as glass or silicon oxide or other materials such as aluminum oxide, combinations of these materials or the like. The first carrier substrate 101 is planar to support a semiconductor device such as a first photonic integrated circuit 105 (explained in more detail below).

The first layer of adhesive 103 is on the first carrier substrate 101 arranged to ensure the adhesion of overlying structures (for example the first photonic integrated circuit 105 ) to support. In one embodiment, the first adhesive layer 103 a die attach film, an ultraviolet adhesive that loses its adhesive properties when exposed to ultraviolet light. However, other types of adhesives such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations thereof, or the like can also be used. The first layer of adhesive 103 can in semi-liquid or gel-like form, which is easily deformable under pressure, on the first carrier substrate 101 be applied.

The TIVs 107 will be over the first layer of adhesive 103 and have a first seed layer (not separate from the TIVs 107 shown). The first seed layer will be over the first adhesive layer 103 and comprises a thin layer of a conductive material that aids in the formation of a thicker layer in the subsequent processing steps. The first seed layer may include a titanium layer that is about 1,000 Å thick followed by a copper layer about 5,000 Å thick. The first seed layer can be generated by processes such as sputtering, evaporation or PECVD processes, depending on the desired materials. The first seed layer can be formed in such a way that it has a thickness between approximately 0.3 μm and approximately 1 μm, for example approximately 0.5 μm.

After the first seed layer is formed, a photoresist (not shown separately) is placed over the first seed layer and patterned. In one embodiment, the photoresist can be disposed on the first seed layer, for example by a spin-on coating technique, to a height between about 50 μm and about 250 μm, for example about 120 μm. The photoresist can then be patterned after it has been arranged by exposing the photoresist to a patterned energy source (for example a patterned light source) in order to trigger a chemical reaction and thereby cause a physical change in those portions of the photoresist that are exposed to the patterned light source. A developer is then applied to the exposed photoresist in order to take advantage of the physical changes and, depending on the desired structure, selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist.

In one embodiment, the structure molded into the photoresist is a structure for the TIVs 107 . The TIVs 107 are formed in an arrangement such that the electrical paths are adjacent to the first photonic integrated circuit 105 which is subsequently arranged and can be formed with a spacing (pitch) of less than about 40 μm. Of course, any suitable arrangement for the structure of the TIVs 107 can be used, for example by an arrangement such that one or more first photonic integrated Circuits 105 on opposite sides of the TIVs 107 to be ordered.

In one embodiment, the TIVs 107 are formed within the photoresist and contain one or more conductive materials such as copper, tungsten, other conductive metals, or the like. The TIVs 107 can be formed, for example, by electroplating, electroless plating, or the like. In one embodiment, an electroplating process is used in which the first seed layer and the photoresist are partially or fully immersed in an electroplating solution. The surface of the first seed layer is electrically connected to the negative side of an external DC power supply so that the first seed layer serves as a cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution from which the cathode, e.g., the first seed layer, receives the dissolved atoms, thereby plating the exposed conductive areas of the first seed layer within the opening of the photoresist.

After the formation of the TIVs 107 using the photoresist and the first seed layer, the photoresist can be removed by a suitable removal process. In one embodiment, a plasma ashing process can be used to remove the photoresist, wherein the temperature of the photoresist can be increased until the photoresist undergoes thermal degradation and can be removed. Of course, any other suitable process, such as wet stripping, can also be used. Removal of the photoresist can expose the underlying portions of the first seed layer.

After exposure, the exposed sections of the first seed layer can be removed. In one embodiment, the exposed portions of the first seed layer (e.g., those portions that are not covered by the TIVs 107 are covered) can be removed, for example, by a wet or dry etching process. For example, in a dry etch process, the reactants can be processed using the TIVs 107 be directed as masks on the first seed layer. In another embodiment, etchants can be sprayed or otherwise contacted with the first seed layer to remove the exposed portions of the first seed layer. After the exposed portion of the first seed layer has been etched away, a portion of the first adhesive layer becomes 103 between the TIVs 107 exposed.

1A additionally shows the arrangement of the first photonic integrated circuit 105 on the first adhesive layer 103 . The first photonic integrated circuit 105 is used to send and receive optical signals. In particular, the first photonic integrated circuit converts 105 electrical signals to optical signals for transmission along an optical fiber 901 around (not in 1A-1B but below with reference to FIG 9 shown and described) and converts optical signals from the optical fiber 901 into electrical signals. Thus, the first is a photonic integrated circuit 105 responsible for input / output (I / O) of optical signals to and from the optical fiber 901 .

1B Figure 10 shows a close-up view of the dashed box 110 in 1A and shows a more detailed close-up view of the first photonic integrated circuit 105 . In one embodiment, the first photonic integrated circuit 105 using a silicon-on-insulator substrate (SOI substrate) 151 are formed. In general, an SOI substrate has a layer made of a semiconductor material 153 on, such as silicon, on top of an insulator layer 155 is formed. The insulating layer 155 can for example be a buried oxide layer (BOX) or a silicon oxide layer. The insulating layer 155 is on a substrate 158 provided, typically a silicon substrate or glass substrate. Other substrates such as a multilayer substrate or gradient substrate can also be used.

1B additionally shows the formation of a grating coupler 157 via waveguide 154 that are within the semiconductor material 153 are formed. In one embodiment, the waveguides 154 Silicon waveguides made by structuring the semiconductor material 153 are formed. The structuring of the semiconductor material 153 can be done by acceptable photolithography and etching techniques. For example, a photoresist can be applied to the front side of the semiconductor material 153 be formed and developed. The photoresist can be patterned with openings that support the waveguides 154 are equivalent to. One or more etching processes can be carried out using the structured photoresist as an etching mask. In particular, the front side of the semiconductor material can 153 be etched to form recesses that support the waveguide 154 define; the remaining non-recessed portions of the semiconductor material 153 form the waveguides 154 wherein the sidewalls of the remaining un-recessed sections are the sidewalls of the waveguide 154 define. The etching processes can be anisotropic wet or dry etching. It should be noted that the dimensions of the waveguide 154 depend on the application; in one embodiment point the waveguide 154 have a width of about 500 nm to about 3000 nm, such as about 500 nm, and have a height of about 220 nm to about 300 nm, such as about 250 nm.

The waveguide 154 also have the grating couplers 157 on that in the top sections of the waveguide 154 are formed. The grid coupler 157 enable the waveguides 154 , Light to an overlying light source or optical signal source (for example the optical fiber 901 ) to transmit or light from an overlying light source or optical signal source (for example the optical fiber 901 ) to recieve. The grid coupler 157 can be made by acceptable photolithography and etching techniques. In one embodiment, the grating couplers 157 formed after the waveguide 154 are defined. For example, a photoresist can be applied to the front side of the semiconductor material 153 formed and developed (for example on the waveguides 154 and in the recesses that define them). The photoresist can be patterned with openings that the grating couplers 157 correspond, and one or more etching processes can be carried out using the structured photoresist as an etching mask. In particular, the front side of the semiconductor material can 153 be etched to make recesses in the waveguides 154 to form that the grating coupler 157 define. The etching processes can be anisotropic wet or dry etching.

After the waveguide 154 and the grating coupler 157 have been formed, a dielectric layer 159 at the front of the semiconductor material 153 educated. The dielectric layer 159 is over the waveguides 154 and the grating coupler 157 and formed in the recesses that the waveguide 154 and the grating couplers 157 define. The dielectric layer 159 can be formed from silicon oxide, silicon nitride, a combination thereof, or the like, and can be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on-dielectric process, or a combination thereof. Once formed, the dielectric layer can 159 be planarized, for example by chemical mechanical polishing (CMP) or mechanical grinding, in order to transfer the structure of the waveguide 154 on the dielectric layer 159 to avoid. In one embodiment, the dielectric layer is 159 an oxide of the material of the semiconductor material 153 such as silicon oxide. Due to the different refractive indices of the waveguide materials 154 and the dielectric layer 159 point the waveguide 154 high internal reflections, so that the light depends on the wavelength of the light and the reflection index of the respective materials in the waveguides 154 is included. In one embodiment, the index of refraction of the material is the waveguide 154 higher than the refractive index of the material of the dielectric layer 159 .

1B additionally shows the formation of a redistribution structure 161 such as a back-end-of-line (BEOL) structure over the semiconductor material 153 and the dielectric layer 159 to make electrical connections to the structures within the first photonic integrated circuit 105 to manufacture. In one embodiment, the redistribution structure 161 formed from one or more layers of conductive materials separated from one another by one or more layers of dielectric materials. In some embodiments, the dielectric material is deposited and then patterned to form openings, and then these openings are filled and / or overfilled with a conductive material. The conductive material is then planarized to embed the conductive material in the dielectric material in either a damascene or dual damascene process. After the formation of a first level, further levels can be formed by repeating the Damascene or Double Damascene process.

After the formation of the redistribution structure 161 can contact pads 162 above the redistribution structure 161 be formed (see 1A) to establish an electrical connection between the redistribution structure 161 and produce overlying structures. In one embodiment, the contact pads 162 formed from a conductive material such as aluminum, although other suitable materials such as copper, tungsten, or the like may alternatively be used. The contact pads 162 can be formed by a process such as CVD, although other suitable materials and processes can alternatively be used. After depositing the material for the contact pads 162 can the material to the contact pads 162 be shaped, for example by a photolithographic masking and etching process.

A passivation film 163 will be on the back of the redistribution structure 161 educated. The passivation film 163 may be formed from one or more dielectric materials such as silicon oxide, silicon nitride, and the like, or combinations thereof, by a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, or the like. In a particular embodiment, the passivation film 163 be a three-layer film comprising two layers of dielectric materials sandwiched to respective ones Sides of a layer of a conductive material, for example a metal such as aluminum, abut. Of course, any suitable material and any suitable manufacturing process can be used.

After training the passivation film 163 can be a protective layer 165 over the passivation film 163 are formed. In one embodiment, the protective layer 165 a polymer based dielectric material such as polyimide, although any suitable material such as polybenzoxazole (PBO) or a polyimide derivative can be used. The protective layer 165 can be arranged, for example, by a spin-on coating process. Of course, any suitable material and any suitable process can be used for the deposition.

After the protective layer has been formed 165 can external contacts 164 be formed (see 1A) to make an external connection to the first photonic integrated circuit 105 to manufacture. In one embodiment, the external contacts 164 Conductive pillars, such as copper pillars, and can be formed by first applying the protective layer 165 and the passivation film 163 be structured around sections of the underlying contact pads 162 using, for example, a photolithographic masking process with a photoresist and an etching process. After exposing the contact pads 162 can conductive material through the photoresist and the protective layer 165 plated in the openings and the photoresist removed. The external contacts 164 can be formed with a pitch greater than about 25 µm. Of course, any suitable material, any suitable method, and any suitable pitch can be used.

After training the external contacts 164 become the protective layer 165 , the passivation film 163 , the redistribution structure 161 and a portion of the dielectric layer 159 structured around an opening 171 to form the transmission of light through these layers and to the grating coupler 157 to enable. In one embodiment, the opening 171 may be formed by a photolithographic masking and etching process with a photoresist over the protective layer 165 arranged, exposed and developed around the portion of the protective layer to be removed 165 to expose. One or more anisotropic etch processes are then used to sequentially etch through the remaining layers.

In one embodiment the opening is 171 sized to permit the passage of optical signals to and from the optical fiber 901 to enable. In one embodiment, the opening 171 at the top of the opening 171 have a first width Wi between about 30 µm and about 40 µm and at the bottom of the opening 171 a second width W2 between about 20 µm and about 30 µm. In addition, the opening 171 a first height H1 of no more than about 13.5 µm and extending into the first dielectric layer by a first depth Di of less than about 310 nm 159 extend. Of course, any suitable dimension can be used.

After the opening is formed 171 can the opening 171 with a filler material 173 be filled. In one embodiment, the filler material 173 be a material that is permeable to the passage of light, but still the underlying structures such as the grating coupler 157 and the waveguide 154 protects. In certain embodiments, the filler material 173 a material such as polyimide, epoxy, siloxane, combinations thereof, or the like. The filler material 173 can be arranged or deposited by a deposition process such as spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition or the like. The filler material 173 can be placed or deposited around the opening 171 to fill and overfill, and can be up to a second depth above the protective layer 165 from about 13 µm to about 31 µm can be deposited. Of course, any suitable material, any suitable manufacturing process, and any suitable thickness can be used.

After making the first photonic integrated circuit 105 can be the first photonic integrated circuit 105 be singled out in preparation for the arrangement. In one embodiment, the singulation can be carried out using a saw blade (not separately shown), around the isolator SOI substrate 151 and to cut through overlying structures. However, as those skilled in the art will recognize, the use of a saw blade for singulation is only an illustrative embodiment and is not intended to be limiting. Any method for performing the singulation can be used, such as the use of one or more etchings. These methods and any other suitable method can be used to singulate the structure.

After the isolation, the first photonic integrated circuit is created 105 on the first carrier substrate 101 arranged. In one embodiment, the first photonic integrated circuit 105 for example through a pick-and-place process on the first adhesive layer 103 to be ordered. Of course, any suitable method can be used for arranging the first photonic integrated circuit 105 be used.

With reference back to 1A shows 1A furthermore the encapsulation of the TIVs 107 and the first photonic integrated circuit 105 . Encapsulation can be done in a molding device (in 1A not shown individually), which may have an upper mold section and a lower mold section which is separable from the upper mold section. When the upper mold section is lowered to abut the lower mold section, a mold cavity for the first carrier substrate 101 who have favourited TIVs 107 and the first photonic integrated circuit 105 are formed.

During the encapsulation process, the upper mold section can be arranged adjacent to the lower mold section, thereby creating the first carrier substrate 101 who have favourited TIVs 107 and the first photonic integrated circuit 105 are included within the mold cavity. Once enclosed, the upper mold section and the lower mold section can form an airtight seal to control the inflow and outflow of gases into and out of the mold cavity. After sealing, an encapsulation material can be used 109 be placed within the mold cavity. The encapsulation material 109 may be a molding resin such as polyimide, PPS, PEEK, PES, a heat-resistant crystal resin, combinations thereof, or the like. The encapsulation material 109 may be placed in the mold cavity prior to aligning the upper mold section and the lower mold section or injected into the mold cavity through an injection port.

After the encapsulation material has been introduced 109 into the mold cavity so that the encapsulation material 109 the first carrier substrate 101 who have favourited TIVs 107 and the first photonic integrated circuit 105 encapsulated, the encapsulation material 109 cured to the encapsulation material 109 harden for optimal protection. During the exact curing process at least partially from the material of the encapsulation material 109 Depending on, the curing could, in one embodiment, be in the molding compound as the encapsulation material 109 is selected by a process such as heating the encapsulation material 109 to between about 100 ° C and about 130 ° C, for example about 125 ° C for about 60 s to about 3000 s, for example about 600 s. In addition, initiators and / or catalysts can be present in the encapsulation material 109 included to better control the curing process.

However, as those skilled in the art will recognize, the curing process discussed above is merely an exemplary process and is not intended to limit the present embodiments. Other curing processes such as irradiation or even curing of the encapsulation material can also be used 109 used at ambient temperature. Any suitable curing process can be used and all such methods are intended to be fully included within the scope of the embodiments discussed herein.

2 shows the dilution of the encapsulation material 109 to the TTVs 107 and the external contacts 164 the first photonic integrated circuit 105 to expose for further processing. The thinning can be carried out, for example, by a mechanical grinding or chemical mechanical polishing (CMP) process, in which chemical etching and grinding agents are used, in order to with the encapsulation material 109 and the filler material 173 to react and drag them away until the TIVs 107 and the external contacts 164 the first photonic integrated circuit 105 are exposed. Thus, the first photonic integrated circuit 105 and the TIVs 107 have a planar surface that is also coplanar with the encapsulation material 109 is.

The CMP process discussed above is presented as an exemplary embodiment and is not intended to be limiting. Any other suitable removal process can be used to remove the encapsulation material 109 and the filler material 173 to dilute and the TIVs 107 to expose. For example, a variety of chemical etches can be used. This process and any other suitable process can be used to dilute the encapsulation material 109 and the filler material 173 are used and all such methods are intended to be fully included within the scope of the embodiments.

2 additionally shows the formation of a first redistribution structure 201 with a first redistribution layer 205 that extends through a first dielectric layer 203 extends. In one embodiment, the first dielectric layer can 203 a polymer based dielectric material such as polybenzoxazole (PBO), any suitable material such as polyimide or a polyimide derivative can be used. The first dielectric layer 203 For example, it can be arranged to a thickness between about 5 µm and about 25 µm, for example about 7 µm, by a spin-coating process, any suitable process and thickness being used.

After arranging the first dielectric layer 203 can be the first dielectric layer 203 structured to be senior Expose sections of the underlying structures (e.g. the TIVs 107 and external contacts 164 ). In one embodiment, the first dielectric layer can 203 be patterned, for example, by a photolithographic masking and etching process, wherein a photoresist is arranged, exposed and developed and the photoresist is then used as a mask during an anisotropic etching process. Of course, any suitable process for structuring the first dielectric layer can be used 203 be used.

After structuring the first dielectric layer 203 can be the first redistribution layer 205 be formed to make contact with the underlying conductive areas. In one embodiment, the first redistribution layer 205 be formed by first forming a second seed layer made of a titanium-copper alloy by a suitable manufacturing process such as CVD or sputtering. After the second seed layer has been deposited, a photoresist (not separately shown) can be placed on the second seed layer to form the first redistribution structure 201 prepare. After the photoresist is formed and patterned, a conductive material such as copper can be formed on the second seed layer by a deposition process such as plating. The conductive material can be formed in such a way that it has a thickness between approximately 1 μm and approximately 10 μm, for example approximately 5 μm. Although the materials and processes mentioned herein are suitable for forming the conductive material, these materials are exemplary only. Any other suitable material such as AlCu or Au, and any other suitable manufacturing process such as CVD or PVD can be used to form the first redistribution layer 205 be used.

After the conductive material has been formed, the photoresist can be removed by a suitable removal process such as ashing, wet etching, or plasma etching. In addition, the portions of the second seed layer that were previously covered by the photoresist can be removed after the photoresist has been removed, for example by a suitable etching process in which the conductive material is used as a mask.

After the formation of the first redistribution layer 205 becomes a second dielectric layer 207 over the first redistribution layer 205 educated. In one embodiment, the second dielectric layer can 207 the first dielectric layer 203 be similar, for example in that it is a polymer based dielectric formed by spin coating. Of course, any suitable material and any suitable process can be used for the deposition.

After placing the second dielectric layer 207 can be the second dielectric layer 207 can be structured around conductive sections of the underlying structures (e.g. the first redistribution layer 205 ) to expose. In one embodiment, the second dielectric layer can 207 be patterned, for example, by a photolithographic masking and etching process, wherein a photoresist is arranged, exposed and developed and the photoresist is then used as a mask during an anisotropic etching process. Of course, any suitable process for structuring the second dielectric layer can be used 207 be used.

In a particular embodiment, the first redistribution structure 201 be formed so that the first redistribution structure 201 has a reduced spacing between conductive elements. For example, the conductive elements can be shaped so that they are spaced between approximately 4 μm and approximately 20 μm. However, any suitable pitch can be used.

In addition, after the structuring of the second dielectric layer 207 Contact pads 209 within the openings of the second dielectric layer 207 are formed. In one embodiment, the contact pads 209 Contain aluminum, but other materials such as copper can also be used. The contact pads 209 may be formed by a deposition process such as sputtering to form a layer of material (not shown) that defines the openings within the second dielectric layer 207 fills. After filling, the material can be coated with the second dielectric layer 207 be planarized, for example by a chemical-mechanical polishing process. Of course, any other suitable process can be used to create the contact pads 209 to build.

3 shows the transfer of the structure to a second carrier substrate 301 and removing the first carrier substrate 101 . In one embodiment, the second dielectric layer 207 and the contact pads 209 on the second carrier substrate 301 can be attached, for example using a second adhesive layer 304 . The second carrier substrate 301 and the second adhesive layer 304 can the first carrier substrate 101 and the first adhesive layer 103 (as above with reference to 1A illustrated), although any suitable structures and adhesives can be used.

After the structure has been transferred to the second carrier substrate 301 can be the first carrier substrate 101 removed. In a Embodiment can be the first carrier substrate 101 for example by means of a thermal process, in order to reduce the adhesive properties of the first adhesive layer 103 to change. In a particular embodiment, an energy source such as an ultraviolet laser (UV laser), a carbon dioxide laser (CO2 laser), or an infrared laser (IR laser) is used to create the first adhesive layer 103 to irradiate and heat until the first layer of adhesive 103 at least partially loses their adhesive properties. After the implementation, the first carrier substrate 101 and the first adhesive layer 103 physically separated from each other and removed from the structure.

After attachment to the second carrier substrate 301 can the first photonic integrated circuit 105 , the encapsulation material 109 and the TIVs 107 be thinned to decrease the overall height of the structure. In one embodiment, the dilution can be carried out, for example, by a chemical-mechanical polishing process. Of course, any suitable thinning process can be used, such as, for example, mechanical grinding or etching process.

4th shows that, after thinning the structure, a second redistribution structure 401 on one of the first redistribution structure 201 opposite side of the first photonic integrated circuit 105 can be formed and in electrical communication with the TIVs 107 can be formed. In one embodiment, the second redistribution structure 401 using a series of alternating redistribution layers and dielectric layers. Each of the dielectric layers can be a similar material obtained through similar processes as the first dielectric layer 203 (above with reference to 2 while each of the redistribution layers may be a similar material obtained through similar processes as the first redistribution layer 205 (also above with reference to 2 explained) is formed. Of course, any suitable material and any suitable manufacturing process can be used.

In one embodiment, the second redistribution structure 401 have three redistribution layers and four dielectric layers. However, this number is for illustrative purposes only and is not limiting. Rather, any suitable number of redistribution layers and any suitable number of dielectric layers can be used and all such layers are intended to be fully included within the scope of the embodiments.

In addition, in a specific embodiment, the second redistribution structure 401 be formed so that the second redistribution structure 401 has reduced spacing between conductive elements. For example, the conductive elements can be formed so that they have a spacing of about 4 μm to about 20 μm. Of course, any suitable pitch can be used.

5 shows the formation of underbump metallizations (UBM) 501 in connection with the second redistribution structure 401 . In one embodiment, the formation of the UBMs 501 be initiated by first one of the redistribution layers in the second redistribution structure 401 is exposed, for example by a photolithographic masking and etching process. Of course, any suitable structuring process can be used.

After exposure, the UBMs 501 are formed. In one embodiment, the UBMs 501 have three layers of conductive materials, for example a titanium layer, a copper layer and a nickel layer. However, those skilled in the art will recognize that there are many suitable arrangements of materials and layers that can be used to form the UBMs 501 are suitable, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium / tungsten / copper or an arrangement of copper / nickel / gold. Any suitable materials or layers of material used in the UBMs 501 can be used should be fully included in the scope of the embodiments.

In one embodiment, the UBMs 501 generated by placing each layer over the second redistribution structure 401 is formed. Each layer can be formed by a plating process such as electrochemical plating, although other manufacturing processes such as sputtering, evaporation, or PECVD can be used depending on the materials desired. The UBMs 501 can be formed to have a thickness between about 0.7 µm and about 10 µm, such as about 5 µm.

5 additionally shows the formation of the first external contacts 503 on the UBMs 501 . In one embodiment, the first external contacts 503 for example, contact bumps as part of a ball grid array (BGA), any suitable connection can be used. In one embodiment in which the first external contacts 503 Contact bumps are the first external contacts 503 contain a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In one embodiment in which the first external contacts 503 Tin solder bumps are the first external contacts 503 educated by first forming a tin layer by methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. to a thickness of, for example, about 250 µm. After a layer of tin has been formed on the structure, a remelting process can be performed to bump the material into the desired shape.

6th shows that, after training the first external contacts 503 , the first external contacts 503 on a ring structure 601 can be attached. The ring structure 601 can be a metal ring that is supposed to provide support and stability for the structure during and after a delivery process. In one embodiment, the first external contacts 503 attached to the ring structure, for example by means of ultraviolet adhesive tape 603 alternatively, any other suitable adhesive or attachment may be used.

After the first external contacts have been made 503 on the ring structure 601 can the second carrier substrate 301 are released from the structure, for example by a thermal process, in order to reduce the adhesive properties of the second adhesive layer 303 to change. In a particular embodiment, an energy source such as an ultraviolet laser (UV laser), a carbon dioxide laser (CO2 laser), or an infrared laser (IR laser) is used to create the second adhesive layer 303 to irradiate and heat until the second adhesive layer 303 at least partially loses their adhesive properties. After the implementation, the second carrier substrate 301 and the second adhesive layer 303 physically separated and removed from each other.

6th additionally illustrates the arrangement of second external connections 607 in connection with the first redistribution structure 201 . In one embodiment, the second external connections 607 Contact bumps such as microbumps or C4 bumps (controlled collapse chip connection bumps) and can contain a material such as tin or other suitable materials such as solder, silver or copper. In one embodiment, in which the second external connections 607 If solder bumps are made of tin, the second external connections can 607 may be formed by first forming a tin layer by any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. to a thickness of, for example, about 100 µm. After the formation of a tin layer on the structure, a remelting process is carried out to bring the material into the desired bump shape.

After the formation of the second external connections 607 may have a first electronic integrated circuit (EIC) 605 in contact with the second external terminals 607 and in electrical contact with the first photonic integrated circuit 105 to be brought. In one embodiment, the first electronic integrated circuit can 605 Have devices on a surface of an EIC substrate 609 (For example, a silicon substrate) are formed and used for the first photonic integrated circuit 105 to connect with other devices. For example, the first electronic integrated circuit 605 Control unit, CMOS driver, transimpedance amplifier and the like have to functions such as the control of the high-frequency signal transmission of the first photonic integrated circuit 105 according to electrical signals (digital or analog) received, for example, from separate logic dies.

In one embodiment, the first electronic integrated circuit can 605 also EIC contact pads 611 , an EIC passivation layer 613 , an EIC protective layer 615 and an external EIC contact 617 exhibit. In one embodiment, the EIC contact pads 611 , the EIC passivation layer 613 who have favourited EIC protective layer 615 and the external EIC contact 617 the contact pads 162 , the passivation film 163 , the protective layer 165 and the external contacts 164 be similar to those above with reference to FIG 1A are explained. Of course, any suitable structure can be used.

The first electronic integrated circuit 605 can for example by a pick-and-place process on the second external connection 607 to be ordered. Of course, any suitable method for arranging the first electronic integrated circuit can be used 605 be used. After physical contact is made, a bonding process can be performed to the first electronic integrated circuit 605 with the second external connections 607 connect to. For example, in one embodiment, the second external connections 607 Solder bumps are the bonding process that involves a reflow process in which the temperature of the second external terminals 607 is increased to a point where the second external connections 607 liquefy and flow, creating the first electronic integrated circuit 605 with the second external connections 607 is connected when the second external connections 607 freeze again.

7th shows the placement of a first underfill 701 between the first electronic integrated circuit 605 and the first Redistribution structure 201 . In one embodiment, the first is underfill 701 a protective material that is used to make the first electronic integrated circuit 605 and the first redistribution structure 201 to cushion and support against operational and environmental impairments, such as loads caused by the generation of heat during operation. The first underfill 701 can be in the space between the first electronic integrated circuit 605 and the first redistribution structure 201 injected or otherwise formed and may, for example, contain a liquid epoxy that is between the first electronic integrated circuit 605 and the first redistribution structure 201 deposited and then cured to solidify.

8th shows a singulation process that is used to singulate the structure. In one embodiment, the separation can be carried out using a saw blade (in 8th through the dashed boxes 801 shown) to be performed to the first underfill 701 and the encapsulation material 109 to cut through. As the person skilled in the art will recognize, however, the use of a saw blade is only an exemplary embodiment for the separation and is not intended to be limiting. Any method for performing the isolation can be used, such as the use of one or more etchings. These methods and any other suitable method can be used to singulate the structure.

9 shows the attachment of an optical fiber 901 that acted as an optical input / output port for the first photonic integrated circuit 105 is used. In one embodiment the optical fiber is 901 arranged so that the the optical fiber 901 and the grating coupler 157 optically couples, for example by placing the optical fiber 901 is positioned so that optical signals passing through the optical fiber 901 leave, through the filler material 173 and onto the grating coupler 157 meet. Similarly, the optical fiber 901 positioned so that optical signals passing the grating coupler 157 leave for transmission into the optical fiber 901 be directed. In a particular embodiment, the optical fiber is 901 positioned so that the optical fiber is on one of the grating couplers 157 opposite side of the filler material 173 and the first redistribution structure 201 lies. Of course, any suitable position can be used.

If desired, a trench can be made in the first redistribution structure 201 be formed to arrange the optical fiber 901 to facilitate. In one embodiment, the trench can be formed within the second redistribution structure at any point during the manufacturing process, for example by a photolithographic masking and etching process. Of course, any suitable method or combination of methods can be used.

9 also shows an optional bonding of the first external contacts 503 to another substrate 903 . In one embodiment, the substrate 903 a printed circuit board (PCB) such as a laminate substrate formed as a stack of several thin layers (or laminates) from a polymer material such as bismaleimide triazine (BT), FR-4, ABF, or the like. Of course, any suitable substrate such as a silicon interposer, a silicon substrate, an organic substrate, a ceramic substrate or the like can be used and any such redistribution substrates, the support and connectivity for the first external contacts 503 should be fully included in the scope of the embodiments.

By using the filler material 173 to fill the opening 171 becomes an additional protective layer for the optical path between the optical fiber 901 and the grating coupler 157 provided. In particular, it is due to the presence of the filler material 173 during processes such as the planarization process (above with reference to 2 described) prevents debris from the process from entering the opening 171 enter and disturb the passage of the optical signals. Furthermore, sensitive structures such as the grating coupler are used 157 by the presence of the filler material 173 further protected from such processes, thereby preventing the occurrence of undesirable defects and increasing the overall yield of the manufacturing process.

Furthermore, the described packaging of the first integrated photonic circuit 105 be modularized into an independent package that can achieve good die-to-die bandwidths by the spacing (distances) of the redistribution structures, the TIVs 107 and external contacts 164 be reduced. This means that the standalone package can be quickly installed with other packages or even packaged together with other packages, as required. Thus, the first photonic integrated circuit 105 can be used and integrated in various applications with minimal redesign.

10A-10B show a further embodiment in which the first photonic integrated circuit 105 Light from an optical fiber 901 along one side of the first photonic integrated circuit 105 lies, receives and / or to an optical fiber 901 sends (see 16 ), rather than light from a top surface optical fiber 901 to receive and / or to send to this, whereby 10B a close-up view with more details of the dashed box 1000 in 10A indicates. In this embodiment, the TIVs 107 over the first carrier substrate 101 formed, and the first photonic integrated circuit 105 is on the first carrier substrate 101 arranged as above with reference to FIG 1A described. For example, the TIVs 107 are formed by a photoresist patterning and plating process and the first photonic integrated circuit 105 is arranged through a pick-and-place process. Of course, any suitable method of manufacture or arrangement can be used.

In addition, in this embodiment, the first photonic integrated circuit 105 without the opening 171 are formed. Accordingly, the filler material 173 above the substrate 152 formed, but does not extend into the structure. Without removing the materials for the opening 171 (For example the materials of the filler material 173 , the protective layer 165 , the passivation film 163 , the redistribution structure 161 and the dielectric layer 159 ) the material remains in place to protect the underlying structures during subsequent processing such as chemical-mechanical polishing.

In addition, the waveguide is used in this version 154 modified to take optical signals from a post-formed second waveguide 1101 receive. In particular, the material of the waveguide is used in this embodiment 154 (e.g. silicon) e.g. formed by a photolithographic masking and etching process and designed as a conical waveguide in order to receive optical signals that are not perpendicular to the waveguide 154 but are received at an angle. Of course, any suitable method for forming the waveguide can be used 154 can be used to receive these signals.

10A additionally shows the arrangement of a first semiconductor die 1001 and a second semiconductor die 1003 on the first carrier substrate 101 along with the first photonic integrated circuit 105 . In one embodiment, the first semiconductor die 1001 and the second semiconductor die 1003 set up with the first electronic integrated circuit 605 and the first photonic integrated circuit 105 cooperate to perform a desired function and can be, for example, logic dies, memory dies, ASIC dies, or the like.

For example, in embodiments in which one or more of the first semiconductor dies 1001 and the second semiconductor die 1003 Logic devices are the first semiconductor die 1001 and the second semiconductor die 1003 Devices such as central processing units (CPU), graphics processing units (GPU), system-on-a-chip (SoC) devices, application processor devices (AP) devices, microcontrollers, or the like. Additionally, in embodiments in which one or more of the first semiconductor dies 1001 and the second semiconductor die 1003 Storage devices are the first semiconductor die 1001 and the second semiconductor die 1003 for example, a DRAM die (dynamic random access memory), an SRAM die (static random access memory), an HMC (hybrid memory cube), an HBM (high bandwidth memory) or the like. Of course, any suitable functionalities that are defined by suitable structures should be fully included in the scope of the embodiments.

In one embodiment, both the first semiconductor die 1001 as well as the second semiconductor die 1003 The contact pads 1002 , a die passivation layer 1004 , a die protective layer 1005 and external die contacts 1006 exhibit. In one embodiment, the die contact pads 1002 who have favourited Die Passivation Layer 1004 who have favourited Die Protective Layer 1005 and the external die contacts 1006 the contact pads 162 , the passivation film 163 , the protective layer 165 and the external contact 164 as above with reference to 1A be similar to the one described. Of course, any suitable structure can be used.

10A also shows the encapsulation of the TIVs 107 , the first photonic integrated circuit 105 , the first semiconductor die 1001 and the second semiconductor die 1003 . In one embodiment, the encapsulation may be as described above with reference to FIG 1A and 2 as described. For example, the encapsulation material 109 to the TIVs 107 , the first photonic integrated circuit 105 , the first semiconductor die 1001 and the second semiconductor die 1003 arranged and the encapsulation material 109 can be planarized to remove excess sections and the TIVs 107 , the first photonic integrated circuit 105 , the first semiconductor die 1001 and the second semiconductor die 1003 to expose. Of course, any suitable material and any suitable method can be used.

10A additionally shows that, after the encapsulation material has been placed 109 and performing the chemical mechanical polishing process, a second opening 1007 can be formed as a window extending from one side of the first photonic integrated circuit 105 from extends. However, since the planarization process for encapsulation has already taken place, can the chemical-mechanical polishing process the structures inside the second opening 1007 no more damage and debris from the planarization process cannot enter the second opening 1007 reach.

In one embodiment, the formation of the second opening 1007 be done by a photolithographic masking and etching process. For example, in one embodiment, a photoresist is placed over the structure, imaged using a structured energy source, and developed. When the photoresist is arranged as a mask, one or more etch processes are used to etch through the desired materials and the second opening 1007 to build.

With a view to 10B is the second opening 1007 in one embodiment formed so as to integrate into the first photonic integrated circuit 105 to a second depth D2 to extend between about 13.5 µm and about 17.5 µm. In addition, the second opening 1007 so formed to stand out from a sidewall of the first photonic integrated circuit 105 extend inwardly to a first distance Disi sufficient to enclose the second opening 1007 over the waveguides 154 within the first photonic integrated circuit 105 to form, wherein the first distance Disi is between about 100 microns and about 2.5 mm. Of course, any suitable dimension can be used.

In addition, during the formation of the second opening 1007 a portion of the encapsulation material 109 from the first photonic integrated circuit 105 removed and left out. In one embodiment, the encapsulation material can 109 by a third distance D ₃ between about 5 µm and about 20 µm below the surface of the second opening 1007 be left out. Of course, any suitable dimension can be used.

11A-11B show the formation of a second waveguide 1101 inside the second opening 1007 , in which 11B a close-up and detailed view of the dashed box 1100 in 11A indicates. In one embodiment, the second waveguide is 1101 used to take optical signals from the optical fiber 901 (in this embodiment in 16 shown below) to the waveguide 154 to conduct that already in the first photonic integrated circuit 105 are. By using the second waveguide 1101 , which is formed after the encapsulation process, the waveguides remain 154 protected and less prone to defects during the manufacturing process.

About the formation of the second waveguide 1101 initiate, the recess of the encapsulation material 109 with a dielectric filler material 1103 filled. In one embodiment, the dielectric filler material 1103 a material such as polybenzoxazole (PBO), although any other suitable material such as polyimide or a polyimide derivative can also be used. The first dielectric layer 203 can be placed around the second opening, for example by a spin-on coating process 1007 to fill. If arranged, the dielectric filler material 1103 be cut out, for example by a wet or dry etching process.

When the dielectric filler material 1103 is arranged, becomes the second waveguide 1101 educated. In one embodiment, the second waveguide can 1101 be any type of waveguide, such as a planar waveguide or a channel waveguide, and may contain two different materials, namely a core material and a cladding material, the core material having a higher index of refraction than the cladding material.

In one embodiment, the second waveguide can 1101 be a polymer waveguide and the core material and the cladding material contains a combination of polymer materials such as poly (methyl methacrylate) (PMMA), polystyrene (PS), polycarbonate, polyurethane, benzocyclo-butane, perfluorovinyl ether cyclopolymer, tetrafluoroethylene, perfluorovinyl ether copolymer, silicone, fluorinated poly (arylene ether sulfide, poly (pentafluorostyrene), fluorinated dendrimers, fluorinated hyperbranched polymers, or the like. In another embodiment, the core material and cladding material can include deuterated and halogenated polyacrylates, fluorinated polyimides, perfluorocyclobutyl aryl ether polymers, nonlinear optical polymers, or the like. In another embodiment For example, the core material and the cladding material may contain silicon or silicon dioxide to take advantage of the refractive index between the materials to guide the path of the optical signals through the second waveguide 1101 to limit and restrict.

The core material and the cladding material of the second waveguide 1101 For example, they can be formed by first placing each layer or layer combination within the second opening 1007 by a process such as spin coating, doctor blading, extrusion, lamination, or the like. As each layer is formed, the respective layer can be patterned and shaped to provide optical signals to and from the waveguide 154 which is further within the first photonic integrated circuit 105 is located, to control and direct. For example, during each material layer of the second waveguide 1101 is formed can be a number one or more etches, such as wet or dry etches, can be used to shape the layers of material as desired. Of course, any suitable method can be used.

11A-11B additionally show that the first redistribution structure 201 after the formation of the second waveguide 1101 over the encapsulation material 109 and the first photonic integrated circuit 105 can be formed. In one embodiment, the first redistribution structure 201 as above with reference to 2 described, for example by arranging and structuring dielectric layers and then forming conductive lines over the dielectric layers and through them. Of course, any suitable material and any suitable method can be used.

Because this embodiment has a second waveguide 1101 used to connect the optical fiber 901 from one side of the first photonic integrated circuit 105 allows the conductive layers of the first redistribution structure 201 additionally over the waveguide 154 and the second waveguide 1101 are formed. In this way, a larger area can be made available for production.

12th shows the transfer of the structure to the second carrier substrate 301 using the second adhesive layer 303 . In one embodiment, the transmission may be as described above with respect to 3 described, for example by attaching the first redistribution structure 201 on the second adhesive layer 303 , removing the first carrier substrate 101 and then diluting the encapsulation material, the TIVs 107 , the first photonic integrated circuit 105 , the first semiconductor die 1001 and the second semiconductor die 1003 . Of course, any suitable method can be used.

13th shows the formation of the second redistribution structure 401 in electrical connection with the TIVs 107 . In one embodiment, the second redistribution structure 401 as above with reference to 4th for example, by arranging and patterning dielectric layers and then forming conductive lines over and through the dielectric layers, and repeating this process as desired. Of course, any suitable material and any suitable method can be used.

14th shows the formation of the UBMs 501 and making the first external contacts 503 . In one embodiment, the UBMs 501 and the first external contacts 503 as above with reference to 5 are formed as described. For example, the UBMs 501 through one of the dielectric layers of the second redistribution structure 401 the first external contacts are formed 503 are formed and / or via the UBMs 501 arranged and a remelting process can be carried out. Of course, any suitable method and material can be used.

15th shows the arrangement of the structure on the ring structure 601 , removing the second carrier substrate 301 , arranging the second external connector 607 and arranging the first electronic integrated circuit 605 for example through a pick-and-place process.

15th additionally shows the arrangement of a third semiconductor chip 1501 . In one embodiment, the third semiconductor die 1501 the first semiconductor die 1001 and / or the second semiconductor die 1003 be similar (e.g. it can be a logic die, a memory die, or the like) and can be arranged in a similar manner (e.g. by a pick-and-place process). Of course, any suitable functionality and any suitable method can be used for the arrangement.

16 shows the bonding of the first electronic integrated circuit 605 and the third semiconductor die 1501 to the first redistribution structure 201 . In one embodiment, the bonding may be as described above with respect to FIG 7th described, for example by performing a remelting process. Of course, any suitable method can be used for the bonding.

16 additionally shows the arrangement of the first underfill 701 between the first redistribution structure 201 and the first electronic integrated circuit 605 and the third semiconductor die 1501 and separating the structure in such a way that the second waveguide 1101 planar with the encapsulation material 109 and the first redistribution structure 201 is. In one embodiment, the arrangement of the first underfill 701 and the singulation process as above with reference to FIG 7th and 8th as described. Of course, any suitable method and material can be used.

16 Finally, Figure 8 shows the placement of the optical fiber 901 in optical connection with the second waveguide 1101 . In one embodiment, the optical fiber conducts 901 optical signals in the second waveguide 1101 that receives the optical signals and into the first photonic integrated circuit 105 and towards the waveguide 154 leads. By using the second waveguide 1101 can the waveguide 154 remain protected and fewer defects can occur during the manufacturing process.

17th shows another embodiment in which the structures of the first photonic integrated circuit 105 (as above with reference to 1A-1B described) by the filler material and the formation of the second waveguide 1101 to be protected. In this embodiment, however, is the first electronic integrated circuit 605 along with the first photonic integrated circuit 105 into the encapsulation material 109 embedded. In this implementation, the TIVs 107 not over the first carrier substrate 101 formed and both the first photonic integrated circuit 105 as well as the first electronic integrated circuit 605 are formed, singulated and on the first carrier substrate 101 and the first adhesive layer 103 arranged, for example by a pick-and-place process.

Additionally shows 17th also arranging the encapsulation material 109 the first photonic integrated circuit 105 and the first electronic integrated circuit 605 . In one embodiment, the encapsulation material can 109 as above with reference to 1A are arranged as described. Of course, any suitable material and any suitable method can be used to form the first photonic integrated circuit 105 and the first electronic integrated circuit 605 to encapsulate.

18th Figure 12 shows a planarization process to remove excess encapsulation material 109 and the filler material 173 to remove and the external contacts 164 the first photonic integrated circuit 105 and the external EIC contact 617 the first electronic integrated circuit 605 to expose. In one embodiment, the planarization process can be a chemical mechanical polishing process, although any suitable planarization process such as mechanical grinding or even a series of one or more etching processes can be used.

18th also shows the deposition and structuring of a first hard mask layer 1801 over the encapsulation material 109 , the first photonic integrated circuit 105 and the first electronic integrated circuit 605 . In one embodiment, the first hard mask layer 1801 a material such as titanium, tantalum, combinations thereof, or the like, using a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, or the like. Of course, any suitable material and any suitable method of deposition can be used.

After the first hard mask layer has been deposited 1801 can be the first hard mask layer 1801 be textured around a section of filler material 173 above the grating coupler 157 expose for removal. In one embodiment, the first hard mask layer 1801 patterned around the opening by a photolithographic masking and etching process 1703 above the grating coupler 157 to build. Of course, any suitable method for structuring the first hard mask layer can be used 1801 be used.

In one embodiment, the first hard mask layer 1801 be structured to have an opening with a third width W ₃ for subsequent removal of the underlying filler material 173 and for forming the second waveguide 1101 sufficient (in 18th not shown, but with reference to FIG 21 shown and described). Therefore, in some implementations, the third width W ₃ can be between about 100 µm and about 2.5 mm, and any suitable dimension can be used.

19th shows that after patterning the first hard mask layer 1801 the exposed portion of the filler material 173 can be removed to the grating coupler 157 and the waveguide 154 to expose and a third opening 1901 to build. In one embodiment, the removal can be performed by an ashing process in the presence of oxygen. In such a process, the temperature of the filler material 173 increased until the exposed portions in contact with the oxygen environment undergo a decomposition process and are removed. Of course, any suitable method, such as an anisotropic etching method, can be used to create the exposed portions of the filler material 173 and remove the grating coupler 157 to expose. In one embodiment, the third opening 1901 with the third width W ₃ and a third depth D ₃ of approximately 13.5 μm to approximately 31 μm. Of course, any suitable dimension can be used.

20th shows an optional trimming process that can be used to trim the fill material 173 away from the grating coupler 157 to leave out. In one embodiment, the first hard mask layer 1801 for example, can be removed by a wet or dry etching process. Of course, any suitable method for removing the first hard mask layer can be used 1801 be used.

After removing the first hard mask layer 1801 For example, a separate photolithographic masking and etching process can be used to fill the material 173 to leave out. By leaving out the material, the third opening 1901 can be expanded to a fourth width W ₄ between approximately 100 μm and approximately 2.5 mm. Of course, any suitable dimension can be used.

21 illustrates that the second waveguide 1101 after the trimming process within the first photonic integrated circuit 105 can be formed. In one embodiment, the second waveguide can 1101 as above with reference to 11 are formed as described. For example, a number of polymer materials are placed in the third opening 1901 secluded and structured. After the deposition, the materials can be planarized. Of course, any suitable method for forming the second waveguide can be used 1101 be used.

21 also shows that the first redistribution structure 201 after forming the second waveguide 1101 can be formed to the first photonic integrated circuit 105 and the first electronic integrated circuit 605 to connect with each other. In one embodiment, the first redistribution structure 201 as above with reference to 2 are formed as described. For example, a series of dielectric and conductive materials are deposited and / or patterned alternately around the first redistribution structure 201 to build. Of course, any suitable method and material can be used.

21 additionally illustrates the formation of the UBMs 502 and the first external contacts 503 . In one embodiment, the UBMs 501 and the first external contacts 503 as above with reference to 5 are formed as described. For example, the UBMs 501 through one of the dielectric layers of the first redistribution structure 201 the first external contacts are formed 503 are above the UBMs 501 formed and / or arranged, and a remelting process can be performed. Of course, any suitable method and material can be used.

21 finally shows the placement of the optical fiber 901 over the second waveguide 1101 . In one embodiment, the optical fiber 901 be arranged in a trench within the first redistribution structure 201 is formed and so positioned to transmit optical signals to the second waveguide 1101 to send and receive from this. Of course, any suitable arrangement can be used.

By using the filler material 173 to protect the underlying structures during the planarization process of the encapsulation material 109 no debris from the planarization process and subsequent processing or operation of the first photonic integrated circuit can be embedded 105 to disturb. Furthermore, the material is the filler material 173 present to protect the underlying structures during the planarization process, resulting in less damage and fewer defects.

22nd illustrates another embodiment in which the in 1A-9 The illustrated modularized embodiment is instead completely integrated into a device with the first semiconductor die 1001 , the second semiconductor die 1003 , the third semiconductor die 1501 and a fourth semiconductor device 2201 (which was the first semiconductor die 1001 may be similar) is integrated. In this embodiment, the first photonic integrated device 105 as above with reference to 1A-1B described with the first semiconductor die 1001 and the second semiconductor die 1003 encapsulated and then the first photonic integrated circuit 105 as above with respect to the 1B described processed. After encapsulation, the first redistribution structure 201 and the second redistribution structure 401 formed and the first electronic integrated circuit 605 and the third semiconductor die 1501 are bonded. In addition, the fourth semiconductor device becomes 2201 similarly to the first redistribution structure 201 bonded like the third semiconductor die 1501 .

By integrating the first photonic integrated circuit 105 with the first semiconductor die 1001 , the second semiconductor die 1003 , the third semiconductor die 1501 and the fourth semiconductor device 2201 a fully integrated device can be obtained in which all the desired functionality is packaged, which is easily scalable to any desired bandwidth. In a particular embodiment, the first semiconductor die 1001 and the second semiconductor die 1003 both logic dies (e.g. LSIs), the third semiconductor die 1501 may be an ASIC device and the fourth semiconductor device 2201 may be a storage device such as high bandwidth memory. Of course, any suitable combination of devices can be used to form a fully integrated device with the first photonic integrated circuit 105 to build.

By using the embodiments described herein, a Inexpensive photonic devices made of silicon are provided which have homogeneous protective layers as the filler material 173 and / or secondary waveguide (e.g. the second waveguide 1101 ) without the use of through-silicon vias in the first photonic integrated circuit 105 used. By using these structures, other structures, such as grating couplers 157 or waveguide 154 , remain protected from damage and contamination during certain in-situ manufacturing processes such as chemical-mechanical polishing processes. By utilizing this protective effect, the entire manufacturing process, which includes the edge coupler-to-grating coupler fiber arrangement, can be simplified.

According to one embodiment, a method of manufacturing a semiconductor device comprises: removing a portion of a first photonic integrated circuit device to form an opening as an optical path to a grating coupler within the first photonic integrated circuit device; filling the opening with a filler material; and forming a first redistribution layer over the filler material. In one embodiment, the method further comprises: forming a via on a carrier substrate; arranging the first photonic integrated circuit device adjacent to the via on the carrier substrate; and encapsulating the via and the first photonic integrated circuit device with an encapsulation material, wherein forming the first redistribution layer forms the first redistribution layer over the filler material. In one embodiment, the method further comprises planarizing the fill material, the via, and the encapsulation material prior to forming the first redistribution layer. In one embodiment, the method further comprises forming a second redistribution layer on a side of the first photonic integrated circuit arrangement that is opposite to the first redistribution layer. In one embodiment, the method further comprises attaching a first electronic integrated circuit to the first redistribution layer. In one embodiment, the filler material contains polyimide.

According to an embodiment, a semiconductor device comprises: a first photonic integrated circuit comprising: a semiconductor substrate; a waveguide formed inside the semiconductor substrate; a grating coupler formed within the semiconductor substrate; a filler material overlying the grating coupler; and external contacts that are planar with the filler material; and a redistribution layer overlying the filler material and the external contacts. In one embodiment, the semiconductor device further comprises an encapsulation material surrounding the first photonic integrated circuit. In one embodiment, the semiconductor device further has vias that extend from a first side of the encapsulation material to a second side of the encapsulation material. In one embodiment, the semiconductor device further comprises an electronic integrated circuit connected to the redistribution layer. In one embodiment, the semiconductor device further comprises a first semiconductor die that lies within the encapsulation material. In one embodiment, the semiconductor device further comprises an electronic integrated circuit connected to the redistribution layer. In one embodiment, the semiconductor device further includes an optical fiber overlying the redistribution layer. In one embodiment the filler material is polyimide.

According to another embodiment, a semiconductor device comprises: a photonic integrated circuit comprising: a first waveguide over a substrate; and a second waveguide at least partially overlying the first waveguide; and a redistribution layer overlying the second waveguide, the redistribution layer having a surface coplanar with a surface of the second waveguide. In one embodiment, the semiconductor device further comprises: an encapsulation material that encapsulates the photonic integrated circuit; and vias extending through the encapsulation material. In one embodiment, the semiconductor device further comprises a first semiconductor die within the encapsulation material. In one embodiment, the semiconductor device furthermore has a second redistribution layer, which lies on a side of the first semiconductor die which is opposite to the redistribution layer. In one embodiment, the first waveguide is a silicon waveguide and the second waveguide is a polymer waveguide. In one embodiment, the semiconductor device further comprises: a dielectric material sandwiched between the second waveguide and the encapsulation material; and an optical fiber adjacent to the second waveguide.

The foregoing outlines the features of various embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure can readily be used as a basis for designing or changing other processes and structures in order to achieve the same purposes and / or achieve the same advantages of the embodiments presented here. The It should also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 62964375 [0001]

Claims (20)

A method of manufacturing a semiconductor device comprising: Removing a portion of a first photonic integrated circuit device to form an opening as an optical path to a grating coupler within the first photonic integrated circuit device; Filling the opening with a filler material; and Forming a first redistribution layer over the filler material. Procedure according to Claim 1 , further comprising: forming a via on a carrier substrate; Arranging the first photonic integrated circuit device adjacent to the via on the carrier substrate; and encapsulating the via and the first photonic integrated circuit arrangement with an encapsulation material, wherein the formation of the first redistribution layer forms the first redistribution layer over the filler material. Procedure according to Claim 2 , further comprising: prior to forming the first redistribution layer, planarizing the fill material, the via, and the encapsulation material. Procedure according to Claim 3 , further comprising: forming a second redistribution layer on a side of the first photonic integrated circuit arrangement that is opposite to the first redistribution layer. Procedure according to Claim 4 further comprising: attaching a first electronic integrated circuit to the first redistribution layer. A method according to any preceding claim, wherein the filler material contains polyimide. A semiconductor device comprising: a first photonic integrated circuit comprising: - a semiconductor substrate; a waveguide formed within the semiconductor substrate; a grating coupler formed within the semiconductor substrate; a filler material overlying the grating coupler; and external contacts that are planar with the filler material; and a redistribution layer overlying the filler material and external contacts. Semiconductor device according to Claim 7 , further comprising an encapsulation material surrounding the first photonic integrated circuit. Semiconductor device according to Claim 8 , further comprising vias extending from a first side of the encapsulation material to a second side of the encapsulation material. Semiconductor device according to Claim 9 , further comprising an electronic integrated circuit bonded to the redistribution layer. Semiconductor device according to Claim 9 or 10 , further comprising a first semiconductor die within the encapsulation material. Semiconductor device according to Claim 11 , further comprising an electronic integrated circuit bonded to the redistribution layer. Semiconductor device according to one of the Claims 7 until 12th , further comprising an optical fiber disposed over the redistribution layer. Semiconductor device according to one of the preceding Claims 7 until 13th , wherein the filler material is polyimide. A semiconductor device comprising: a photonic integrated circuit, comprising: a first waveguide over a substrate; and a second waveguide at least partially over the first waveguide; and a redistribution layer overlying the second waveguide, the redistribution layer having a surface coplanar with a surface of the second waveguide. Semiconductor device according to Claim 15 , further comprising: an encapsulation material that encapsulates the photonic integrated circuit; and vias extending through the encapsulation material. Semiconductor device according to Claim 16 , further comprising a first semiconductor die within the encapsulation material. Semiconductor device according to Claim 17 , further comprising a second redistribution layer which is arranged on a side of the first semiconductor die that is opposite to the redistribution layer. Semiconductor device according to Claim 17 or 18th , wherein the first waveguide is a silicon Is waveguide and the second waveguide is a polymer waveguide. Semiconductor device according to Claim 19 , further comprising: a dielectric material disposed between the second waveguide and the encapsulation material; and an optical fiber adjacent the second waveguide.

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