DE102013211360A1 - Semiconductor circuit breaker and method of making a semiconductor circuit breaker - Google Patents

Abstract

The invention relates to a semiconductor power switch (100) having a carrier substrate (110) and a first semiconductor layer (130) of a first semiconductor material applied to the carrier substrate (110). Furthermore, the semiconductor power switch (100) comprises a second semiconductor layer (135) made of a second semiconductor material applied to the first semiconductor layer (130), the band gap of the first semiconductor material being different from the band gap of the second semiconductor material. The semiconductor power switch (100) also has a drain terminal (145) and a source terminal (150) which are embedded in at least the second semiconductor layer (135), wherein at least one boundary layer (150) is formed by means of the drain terminal (145) and the source terminal (150). 140) between the first and second semiconductor material is electrically contacted. Further, the semiconductor power switch (100) includes a channel region (155) between the drain terminal (145) and the source terminal (150), the channel region (155) being configured to act as an electrical power switch. Finally, the semiconductor power switch (100) comprises a gate terminal (170) which at least partially covers the channel region (155).

Description

State of the art

The present invention relates to a semiconductor power switch and a method of manufacturing a semiconductor power switch.

An HEMT transistor (HEMT transistor = high-electron mobility transistor) is a special design of the field-effect transistor, which is characterized by a conductive channel with a high charge carrier mobility. However, the realization of power transistors with sufficiently high breakdown voltages is particularly difficult.

Against this background, the present invention provides a semiconductor power switch and a method of manufacturing a semiconductor power switch according to the main claims. Advantageous embodiments emerge from the respective subclaims and the following description.

• – einem Trägersubstrat;
• – einer auf dem Trägersubstrat aufgebrachte erste Halbleiterschicht aus einem ersten Halbleitermaterial;
• – eine auf der ersten Halbleiterschicht aufgebrachte zweite Halbleiterschicht aus einem zweiten Halbleitermaterial, wobei der Bandabstand des ersten Halbleitermaterials sich vom Bandabstand des zweiten Halbleitermaterials unterscheidet;
• – einen Drainanschluss und einen Sourceanschluss, die zumindest in der zweiten Halbleiterschicht eingebettet sind, wobei mittels des Drainanschlusses und des Sourceanschlusses zumindest eine Grenzschicht zwischen dem ersten und zweiten Halbleitermaterial elektrisch kontaktierbar ist;
• – einen Kanalbereich zwischen dem Drainanschluss und dem Sourceanschluss, wobei der Kanalbereich ausgebildet ist, um als elektrischer Leistungsschalter zu wirken; und
• – einen Gateanschluss, der zumindest teilweise den Kanalbereich überdeckt.

In the present case, a semiconductor power switch with the following features is presented:

• A carrier substrate;
• A first semiconductor layer of a first semiconductor material applied to the carrier substrate;
• A second semiconductor layer of a second semiconductor material deposited on the first semiconductor layer, the band gap of the first semiconductor material being different from the band gap of the second semiconductor material;
• A drain connection and a source connection, which are embedded at least in the second semiconductor layer, wherein at least one boundary layer between the first and second semiconductor material can be electrically contacted by means of the drain connection and the source connection;
• A channel region between the drain and the source, the channel region being configured to act as an electrical power switch; and
• A gate connection which at least partially covers the channel region.

A circuit breaker may be understood to mean a switching element which is designed to switch a current and / or a voltage which is greater than a predetermined minimum size. In this case, the power switch can be designed such that it can switch a current and / or a voltage which is significantly above a current and / or a voltage which is used in elements from the field of semiconductor memory technology. A carrier substrate can be understood, for example, as a semiconductor substrate or crystal, onto which further (semiconductor) structures can be applied so that the carrier substrate forms a holding element for the further structures. A band gap can be understood to mean a band gap or a "forbidden zone" representing an energetic distance between a valence band and a conduction band of a solid. A channel region may, for example, be understood as a channel of a field-effect transistor.

The approach presented here is based on the finding that a heterostructure of two semiconductor layers can be used for switching high currents and / or voltages, the semiconductor materials used in these two layers having different band gaps. As a result, a very fast-switching semiconductor structure can be realized. In particular, by the use of an interface between the first or second semiconductor layer, which has a particularly high electron mobility, thus a semiconductor power switch can be realized, which can be realized in addition to the ability to switch high power also by the relatively simple technical manufacturing method. Thus, such a semiconductor power switch is also inexpensive to produce.

• – Bereitstellen eines Trägersubstrats,
• – Aufbringen einer ersten Halbleiterschicht aus einem ersten Halbleitermaterial auf dem Trägersubstrat und Aufbringen einer zweiten Halbleiterschicht aus einem zweiten Halbleitermaterial auf der ersten Halbleiterschicht, wobei der Bandabstand des ersten Halbleitermaterials sich vom Bandabstand des zweiten Halbleitermaterials unterscheidet;
• – Ausbilden eines Drainanschlusses und einen Sourceanschlusses, die zumindest in der zweiten Halbleiterschicht eingebettet werden, wobei mittels des Drainanschlusses und des Sourceanschlusses zumindest eine Grenzschicht zwischen dem ersten und zweiten Halbleitermaterial elektrisch kontaktierbar ist und durch den Drainanschluss und den Sourceanschluss ein Kanalbereich zwischen dem Drainanschluss und dem Sourceanschluss definiert wird, wobei der Kanalbereich ausgebildet ist, um als elektrischer Leistungsschalter zu wirken; und
• – Anordnen eines Gateanschlusses, der zumindest teilweise den Kanalbereich überdeckt.

In the present case, a method for producing a semiconductor power switch is also presented, the method having the following steps:

• Providing a carrier substrate,
• Depositing a first semiconductor layer of a first semiconductor material on the carrier substrate and depositing a second semiconductor layer of a second semiconductor material on the first semiconductor layer, the band gap of the first semiconductor material being different from the band gap of the second semiconductor material;
• - Forming a drain terminal and a source terminal, which are embedded at least in the second semiconductor layer, wherein by means of the drain terminal and the source terminal, at least one boundary layer between the first and second semiconductor material is electrically contacted and through the drain terminal and the source terminal, a channel region between the drain terminal and the Source terminal is defined, wherein the channel region is formed to act as an electrical power switch; and
• Arranging a gate connection which at least partially covers the channel region.

Particularly favorable is an embodiment of the present invention, wherein the channel region is formed to nondestructively conduct an electric current of at least one ampere, in particular an electric current of at least 10 amps and / or wherein the channel region is formed to non-destructive an electrical voltage of at least 50 volts, in particular to block an electrical voltage greater than 100 volts. Such an embodiment of the present invention offers the advantage that high currents or voltages can be switched by the semiconductor power switches without the power switch itself being employed.

According to another embodiment of the present invention, the first and second semiconductor materials may form a III / V compound semiconductor composite. Such an embodiment of the present invention offers the advantage of a particularly good previously very high electron mobility at a boundary between the first and second semiconductor material. As a result, can be realized particularly fast switching circuit breaker.

Another embodiment of the present invention is advantageous in which the first semiconductor material comprises AlGaN and the second semiconductor material comprises GaN, or in that the first semiconductor material comprises GaN and the second semiconductor material comprises AlGaN. Such an embodiment of the present invention offers the advantage that semiconductor materials which are technically particularly good and easy to process can be used for a circuit breaker, so that such a circuit breaker can also be produced very inexpensively in addition to its good circuit properties.

According to a further embodiment of the present invention, the carrier substrate may comprise a holding layer of a holding material, wherein the holding material is different from a main material of the carrier substrate, in particular wherein the main material of the carrier substrate comprises silicon, wherein the first semiconductor material is arranged on the holding layer. Such an embodiment of the present invention offers the advantage that, provided that a suitable buffer layer is used, a good crystal quality of the first semiconductor layer can be achieved, and at the same time large-area and inexpensive substrates can be used.

According to a particularly favorable embodiment of the present invention, the gate connection and the channel region can be separated by gate oxide layer in an electrically insulating manner, in particular wherein at least one predetermined type of charge carriers is embedded in the gate oxide layer and / or the gate oxide layer has a predetermined density of charge carriers. Such an embodiment of the present invention offers the advantage of the possibility of setting a type of conduction of the circuit breaker, in particular the design of the circuit breaker as a self-locking or self-conducting. Also, a breakdown voltage or activation voltage may be adjusted by a thickness of the gate oxide layer and / or the density of the predetermined charge carriers in the gate oxide layer.

The invention will now be described by way of example with reference to the accompanying drawings. Show it:

1 a cross-sectional view through a semiconductor power switch according to an embodiment of the present invention;

2 a flowchart of a method according to an embodiment of the present invention; and

3 a representation of energy levels in materials along the in 1 represented cross-sectional view occur.

In the following description of favorable embodiments of the present invention, the same or similar reference numerals are used for the elements shown in the various figures and similar acting, with a repeated description of these elements is omitted.

1 shows a cross-sectional view through a semiconductor power switch 100 according to an embodiment of the present invention. The circuit breaker 100 includes a semiconductor or carrier substrate 110 which is a major ingredient 115 (For example, a silicon crystal with 111 lattice structure) and one on the main component 115 applied buffer layer 120 includes. The buffer layer 120 For example, it may consist of an AlN seed layer followed by a sequence of AlGaN layers with gradually decreasing Al concentration. In order to improve the breakdown strength, targeted doping with, for example, carbon or iron foreign atoms of at least part of this buffer structure can be used for charge carrier compensation.

The buffer layer 120 serves a very good adhesion base for one on the buffer layer 120 arranged semiconductor heterostructure 125 ,

This semiconductor heterostructure 125 For example, a stack of two layers be different semiconductor materials. For example, these different semiconductor materials may consist of or comprise semiconductor materials having a different band gap or a different band gap. The semiconductor materials of the heterostructure 125 can be considered as a first semiconductor layer 130 (of a first semiconductor material) and a second semiconductor layer disposed on the first semiconductor layer 135 (of a second semiconductor material) and form a III-V compound semiconductor or a III-V compound semiconductor system. This means that the semiconductor material of the first semiconductor layer 130 may be a III material (ie, a material of the 3rd main group of the periodic table), whereas the semiconductor material of the second semiconductor layer 135 can be a V material (ie a material from the 5th main group of the periodic table). Also, the first semiconductor material may be a V-type material and the second semiconductor material may be a III-type material. In particular, the first semiconductor material may be AlGaN and the second semiconductor material may be GaN (or comprise these materials accordingly) or vice versa.

Between the two semiconductor materials is a boundary layer 140 formed, in which electrons have a particularly high mobility. This boundary layer 140 acts as a two-dimensional electron gas (2DEG) and provides a very good circuit option for high power, ie high currents and / or voltages. To the boundary layer 140 to be able to contact electrically is a drain connection 145 and a source terminal 150 provided by the second semiconductor layer 135 through to the boundary layer 140 or into the first semiconductor layer. Laterally to the drain connection 145 or the source connection 150 , ie the side facing away from the other terminal in each case, is a lateral insulation layer 153 provided, which is a drain of electrons from a channel region 160 between which a drain connection 145 and the source terminal 150 prevented.

On a surface 160 the second semiconductor layer 135 is also a gate oxide layer 165 arranged as a gate dielectric. On the gate oxide layer 165 is in the area of the canal area 155 a gate connection 170 provided so that the semiconductor circuit breaker 100 is formed as a field effect transistor. In this respect, the channel area 155 Also be understood as a channel of a field effect transistor.

In order to now have a particularly good setting of a threshold voltage of the semiconductor circuit breaker 100 to reach, are now in the gate oxide layer 165 Specifically introduced charge carriers, so that a corresponding electric field is produced, which is equivalent to the application of an external voltage to the gate electrode. Thus, the threshold voltage of the transistor can be controlled to move, for example, to realize a positive threshold voltage, so a self-locking device. The threshold voltage of the transistor modified in this way depends on the area density and the distribution of the charge carriers.

The charge carriers can be introduced into the dielectric by various methods. For example, electrically charged foreign atoms can be introduced into the gate dielectric by means of ion implantation.

According to a further variant, this introduction of charges into the gate dielectric can be effected by depositing a layer stack which has analogous properties to memory cell technology (eg EPROM or EEPROM devices). In this it is possible to permanently store a certain amount of charge in the layer stack by applying a suitable gate voltage. Here, electrons are injected by the application of a suitable gate voltage to the control oxide in the adhesion sites of the nitride layer. It can also be used in this variant, a deletion of memory technology, z. B. local UV irradiation to simultaneously produce on a chip devices with standard threshold voltage and components with modified threshold voltage. This can be z. B. in the creation of monolithic integrated circuits advantageous. In a further variant, a targeted introduction of charge by the choice of suitable materials and the implementation of a suitable annealing process (eg a SiO ₂ / Al ₂ O ₃ -layer stack with an annealing process at a high temperature between 1000-1200 ° C, See, for example, "Gas Sensor and Method of Making Such," R341737.

In this respect, the illustrated structure of a semiconductor circuit breaker 100 denote as standard HEMT structure with gate dielectric. The structure of the HEMT transistor consists of layers of different semiconductor materials with different sized band gaps (so-called heterostructure). For this purpose, in particular compound semiconductors come into question, which consist of elements of the III / V group of the periodic table. For example, the material system GaN / AlGaN can be used. If these two materials are separated, a two-dimensional electron gas is formed at the interface of these materials on both sides of the GaN, which can serve as a conductive channel, since the electron mobility is very high therein (typically 2000 cm ² / Vs).

Such GaN HEMT transistors can be obtained by epitaxial deposition of GaN / AlGaN Heterostructures on Si, SiC or sapphire substrates produce. These components are always self-conducting due to the presence of the highly conductive channel. However, self-locking components are desired in many applications, for example in the automotive sector, for safety and circuit aspects. In order to realize self-blocking GaN devices, it is therefore necessary to use the 2DEG in the boundary layer 140 locally by means of a suitable method in the canal area. Although several such methods already appear successful, such as local thinning of the AlGaN barrier, fluorine implantation or inversion channel devices, these are generally associated with significant performance penalties and / or reliability issues. In the approach presented here, a structure is proposed which addresses this problem and makes it possible to realize high-performance self-blocking transistors based on GaN.

In particular, an approach for a manufacturing method is proposed in the present case, which allows targeted charge in a gate dielectric 165 in order to adjust the threshold voltage of the GaN-HEMT. By means of a simple method, it is thus possible to realize self-locking components which have several advantages over the conventional concepts.

The approach proposed here can thus be used to produce a component in which the charge carriers are attached to a 2-dimensional heterostructure interface 140 move, for example in the GaN / AlGaN material system. In this case, the heterostructure 125 laterally by source 150 and drain connections 145 be contacted, and the channel area 155 between source 155 and drain 145 through a gate electrode 170 controlled. The gate electrode 170 is from the channel area 155 through a gate dielectric 165 separated, in which specifically stable charges can be introduced, which set the threshold voltage of the transistor.

One approach of such a device fabrication process may include the following steps. First, a deposition of a buffer layer 120 and a GaN / AlGaN heterostructure 125 on a main ingredient 115 a carrier substrate 110 respectively. After this, a lateral component isolation can be carried out, for example by ion implantation in the lateral insulation layer 153 of the circuit breaker 100 out 1 , This is followed by deposition of a gate dielectric 165 , in which targeted charges can be introduced. Depending on their polarity, surface concentration and distribution, these charges cause a shift in the electrical properties of the HEMT transistor 100 , In particular, for example, self-locking components as a circuit breaker 100 getting produced. This can be followed by deposition and patterning of a gate electrode 170 followed by a contacting of the 2DEG (ie the boundary layer 140 ) by source 150 and drain connections 145 he follows.

2 shows a flowchart of a method 200 for manufacturing a semiconductor power switch according to an embodiment of the present invention. In this case, the method 200 one step 210 the provision of a carrier substrate. Furthermore, the method comprises 200 one step 220 depositing a first semiconductor layer of a first semiconductor material on the carrier substrate and applying a second semiconductor layer of a second semiconductor material on the first semiconductor layer, the band gap of the first semiconductor material being different from the band gap of the second semiconductor material. Furthermore, the method comprises 200 one step 230 forming a drain terminal and a source terminal, which are embedded at least in the second semiconductor layer, wherein by means of the drain terminal and the source terminal at least one boundary layer between the first and second semiconductor material is electrically contacted and through the drain terminal and the source terminal, a channel region between the drain terminal and the Source terminal is defined, wherein the channel region is formed to act as an electrical power switch. Finally, the process includes 200 one step 240 arranging a gate terminal that at least partially covers the channel area. The steps 230 and 240 can also be executed in a different order than shown here.

To a particularly good operation of the circuit breaker 100 can be achieved, the gate dielectric can be varied according to the desired conditions of use. For example, a proposed with the approach presented here variant of the gate dielectric and the method for producing the circuit breaker 100 used to stably charge in the gate dielectric 165 contribute. According to a first variant, this introduction of charges into the gate dielectric can take place by depositing a layer stack which has analogous properties to memory cell technology (eg EPROM or EEPROM components). In this it is possible to permanently store a certain amount of charge in the layer stack by applying a suitable gate voltage. This structure may for example consist of a SONOS structure, as described in the 2 is exemplified in the form of an energy level diagram.

• 2) Abscheidung einer dielektrischen Schicht, z. B. SiO2, und gezielte Einbringung von Ladung mittels Ionenimplantation. Diese Variante hat den Vorteil, dass durch die Wahl einer geeigneten Implantationsdosis die elektrischen Eigenschaften des Bauelements (in einem bestimmten Intervall) kontinuierlich eingestellt werden können. Ein ähnliches Verfahren wird z. B. in sogenannten „nanocrystal MOS memories" angewandt, siehe z. B. US 6,690,059 B1 Feb 10 2004.
• 3) Abscheidung eines Schichtstapels und gezielte Einbringung von Ladung durch ein geeignetes Temperverfahren (z. B. ein SiO2/Al2O3 Schichtstapel mit einem Temperverfahren bei einer hohen Temperatur zwischen 1000–1200°C, siehe z.

Here, electrons are injected by the application of a suitable gate voltage to the control oxide in the adhesion sites of the nitride layer. It can also be used in this variant, a deletion of memory technology, z. B. local UV irradiation to simultaneously produce on a chip devices with standard threshold voltage and components with modified threshold voltage. This can be z. B. in the creation of monolithic integrated circuits advantageous.

• 2) deposition of a dielectric layer, e.g. As SiO2, and targeted introduction of charge by ion implantation. This variant has the advantage that by selecting a suitable implantation dose, the electrical properties of the component (at a certain interval) can be adjusted continuously. A similar process is z. B. in so-called "nanocrystal MOS memories" applied, see eg. US Pat. No. 6,690,059 B1 Feb 10 2004.
• 3) deposition of a layer stack and targeted introduction of charge by a suitable annealing process (eg a SiO 2 / Al 2 O 3 layer stack with an annealing process at a high temperature between 1000-1200 ° C., see, for example, US Pat.

The invention can be used in all power electronic systems for converting electrical energy, for. B. in the automotive field in hybrid or electric vehicles, as well as in the photovoltaic field for the realization of z. B. inverter systems.

The embodiments described and shown in the figures are chosen only by way of example. Different embodiments may be combined together or in relation to individual features. Also, an embodiment can be supplemented by features of another embodiment.

Furthermore, method steps according to the invention can be repeated as well as carried out in a sequence other than that described.

If an exemplary embodiment comprises a "and / or" link between a first feature and a second feature, then this is to be read so that the embodiment according to one embodiment, both the first feature and the second feature and according to another embodiment either only first feature or only the second feature.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 6690059 B1 [0033]

Claims (7)

Semiconductor circuit breaker ( 100 ) having the following features: - a carrier substrate ( 110 ); - one on the carrier substrate ( 110 ) applied first semiconductor layer ( 130 ) of a first semiconductor material; One on the first semiconductor layer ( 130 ) applied second semiconductor layer ( 135 ) of a second semiconductor material, wherein the band gap of the first semiconductor material differs from the band gap of the second semiconductor material; A drain connection ( 145 ) and a source connection ( 150 ), which at least in the second semiconductor layer ( 135 ) are embedded, whereby by means of the drain connection ( 145 ) and the source connection ( 150 ) at least one boundary layer ( 140 ) is electrically contactable between the first and second semiconductor material; A channel area ( 155 ) between the drain ( 145 ) and the source ( 150 ), where the channel area ( 155 ) is designed to act as an electrical power switch; and - a gate connection ( 170 ), which at least partially covers the channel area ( 155 ) covered. Semiconductor circuit breaker ( 100 ) according to claim 1, characterized in that the channel region ( 155 ) is designed to nondestructively conduct an electric current of at least one ampere, in particular an electric current of at least 10 amps and / or that the channel region is formed to non-destructive an electrical voltage of at least 50 volts, in particular an electrical voltage of 100 volts to lock. Semiconductor circuit breaker ( 100 ) according to one of the preceding claims, characterized in that the first and second semiconductor material comprise a III / V compound semiconductor composite ( 125 ) form. Semiconductor circuit breaker ( 100 ) according to claim 3, characterized in that the first semiconductor material AlGaN and the second semiconductor material comprises GaN, or that the first semiconductor material comprises GaN and the second semiconductor material comprises AlGaN. Semiconductor circuit breaker ( 100 ) according to one of the preceding claims, characterized in that the carrier substrate ( 110 ) at least one holding layer ( 120 ) comprises a holding material, wherein the holding material from a main material ( 115 ) of the carrier substrate ( 110 ), in particular where the main material ( 115 ) of the carrier substrate ( 110 ) Silicon, wherein the first semiconductor material on the support layer ( 115 ) is arranged. Semiconductor circuit breaker ( 100 ) according to one of the preceding claims, characterized in that the gate connection ( 170 ) and the channel area ( 155 ) through a gate oxide layer ( 165 ) is electrically isolated, in particular wherein in the gate oxide layer ( 165 ) at least one predetermined type of charge carriers is embedded and / or wherein the gate oxide layer ( 165 ) has a predetermined density of charge carriers. Procedure ( 200 ) for producing a semiconductor circuit breaker ( 100 ), the process ( 200 ) comprises the following steps: - providing ( 210 ) of a carrier substrate ( 110 ), - application ( 220 ) a first semiconductor layer ( 130 ) of a first semiconductor material on the carrier substrate ( 110 ) and applying a second semiconductor layer ( 135 ) of a second semiconductor material on the first semiconductor layer ( 130 ), wherein the band gap of the first semiconductor material is different from the band gap of the second semiconductor material; - training ( 230 ) of a drain connection ( 145 ) and a source connection ( 150 ), which at least in the second semiconductor layer ( 135 ), whereby by means of the drain connection ( 145 ) and the source connection ( 150 ) at least one boundary layer between the first and second semiconductor material is electrically contactable and through the drain terminal ( 145 ) and the source terminal ( 150 ) a channel area ( 155 ) between the drain terminal and the source terminal, the channel area being formed to act as an electrical power switch; and - arranging ( 240 ) of a gate connection ( 170 ), such that the gate connection ( 170 ) at least partially the channel region ( 155 ) covered.

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