DE102012109548B4 - Readout gate - Google Patents

Abstract

Semiconductor component (1,1') with a photoconductive semiconductor substrate (2) and at least two modulation gates (3, 3', 4, 4', 5, 5'),wherein the modulation gates (3, 3', 4, 4', 5, 5') have a length (LMG) and are arranged parallel to one another in the longitudinal direction on the substrate (2), andwherein the modulation gates (3, 3', 4, 4', 5, 5') are designed to generate and vary a potential difference (Umod) within the substrate (2) at least between substrate sections on which the modulation gates (3, 3', 4, 4', 5, 5') are arranged,wherein the semiconductor component (1,1') is designed such that incident electromagnetic radiation is at least partially directed into a substrate section between and below the modulation gates (3, 3', 4, 4', 5, 5') and can generate charge carriers there,wherein the semiconductor component (1,1') has at least two readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'),wherein the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') have a length (LAG) which is greater than their width (BAG), and in the longitudinal direction parallel to the modulation gates (3, 3', 4, 4', 5, 5') which are arranged between the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') are arranged at a distance (ΔAG) from one another on the substrate (2), wherein the distance (ΔAG) of the readout gates from one another forms the channel length of the semiconductor component, and wherein the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') are arranged for collecting charge carriers in the substrate (2) below the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and for conducting the collected charge carriers in the longitudinal direction of the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), wherein the semiconductor component (1,1') has at least one readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') for each readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), and wherein the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is connected to the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') are arranged adjacent to one another and are designed to read out the charge carriers accumulated in the substrate (2) below the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), wherein the minimum distance (Δmin) between at least one point on the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is greater than half the channel length (ΔAG).

Description

The present invention relates to a semiconductor component with a photoconductive semiconductor substrate and at least two modulation gates, wherein the modulation gates have a length and are arranged parallel to one another in the longitudinal direction on the substrate, and wherein the modulation gates are designed to generate and vary a potential difference within the substrate at least between substrate sections on which the modulation gates are arranged, wherein the semiconductor component is designed such that incident electromagnetic radiation can at least partially reach a substrate section between and below the modulation gates and generate charge carriers there, wherein the semiconductor component has at least two readout gates, wherein the readout gates have a length that is greater than their width and are arranged on the substrate at a distance from one another in the longitudinal direction parallel to the modulation gates that are arranged between the readout gates, wherein the distance forms the channel length of the semiconductor component, and wherein the readout gates are designed to collect charge carriers in the substrate below the readout gates and to conduct the collected charge carriers in the longitudinal direction the readout gates are set up.

The present invention also relates to a detector for distance measurement and a sensor for three-dimensional image capture.

Such semiconductor components with a photoconductive semiconductor substrate and at least two modulation gates are used in particular for distance measurement by measuring the transit time of electromagnetic signals. The distance traveled by this signal and thus the distance of an object reflecting the radiation is determined from the measured transit time of an electromagnetic signal with a known propagation speed, i.e. generally the speed of light. For this purpose of distance measurement, such semiconductor components are used in particular in corresponding detectors. For three-dimensional detection of individual objects or entire environmental areas, sensors for three-dimensional image capture are used which have such detectors for distance measurement.

From the EN 10 2004 016 624 A1 A semiconductor component for distance measurement is known with a photoconductive layer, at least two modulation gates and at least two readout electrodes connected to the photoconductive layer, wherein the readout electrodes each have at least two discrete electrode sections arranged next to one another at a distance. In order to reduce crosstalk between the modulation gates and the readout electrodes, at least two gates are also provided which surround the readout electrodes.

The time of flight of an electromagnetic signal and thus a distance measurement is carried out by detecting the amplitude and phase of the electromagnetic signal. Such a general method for detecting the amplitude and phase of the electromagnetic signal is known from the state of the art, for example from DE 198 21 974 A1 , known. The environment is exposed to intensity-modulated electromagnetic radiation by means of an emitter at a known position and the radiation reflected by an object in the irradiated environment is detected by a detector. For this purpose, a photonic mixer detector is used, which, for example, is a semiconductor component according to the EN 10 2004 016 624 A1 Within the photoconductive layer, charge carriers are generated by the incident photons of the intensity-modulated reflected electromagnetic radiation. A current or voltage signal proportional to the number of charge carriers generated and thus to the number of incident photons is read out using readout electrodes. In general, the intensity-modulated reflected electromagnetic radiation is superimposed by uncorrelated ambient radiation. In order to be able to specifically evaluate the amplitude and phase of an intensity-modulated electromagnetic wave, the modulation gates are biased with a modulated voltage. This voltage applied to the modulation gates generates a corresponding potential difference within the photoconductive semiconductor substrate and drives the generated charge carriers down the potential gradient in the direction of the substrate section below the modulation gate with lower potential. These shifted charge carriers are read out via the nearest readout electrode. Further variants of such sensors are known from the US 2003 / 0 223 053 A1 as well as from the EP 1 513 202 A1 known.

It is crucial for the detection of the amplitude and phase of the intensity-modulated radiation that the modulated voltage signal applied to the modulation gates is correlated as a reference signal in a phase-locked manner with the intensity modulation that was previously imposed on the electromagnetic radiation to be detected. In general, the same frequencies are selected for the voltage modulation signal and the intensity modulation signal in order to simplify the evaluation. The modulation signal can generally have any periodic, in particular in particular, for example, have a sinusoidal or quasi-periodic structure. In order to produce a maximum potential gradient between the two modulation gates, the modulation signals applied to the modulation gates preferably have a phase shift of 180° to one another. In this way, a voltage or current signal is measured via the readout electrodes, which is a function of the product of the number of charge carriers generated and the modulation voltage. By forming the difference between the signals measured at the different readout electrodes, the uncorrelated background radiation is statistically averaged out and the resulting difference signal is essentially proportional to both the intensity of the incident intensity-modulated electromagnetic radiation and its phase shift relative to the modulation voltage. If the phase difference between the voltage modulation signal and the intensity modulation signal is known, the phase shift can be determined, which is based on the distance traveled by the reflected signal and the associated propagation time. Preferably, at least two such semiconductor components or photomixing elements are used for a fast and efficient evaluation of the amplitude and phase information of the incident electromagnetic signal, wherein the modulation voltages at the modulation gates of the second element have a phase shift of 90° to the modulation voltages of the first element.

For the most precise signal evaluation possible, a high charge carrier conversion efficiency is particularly desirable, whereby the charge carrier conversion efficiency describes the voltage share per charge carrier generated in a photosensitive material. A high charge carrier conversion efficiency therefore leads to a large voltage signal per generated charge carrier and thus to the fact that even a small number of generated charge carriers leads to a voltage signal that is large enough to be detected and further processed by the readout electronics.

The present invention is based on the object of further developing known semiconductor components of the type mentioned at the outset in such a way that they have an improved sensitivity and in particular an increased charge carrier conversion efficiency, and of making these available for the purpose of increasing sensitivity, in particular for detectors for distance measurement and sensors for three-dimensional image capture.

The present object is achieved in that the semiconductor component has at least one readout node for each readout gate, wherein the readout node is arranged adjacent to the readout gate and is configured to read out the charge carriers accumulated in the substrate below the readout gate, and wherein the minimum distance between at least one point on the readout gate and the readout node closest to this point is greater than half the channel length.

Electrodes or diodes, and in particular pn diodes, can serve as readout nodes, with the photoconductive substrate consisting of p- or n-doped silicon, for example. However, metal-semiconductor junctions with diode-like, non-ohmic characteristics are also conceivable as readout nodes. It goes without saying that, depending on the substrate doping, both electrons and holes can serve as charge carriers to be read out.

A gate in the sense of the present invention is a structure by means of which a voltage signal can be applied to a semiconductor substrate without a current flowing between the gate and the semiconductor substrate.

In the following, a strip-shaped gate means a gate structure that has a length that is greater than its width. The long side of a gate is understood to mean a side of the gate that extends essentially in the longitudinal direction of the gate, i.e. along the length of the gate. A transverse side of a gate, on the other hand, is understood to mean a side of the gate that extends essentially in the transverse direction of the gate, i.e. along the width of the gate. Depending on the pixel size, strip-shaped gates are generally preferred, i.e. both modulation gates and readout gates each have a length that is greater than their width. In the case of very small pixels, however, a design of the modulation gates in which the length of the modulation gates is not greater than their width can also be advantageous for reasons of space.

In general, electromagnetic radiation generating photocharge carriers can be incident both on the substrate top side, i.e. the substrate side on which the modulation and readout gates are arranged, and on the substrate bottom side, i.e. the side opposite the substrate top side. In the first case, it is advantageous if the modulation gates are photogates, so that the incident electromagnetic radiation passes through the modulation gates into the substrate section between and below them and generates photocharge carriers there. In the second case, i.e. in the case of backlighting, the modulation gates can also be It is more important that the substrate underside or backside is not shielded in a photo-opaque manner, at least in the section opposite the modulation gates.

A photocharge carrier in the sense of the present invention is a charge carrier that was generated in the semiconductor substrate by an interaction of the substrate with photons, and a photogate is understood to be a gate that is at least partially permeable or transparent to electromagnetic radiation.

The maximum distance between the readout gates of the semiconductor component, i.e. the maximum distance perpendicular to the longitudinal direction of the readout gates between two facing, preferably parallel side edges of the readout gates, represents the maximum distance that photocharge carriers must travel directly until they reach the substrate section below a readout gate as a result of the displacement by the modulation voltage, and is therefore also referred to as the channel length.

The use of at least one readout node per readout gate, whereby the minimum distance between at least one point on the readout gate and the readout node closest to this point, i.e. the minimum distance between the selected point and the side edge of the readout node, is greater than half the channel length, makes it possible to significantly reduce the total area of the readout nodes compared to the use of a plurality of discrete readout nodes arranged at close distances. By reducing the total area of the readout nodes per readout gate, their capacitance also decreases, which in turn is proportional to the reciprocal of the charge carrier conversion efficiency. In other words, reducing the total area of the readout nodes results in an increase in the charge carrier conversion efficiency. Furthermore, reducing the readout node area also reduces the risk of crosstalk between the readout nodes and the modulation gates in the form of dark currents. This reduces the risk of interference with the readout node and thus the detected signal due to strong modulation signals.

In general, both the readout nodes and the readout gates are arranged on the surface of the semiconductor substrate and thus cover part of the photoconductive surface. In contrast to the substrate sections covered by the modulation gates, the substrate sections below the readout nodes and readout gates, to which no modulation voltage is applied, cannot contribute to the useful signal with the photocharge carriers generated in them, i.e. to the signal from which the distance information is obtained. It is therefore advantageous to darken these with shielding elements, for example with a metal layer in the CMOS process, so that no electromagnetic radiation can penetrate through the shielded substrate surface and in order to reduce the radiation background. The smaller the semiconductor substrate area covered by the readout nodes and readout gates, the larger the area available for detecting the useful signal. In general, when the readout gates are subjected to a constant voltage, they also help to shield the readout nodes against crosstalk from the modulation gates. With small readout node areas, the readout gate area can also be reduced without adversely affecting the crosstalk protection function of the readout gates. This leads to an increase in the fill factor, i.e. the portion of the semiconductor substrate that can be used to capture the useful signal.

An arrangement of the modulation gates between the readout gates means that the modulation gates generate a potential barrier in the form of a potential gradient with a potential maximum as a result of the applied modulation voltage between the readout gates. This enables the photocharge carriers to be effectively shifted by the modulation voltages and at the same time the potential barrier prevents the generated photocharge carriers from being read out via the wrong readout gate, i.e. at a given time via the readout gate on the side of the current potential maximum. Rather, it can be ensured that the generated photocharge carriers are read out via the correct readout gate, i.e. at a given time via the readout gate on the side of the current potential minimum. In particular, this arrangement can also ensure that the semiconductor substrate areas below the readout gates are at a lower potential than the areas below the modulation gates and that, in addition, the absolute potential minimum is located below the readout nodes, which simplifies reading out. Furthermore, with this arrangement it is possible to arrange several semiconductor components according to the invention in series next to one another in the form of an array on a common semiconductor substrate, with adjacent semiconductor components each sharing at least one readout gate and the readout nodes which read out the charge carriers accumulated under this readout gate during operation of the semiconductor components. The fill factor can be further increased by such an arrangement.

According to the present invention, the fill factor and the charge carrier conversion efficiency are increased in particular by the fact that the length of the readout gates is no longer limited by the modulation frequency when the photocharge carriers are considered to be separated when they reach the substrate section below the readout gates, i.e. are effectively no longer influenced by the modulation voltage. Due to this independence, the photocharge carriers no longer have to have reached a readout node within half a period of the modulation signal in order to be read out correctly. This therefore allows the readout gates to be designed in such a way that they have points whose minimum distance from the nearest readout node is greater than half the channel length. In general, one readout node per readout gate is sufficient, in contrast to the arrangement known from the prior art with a plurality of readout nodes arranged close together. In the case of elongated readout gates, more than one readout node can be provided, although the distances between adjacent readout nodes in the case of narrow gates, ie gates whose width is significantly smaller than the channel length, are at least two half channel lengths, ie at least one channel length. It is generally preferred here and in the following to design the readout gates as narrow as possible, so that their width is significantly smaller than the channel length.

Since, as already discussed, the area for a voltage pass-through from the modulation gates to the readout nodes is relatively small, it is also conceivable that the readout gates are also subjected to a modulated voltage. In this case, the photocharge carriers generated can still be separated according to the modulation signal if the modulation frequency and the distance between the individual readout nodes are selected appropriately, which may make it possible to dispense with optical covering of the readout gates.

In one embodiment, the minimum distance between at least one point on the readout gate and the readout node closest to this point is greater than the channel length and preferably greater than twice the channel length. Such an inventive design of the readout gates and arrangement of the readout nodes leads to a distribution of the readout nodes that has an increased fill factor and an increased charge carrier conversion efficiency.

In a further embodiment, the minimum distance between at least one point on the readout gate and the readout node closest to this point is greater than 5 µm, preferably greater than 10 µm and particularly preferably greater than 20 µm. It has been shown that such an inventive design of the readout gates and arrangement of the readout nodes in conventional modulation gate arrangements has an increased fill factor and an increased charge carrier conversion efficiency.

In one embodiment of the present invention, the semiconductor component has exactly one readout node for each readout gate. If the exactly one readout node is arranged in the longitudinal direction at one end of the readout gate, whose accumulated charge carriers the readout node reads out during operation of the semiconductor component, and if the readout gate has a length that is at least equal to half, whole or double the channel length, the minimum distance between points on the end of the readout gate opposite the readout node and the readout node is at least half, whole or double the channel length. With exactly one readout node per readout gate, the total area of the readout nodes per readout gate can in particular be minimized.

In one embodiment, the width of the readout gates is less than a quarter of the channel length, preferably less than a fifth and particularly preferably less than a sixth of the channel length. As already explained above, a readout gate that is as narrow as possible and in which the width is smaller than the channel length is advantageous. It has been shown that a width of the readout gates that is less than a quarter of the channel length, preferably less than a fifth and particularly preferably less than a sixth of the channel length has advantages.

In an embodiment according to the invention, the length of the readout node is smaller than the length of the readout gate, the accumulated charge carriers of which the readout node reads out during operation of the semiconductor component. The use of a readout node with a shorter length than the length of the readout gate allows the total readout node area to be significantly reduced compared to the prior art.

In a further embodiment according to the present invention, the ratio between the length of the readout node and the length of the readout gate, the accumulated charge carriers of which are read out by the readout node during operation of the semiconductor component, is at most 1:10, preferably at most 1:50 and particularly preferably at most 1:100. For length differences in the range specified here, it has been shown that the described advantages resulting from a shorter length of the readout node compared to the length of the readout segates resulting advantages are clearly pronounced.

A further embodiment is characterized in that the area of the readout node is at least ten times smaller, preferably at least fifty times smaller and particularly preferably at least one hundred times smaller than the total area of the adjacent readout gates whose accumulated charge carriers the readout node reads out during operation of the semiconductor component. The term area refers here and below to the area in a vertical plan view of the top side of the semiconductor substrate. The size of the readout gates is set a lower limit in that the readout gate structure should have the same length as the modulation gates in order to ensure the shortest possible distance for all photocharge carriers generated below and between the modulation gates in the semiconductor substrate to an area in which they are located under a readout gate and can thus be considered separate.

Readout gate structure here and in the following means both a single strip-shaped readout gate arranged parallel to the modulation gates, and two strip-shaped readout gates arranged at a distance from one another along a common longitudinal axis parallel to the modulation gates. In the case of two readout gates arranged at a distance from one another along a common longitudinal axis, a readout node is preferably arranged between the two readout gates. Readout gate structures with the same length as the modulation gates make it possible to increase the distance between the readout gates and thus the substrate area covered by the modulation gates and which is decisive for signal detection. Likewise, the modulation frequency can be increased in addition to or instead of this, which allows for more precise distance resolution. A further increase in the fill factor can be achieved by using the smallest possible readout node area in accordance with the size ratios given above. Furthermore, such a small readout node area ensures high charge carrier conversion efficiency.

In one embodiment of the present invention, exactly three modulation gates arranged parallel to one another in the longitudinal direction are provided between the readout gates. Such a three-gate structure with a non-modulated middle gate between two modulated modulation gates increases the contrast. A temporally constant voltage is applied to the middle gate. Nevertheless, it is referred to here and below as a modulation gate, since the temporally constant potential step caused by it is part of the potential gradient varied by means of the modulation voltages. This additional gate therefore increases the number of potential steps below the modulation gates from two to three compared to an embodiment with exactly two modulation gates, which means that the potential gradient and thus also the modulation drift field are more uniform at the same potential level. This reduces the risk that charge carriers within a potential step are not effectively displaced due to a potential step width that is too large. Embodiments with more than three modulation gates arranged parallel to one another in the longitudinal direction between the readout gates are also conceivable, for example four modulation gates. With four modulation gates, the two middle gates are preferably also modulated, whereby they are varied in phase with the nearest outer modulation gate, but only with half the potential difference. This results in a four-stage potential gradient with equal distances between the individual stages.

In an embodiment according to the invention, the readout node is arranged on the longitudinal axis of the readout gate, the accumulated charge carriers of which the readout node reads out during operation of the semiconductor component. Arranged on the longitudinal axis here and in the following means that the readout node is arranged such that at least a portion of it covers the longitudinal axis of the readout gate. Such an arrangement enables photocharge carriers displaced in the longitudinal direction of the readout gate to reach the readout node directly without having to be additionally displaced further in the transverse direction of the readout gate. Reading is thus more direct than in the case of an arrangement of the readout node next to the longitudinal axis of the readout gate.

In one embodiment of the semiconductor component, the width of the readout node is smaller than the width of the readout gate, the accumulated charge carriers of which the readout node reads out. A smaller width of the readout node compared to the width of the readout gate allows the readout node to be arranged within the readout gate next to the modulation gates without the readout node being directly adjacent to a modulation gate, thereby preventing crosstalk from the modulation gates to the readout node.

In one embodiment, the readout node is arranged at least partially in a recess of the readout gate, the accumulated charge carriers of which are read out by the readout node during operation of the semiconductor component, and is laterally at least partially surrounded by the latter. Such an arrangement is particularly advantageous if the The readout node is arranged at the long end of the readout gate and should not protrude beyond it if possible. This ensures a compact arrangement of the gate and node structures and at the same time effective shielding against crosstalk of the modulation voltage to the readout node.

In one embodiment, the recess for receiving the readout node is arranged in the middle in the transverse direction of the readout gate, whose accumulated charge carriers the readout node reads out during operation of the semiconductor component. As a result, the readout node is effectively shielded against crosstalk of the modulation voltage on both modulation gate sides, which is particularly advantageous in the case of an arrangement of several semiconductor components in series next to one another on a common semiconductor substrate in the form of an array, with adjacent semiconductor components each sharing a readout gate and the readout nodes which read out the charge carriers accumulated under this readout gate during operation of the semiconductor component. Modulation gates are therefore arranged on two sides of a readout gate. In addition, the symmetry of the arrangement is increased in this case, which is generally advantageous when structuring semiconductor components according to the invention, since this prevents the readout conditions for one readout node from deviating from those of another, which could otherwise lead to direction-dependent falsifications and inaccuracies in the measurement results.

In one embodiment, the readout node is arranged completely in the recess for receiving the readout node, so that the readout node is completely enclosed laterally by the readout gate, the accumulated charge carriers of which the readout node reads out during operation of the semiconductor component. This allows the readout node to be effectively shielded in all directions against possible crosstalk of the modulation voltages and, on the other hand, to arrange the readout node at any point along the longitudinal axis of the readout gate within the same. An arrangement in the longitudinal direction of the readout gate in the middle of the same is particularly advantageous, as a result of which the maximum path that the photocharge carriers collected below the readout gate have to travel to the readout node is halved compared to an arrangement of the readout node at a longitudinal end of the readout gate. Halving the distance to be covered in this way enables the generated photocharge carrier quantity to be read out more quickly and thus enables the distance of surrounding objects to be recorded more quickly.

In one embodiment, the readout gate has a first section whose width is less than or equal to the width of the readout node, and a second section adjoining the first section whose width increases towards the readout node, wherein the recess at least partially accommodating the readout node is arranged in a region of the second section that has a maximum width. In particular, this can be achieved by the readout gate widening in a funnel shape towards the readout node and enclosing it laterally. Such a funnel-shaped readout gate enables effective lateral shielding against the modulation voltages and at the same time the readout gate has the smallest possible width in the remaining extension area thereof, thereby increasing the fill factor. However, a readout gate that widens in a circle towards the readout node, for example, is also conceivable.

In a further embodiment of the semiconductor component according to the invention, the mutually facing longitudinal sides of the readout gate and the closest modulation gate run parallel to one another, so that the modulation gate has a recess arranged on the readout gate side. Such an arrangement ensures that, despite the section-wise widening of the readout gate, the surface section of the semiconductor substrate between the readout gates is spanned as completely as possible by the modulation gates, which ensures that a clearly pronounced potential gradient is generated in this entire area and thus, if possible, all photocharge carriers generated within the semiconductor substrate can be read out.

In a further embodiment, the recess of the readout gate is arranged in the middle in the longitudinal direction of the readout gate. Here and in the following, an arrangement in the middle in the longitudinal direction of the readout gate means that the recess is arranged such that at least a partial section of it covers the central transverse axis of the readout gate. Such an arrangement in the middle minimizes the maximum path length to be covered by the photocharge carriers in the longitudinal direction of the readout gate and thus enables accelerated readout of the generated photocharge carriers that are accumulated under the readout gate.

In an embodiment of the semiconductor component according to the invention, the readout node is arranged at a longitudinal end of the readout gate, the accumulated photocharge carriers of which are read out by the readout node during operation of the semiconductor component. By arranging the readout node at the longitudinal end, the closest possible proximity to the modulation gates is achieved. guaranteed. In this case, the readout node is arranged, for example, in the longitudinal direction of the readout gate below the modulation gates if the readout gate has no recess and extends over the same length as the modulation gates. Arranged in the longitudinal direction of the readout gate below the modulation gates means that the modulation gates extend in the longitudinal direction a maximum of the same distance as the readout gate and an imaginary straight line through the outermost edge points of the modulation gates in the longitudinal direction of the readout gate does not overlap with or intersect the readout node. However, the readout node can also be shielded from the readout gate on the three sides closest to the modulation gates in the case of a funnel-shaped readout gate or at least a readout gate that widens towards the readout node, in particular widens in a circle. Thus, crosstalk of the modulation voltage is avoided in these arrangements, even if the readout node is not arranged in the longitudinal direction of the readout gate below the modulation gates, but rather at the same height as them.

In one embodiment, the readout node is arranged between two readout gates arranged along a common longitudinal axis, the accumulated photocharge carriers of which are read out by the readout node during operation of the semiconductor component. In this case, the readout node is directly adjacent to the modulation gates on two sides. This entails the risk of crosstalk of the modulation voltage to the readout node, although this effect is smaller overall due to the small crosstalk area compared to the embodiments known from the prior art. At the same time, the fill factor is increased compared to embodiments in which the readout node is arranged within a recess of the readout gate and the readout gate therefore extends around the readout node, since such a further extending readout gate leads to an increase in the area not contributing to the useful signal.

In a variant of this embodiment, the two readout gates arranged along a common longitudinal axis each have the same length. As a result, the maximum distance to be covered by the photo charge carriers within one of the readout gates to a readout node is minimized to half compared to an arrangement at the longitudinal end of a readout gate, which increases the readout speed.

In one embodiment of a semiconductor component according to the invention, the ratio of the length to the width of the readout node is at most 3:1, preferably at most 2:1 and particularly preferably 1:1. Consequently, such a readout node according to the invention is very compact and thus contributes in particular to an increase in the charge carrier conversion efficiency.

In one embodiment, the readout node has a rectangular, preferably square basic shape. Such basic shapes are particularly easy and therefore inexpensive to produce, with a square embodiment having a minimum length-to-width ratio of 1:1 and thus providing a very compact readout node.

In a further embodiment according to the invention, the readout node has a circular basic shape. Such a basic shape is also easy and therefore inexpensive to produce and has a minimal length to width ratio of 1:1. It provides a very compact readout node whose edge geometry is also the same in every direction, thus achieving uniform readout behavior in every direction.

One embodiment of the invention relates to a detector for distance measurement, which has a semiconductor component according to the invention and a modulation gate control device connected to the modulation gates for generating and controlling a variable potential difference between the modulation gates. By means of this modulation gate control device, the modulation voltage can be applied to the modulation gates with a preferred phase difference of 180° between the modulation gates, thus enabling the use of the semiconductor component according to the invention for distance measurement and in particular for amplitude and phase evaluation of incident intensity-modulated electromagnetic radiation.

Furthermore, a detector according to the invention in one embodiment has a readout gate control device connected to the readout gates for applying and controlling a constant voltage to the readout gates. Constant voltage means a voltage that is constant over time, in contrast to the modulation voltage at the modulation gates that varies over time. By means of such a constant voltage at the readout gates, these can be set to a potential minimum compared to the potential gradient generated by the modulation voltage. This ensures that all photocharge carriers displaced along the potential gradient reach the substrate area below a readout gate at the foot of the potential gradient and are collected there. In particular, the photocharge carriers collected there are In the case of a temporally constant potential minimum, charge carriers are shielded against further displacement under the influence of the modulation voltage and the charge carriers, once they have passed under a readout gate, essentially only move along the longitudinal direction of the readout gate.

In one embodiment, the readout gate control device is designed to apply and control a constant voltage to the readout gates, wherein the voltage has a potential gradient falling in the longitudinal direction of the readout gate to the readout node, which reads out the accumulated photo charge carriers of the readout gate during operation of the semiconductor component. Due to such a potential gradient, a drift field arises below the readout gate in the direction of the readout node, whereby the charge carrier transport is additionally accelerated and thus, in combination with suitably modulated modulation voltages, the charge carrier separation can be further improved.

In one embodiment, the readout control device is connected to the readout gates at the two opposite longitudinal ends of the readout gate. By means of such a connection, a potential gradient is generated along the readout gate when different potentials are applied to the two contacts, which brings with it the advantages already explained. In a further embodiment, the readout control device is additionally connected to the readout gates between two adjacent readout nodes. By means of such a connection, the potential between the two adjacent readout nodes can be raised and thus a potential gradient can be generated along the readout gate towards the two readout nodes.

In one embodiment, the detector according to the invention for distance measurement has a plurality of semiconductor components according to the invention, which are arranged next to one another so that they form a pixel matrix, and means for detecting the photo charge carrier sums read out via the individual readout nodes. It is particularly advantageous if several semiconductor components according to the invention are arranged next to one another in a row on a common semiconductor substrate and thus form a pixel array. It is particularly advantageous here if semiconductor components arranged next to one another in a row each share a readout gate and the readout nodes which read out the charge carriers accumulated under this readout gate during operation of the semiconductor component.

One embodiment of the invention relates to a sensor for three-dimensional image capture, which is characterized in that it has a detector according to the invention, an imaging optics for projecting incident electromagnetic radiation onto the detector and means for evaluating the detected measurement signals. By means of the imaging optics, the intensity-modulated electromagnetic radiation reflected from surrounding objects towards the sensor can be effectively imaged onto the semiconductor substrate of the semiconductor components, the sensor surface being formed by the semiconductor substrate of the semiconductor components. By means of the means for evaluating the detected measurement signals, the photocharge carrier sums read out at the individual readout nodes can be evaluated in such a way that the amplitude and phase information of the incident intensity-modulated electromagnetic radiation is recorded by forming the difference and the distance information of the objects reflecting the intensity-modulated radiation is determined from this.

• 1 eine erste schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 2 eine zweite schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 3 eine dritte schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 4 eine vierte schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 5 eine fünfte schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 6 eine sechste schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 7 eine siebte schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 8 eine achte schematische Darstellung zweier nebeneinander angeordneter Halbleiterbauelemente in Draufsicht,
• 9a eine schematische Darstellung eines Schnitts senkrecht zur Längsachse der Gates durch ein Halbleiterbauelement,
• 9b eine schematische Darstellung des Potentialverlaufs im Halbleitersubstrat des Halbleiterbauelements in 9a und
• 9c eine schematische Draufsicht auf einen Ausschnitt des Halbleiterbauelements in 9a.

Further advantages, features and possible applications of the present invention will become clear from the following description of preferred embodiments and the associated figures. They show:

• 1 a first schematic representation of two semiconductor components arranged next to each other in plan view,
• 2 a second schematic representation of two semiconductor components arranged next to each other in plan view,
• 3 a third schematic representation of two semiconductor components arranged next to each other in plan view,
• 4 a fourth schematic representation of two semiconductor components arranged next to each other in plan view,
• 5 a fifth schematic representation of two semiconductor components arranged next to each other in plan view,
• 6 a sixth schematic representation of two semiconductor components arranged next to each other in plan view,
• 7 a seventh schematic representation of two semiconductor components arranged next to each other in plan view,
• 8th an eighth schematic representation of two semiconductor components arranged next to each other in plan view,
• 9a a schematic representation of a section perpendicular to the longitudinal axis of the gates through a semiconductor device,
• 9b a schematic representation of the potential curve in the semiconductor substrate of the semiconductor device in 9a and
• 9c a schematic plan view of a section of the semiconductor device in 9a .

In 1 a schematic plan view of two semiconductor components 1, 1' arranged next to one another is shown, the first semiconductor component 1 having three strip-shaped modulation gates 3, 4, 5 arranged parallel next to one another and two strip-shaped readout gates 6, 7 arranged parallel to one another in the longitudinal direction. The modulation gates 3, 4, 5 are arranged between the readout gates 6, 7. Both readout gates 6, 7 each have a readout node 8, 9 at one longitudinal end. The length L _AG of the readout gates 6, 7 together with the length L _AK of the readout nodes 8, 9 is equal to the length L _MG of the modulation gates 3, 4, 5. In addition, the length L _AG of the readout gates 6, 7 is greater than the channel length Δ _AG . The points on the ends of the readout gates 6, 7 opposite the readout nodes 8, 9 therefore have a minimum distance Δ _min to the respective readout node 8, 9 which is equal to the length L _AG of the readout gates 6, 7 and thus greater than the channel length Δ _AG and in particular greater than half the channel length Δ _AG . In the embodiment shown, all three modulation gates 3, 4, 5 have the same shape and dimensions. Likewise, the shapes of the two readout gates 6, 7 are the same as the shapes of the two readout nodes 8, 9 are the same. The two readout nodes 8, 9 each have a rectangular basic shape with a width B _AK which is equal to the width B _AG of the readout gates 6, 7 but smaller than the length L _AK of the readout nodes 8, 9. The width B _MG of the modulation gates 3, 4, 5 is greater than the width B _AG of the readout gates 6, 7. The semiconductor component 1 is axially symmetrical with respect to the central longitudinal axis of the modulation gate 5. In addition to the first semiconductor component 1, a second semiconductor component 1' with three modulation gates 3', 4', 5', two readout gates 6', 7' and two readout nodes 8', 9' is shown. The second semiconductor component 1' has the same technical features as the first semiconductor component 1, with the same dashed and undashed reference numbers designating the same elements. The two semiconductor components 1, 1' are therefore axially symmetrical with respect to the central longitudinal axis of the readout gate 7/7'. The two semiconductor components 1, 1' arranged next to one another share the readout gate 7/7' arranged between them and the associated readout node 9/9'. For this purpose, both semiconductor components 1, 1' are arranged on a common photoconductive semiconductor substrate 2 (not shown). The modulation gates 3, 3', 4, 4' are each supplied with a modulation voltage U _mod , the phase difference between modulation gates 3 and 4 or 3' and 4' being 180° in each case. The voltage of the middle gate 5, 5' is kept constant in each case, but is part of the potential gradient as the middle potential level between the two potential levels of the modulation gates 3 and 4 or 3' and 4', by which the potential difference between the modulation gates 3 and 4 or 3' and 4' varies. In order to use the readout gate 7/7' and the readout node 9/9' for both semiconductor components 1, 1', the two modulation gates 4 and 4' are supplied with in-phase modulation voltages U _mod . The central longitudinal axis of the readout gate 7/7' therefore also forms an axis of symmetry of the potential profile generated below the two semiconductor components 1, 1' in the common photoconductive semiconductor substrate 2 (not shown). Photocharge carriers generated in the photoconductive semiconductor substrate 2 (not shown) are displaced by the applied modulation voltages U _mod along the potential gradients to the readout gates 6, 6', 7, 7' arranged at the foot of the potential gradient at this time and accumulated under them. These photocharge carriers are then shifted further along the longitudinal direction of the readout gates 6, 6', 7, 7' to the readout nodes 8, 8', 9, 9' and read out via the readout nodes 8, 8', 9, 9', or in the embodiment shown, are partially shifted directly to the readout nodes 8, 8', 9, 9' and read out by them due to the potential differences resulting from the modulation voltages U _mod .

In 2 is a plan view of two semiconductor components 1, 1' according to the invention arranged next to one another, which differ from the 1 shown arrangement only in that in 2 the readout nodes 8, 8', 9, 9' are arranged in the longitudinal direction of the readout gates 61, 61', 62, 62', 71, 71', 72, 72' in the middle between them and thus divide the readout gates 61, 61', 62, 62', 71, 71', 72, 72' into two separate readout gates 61 and 62 or 71/71' and 72/72' or 61' and 62' arranged along a common longitudinal axis. The present embodiment is therefore also axially symmetrical with respect to an imaginary axis of symmetry that runs through the centers of the readout nodes 8, 8', 9, 9'. The maximum distance to be covered by the photocharge carriers along the readout gates 61, 61', 62, 62', 71, 71', 72, 72' is only half of that in 1 illustrated embodiment, which allows a faster reading of the accumulated charge carriers. The points on the ends of the readout gates 61, 61', 62, 62', 71, 71', 72, 72' opposite the readout nodes 8, 8', 9, 9' thus have a minimum distance Δ _min to the respective readout node 8, 8', 9, 9', which is half as large as in the case of the embodiment in 1 However, the length L _AG of the readout gates 61, 61', 62, 62', 71, 71', 72, 72' is greater than half the channel length Δ _AG . Thus, the points on the ends of the readout gates 61, 61', 62, 62', 71, 71', 72, 72' opposite the readout nodes 8, 8', 9, 9' also have a minimum distance Δ _min to the respective readout node 8, 8', 9, 9' that is greater than half the channel length Δ _AG .

3 shows a plan view of two semiconductor components 1, 1' according to the invention arranged next to one another, which differ from the 1 shown arrangement in that a readout node 81, 81', 82, 82', 91, 91', 92, 92' is arranged in the longitudinal direction at both ends of the readout gates 6, 6', 7, 7'. Thus, the semiconductor components 1, 1' have two readout nodes 81, 81', 82, 82', 91, 91', 92, 92' for each readout gate 6, 6', 7, 7'. The readout nodes 81, 81', 82, 82', 91, 91', 92, 92' all have the same square basic shape with a width B _AK that is equal to the length L _AK of the readout nodes 81, 81', 82, 82', 91, 91', 92, 92'. The embodiment is axially symmetrical with respect to an imaginary axis of symmetry that runs through the center points between the readout nodes 81 and 82, 91/91' and 92/92' and 81' and is thus identical to the central transverse axes of the readout gates 6, 6', 7, 7' and the modulation gates 3, 3', 4, 4', 5, 5'. In addition, the length L _AG of the readout gates 6, 6', 7, 7' is greater than the channel length Δ _AG . Thus, the points on the central transverse axes of the readout gates 6, 6', 7, 7', i.e. on the readout gates 6, 6', 7, 7' in the middle between the readout nodes 81 and 82, 91/91' and 92/92' or 81' and 82' have a minimum distance Δ _min to the respective readout node 81 and 82, 91/91' and 92/92' or 81' and 82', which is half the length L _AG of the readout gates 6, 6', 7, 7' and is therefore greater than half the channel length Δ _AG .

In the 4 The embodiment shown differs from the embodiment in 1 merely in that the readout gates 6, 6', 7, 7' are wider and have the same length L _AG as the modulation gates 3, 3', 4, 4', 5, 5', ie L _AG is equal to L _MG . The width B _AG of the readout gates 6, 6', 7, 7' is greater than the width B _AK of the readout nodes 8, 8', 9, 9'. The readout nodes 8, 8', 9, 9' are each arranged in a recess 10, 10', 11, 11' at the long end of the readout gates 6, 6', 7, 7'. Thus, the readout nodes 8, 8', 9, 9' are surrounded on three sides by the readout gates 6, 6', 7, 7' and, in particular on the modulation gate side, are shielded by the readout gates 6, 6', 7, 7' against an overlap of the modulation voltages U _mod applied to the modulation gates 3, 3', 4, 4', 5, 5'.

In 5 Two semiconductor components 1, 1' according to the invention arranged next to one another are shown in a plan view, wherein the semiconductor components 1, 1' and their arrangement differ from the 4 shown only in that the readout nodes 8, 8', 9, 9' are arranged in the longitudinal direction of the readout gates 6, 6', 7, 7' in the middle in a recess 10, 10', 11, 11' in the same. This embodiment is therefore additionally axially symmetrical with respect to an imaginary axis of symmetry which runs through the centers of the readout nodes 8, 8', 9, 9'. The readout nodes 8, 8', 9, 9' are in this case completely enclosed by the readout gates 6, 6', 7, 7'. Due to the arrangement in the longitudinal direction of the readout gates 6, 6', 7, 7' in the middle, in the present case the maximum distances to be covered by the collected photo charge carriers under the readout gates 6, 6', 7, 7' are reduced compared to the 4 The points on the ends of the readout gates 6, 6', 7, 7' opposite the readout nodes 8, 8', 9, 9' have a minimum distance Δ _min to the respective readout node 8, 8', 9, 9', which is half as large as in the case of the embodiment in 4 . The length L _AG of the readout gates 6, 6', 7, 7' is in turn greater than half the channel length Δ _AG and thus the minimum distance Δ _min of the points on the ends of the readout gates 6, 6', 7, 7' opposite the readout nodes 8, 8', 9, 9' to the respective readout node 8, 8', 9, 9' is greater than half the channel length Δ _AG .

In the 6 The embodiment shown also shows two semiconductor components 1, 1' according to the invention arranged next to one another in a plan view. The embodiment shown differs from the one shown in 5 shown in that in addition to the readout nodes 82, 82', 92, 92' arranged in the middle of the readout gates 6, 6', 7, 7' in a recess 10, 10', 11, 11', in addition in the longitudinal direction at both longitudinal ends of the readout gates 6, 6', 7, 7' a readout node 81, 81', 83, 83', 91, 91', 93, 93' in the same way as the readout nodes 8, 8', 9, 9' in 4 is arranged. The semiconductor components 1, 1' therefore have three readout nodes 81, 81', 82, 82', 83, 83', 91, 91', 92, 92', 93, 93' for each readout gate 6, 6', 7, 7'. The readout nodes 81, 81', 82, 82', 83, 83', 91, 91', 92, 92', 93, 93' all have the same square basic shape with a width B _AK that is equal to the length L _AK of the readout nodes 81, 81', 82, 82', 83, 83', 91, 91', 92, 92', 93, 93'. In addition, the distances between neighboring readout nodes 81, 81', 82, 82', 83, 83', 91, 91', 92, 92', 93, 93' are greater than the channel length Δ _AG . Thus, the points on the readout gates 6, 6', 7, 7' in the middle between neighboring readout nodes 81, 81', 82, 82', 83, 83', 91, 91', 92, 92', 93, 93' have a minimum distance Δ _min to the respective neighboring readout nodes 81, 81', 82, 82', 83, 83', 91, 91', 92, 92', 93, 93' which is greater than half the channel length Δ _AG .

In 7 Two semiconductor components 1, 1' arranged next to each other can be seen in a plan view, wherein the semiconductor components 1, 1' shown are arranged opposite to the semiconductor components 1, 1' shown in 1 The semiconductor components 1, 1' shown in FIG. 1 differ in that they are widened in a funnel shape at the end on the readout node side, i.e. they each have a first section 12, 12', 13, 13', whose width B _AG is equal to the width B _AK of the readout nodes 8, 8', 9, 9', and a second section 14, 14', 15, 15', which widens symmetrically and constantly towards the readout nodes 8, 8', 9, 9'. The second section 14, 14', 15, 15' reaches a maximum width at the level of the readout nodes 8, 8', 9, 9' and runs from there to the end of the readout gates 6, 6', 7, 7' with a constant maximum width. The readout nodes 8, 8', 9, 9' are therefore wider than in the embodiment in FIG. 1. 1 not only on one side, but rather on three sides by the readout gates 6, 6', 7, 7' in the recesses 10, 10', 11, 11'. In particular, the readout nodes 8, 8', 9, 9' are shielded on the modulation gate side from the neighboring modulation gates 3, 3', 4, 4' by the readout gates 6, 6', 7, 7' against an overreach of the modulation voltage U _mod . For a compact construction of the semiconductor components 1, 1' with the maximum possible semiconductor substrate area 2 (not shown) covered by the modulation gates 3, 3', 4, 4', 5, 5', the embodiment in 7 the advantages of narrow readout gates 6, 6', 7, 7', as used in 1 are shown, and a three-sided shielding of the readout nodes 8, 8', 9, 9' by the readout gates 6, 6', 7, 7' of an embodiment as shown in 4 In particular, the modulation gates 3, 3', 4, 4' adjacent to the readout gates 6, 6', 7, 7' each have a recess 16, 16', 17, 17' on the readout gate side at the level of the second sections 14, 14', 15, 15' of the readout gates 6, 6', 7, 7'. The shapes of the recesses 16, 16', 17, 17' are identical to those in comparison to the embodiments in 1 additional sections of the readout gates 6, 6', 7, 7'. Thus, the adjacent side edges of the readout gates 6, 6', 7, 7' and the modulation gates 3, 3', 4, 4' run parallel to each other.

In 8th Two adjacent semiconductor components 1, 1' are shown, wherein the readout gates 6, 6', 7, 7' are again designed in a funnel shape and wherein the readout nodes 8, 8', 9, 9' are arranged in the longitudinal direction of the readout gates 6, 6', 7, 7' in the middle in recesses 10, 10', 11, 11' in the same. The readout gates 6, 6', 7, 7' therefore each have a first section 12, 12', 13, 13' at both ends in the longitudinal direction, the width B _AG of which is equal to the width B _AK of the readout nodes 8, 8', 9, 9', to which a second section 14, 14', 15, 15' arranged in the middle in the longitudinal direction of the readout gate 6, 6', 7, 7' is connected. The two second sections 14, 14', 15, 15' are arranged to merge directly into one another. The modulation gates 3, 3', 4, 4' adjacent to the readout gates 6, 6', 7, 7' in turn have recesses 16, 16', 17, 17' arranged on the readout gate side for the funnel-shaped sections of the readout gates 6, 6', 7, 7' with the readout nodes 8, 8', 9, 9'. The shapes of the recesses 16, 16', 17, 17' are identical to those in comparison to the readout gates 61, 61', 62, 62', 71, 71', 72, 72' in the embodiment in 2 additional sections of the readout gates 6, 6', 7, 7'. Thus, in this embodiment, the adjacent side edges of the readout gates 6, 6', 7, 7' and the modulation gates 3, 3', 4, 4' run parallel to each other. Thus, the embodiment in 8th the advantages of narrow readout gates 6, 6', 7, 7', as used in 2 are shown, with the advantages of all-round shielding of the readout nodes 8, 8', 9, 9' arranged in the recesses 10, 10', 11, 11' of the readout gates 6, 6', 7, 7' against the modulation voltages U _mod applied to the modulation gates 3, 3', 4, 4', 5, 5' by the readout gates 6, 6', 7, 7'.

In 9a is a schematic section through a semiconductor component 1 according to the invention perpendicular to the longitudinal axes of the gates 3, 4, 6, 7. Two readout gates 6 and 7 with a rectangular cross-section can be seen, which are arranged on a semiconductor substrate 2. Between the two readout gates 6 and 7, two modulation gates 3 and 4 are shown, which also have a rectangular cross-section, wherein the width B _MG of the modulation gates 3, 4 is significantly larger than the width B _AG of the readout gates 6, 7. A shielding element 18, 19 with a rectangular cross-section is arranged above the readout gates 6, 7, which is impermeable to the electromagnetic radiation to be detected and thus shields the readout gates 6, 7 against this radiation. Incident electromagnetic radiation therefore only reaches the photoconductive semiconductor substrate 2 through the modulation gates 3, 4 designed as photogates and generates photo charge carriers there in proportion to their intensity. The structure of the semiconductor component 1 shown is axially symmetrical with respect to an imaginary axis of symmetry that runs in the middle between the two modulation gates 3 and 4 perpendicular to the surface of the semiconductor substrate 2. In 9b is for the 9a The gate arrangement shown shows a snapshot of the potential U(s) generated within the photoconductive semiconductor substrate 2 by the modulation voltage U _mod applied to the modulation gates 3, 4 and the same time-constant readout voltages U _AG applied to the readout gates 6, 7. The time-varying potential U(s) is a function of the Location s in the transverse direction to the gates 3, 4, 6, 7. Due to the readout voltage U _AG applied to the readout gates 6 and 7, the substrate areas below the readout gates 6, 7 are each at a potential minimum, with the substrate section below the modulation gate 3 at a potential maximum at the time shown and the potential section below the modulation gate 4 at a relatively lower potential level. As a result of the temporal variation of the modulation voltage U _mod, the areas below the modulation gates 3, 4 vary alternately between the two potential levels of the modulation voltage U _mod shown. The photocharge carriers generated in the semiconductor substrate are each shifted down the potential gradient from the side with the higher potential level to the side with the lower potential level. In the process, they are collected under the readout gate 6, 7, which is arranged adjacent to the modulation gate 3, 4 with the currently lower potential level. In 9c is an excerpt from 9a shown semiconductor component 1 in a plan view, wherein the two shielding elements 18, 19 are not shown. It can be seen that the two readout nodes 8, 9 in the present case are each arranged at one end of the readout gates 6, 7 in the longitudinal direction of the gates 3, 4, 6, 7 below the height of the modulation gates 3, 4 and the readout gates 6, 7. The readout gates 6, 7 extend in the longitudinal direction over the same length as the modulation gates 3, 4. The readout nodes have a rectangular floor plan with a smaller width B _AK than the width B _AG of the readout gates 6, 7. Such a compact and small area of the readout nodes 8, 9 shown here in relation to the readout gates 3, 4 leads to a high charge carrier conversion efficiency. At the same time, the readout nodes 8, 9 are effectively shielded against crosstalk of the modulation voltage U mod by the fact _that they are not arranged at the same height as the modulation gates 3, 4 and by the fact that the width B _AG of the readout gates 6, 7 is greater than the width B _AK of the readout nodes 8, 9.

List of reference symbols

1.1'

Semiconductor component

2

Photoconductive semiconductor substrate

3, 3'

First modulation gate

4, 4'

Second modulation gate

5, 5'

Third modulation gate

6, 6'

Readout gate

61, 61'

Readout gate

62, 62'

Readout gate (along common longitudinal axis with 61, 61')

7, 7'

Readout gate

71, 71'

Readout gate

72, 72'

Readout gate (along common longitudinal axis with 71, 71')

8, 8'

Reading node

81, 81'

Reading node

82, 82'

Reading node

83, 83'

Reading node

9, 9'

Reading node

91, 91'

Reading node

92, 92'

Reading node

93, 93'

Reading node

10, 10'

Recess of a readout gate

11, 11'

Recess of a readout gate

12, 12'

First section of a readout gate

13, 13'

First section of a readout gate

14, 14'

Second section of a readout gate

15, 15'

Second section of a readout gate

16, 16'

Recess of the first modulation gate

17, 17'

Recess of the second modulation gate

18

Shielding element for a readout gate

19

Shielding element for a readout gate

BAC

Readout node width

LAC

Readout node length

BAG

Readout gate width

LAG

Readout gate length

BMG

Modulation gate width

LMG

Modulation gate length

ΔAG

Channel length

Δmin

Minimum distance between a point on a readout gate and the readout node closest to the point

Umod

Modulation voltage at the modulation gates

UAG

Readout voltage at the readout gates

U(s)

Potential in the semiconductor substrate as a function of s

s

Location across the gates

Claims (30)

Semiconductor component (1,1') with a photoconductive semiconductor substrate (2) and at least two modulation gates (3, 3', 4, 4', 5, 5'), wherein the modulation gates (3, 3', 4, 4', 5, 5') have a length (L _MG ) and are arranged parallel to one another in the longitudinal direction on the substrate (2), and wherein the modulation gates (3, 3', 4, 4', 5, 5') are designed to generate and vary a potential difference (U _mod ) within the substrate (2) at least between substrate sections on which the modulation gates (3, 3', 4, 4', 5, 5') are arranged, wherein the semiconductor component (1,1') is designed such that incident electromagnetic radiation is at least partially directed into a substrate section between and below the modulation gates (3, 3', 4, 4', 5, 5') and can generate charge carriers there, wherein the semiconductor component (1,1') has at least two readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), wherein the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') have a length (L _AG ) which is greater than their width (B _AG ) and are arranged in the longitudinal direction parallel to the modulation gates (3, 3', 4, 4', 5, 5') which are arranged between the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') are arranged at a distance (Δ _AG ) from one another on the substrate (2), wherein the distance (Δ _AG ) of the readout gates from one another forms the channel length of the semiconductor component, and wherein the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') for collecting charge carriers in the substrate (2) below the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and for conducting the collected charge carriers in the longitudinal direction of the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), wherein the semiconductor component (1,1') has at least one readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') for each readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), and wherein the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is connected to the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and is designed to read out the charge carriers accumulated below the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') in the substrate (2), wherein the minimum distance (Δ _min ) between at least one point on the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is greater than half the channel length (Δ _AG ). Semiconductor component (1,1') according to Claim 1 , characterized in that the minimum distance (Δ _min ) between at least one point on the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') closest to this point is greater than the channel length (Δ _AG ). Semiconductor component (1,1') according to Claim 1 or 2 , characterized in that the minimum distance (Δ _min ) between at least one point on the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') closest to this point is greater than 5 µm. Semiconductor component (1,1') according to one of the preceding claims, characterized in that the semiconductor component (1,1') has exactly one readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') for each readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the preceding claims, characterized in that the width (B _AG ) of the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') is smaller than a quarter of the channel length (Δ _AG ). Semiconductor component (1,1') according to one of the preceding claims, characterized in that the length (L _AK ) of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is smaller than the length (L _AG ) of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), the accumulated charge carriers of which the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') during operation of the semiconductor device. Semiconductor component (1,1') according to Claim 6 , characterized in that the ratio between the length (L _AK ) of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') and the length (L _AG ) of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') is at most 1:10. Semiconductor component (1,1') according to one of the preceding claims, characterized in that the area of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is at least ten times smaller than the total area of the adjacent readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the preceding claims, characterized in that exactly three modulation gates (3, 3', 4, 4', 5, 5') arranged parallel to one another in the longitudinal direction are provided between the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the preceding claims, characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged on the longitudinal axis of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the preceding claims, characterized in that the width (B _AK ) of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is smaller than the width (B _AG ) of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the preceding claims, characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged at least partially in a recess (10, 10', 11, 11') of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to Claim 12 , characterized in that the recess (10, 10', 11, 11') for receiving the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged in the middle in the transverse direction of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the Claims 12 or 13 , characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged completely in the recess (10, 10', 11, 11') for receiving the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93'), so that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is completely enclosed laterally by the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the Claims 12 until 14 , characterized in that the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') has a first section (12, 12', 13, 13'), the width (B _AG ) of which is less than or equal to the width (B _AK ) of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93'), and a second section (14, 16) adjoining the first section (12, 12', 13, 13'), the width (B _{AG ) of which is smaller than or equal to the width (B AK} ) of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93'), wherein the recess (11, 12) at least partially accommodating the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged in a region of the second section (14, 16) which has a maximum width. Semiconductor component (1,1') according to Claim 15 , characterized in that the mutually facing longitudinal sides of a readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') and of the nearest modulation gate (3, 3', 4, 4') run parallel to one another, so that the modulation gate (3, 3', 4, 4') has a recess (16, 16', 17, 17') arranged on the readout gate side. Semiconductor component (1,1') according to one of the Claims 14 until 16 , characterized in that the recess (10, 10', 11, 11') of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') is arranged in the middle in the longitudinal direction thereof. Semiconductor component (1,1') according to one of the Claims 1 until 16 , characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged at a longitudinal end of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Semiconductor component (1,1') according to one of the Claims 1 until 10 , characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is arranged between two readout gates (61, 61', 62, 62', 71, 71', 72, 72') arranged along a common longitudinal axis. Semiconductor component (1,1') according to Claim 19 , characterized in that the two readout gates (61, 61', 62, 62', 71, 71', 72, 72') arranged along a common longitudinal axis each have the same length (L _AG ). Semiconductor component (1,1') according to one of the preceding claims, characterized in that the ratio of the length (L _AK ) to the width (B _AK ) of the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') is at most 3:1. Semiconductor component (1,1') according to one of the preceding claims, characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') has a rectangular basic shape. Semiconductor component (1,1') according to one of the Claims 1 until 21 , characterized in that the readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') has a circular basic shape. Detector for distance measurement, wherein the detector comprises a semiconductor component (1,1') according to one of the preceding claims and a modulation gate control device connected to the modulation gates for generating and controlling a variable potential difference (U _mod ) between the modulation gates (3, 3', 4, 4', 5, 5'). Detector for distance measurement according to Claim 24 , characterized in that it has a readout gate control device connected to the readout gates for applying and controlling a constant voltage (U _AG ) to the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Detector for distance measurement according to Claim 25 , characterized in that the readout gate control device is designed to apply and control a constant voltage (U _AG ) to the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'), wherein the voltage (U _AG ) is in each case a voltage in the longitudinal direction of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') to a readout node (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93') which collects the charge carriers of the readout gate (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') during operation of the semiconductor component, has a decreasing potential gradient. Detector for distance measurement according to Claim 26 , characterized in that the readout control device is connected to the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') at the two opposite longitudinal ends of the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72'). Detector for distance measurement according to Claim 27 , characterized in that the readout control device is connected to the readout gates (6, 6', 61, 61', 62, 62', 7, 7', 71, 71', 72, 72') between two adjacent readout nodes (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93'). Detector for distance measurement according to one of the Claims 24 until 28 , characterized in that it comprises a plurality of semiconductor components (1, 1') which are arranged next to one another so that they form a pixel matrix, and means for detecting the charge carrier sums read out via the individual readout nodes (8, 8', 81, 81', 82, 82', 83, 83', 9, 9', 91, 91', 92, 92', 93, 93'). Sensor for three-dimensional image capture, whereby the sensor has a detector according to Claim 28 , an imaging optics for projecting incident electromagnetic radiation onto the detector and means for evaluating the detected measurement signals.

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