DE102012107639A1 - Method for reading data from e.g. phase change RAM, involves scanning voltage level difference between data voltage and reference voltages to produce differential output signals, and amplifying output signals to produce read data - Google Patents

Abstract

The method involves receiving data voltage and reference voltages at a sense amplifier, where the data voltage corresponds to data stored in memory cells. A voltage level difference between the data voltage and the reference voltages at the sense amplifier is scanned to produce differential output signals. The differential output signals are amplified at another sense amplifier, to produce read data for the memory cells. A control logic unit (1220) is provided for controlling overall operation of a controller (1200). An independent claim is also included for a non-volatile memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims under 35 USC § 119 the priority of Korean Patent Application No. 10-2011-0085146 filed with the Korean Intellectual Property Office on 25 August 2011, and the Korean Patent Application No. 10-2011-0110719 filed on 27 October 2011 with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.

BACKGROUND

Technical area

The inventive concept relates to a data read circuit, and more particularly to a data read circuit for performing a data read operation using a plurality of reference voltages, a nonvolatile memory device having the data read circuit, and to a method of reading data from the nonvolatile memory device.

Discussion of the Related Art

A semiconductor memory is an electronic data storage device implemented on a semiconductor-based integrated circuit. Examples of semiconductor memory devices may include volatile memory devices and non-volatile memory devices. Volatile memory devices require power to maintain the stored information, non-volatile memory devices require no power.

Examples of nonvolatile memory devices may include phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM) Magnetic Random Access Memory) and a ferroelectric random access memory (FRAM). A PRAM stores data by changing the state of matter from which the device is made. An RRAM uses a variable resistance material, such as complex metal oxides whose resistance values change when a voltage is applied to store data, MRAM data is stored by magnetic storage elements formed of two ferromagnetic plates, and a FRAM uses a ferroelectric one Layer to store data.

Semiconductor memory devices with improved performance are being developed at a near-rage speed. Improved performance can be achieved by increasing a degree of integration, increasing an operating speed, or by guaranteeing data reliability. However, due to a number of factors, such as process variations that occur when the semiconductor memory device is manufactured, or a variation in the signals provided to circuits for operating the semiconductor memory device (e.g., data writing or reading circuits), degradation may occur the performance still occur. Accordingly, there is a need for a semiconductor memory device capable of reducing degradation in performance.

SHORT VERSION

The inventive concept provides a data read circuit capable of improving the performance of a semiconductor memory device by guaranteeing data reliability with respect to several factors, which typically have a negative impact on performance, for example. The inventive concept provides a nonvolatile memory device having the data read circuit and a method of reading data from the nonvolatile memory device.

According to an exemplary embodiment of the inventive concept, a method for reading out data from a nonvolatile memory device comprises: receiving a data voltage, a first reference voltage and a second reference voltage at a first sense amplifier, the data voltage corresponding to data that is in one Memory cell are stored; sampling a voltage level difference between the data voltage and the first and second reference voltages at the first sense amplifier to produce first and second differential output signals; and amplifying the first and second differential output signals at a second sense amplifier to generate read data for the memory cell.

The second sense amplifier amplifies the first and second output signals after a first delay.

The first delay is a time from when the first sense amplifier is activated until when the second sense amplifier is activated.

The method further comprises precharging first and second differential output terminals of the first sense amplifier to voltages of a first level in response to a control signal prior to receiving the data voltage and the first and second reference voltages.

The sampling performed on the first sense amplifier includes: storing two voltage levels applied to the first and second differential output terminals, the two voltage levels being based on the voltage level difference between the data voltage and the first and second differential amplifiers second reference voltage are based.

The sampling performed on the first sense amplifier includes: providing the two voltage levels from the first sense amplifier as the first and second differential output signals for the second sense amplifier in response to a version of the control signal resulting from the first delay wherein the gain performed on the second sense amplifier comprises: amplifying the first and second differential output signals; and an output of the amplified first and second differential output signals as the read data.

According to an exemplary embodiment of the inventive concept, a nonvolatile memory device comprises: a cell array having a plurality of memory cells; and a sense amplifying circuit configured to receive a data voltage of a memory cell, a first reference voltage, and a second reference voltage during a data read operation of the memory cell to generate differential output signals based on a voltage level. Difference between the data voltage and the first and the second reference voltage to generate, and to output the differential output signals as read from the memory cell data.

The sense amplifier circuit comprises: a first sense amplifier in response to a control signal, the first sense amplifier configured to receive the data voltage and the first and second reference voltages, and the differential output signals based on the voltage level To produce difference between the data voltage and the first and second reference voltages; a delay unit configured to receive the control signal and to generate a delayed control signal; and a second sense amplifier, wherein the second sense amplifier is configured to amplify the differential output signals in response to the delayed control signal and output the amplified differential output signals as the data read from the memory cell.

The nonvolatile memory device further includes: a first reference voltage generation unit configured to generate the first reference voltage; and a second reference voltage generating unit configured to generate the second reference voltage, wherein the first and second reference voltage generating units are separate from the cell array.

The nonvolatile memory device further comprises a reference cell array, the reference cell array comprising: a first reference cell configured to generate the first reference voltage; and a second reference cell configured to generate the second reference voltage.

The first and second reference cells have the same structure as the memory cell.

The data voltage has a high voltage level or high voltage level or a low voltage level.

The first reference voltage has the same voltage level as the data voltage, and the second reference voltage has a voltage level different from the data voltage.

The second reference voltage has the same voltage level as the data voltage, and the first reference voltage has a voltage level different from the data voltage.

The memory cell is a Magnetic Random Access Memory (MRAM), a Phase Change Random Access Memory (PRAM), a Resistive Random Access Memory (RRAM) Access Memory) or a Ferroelectric Random Access Memory (FRAM).

According to an exemplary embodiment of the inventive concept, a nonvolatile memory device comprises: a cell arrangement comprising a memory cell, a first reference cell and a second reference cell wherein the memory cell is connected to a first bit line, wherein the first reference cell is connected to a second bit line and the second reference cell is connected to a third bit line; and a sense amplifier configured to receive a data voltage of the memory cell provided from the first bit line, a first reference voltage of the first reference cell provided from the second bit line, and a second reference voltage of the second reference cell received from the third bit line is arranged to receive, and in response to the reception of the data voltage and the first and the second reference voltage, the sense amplifier is configured to determine a difference between the data voltage and the first and the second reference voltage and this difference as data consisting of Memory cell are read out.

The difference between the data voltage and the first and second reference voltages is determined after a time delay which is measured from when a first portion of the sense amplifier is activated by a control signal until a delayed version of the control signal activates a second portion of the sense amplifier.

The data voltage is generated by a data voltage generating unit having the memory cell, the first reference voltage is generated by a first reference voltage generating unit having the first reference cell, and the second reference voltage is generated by a second reference voltage generating unit having the second reference cell, wherein the data voltage generating unit, the first reference voltage generation unit and the second reference voltage generation unit each have the same structure.

According to an exemplary embodiment of the inventive concept, a nonvolatile memory device comprises: a first sense amplifier, a second sense amplifier and a delay unit, the first sense amplifier having a first input unit for receiving a data voltage, a second input unit for receiving a first and a second reference voltage a biasing unit for biasing the first sense amplifier, a pre-charge unit for pre-charging a first differential output terminal connected to the first input unit, and a second differential output terminal connected to the second input unit a first capacitor for storing a first voltage at the first differential output terminal and a second capacitor for storing a second voltage at the second Dif ferential output node, wherein the first and second voltages are based on a voltage level difference between the data voltage and the first and second reference voltages; the delay unit for receiving a control signal which activates the pre-charging unit, which delays the control signal and provides the delayed control signal for the second sense amplifier; and the second sense amplifier having a second bias unit for receiving the delayed control signal to activate the second sense amplifier and a latch having a first node connected to the first differential output terminal and a second node Node, which is connected to the second differential output terminal, and wherein, when the second sense amplifier is activated, the latch amplifies the stored first and second voltages and outputs the amplified first and second voltages via the first and second differential output terminals, respectively.

The first input unit has a first and a second serially connected transistor.

The first and second transistors comprise metal oxide semiconductor transistors.

The second input unit has a third and a fourth serially connected transistor.

The third and fourth transistors comprise metal oxide semiconductor transistors.

According to an exemplary embodiment of the inventive concept, a Spin Torque Transfer (STT) MRAM device comprises: a sense amplifier having a first node receiving a data voltage provided by a memory cell, a second node receiving a first reference voltage, a third node receiving a second reference voltage, and a fourth node outputting a signal as data read out from the memory cell, the signal being at a voltage level difference between the second reference voltage Data voltage and the first and second reference voltage is based.

The first reference voltage is provided by a first reference voltage generating unit and the second reference voltage is provided by a second reference voltage generating unit.

The first and second reference voltage generating units are included in a memory cell array or are separate from the memory cell array.

The voltage level difference between the data voltage and the first and second reference voltages is stored in at least two capacitors of the sense amplifier.

The first node is connected to a gate of a first transistor, the second node is connected to a gate of a second transistor, and the third node is connected to a gate of a third transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

1 FIG. 3 is a block diagram of a memory system according to an exemplary embodiment of the inventive concept; FIG.

2A is a block diagram showing a nonvolatile memory device, which in 1 is shown in accordance with an exemplary embodiment of the inventive concept illustrated;

2 B a circuit diagram of a memory cell in the nonvolatile memory device, which in 2A is shown is;

2C is a cross-sectional view of a magnetic tunnel junction (MTJ) of the memory cell, which in 2 B is shown;

3 Fig. 12 is a circuit diagram illustrating a data read circuit which may be included in a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

4 FIG. 10 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept; FIG.

5 is a circuit diagram illustrating a data read circuit of the non-volatile memory device, which in 4 is illustrated according to an exemplary embodiment of the inventive concept;

6 Fig. 10 is a block diagram of a sense amplification circuit included in a data read circuit according to an exemplary embodiment of the inventive concept;

7 and 8th Wiring diagrams are showing the sense amplification circuit, which in 6 according to an exemplary embodiment of the inventive concept;

9A . 9B . 10A and 10B Are graphs showing input / output waveforms of the sense amplification circuit, which is shown in FIG 6 according to an exemplary embodiment of the inventive concept is shown;

11A Figure 4 is a graph for comparing a data signal waveform of a conventional data read circuit with a data signal waveform of a data read circuit according to an exemplary embodiment of the inventive concept;

11B Fig. 10 is a graph for comparing an access time in a conventional data read-out operation with an access time in a data read-out operation according to an exemplary embodiment of the inventive concept;

12 and 13 Are flowcharts illustrating a method of reading data from a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

14 Fig. 12 is a circuit diagram illustrating a data read circuit which may be included in a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

15 Fig. 10 is a block diagram of a data read circuit which may be included in a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

16A and 16B Block diagrams of non-volatile memory devices are the data-reading circuit of the 15 according to an exemplary embodiment of the inventive concept;

16C is a perspective view of a non-volatile memory cell, which in the 16A and 16B is illustrated according to an exemplary embodiment of the inventive concept;

17 10 is a circuit diagram illustrating a data read-out operation of a non-volatile memory device according to an exemplary embodiment of the inventive concept;

18A FIG. 12 is a block diagram illustrating a sense amplification circuit unit incorporated in FIG 17 according to an exemplary embodiment of the inventive concept is shown;

18B Figure 12 is a table for explaining the output of Multi-Bit Least Significant Bit (LSB) data and Most Significant Bit (MSB) data according to an exemplary embodiment of the inventive concept;

19A and 19B Wiring diagrams are a decode circuit of the 18A illustrate in accordance with exemplary embodiments of the inventive concept;

20 FIG. 12 is a block diagram illustrating a nonvolatile memory device incorporating the data read circuit of FIG 15 according to an exemplary embodiment of the inventive concept;

21 and 22 Block diagrams of non-volatile memory devices having different layouts according to exemplary embodiments of the inventive concept;

23 Fig. 10 is a circuit diagram of a data read circuit which may be included in a non-volatile memory device according to an exemplary embodiment of the inventive concept;

24 FIG. 12 is a block diagram of an electronic system including a nonvolatile memory device according to an exemplary embodiment of the inventive concept; FIG.

25 10 is a block diagram of a single-chip microcomputer having a non-volatile memory device according to an exemplary embodiment of the inventive concept; and

26 FIG. 10 is a block diagram of an information processing system having a nonvolatile memory device / system according to an exemplary embodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the drawings and the description, like reference numbers may refer to like elements.

Examples of nonvolatile memory devices may include phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM) Magnetic Random Access Memory) and a ferroelectric random access memory (FRAM). The nonvolatile memory devices such as the PRAM, the RRAM and the MRAM may have low cost and high capacity features of a dynamic random access memory (DRAM), a static random access memory (SRAM) speed Memory) and have a non-volatile flash memory. For example, a read access time of a Spin Torque Transfer (STT) -MRAM has been reduced to 10 ns or less.

In general, a non-volatile memory device has a read circuit for reading out data from a memory cell, and the read circuit has a sense amplifier for comparing a developed voltage of the memory cell with a reference voltage. In a nonvolatile memory device such as an MRAM, a PRAM, and an RRAM, variations in a resistance value of a cell storing data, a bias current value of a current source, and a bit line resistance component may occur. In addition, since the reference voltage applied from outside is transferred over the entire memory area, a variation in the reference voltage may occur. Deterioration of performance may occur due to such variations.

1 FIG. 10 is a block diagram of a memory system according to an exemplary embodiment of the inventive concept. FIG. As in 1 shown can be a storage system 100 a nonvolatile storage device 1100 and a controller 1200 exhibit. The nonvolatile storage device 1100 may comprise a memory cell array having a plurality of nonvolatile memory cells and a peripheral circuit for performing read-write operations with respect to the memory cell array. The controller 1200 generates a command / address (CMD = Command) for controlling the nonvolatile memory device 1100 and sees write data DATA for the nonvolatile memory device 1100 or retrieves read data DATA from the nonvolatile memory device 1100 ,

The controller 1200 can be a host interface (IF) or a host interface 1210 for coupling to a host and a memory interface (IF) or a memory interface 1230 for coupling to the nonvolatile memory device 1100 exhibit. A control logic unit 1220 to control the overall operation of the controller 1200 can continue in the controller 1200 be included. For example, the control logic unit sees 1120 various control signals for read / write operations with respect to the nonvolatile memory device 1100 to the non-volatile storage device 1100 through the memory IF 1230 according to a command input from the host. A RAM can be inside or outside the control logic unit 1220 such that write data can be preliminarily stored in the RAM in a data write operation, or read data can be preliminarily stored in the RAM in a data read operation.

Names of components disclosed herein represent examples that may be applied to the inventive concept and the nonvolatile memory device 1100 and the controller 1200 could be implemented with separate semiconductor chips or separate semiconductor packages. The nonvolatile storage device 1100 and the controller 1200 may be integrated in a single chip or in a single semiconductor package, and in this case, may be applied to the non-volatile memory device 1100 itself are referred to as a memory system having a memory device and a controller. The storage system 1000 , which is the non-volatile memory device 1100 and the controller 1200 may be implemented with a memory card such as a Secure Digital (SD) card, a Multi Media Card (MMC) or the like.

The 2A . 2 B and 2C FIGs. are diagrams showing an example of the nonvolatile memory device 1100 , what a 1 is shown to illustrate. The 2A Fig. 10 is a block diagram of an MRAM device as an example of the nonvolatile memory device 1100 , the 2 B is a circuit diagram of a unit cell, which in 2A is shown, and 2C FIG. 12 is a cross-sectional view of a structure of a magnetic tunnel junction (MTJ) of the unit cell, which is shown in FIG 2 B is shown.

Referring to the 2A . 2 B and 2C becomes an operation of the nonvolatile memory device 1100 to be discribed. As in 2A 1, the nonvolatile memory device may be shown 1100 a cell arrangement 1110 comprising a plurality of memory cells, a row decoder 1120 for selecting a word line WL of the cell arrangement 1110 , a column decoder 1130 for selecting a bit line BL of the cell array 1110 , a pre-charge circuit unit 1140 for performing a precharge operation with respect to a bit line BL and a sense amplification circuit block 1150 for sampling / amplifying data of a bit line BL of a memory cell 1111 in the cell arrangement 1110 exhibit. The nonvolatile storage device 1100 can be a power generation unit 1160 for generating a current which is provided for a word line WL and / or a bit line BL, and reference voltage generation units 1171 and 1172 for generating different reference voltages VREFH and VREFL for reading and sampling data, respectively. In 2A are a first reference voltage generation unit 1171 for generating a high-level reference voltage VREFH and a second reference voltage generating unit 1172 for generating a low-level reference voltage VREFL as examples.

The cell arrangement 1110 wiest a plurality of memory cells (for example, MRAM cells) 1111 which are formed in intersecting areas between word lines WL and bit lines BL. Each of the memory cells 1111 may comprise a single cell transistor (CT = cell transistor) and a single MTJ.

Both the row decoder 1120 as well as the column decoder 1130 may comprise a plurality of metal oxide semiconductor (MOS) based switches. The row decoder 1120 selects word lines WL in response to row addresses and the column decoder 1130 selects bit lines BL in response to column addresses. The precharge circuit unit 1140 charges the bit lines BL to a predetermined precharge level and thereafter, in data read operations, voltages of the bit lines BL according to a data value stored in the memory cell 1111 stored, developed. The read-amplification circuit block 1150 has a plurality of sense amplifying circuits for the bit lines BL, and samples and amplifies the developed voltages of the bit lines BLab.

The electricity which is in the power generation unit 1160 is provided for the bit lines BL as a constant value. The voltage level of the bit lines BL may be a level based on a current value stored in the power generation unit 1160 is generated and a data value stored in the memory cell 1111 is stored. For example, the MTJ has the memory cell 1111 according to a written data value, a high resistance value or a low resistance value, and a voltage of a different level according to a change in the resistance value is for the sense-amplification circuit block 1150 provided as a data voltage.

According to an exemplary embodiment of the inventive concept, at least two reference voltages VREFL and VREFH are for the sense-amplification circuit block 1150 intended. Although the first reference voltage VREFH and the second reference voltage VREFL are respectively in the first reference voltage generation unit 1171 and the second reference voltage generation unit 1172 the nonvolatile memory device 1100 in 2A can be generated, the first reference voltage VREFH and the second reference voltage VREFL also by the controller 1200 (in 1 ) and for the non-volatile memory device 1100 be provided. The read-amplification circuit block 1150 has a plurality of sense amplifying circuits corresponding to the bit lines BL, and each of these read amplifying circuits receives the data voltage and the first and second reference voltages VREFH and VREFL through an input terminal.

The sense amplifying circuit generates a differential output signal (hereinafter also referred to as "differential output signals") according to a voltage level difference between the data voltage and the first and second reference voltages VREFH and VREFL. In other words, the read amplification circuit generates the differential output signal by differentially amplifying the data voltage input as a single signal. The differential output signal may be generated using at least one capacitor for storing voltages corresponding to the voltage level difference between the data voltage and the first and second reference voltages VREFH and VREFL, and for this purpose, the sense-amplification circuit an integrating circuit for integrating voltages using the at least one capacitor. Read data is generated by sampling / amplifying the differential output signal at a predetermined timing. The detailed operation of the sense-amplification circuit block 1150 will be described later.

2 B is a circuit diagram showing a unit cell which is in 2A is shown, illustrated, and as in 2 B is shown, the memory cell 1111 have an MTJ and a CT. A gate of the CT is connected to a word line (eg, a first word line WL0), and an electrode of the CT is connected to a bit line (eg, a first bit line BL0) through the MTJ. Another electrode of the CT is connected to a source line (eg a first source line SL0). A current for writing data may be supplied in a direction from a bit line to a source line or in a direction from a source line to a bit line. According to a direction in which power is supplied, the direction of a vector which is in the MTJ is determined, and in a subsequent data read operation, a resistance value formed in the MTJ varies according to the predetermined direction of the vector.

2C FIG. 12 is a cross-sectional view of the structure of the MTJ of the unit cell, which is shown in FIG 2 B is shown. As in 2C is shown, the MTJ can be a fixed layer 1111_1 , a free shift 1111_2 and a tunnel layer 1111_3 which is arranged therebetween. The MTJ may further comprise a first electrode E1 which defines the fixed layer 1111_1 contacted and having a second electrode E2, which is the free layer 1111_2 contacted. Although in 2C not shown, an antiferromagnetic layer may further be provided, for example, between the first electrode E1 and the fixed layer 1111_1 to the magnetization direction of the solid layer 1111_1 to fix.

The magnetization direction of the solid layer 1111_1 is fixed and the magnetization layer of the free layer 1111_2 may be the same as or opposite to the magnetization direction of the solid layer 1111_1 , Write currents WC1 and WC2 can be applied between the first electrode E1 and the second electrode E2, and the magnetization direction of the free layer 1111_2 is determined according to the directions of the write currents WC1 and WC2. For example, in an application or an application of the write current WC1 from the second electrode E2 to the first electrode E1, the free layer 1111_2 be magnetized in the same direction of magnetization as the solid layer 1111_1 ,

The resistance value of the MTJ varies according to the magnetization direction of the free layer 1111_2 , For example, when the magnetization direction of the free layer 1111_2 the same is like that of the solid layer 1111_1 , the resistance value of the MTJ low, which may correspond to a storage of a date "0". On the other hand, when the magnetization direction of the free layer 1111_2 opposite to that of the solid layer 1111_1 is, the resistance value of the MTJ high, which may correspond to a storage of a date "1".

3 is a circuit diagram showing a data-reading circuit 1300 which may be included in a nonvolatile memory device according to an exemplary embodiment of the inventive concept. The data read circuit 1300 may comprise circuits arranged on a read path for intervening in a data read operation. The data read circuit 1300 can at least some of the components or components which in 2A are shown, or other ingredients which are shown in 2A not shown, have. Although the data-reading circuit 1300 for reading data from individual memory cells 1111 in 3 5, a plurality of data read circuits may be used to read out data from the plurality of memory cells in parallel 1111 in the nonvolatile memory device 1100 be provided.

With reference to the 1 and 3 Be a detailed structure and operation of the data-reading circuit 1300 to be discribed.

As in 3 shown, the data read circuit 1300 a precharge circuit 1141 , which is connected to a bit line, for precharging the bit line to a predetermined level, a bit line selection circuit 1131 for selecting a bit line, a clamping circuit 1191 for clamping or clamping a bit line, a current source 1161 for providing a current for a bit line and a sense amplification circuit 1151 for receiving a data voltage VSA and at least two reference voltages VREFH and VREFL and performing a sample / amplify operation in response thereto. A resistor Rb1, which in 3 2, indicates a resistance component resulting from a bit line and an output VOUT of the sense-amplification circuit 1151 is latched by a latch circuit and provided as read data to the outside.

The precharge circuit 1141 may be arranged to match each bit line, and may be in the precharge circuit unit 1140 , what a 2A is shown to be included. The bit line selection circuit 1131 is a circuit which is turned on / off in response to a decode result of a column address, and may be in the column decoder 1130 which is in 2A is shown to be included. The clamping circuit 1191 may also be arranged to correspond to each bit line and the sense-amplification circuit 1151 is provided to sample and amplify the data voltage VSA of each bit line, and may be included in the read amplification circuit block 1150 which is in 2A is shown to be included. The power source 1161 can in the power generation unit 1160 , what a 2A shown, or the current, which is in the power generation unit 1160 may be generally provided for a plurality of bit lines.

According to an exemplary embodiment of the inventive concept, the nonvolatile memory device performs 1100 if they have the data in the memory cell 1111 are stored, read, sample / amplify operations using the at least two reference voltages VREFH and VREFL. The nonvolatile storage device 1100 Also performs an integrating operation according to a voltage level difference between the data voltage VSA and the at least two reference voltages VREFH and VREFL, and generates a differential output obtained by differentially amplifying the data voltage VSA based on the integrating operation. The nonvolatile storage device 1100 also generates the output VOUT by performing sample / amplify operations on the differential output. For this purpose, the read amplification circuit 1151 a first sense amplifier for generating the differential output signal in response to the data voltage VSA and a second sense amplifier for generating the output VOUT by sampling / amplifying the differential output signal. The first sense amplifier may be implemented with an integrating circuit which performs a differential amplification operation on the input signals representing the data voltages VSA and which have at least two reference voltages VREFH and VREFL.

The detailed operation of the data read circuit 1300 which is in 3 will now be described. It is assumed that the at least two reference voltages VREFH and VREFL are the first and second reference voltages VREFH and VREFL.

A bit line connected to the memory cell 1111 is precharged to a certain level and then the bit line selection circuit 1131 selected to get data from the memory cell 1111 read. A predetermined voltage is for a gate of the clamping circuit 1191 provided, and the power source 1161 sees a current having a predetermined level for a first input terminal (eg, an input terminal for receiving the data voltage VSA) of the sense-amplifying circuit 1151 in front. The MTJ of the memory cell 1111 has a resistance which varies according to stored data and the data voltage VSA of the first input terminal of the read-amplification circuit 1151 is developed according to the resistance value of the MTJ.

A second and a third terminal of the sense-amplification circuit 1151 receive the first and second reference voltages VREFH and VREFL. As mentioned above, the first and second reference voltages VREFH and VREFL in the nonvolatile memory device 1100 may be generated using a predetermined power voltage provided from the outside, or may be provided directly from the outside.

In the read amplification circuit 1151 the level of the data voltage VSA is compared with the level of the first reference voltage VREFH and the level of the second reference voltage VREFL, and a differential output signal is generated by performing an integrating operation according to a voltage level difference. By sampling and amplifying the differential output signal at a particular time during the generation of the differential output signal, the output VOUT is generated. The first and second reference voltages VREFH and VREFL may have certain voltage levels, and when the data voltage VSA is developed, the voltage level difference between the data voltage VSA and the first and second reference voltages VREFH and VREFL occurs.

4 FIG. 10 is a block diagram of a nonvolatile memory device according to an exemplary embodiment of the inventive concept. FIG. 5 FIG. 12 is a circuit diagram of a data read circuit of the nonvolatile memory device incorporated in FIG 4 is shown, according to an exemplary embodiment of the inventive concept. When a structure and an operation of the non-volatile memory device incorporated in the 4 and 5 are shown, the same components as those used in the 2A . 2 B and 2C are not described in detail.

As in 4 shows the non-volatile memory device 1100 the cell arrangement 1110 for storing data, the row decoder 1120 for selecting a word line WL and the column decoder 1130 for selecting a bit line BL. The nonvolatile storage device 1100 may further the precharge circuit unit 1140 for precharging a bit line BL to a predetermined level, the read amplification circuit 1150 for sampling / amplifying data of a bit line BL of a memory cell 1111 in the cell arrangement 1110 and the power generation unit 1160 for generating a current which is provided for a word line WL and / or a bit line BL. The cell arrangement 1110 has a plurality of memory cells (for example MRAM cells) 1111 to store data on.

The nonvolatile storage device 1100 , what a 4 3, generates reference voltages for reading out data (eg, the first and second reference voltages VREFH and VREFL) from the MRAM cell 1111 , For this purpose, the nonvolatile memory device 1100 continue a reference cell array 1180 comprising a plurality of reference cells for providing the first and second reference voltages VREFH and VREFL. The memory cell 1111 the cell arrangement 1110 for storing data and a reference cell of the reference cell array 1180 can have the same cell structure.

In reference cells 1181 and 1182 the reference cell arrangement 1180 For example, data corresponding to a logical "high" or a logical "low" may be stored. For example, logical high data may be in a cell (for example, first cell 1181 ) of the reference cell array 1180 and low logical data can be written to another cell (for example, second cell 1182 ) of the reference cell array 1180 to be written. In the reference cell arrangement 1180 can pairs the first reference cell 1181 and the second reference cell 1182 may be included so that they correspond to at least some of the word lines WL, or there may be pairs of the first reference cell 1181 and the second reference cell 1182 be included so that they correspond to each word line WL. Thus, in a data read-out operation regarding the cell arrangement 1110 Information which in or on the first reference cell 1181 and the second reference cell 1182 the reference cell arrangement 1180 are written, also read out.

A data write operation on the first and second reference cells 1181 and 1182 during a data-write operation with respect to the memory cell 1111 be performed. The data write operation on the first and second reference cells 1181 and 1182 can be performed once initially and by a repeated reading of the first and second reference cell 1181 and 1182 on which the data-write operation is performed once, the first and second reference voltages VREFH and VREFL can be obtained. When a word line WL of the cell array 1110 can also be selected, the first and second reference cell 1181 and 1182 be selected such that in a data write operation with respect to the selected word line WL of the cell array 1110 the selected first and second reference cells 1181 and 1182 can also be written or described. In other words, the data-writing operation with respect to the first and second reference cells 1181 and 1182 be repeated on each data update. In the case of a memory such as an MRAM, a data value (eg, a resistance value of an MTJ) which may be in the memory cell 1111 or the first and second reference cells 1181 and 1182 is stored, change over time. As a result, a data rewrite operation on the memory cell 1111 according to a predetermined period of time and during the data rewriting operation with respect to the memory cell 1111 may also perform a data rewrite operation on the first and second reference cells 1181 and 1182 be performed.

Bit lines BL are additionally arranged so that they match the reference cell arrangement 1180 and a precharge operation and a select operation with respect to these bit lines BL become identical or similar to the bit lines BL according to the cell arrangement 1110 , which stores data, performed. In the data readout operation, the column decoder selects 1130 Bit lines BL, which with the first reference cell 1181 and the second reference cell 1182 are connected. Voltages of the bit lines BL connected to the first reference cell 1181 and the second reference cell 1182 are developed and the voltages developed are used for the sense-amplification circuit block 1150 are each provided as the first reference voltage VREFH and the second reference voltage VREFL. The read-amplification circuit block 1150 has a plurality of sense amplifying circuits, each of which receives the first and second reference voltages VREFH and VREFL together with the data voltage VSA corresponding thereto.

One of logical high data and logical low data is in the memory cell 1111 saved. The first reference cell 1181 stores logical high data and the second reference cell 11182 stores logical low data. According to the data stored in the memory cell 1111 are stored, the data voltage VSA has approximately the same level as one of the first reference voltage VREFH and the second reference voltage VREFL, and has a level different from the other thereof. When a differential amplification operation is performed according to a voltage level difference between the data voltage VSA and the first and second reference voltages VREFH and VREFL, for example, when high logic data is in the memory cell 1111 are stored, a differential output signal corresponding largely to a voltage level difference between the data voltage VSA and the second reference voltage VREFL is generated.

A structure and operation of the data read circuit 1300 which is in 5 will now be described. The data read circuit 1300 may comprise a sense (VSA) path circuit for generating the data voltage VSA in accordance with data stored in the memory cell 1111 and a second reference (VREFL) path circuit for generating the second reference voltage VREFL. The first reference (VREFH) path circuit and the second reference (VREFL) path circuit may have the same circuits as those included in the sense (VSA) path circuit. For example, as in 5 1, the first reference (VREFH) path circuit is a precharge circuit 1142 , a bit line selection circuit 1132 , a clamping circuit 1192 and a power source 1162 which, with the first reference cell 1181 and the second reference (VREFL) path circuit may be a precharge circuit 1143 , a bit line selection circuit 1133 , a clamping circuit 1193 and a power source 1163 which, with the second reference cell 1182 are connected. While power sources 1161 to 1163 When different power sources are shown, power may be from a common power source which is one of these power sources 1161 to 1163 is to be used.

The data voltage VSA is for a first one Input terminal of the sense-amplification circuit 1151 by a bit line (eg, a first bit line) connected to the memory cell 1111 is connected, provided. The first and second reference voltages VREFH and VREFL are for a second and a third input terminal of the sense-amplification circuit 1151 via bitlines (eg, first and second reference bitlines) provided with the first and second reference cells 1181 and 1182 are connected. The read-amplification circuit 1151 generates the output VOUT based on the integrate and sample / amplify operations described above.

According to the structure which in 5 is a pair of first and second reference cells 1181 and 1182 arranged to be with a plurality of memory cells 1111 the cell arrangement 1110 and therefore a territorial disadvantage is not large. For example, multiple memory cells 1111 and the first and second reference cells 1181 and 1182 be arranged to correspond to a single word line, and a plurality of read-amplification circuits 1151 for sampling data of the memory cells 1111 may commonly use the first and second reference voltages VREFH and VREFL, which are respectively in the first and second reference cells 1181 and 1182 be generated.

6 FIG. 10 is a block diagram of a sense amplification circuit included in a data read circuit according to an exemplary embodiment of the inventive concept. FIG.

As in 6 is shown, the sense amplification circuit 1151 may be arranged to correspond to each of a plurality of bit lines, and may include a first sense amplifier 2100 and a second sense amplifier 2200 exhibit. A delay unit 2300 for controlling an activation time or an activation time of the first sense amplifier 2100 and / or the second sense amplifier 2200 can continue in the read amplification circuit 1151 be included. The first sense amplifier 2100 receives the data voltage VSA and the first and second reference voltages VREFH and VREFL and generates differential output signals VOUT and VOUTb which are developed according to a voltage level difference between the data voltage VSA and the at least two reference voltages VREFH and VREFL.

For example, when the first and second reference voltages VREFH and VREFL are designated by reference cells as in FIG 4 which produces differential output signals VOUT and VOUTb according to a voltage level difference between the data voltage VSA and mainly one of the first and second reference voltages VREFH and VREFL. The second sense amplifier 2200 samples / amplifies the differential output signals VOUT and VOUTb and outputs the sampled / amplified signals. Although output terminals of the first and second sense amplifiers 2100 and 2200 are shared and the input terminal and the output terminal of the second sense amplifier 2200 in each other 6 coupled, the exemplary embodiment of the inventive concept is not limited thereto. For example, the second sense amplifier 2200 output the sampled and amplified signals of the differential output signals VOUT and VOUTb through another output terminal.

A control signal Ctrl for activating the first sense amplifier 2100 is for the first sense amplifier 2100 provided and the control signal Ctrl is for the second sense amplifier 2200 about the delay unit 2300 intended. Thus, the second sense amplifier becomes 2200 activated after a predetermined delay. After the differential output signals VOUT and VOUTb according to the differential amplification operation of the first sense amplifier 2100 are developed, and the second sense amplifier 2200 is activated after the predetermined delay, the differential output signals VOUT and VOUTb by the second sense amplifier 2200 sensed / amplified. In this way, by sampling / amplifying sufficiently developed differential output signals VOUT and VOUTb, the accuracy of the data read out can be improved. Moreover, by latching the amplified differential output signals VOUT and VOUTb at a predetermined time, a read data signal having a full digital voltage level can be generated.

The 7 and 8th are schematic diagrams showing the sense-amplification circuit 1151 which is in 6 is shown in accordance with an exemplary embodiment of the inventive concept. 7 is a circuit diagram showing the sense-amplification circuit 1151 which is in 6 is shown, illustrated, and 8th has circuit diagrams (a) and (b), each of which the first sense amplifier 2100 and the second sense amplifier 2200 of the 7 show which are separated from each other. Referring to the 7 and 8th become a structure and an operation of the read-amplification circuit 1151 to be discribed.

The read-amplification circuit 1151 can be the first sense amplifier 2100 , the second sense amplifier 2200 and the delay unit 2300 exhibit. The first sense amplifier 2100 can be a first input unit 2110 for receiving a data voltage VSA, which corresponds to a data value stored in a memory cell, a second input unit 2120 for receiving the first and second reference voltages VREFH and VREFL and a bias unit 2130 (biasing unit) around the first sense amplifier 2100 under pretension. The first sense amplifier 2100 can be one or more capacitors or capacities 2141 and 2142 for storing the differential amplification signal based on differences between the data voltage signal VSA and the first and second reference voltages VREFH and VREFL, and a precharge unit 2150 for precharging a differential output terminal (also referred to hereinafter as differential output terminals) to a predetermined level.

The first input unit 2110 has a plurality of input terminals for receiving the data voltage VSA. For example, the first input unit 2110 two metal oxide semiconductor (MOS) transistors of a layered structure, and the data voltage VSA is provided for gates of the two MOS transistors. The second input unit 2120 has a plurality of input terminals for receiving the first and second reference voltages VREFH and VREFL, and, for example, the second input unit 2120 also two MOS transistors of a layered structure. The first reference voltage VREFH and the second reference voltage VREFL are respectively for gates of the two MOS transistors of the second input unit 2120 intended. The first capacitor 2141 is with the first input unit 2110 connected via a first differential output terminal, and the second capacitor 2142 is with the second input terminal 2120 connected via a second differential output terminal.

Before a data read operation, the precharge unit becomes 2150 of the first sense amplifier 2100 in response to the control signal Ctrl, and the differential output terminal (eg, the first and second differential output terminals) of the first sense amplifier 2100 is precharged to a predetermined precharge voltage. Thereafter, according to a voltage level difference between the data voltage VSA, which changes for the first input unit 2010 is provided and that of the first and the second reference voltage VREFH and VREFL, which for the second input unit 2120 are provided, a value of a current passing through the differential output terminal, and accordingly, a level of a voltage applied to the differential output terminal also changes. The changed voltage is in the first capacitor 2141 and the second capacitor 2142 saved.

For example, when the first and second reference voltages VREFH and VREFL are generated from a reference cell array and a data of a memory cell has a logical high value, the data voltage VSA and the first reference voltage VREFH have substantially the same level, and accordingly, an integrating operation is performed mainly based on a voltage level difference between the data voltage VSA and the second reference voltage VREFL. As a result of the integrating operation, a voltage difference between the differential output signals VOUT and VOUTb gradually increases.

The second sense amplifier 2200 is activated after a predetermined delay, starting from when the pre-charging unit 2150 of the first sense amplifier 2100 is activated. For example, the control signal Ctrl, which is for the precharge unit, occurs 2150 is provided by the delay unit 2300 through and is for a bias unit 2220 of the second sense amplifier 2220 intended. In other words, at time for the integrating operation of the first sense amplifier 2100 ensure an activation time for the second sense amplifier 2200 is adjusted (or a sampling timing for the differential output signals VOUT and VOUTb is adjusted). When the differential output signals VOUT and VOUTb, which outputs the first sense amplifier 2100 are sufficiently developed, becomes the second sense amplifier 2200 activated and the second sense amplifier 2200 samples / amplifies the differential output signals VOUT and VOUTb, generating the amplified differential output signals VOUT and VOUTb. The amplified differential output signals VOUT and VOUTb may be at a time after the sampling operation using the latch 2210 be latched and the latched signals can be provided as read data to the outside.

While in 8th the delay unit 2300 is implemented using a plurality of inverters, and a sampling time is adjusted by delaying the control signal Ctrl representing the precharge unit 2150 of the first sense amplifier 2100 controls, the exemplary embodiment of the inventive concept is not necessarily limited thereto. For example, the pre-charging unit 2150 of the first sense amplifier 2100 and the bias unit 2220 of the second sense amplifier 2200 be controlled by different control signals, and if the activation times for these control signals are adjusted, the delay unit 2300 not needed. Furthermore, the delay unit 2300 can be constructed from other forms of time delay circuits. In the case that the first sense amplifier 2100 and the second sense amplifier 2200 to sample / amplify an input signal, For example, their voltage gains may be determined according to characteristics of elements such as MOS transistors included in the first and second sense amplifiers 2100 and 2200 are changed. By adjusting a voltage gain for a gain operation, output waveforms of the first and second sense amplifiers 2100 and 2200 be changed.

The 9A . 9B . 10A and 10B are graphs which show input / output waveforms of the sense-amplification circuit 1151 which is in 6 according to an exemplary embodiment of the inventive concept, show. The 9A and 9B FIG. 4 are graphs for a case when the first and second reference voltages VREFH and VREFL are generated from a reference cell array such as that shown in FIG 4 is shown, and the 10A and 10B are graphs for a case when the first and second reference voltages VREFH and VREFL of reference voltage generating units such as those shown in FIG 2A are shown generated. Referring to the 7 to 10B becomes an operation of the read-amplification circuit 1151 to be discribed. It is assumed that a logical high date is stored in a memory cell.

As in the 9A and 9B 2, hold the differential output signals VOUT and VOUTb of the first sense amplifier 2100 a precharge level keeps Vprech ahead of a developmental stage. In a selection of a memory cell for a data read-out operation, the data voltage VSA of a bit line connected to the memory cell is developed. When a first reference cell and a second reference cell are selected together with the selection of the memory cell, the first reference voltage VREFH and the second reference voltage VREFL are developed. The data voltage VSA has substantially the same value as the first reference voltage VREFH.

In accordance with a change in the voltage level difference between the data voltage VSA and the second reference voltage VREFL, the differential output signals VOUT and VOUTb are developed, and after a predetermined delay, a sampling operation is performed. The sampling operation may be accomplished by activating the second sense amplifier 2200 and the sampling operation amplifies the differential output signals VOUT and VOUTb to a fully digital level. The amplified differential output signals VOUT and VOUTb are latched at a predetermined time after the sampling operation, and the latched information is provided as read data to the outside.

As in the 10A and 10B 2, the first reference voltage VREFH and the second reference voltage VREFL, which are generated by reference voltage generating units, have constant voltage levels. When a memory cell for a data read-out operation is selected, the data voltage VSA of a bit line connected to the memory cell is developed, and the level of the data voltage VSA gradually increases, such that at a predetermined time the level of the data voltage VSA exceeds the level of the first reference voltage VREFH.

The differential output signals VOUT and VOUTb of the first sense amplifier 2100 maintain the precharge level Vprech before a stage of development and are developed as the data voltage VSA changes. A sampling operation is performed after a predetermined delay from the development of the differential output signals VOUT and VOUTb. The sampling operation may be performed within a predetermined time from when the data voltage VSA has the same level as the first reference voltage VREFH. By the sampling operation, the differential output signals VOUT and VOUTb are amplified to a full digital level, and the amplified differential output signals VOUT and VOUTb are latched at a predetermined time after the sampling operation. The latched information is provided as read-out data to the outside.

11A FIG. 12 is a graph comparing a data signal waveform of a conventional data read circuit with a data signal waveform of a data read circuit according to an exemplary embodiment of the inventive concept; and FIG 11B FIG. 10 is a graph for comparing an access time in a conventional data read-out operation with an access time in a data read-out operation according to an exemplary embodiment of the inventive concept. FIG.

As in 11A 5, in a sense amplification circuit according to an exemplary embodiment of the inventive concept, since a differential output stored in an integrating capacitor is directly provided as an input of a sense amplifier for sample / amplification operations, the differential output is amplified by a strong gain, and thus it can be immediately developed to a full digital level. Consequently, by applying an exemplary embodiment of the inventive concept, a development speed and a capability for full digital voltage recovery are superior to a conventionally designed data read circuit.

An access time in a conventional case and an access time regarding an exemplary embodiment of the inventive concept are shown in FIG 11B shown. The access time can be defined as a time from when a sense amplifier is activated until then, when a developed voltage difference 100 reached mV. As the number of cells per bit line increases, the access time as a whole also increases. However, according to an exemplary embodiment of the inventive concept, the access time may be reduced to 2 ns or less in total.

The 12 and 13 13 are flowcharts illustrating a method of reading data from a nonvolatile memory device according to an exemplary embodiment of the inventive concept.

According to the method, a data voltage originating from a memory cell and at least two reference voltages are provided for a read-amplification circuit. The sense amplifier circuit may include a first sense amplifier for differentially amplifying voltage level differences between the data voltage and the first and second reference voltages, and a second sense amplifier for receiving and sampling / amplifying an output of the first sense amplifier. The first sense amplifier may be implemented with an integrating circuit for generating a differential output signal corresponding to the data voltage and outputting the differential output signal through a differential output terminal. The second sense amplifier may be implemented with an amplifier circuit for receiving the differential output signal through the differential output terminal, amplifying the received differential output signal, and outputting the amplified signal through the differential output terminal.

By providing a predetermined control signal for the first sense amplifier, the first sense amplifier is activated in operation S11. The first sense amplifier may include a precharge unit for precharging the differential output terminal to a predetermined level, and the predetermined control signal may be a precharge control signal for activating the precharge unit. In operation S12, a memory cell is selected according to a result of decoding an address provided from the outside. A data voltage corresponding to data stored in the selected memory cell is generated, and the first reference voltage and the second reference voltage are generated to read the data stored in the memory cell in operation S13. The first reference voltage and the second reference voltage may be generated by reference voltage generation units that generate predetermined DC voltage values as in the previous embodiments, or they may be voltages developed by reference cells including logic high information and logic Save -low information.

The first sense amplifier receives the data voltage and the first and second reference voltages and amplifies a voltage level difference between the data voltage and the first and second reference voltages, thereby generating differential output signals in an operation S14. The first sense amplifier may each have two input terminals for generally receiving the data voltage and two input terminals for receiving the first reference voltage and the second reference voltage. The first sense amplifier may be implemented with an integrating circuit for performing an integrating operation by using one or more capacitors, and stores a voltage corresponding to the integrating operation in the one or more capacitors. A voltage level stored in each of the one or more capacitors changes according to a voltage level difference between the data voltage and the first and second reference voltages, and for example, when the first and second capacitors include in the first sense amplifier are generated, a voltage at a node of the first capacitor and a voltage at a node of the second capacitor as differential output signals.

After a predetermined delay, the second sense amplifier is activated in an operation S15. The delay can be adjusted by a delay means such as an inverter chain. The delay time may be a time from when the first sense amplifier is activated (or a precharge unit of the first sense amplifier is activated) to when a bias voltage is applied to the second sense amplifier. In this case, a signal obtained by delaying the precharge control signal may be used as a control signal for controlling the bias of the second sense amplifier.

The second sense amplifier is connected to a differential output terminal of the first sense amplifier to receive the differential output signal. At the time when the second sense amplifier is activated, the differential output signal is sampled and the amplified differential output signal is read as read data in an operation S16 generated. The output terminal of the second sense amplifier may be generally connected to the differential output terminal of the first sense amplifier so that the read-out data may be output through the differential output terminal.

13 FIG. 10 is a flow chart illustrating detailed operations of the first sense amplifier and the second sense amplifier. FIG. As in 13 2, a precharge operation is performed on the first sense amplifier according to the precharge control signal in operation S21. The precharge operation may be performed by precharging a level of the differential output terminal to a predetermined level.

By providing the data voltage and the first and second reference voltages to the first sense amplifier, an operation of integrating a voltage level difference between the data voltage and the first and second reference voltages is performed in an operation S22. When the first and second reference voltages of reference cells are generated, a level of one of the first and second reference voltages has approximately the same value as the level of the data voltage, and a level of the other reference voltage has a value different from the level of the data voltage. For example, when a logic high data is stored in a memory cell, the data voltage has approximately the same level as the level of the first reference voltage such that a voltage level difference between the data voltage and the second reference voltage is largely integrated. The first sense amplifier generates a differential output corresponding to the integration operation in operation S23.

After a predetermined delay from when the precharge is performed, the second sense amplifier is activated in an operation S24. The second sense amplifier receives the differential output signal from the first sense amplifier and samples and amplifies the differential output signal after the predetermined delay, thereby producing the amplified differential output signal in an operation S25. At a predetermined timing from the start of the amplifying operation, the amplified differential output is latched in an operation S26 and the latched differential output is output as read data in an operation S27.

14 FIG. 12 is a circuit diagram illustrating a data read circuit that may be included in a nonvolatile memory device according to an exemplary embodiment of the inventive concept. As in 14 can be shown, a data reading circuit 3,100 be arranged to each of a plurality of bit lines, which in the non-volatile memory device 1100 are included.

The data reading circuit 3,100 can use various circuits to read data from a memory cell 3110 for example, a precharge circuit 3130 which is connected to a bit line to precharge the bit line to a predetermined level, a bit line selection circuit 3120 for selecting a bit line, a clamping circuit 3140 for clamping a bit line and a current source 3150 for providing a current for a bit line. In 14 is the memory cell 3110 an MRAM cell having an MTJ, which is an example.

The data reading circuit 3,100 may be a first read amplification circuit 3160 for performing sampling / amplification operations based on an integrating operation using a plurality of reference voltages according to an exemplary embodiment of the inventive concept and a second read-amplifying circuit 3170 for performing general sample / amplify operations. The data reading circuit 3,100 can continue a first control circuit 3161 for controlling a selection of the first read amplification circuit 3160 in response to a first control signal Ctrl11 and a second control circuit 3171 for controlling the selection of the second read amplification circuit 3170 in response to a second control signal Ctrl12, such that the data read circuit 3,100 optionally the first read amplification circuit 3160 and the second read-amplification circuit 3170 operates.

The first control circuit 3161 and the second control circuit 3171 may be implemented with MOS transistors which receive the first control signal Ctrl11 and the second control signal Ctrl12 respectively through gate electrodes. A first and a second electrode of the first control circuit 3161 are each connected to an input terminal of the first sense amplifying circuit 3160 (For example, a first input terminal, which receives the data voltage VSA) and an output terminal of the first sense-amplifying circuit 3160 connected. A first and a second electrode of the second control circuit 3171 are each connected to an input terminal of the second read-amplification circuit 3170 (For example, a first input terminal, which has an output VOUT1 of the first control circuit 3161 receives) and an output terminal of the second read amplification circuit 3170 connected. The first read amplification circuit 3160 receives the first and second reference voltages VREFH and VREFL through second and third input terminals, respectively. The first and second reference voltages VREFH and VREFL may be DC voltages that are present in the nonvolatile memory device 1100 are generated by using a voltage provided from outside, or DC voltages provided directly from the outside, as mentioned above. The first and second reference voltages VREFH and VREFL may be voltages developed by reference cells storing logic high information or logic low information.

The second read-amplification circuit 3170 receives a reference voltage VREF through a second input terminal. The reference voltage VREF may be a DC voltage used in the nonvolatile memory device 1100 is generated, or is provided directly from the outside. The reference voltage VREF may have a level approximately corresponding to an average value between the first reference voltage VREFH and the second reference voltage VREFL.

As in 14 is shown, the data reading circuit 3,100 the first read amplification circuit 3160 based on an integrating circuit which uses two reference voltages VREFH and VREFL, as well as the second read-amplifying circuit 3170 which performs an amplification operation using the single reference voltage VREF. In a test mode of the nonvolatile memory device 1100 may be the first control signal Ctrl11 and the second control signal Ctrl12 for the first read-amplifying circuit 3160 and the second read-amplification circuit 3170 be provided such that characteristics of output waveforms, which using the first read-amplifying circuit 3160 and the second read-amplification circuit 3170 can be determined. When the second sense-amplifying circuit 3170 is selected, the data voltage VSA from the bit line BL passes through the first control circuit 3161 and is for the first input terminal of the second read amplification circuit 3170 intended. The second read-amplification circuit 3170 compares the data voltage VSA with the reference voltage VREF and outputs a gain signal VOUT2 according to this comparison result.

On the other hand, when the first read amplification circuit 3160 is selected, the data voltage VSA for the first input terminal of the first read-amplifying circuit 3160 and as mentioned in the foregoing embodiments, an integrating operation is performed in accordance with a voltage level difference between the data voltage VSA and the first and second reference voltages VREFH and VREFL, and a differential output signal corresponding to an integration result is generated. Thereafter, at a predetermined timing, the differential output signal is sampled / amplified such that a gain signal VOUT1 from the first read amplification circuit 3160 is issued. The output terminal of the first sense amplification circuit 3160 can through the second control circuit 3171 electrically to the output terminal of the second read amplification circuit 3170 be connected.

In the test mode, a waveform of a data signal may be analyzed using the gain signals VOUT1 and VOUT2 derived from the first and second read amplification circuits 3160 and 3170 be issued. By referring to a result of this analysis, one of the first read amplification circuit 3160 and the second read-amplification circuit 3170 be set so that they are in a normal operation of the non-volatile memory device 1100 be used. For example, when the gain signal VOUT2, which is from the second read amplification circuit 3170 is spent more time to reach a fully digital level, the first read amplification circuit 3160 chosen so that it is in the normal operation of the non-volatile memory device 1100 is activated. The nonvolatile storage device 1100 may comprise a mode register set (MRS) which stores MRS code for setting an operation mode such that the first control circuit 3161 and the second control circuit 3171 by an MRS code in an initial operation of the nonvolatile memory device 1100 can be controlled.

15 FIG. 12 is a block diagram of a data read circuit that may be included in a nonvolatile memory device according to an example embodiment of the inventive concept. For the sake of simplicity, of the components described above, only one read amplification circuit is shown in the data read circuit.

A data reading circuit 4300 for reading out data from a unit cell storing data of two bits or more is in 15 shown. For example, the nonvolatile memory device 1100 Two-bit data per Store memory cell (or per unit cell). By using a multi-level cell (MC = Mulit-Level Cell), a unit cell for storing single two-bit data can be implemented, or by using two single-level cells, a unit cell for storing two-bit Data are implemented.

When two-bit data is stored in a unit cell, the data voltage VSA supplied through a bit line connected to the unit cell has one of four level states. A plurality of reference voltages are used to read data stored in such a unit cell and, for example, four reference voltages VREFH, VREFL, VREFHM and VREFLM may be used. Similar to the previous embodiments, these reference voltages VREFH, VREFL, VREFHM and VREFLM may be generated by reference cells respectively storing the four data states. The reference voltages VREFH, VREFL, VREFHM and VREFLM may be used in the nonvolatile memory device 1100 may be generated by using a voltage provided from outside, or they may be DC voltages provided directly from outside.

The data reading circuit 4300 may be a first read amplification circuit 4310 and a second read-amplification circuit 4320 which correspond to a bit line. The first read amplification circuit 4310 and the second read-amplification circuit 4320 receive a data voltage VSA and at least two reference voltages each. For example, when storing two-bit data in a unit cell, four reference voltages may be generated, the first sense-amplifying circuit 4310 may receive the first and fourth reference voltages VREFH and VREFL, and the second sense-amplifying circuit 4320 may receive the second and third reference voltages VREFHM and VREFLM.

Each of the first and second sense amplifying circuits 4310 and 4320 amplifies differentially input voltages and performs sampling / amplification operations on differential output signals as described in the previous embodiments. The first read amplification circuit 4310 integrates a voltage level difference between the data voltage VSA and the first and fourth reference voltages VREFH and VREFL to produce differential output signals, and samples / amplifies the differential output signals at a predetermined time, thereby producing amplified differential output signals VOUT1 and VOUT1b generated. Similarly, the second sense amplification circuit integrates 4320 a voltage level difference between the data voltage VSA and the second and third reference voltages VREFHM and VREFLM to produce differential output signals and samples / amplifies the differential output signals at a predetermined time, thereby producing amplified differential output signals VOUT2 and VOUT2b. The data reading circuit 4300 can continue a decode circuit 4330 for receiving the amplified differential output signals VOUT1, VOUT1b, VOUT2 and VOUT2b.

The decode circuit 4330 decodes the amplified differential output signals VOUT1, VOUT1b, VOUT2 and VOUT2b to generate a data signal Data. The level of the data voltage VSA has a different value according to data stored in a unit cell, and the amplified differential output signals VOUT1, VOUT1b, VOUT2 and VOUT2b based on the integrating and sampling / amplifying operations which represent the data voltage VSA can also have different levels. The decode circuit 4330 analyzes the amplified differential output signals VOUT1, VOUT1b, VOUT2 and VOUT2b to generate the two-bit data signal Data.

During an exemplary embodiment for reading two-bit data for a unit cell and an exemplary embodiment with the two sense amplifying circuits 4310 and 4320 per unit cell in 15 are shown, the inventive concept is not limited thereto. For example, to improve the accuracy of the decoding operation, three or more read-amplification circuits may be arranged for a one-time cell. In this case, by properly combining the four reference voltages VREFH, VREFL, VREFHM, VREFLM, different dual reference voltages may be provided for different sense amplifying circuits. For example, in the case where four sense amplifying circuits are used, the data read circuit may include the two sense amplifying circuits each including the first and fourth reference voltages VREFH and VREFL and the second and third reference voltages VREFHM and VREFLM , as in 15 shown is received. The other two read amplification circuits may be the same as those used in 15 with the exception that the first and third reference voltages VREFH and VREFLM are provided for one of these sense amplifying circuits, and the second and fourth reference voltages VREFHM and VREFL are provided for the other of these read amplifying circuits.

Data of three bits or more can be stored in each unit cell, and in this case, a larger number of reference voltages of reference cells or reference voltage generation units can be generated.

The 16A and 16B are circuit diagrams of nonvolatile memory devices which comprise the data read circuit 4300 of the 15 according to exemplary embodiments of the inventive concept. In describing the present embodiments, the same or similar components as those of the above-described embodiments can perform substantially the same operations, and thus a detailed description thereof will be omitted.

Referring to 16A can be a non-volatile storage device 4100 a memory cell array 4110 which comprises a plurality of memory cells 4111 (for example, MRAM cells) as a nonvolatile cell array, a row decoder 4120 for selecting a word line WL of the memory cell array 4110 , a column decoder 4130 (as in a bit line BL of the memory cell array 4110 , a precharge circuit unit 4140 for performing a precharge operation and a sense amplification circuit block 4150 to sample / amplify data.

In addition, the non-volatile memory device 4100 first to fourth reference voltage generating units 4171 . 4172 . 4173 and 4174 for generating different reference voltages VREFL, VREFLM, VREFHM and VREFH for data sampling. For example, the first reference voltage generating unit generates 4171 a low-level reference voltage VREFL, the second reference voltage generation unit 4172 generates a low intermediate level reference voltage VREFLM, the third reference voltage generation unit 4173 generates a high intermediate level reference voltage VREFHM and the fourth reference voltage generation unit 4174 generates a high-level reference voltage VREFH. In 16A are the first to fourth reference voltage generation units 4171 to 4174 as blocks having different functions, but a single functional block may generate a plurality of reference voltages.

Furthermore, according to the exemplary embodiments of the inventive concept, the plurality of reference voltages VREFL, VREFLM, VREFHM, VREFH, for example, the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH, for the sense-amplification circuit 4150 intended. In 16A The first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH are respectively passed through the first to fourth reference voltage generating units 4171 to 4174 generated in the non-volatile memory device 4100 however, the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH may be generated by an external controller (not shown) and for the nonvolatile memory device 4100 be provided. The read-amplification circuit block 4150 receives a data voltage VSA and the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH. For example, each read amplification circuit in the read amplification circuit block receives 4150 the data voltage VSA receives at least one of the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH and performs sampling and amplification operations using the received signals. The number of reference voltages and components related to the reference voltages can be varied in various ways to obtain these principles.

16B FIG. 14 illustrates an example for generating a reference voltage on one of the one of FIG 16A different way. For example, a non-volatile memory device generates 4100 , what a 16B is illustrated, reference voltages (for example, the first to fourth reference voltage VREFL, VREFLM, VREFHM and VREFH) for reading data from a reference cell. For this purpose, the nonvolatile cell array of the nonvolatile memory cell device 4100 furthermore a reference cell arrangement 4180 in addition to the memory cell array 4110 on. The reference cell arrangement 4180 may comprise reference cells having resistors corresponding to a plurality of data states. For example, when data is sampled using four reference voltages, the reference cell arrangement 4180 first to fourth reference cells 4181 to 4184 which provide the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH. The memory cell 4111 the cell arrangement 4110 which stores data, and the first to fourth reference cells 4181 to 4184 the reference cell arrangement 4180 can have the same cell structure.

Any of a date "00", "01", "10" and "11" may be in the first to fourth reference cell 4181 to 4184 the reference cell arrangement 4180 be saved. A write operation with respect to the first to fourth reference cells 4181 to 4184 can be done once. A date "00" becomes the first reference cell 4181 written, a date "01" becomes the second reference cell 4182 written, a date "10" is in the third reference cell 4183 written and a date "11" is in the fourth reference cell 4184 written. In the reference cell arrangement 4180 can be the first to fourth reference cell 4181 to 4184 may be arranged to correspond to at least some of the word lines WL, or alternatively, the first to fourth reference cells 4181 to 4184 be arranged so that they correspond to each of the word lines WL. As a result, during a reading operation, regarding the memory cell array 4110 Information which in the first to fourth reference cell 4181 to 4184 the reference cell arrangement 4180 written, also read.

16C FIG. 12 is a perspective view of a non-volatile memory cell incorporated in the 16A and 16B is illustrated according to an exemplary embodiment of the inventive concept. In 16C An STT MRAM serves as an example of the nonvolatile memory cell. A nonvolatile memory device may store data of at least two bits per unit cell using a multi-level cell (MLC). The unit cell may be configured by allowing an MTJ cell to have any resistor selected among four resistors, or by allowing two MTJ cells each to have any resistor selected among two resistors. 16C illustrates an example in which two MTJ cells are arranged in a unit cell.

Referring to 16C can the memory cell 4111 a first MTJ cell 410 , a second MTJ cell 420 and a cell transistor CT (CT = cell transistor). A gate of the cell transistor CT is connected to a word line (eg, a first word line WL0), and an electrode of the cell transistor CT is connected to a bit line (eg, a first bit line BL0) via a plurality of MTJ cells, namely, the first and second MTJ cells. cell 410 and 420 connected. In addition, the other electrode of the cell transistor CT is connected to a source line SL0.

The first MTJ cell 410 has a first fixed layer 413 , a first free layer 411 and a first tunnel layer 412 on which between the first fixed layer 413 and the first free layer 411 is arranged. The second MTJ cell 420 has a second fixed layer 423 , a second free layer 421 and a second tunnel layer 422 which is between the second pinned layer 423 and the second free layer 421 is arranged on. Magnetization directions of the first and second fixed layer 413 and 423 are fixed and magnetization directions of the first and second free layers 411 and 421 may be the same under different conditions as or opposite to the magnetization direction of the first and second pinned layers 413 and 423 be. An element for fixing the magnetization directions of the first and second fixed layers 413 and 423 For example, an antiferromagnetic layer may be further provided.

17 Fig. 10 is a circuit diagram illustrating a data read operation of the nonvolatile memory device 4100 according to an exemplary embodiment of the inventive concept. For ease of description, an illustration of various circuits used in a data transfer circuit (eg, memory cell 4111 ) or a reference transmission circuit (for example, first to fourth reference cells 4181 to 4184 ) are omitted.

Referring to the 16A and 16B are the data voltage VSA and the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH generated by the data transmission circuit R and the reference transmission circuit for the sense amplification circuit block 4150 intended. The read-amplification circuit block 4150 comprises a plurality of read-amplification circuit units. For example, each read-amplification circuit unit 4151 be arranged so that it corresponds to any data transmission circuit. Although in 17 not shown, the other sense amplifying circuit units may be arranged to correspond to respective data transmission circuits, and the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH may be ordinarily provided for the plurality of sense amplifying circuit units.

The read-amplification circuit unit 4151 samples and amplifies the data voltage VSA and may be present in the sense-amplification circuit block 4150 of the 16A and 16B be included. The output of the sense-amplification circuit unit 4151 may be latched by a predetermined latch circuit (not shown) and may be provided as read data to the outside.

According to the present embodiment, the sense amplification circuit unit 4151 Perform sampling and amplification operations using the data voltage VSA and the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH. The first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH may have voltages corresponding to data values shown in the first to the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH fourth reference cell 4181 to 4184 stored are developed. When the data voltage VSA is developed, a difference occurs in voltage levels between the data voltage VSA and the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH. For example, if a date has "00" in the memory cell 4111 is written, the data voltage VSA and the first reference voltage VREFL the same voltage level and a difference in level occurs between the data voltage VSA and the second to fourth reference voltage VREFLM, VREFHM and VREFH.

The read-amplification circuit unit 4151 compares a level of the data voltage VSA and levels of the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH and amplifies differences in the voltage level therebetween to produce output signals, and performs decoding operations on the output signal to multi-bit least -Significant bit (LSB) data and Most Significant Bit (MSB) data to produce. An operation for generating the output signal may include an operation for generating a differential signal corresponding to the differences in a level between the data voltage VSA and the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH, and operations for sampling and amplifying the generated one differential signal. In addition, the operation for generating the differential signal may be performed by an integrated circuit using a capacitor (not shown), and an operation for accumulating the differences in the voltage level between the data voltage VSA and the first to fourth reference voltages VREFL , VREFLM, VREFHM and VREFH in the capacitor can be performed.

In addition, the read-amplification circuit unit 4151 a plurality of sense amplifying circuits (not shown) corresponding to a data transmission circuit, and may also include a decoder (not shown) for generating the multi-bit LSB data and the MSB data by combining Have output signals of the sense-amplifying circuits. The first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH may be classified as at least two reference voltage combinations, each having at least one reference voltage, and the reference voltage combinations are provided for the respective sense amplifying circuits. Each of the read-amplification circuits receives a combination of the data voltage VSA and a reference voltage and generates an output signal which is generated due to a difference in the level of the received signals.

18A FIG. 10 is a block diagram showing the sense amplification circuit unit. FIG 4151 illustrated in accordance with an exemplary embodiment of the inventive concept. 18B FIG. 14 is a table for explaining the outputs of multi-bit LSB data and MSB data according to an exemplary embodiment of the inventive concept. FIG.

Referring to 18A includes the read-amplification circuit unit 4151 a plurality of sense amplifying circuits to correspond to a data voltage VSA or the memory cell 4111 correspond. For example, the read-amplification circuit unit 4151 a first to fourth sense amplifying circuit 431 to 434 and a decoder circuit 441 exhibit. Each of the first to fourth read amplification circuits 431 to 434 usually receives the data voltage VSA due to data stored in the memory cell 4111 and also receives any reference voltage combination of a plurality of reference voltage combinations. For example, the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH may be classified as four reference voltage combinations, and the reference voltage combinations are for the respective first to fourth sense amplifying circuits 431 to 434 intended. The first to fourth sense amplification circuits 431 to 434 generate output signals by performing sampling and amplification operations using voltage inputs thereto. For example, the first sense amplification circuit generates 431 a first output signal VOUT by performing a sampling and amplifying operation using the data voltage VSA and the first and fourth reference voltages VREFL and VREFH.

Using the method described above, the second read amplification circuit receives 432 the data voltage VSA and the second and third reference voltages VREFLM and VREFHM and generates a second output signal VOUTM. In addition, the third sense amplification circuit receives 433 the data voltage VSA and the first and second reference voltages VREFL and VREFLM and generates a third output signal VOUTLM. In addition, the fourth sense amplification circuit receives 434 the data voltage VSA and the third and fourth reference voltages VREFHM and VREFH and generates a fourth output signal VOUTHM.

The first to fourth output signals VOUT, VOUTM, VOUTLM, and VOUTHM, each through the first to fourth read amplification circuit 431 to 434 are generated for the decoder circuit 441 intended. The decode circuit 441 decodes the received output signals to output the multibit MSB data and LSB data of the MLC.

18A Fig. 12 illustrates an example of a circuit for reading out the MLC which stores data of two bits per unit cell, but the present inventive concept is not limited thereto. For example, a different number of sense amplifying circuits may be arranged to correspond to one unit cell, and combinations of the first to fourth reference voltages VREFL, VREFLM, VREFHM and VREFH provided for the respective read amplifying circuits may be performed be defined in different ways. In addition, the MLC can store data of more than three bits per unit cell. In this case, a larger number of reference voltages may be generated from the reference cells or may be provided from the outside. Additionally is in 18A the decode circuit 441 in the read-amplification circuit unit 4151 included, the decoder circuit 441 but may be included in a separate decoder circuit block (not shown) external to the read amplification circuit unit 4151 is arranged.

Still referring to 18B For example, the data voltage VSA is developed in various ways according to a data stored in the MLC, and the output signals obtained from the first to fourth sense amplifying circuits 431 to 434 the read-amplification circuit unit 4151 be issued vary.

For example, when a data "00" is stored in the MLC, the data voltage VSA generated by the MLC is the same as the first reference voltage VREFL. As a result, the first sense amplifying circuit samples 431 and amplifies a difference in level between the data voltage VSA and the fourth reference voltage VREFH to output the first output signal VOUT having a logic low level L. The second read-amplification circuit 432 samples and amplifies a difference in level between the data voltage VSA and the second and third reference voltages VREFLM and VREFHM to output the second output signal VOUTM having a logic low level L. The third read-amplification circuit 433 samples and amplifies a difference in level between the data voltage VSA and the second reference voltage VREFLM to output the third output signal VOUTLM having a logic low level L. The fourth read-amplification circuit 434 samples and amplifies a difference in level between the data voltage VSA and the third and fourth reference voltages VREFHM and VREFH to output the fourth output signal VOUTHM having a logical low level L.

In addition, when a data "01" is stored in the MLC, the data voltage VSA generated by the MLC is the same as the second reference voltage VREFLM. As a result, a difference occurs in the level between the data voltage VSA and the first, third and fourth reference voltages VREFL, VREFHM and VREFH, and the difference in level is sampled and amplified by the read-and-boost circuits. In this case, the first sense amplification circuit is 431 the first output signal VOUT having a logic low level L, the second sense-amplifying circuit 432 outputs the second output signal VOUTM having a logical low level L, the third sense amplification circuit 433 outputs the third output signal VOUTLM, which is a logic high level H and the fourth read amplification circuit 434 outputs the fourth output signal VOUTHM, which has a logic low level L.

In addition, when a data "10" is stored in the MLC, the data voltage VSA generated by the MLC is the same as the third reference voltage VREFHM. In this case, the first to third read amplification circuits give 431 to 433 the first to third output signals VOUT, VOUTM and VOUTLM each having a logic high level H. Furthermore, there is the fourth sense amplification circuit 434 the fourth output signal VOUTHM, which has a logic low level L. In addition, when a data "11" is stored in the MLC, the data voltage VSA generated by the MLC is the same as the fourth reference voltage VREFH. In this case, the first to fourth sense amplifying circuits give 431 to 434 the first to fourth output signals VOUT, VOUTM, VOUTLM and VOUTHM each having a logical high level H.

The 19A to 19B are schematics showing the decode circuit 441 of the 18A according to exemplary embodiments of the inventive concept. As in 19A is illustrated, a decoder circuit 441A a first XOR gate 451 and a second XOR gate 452 to perform XOR operations. Referring to the 18A and 19A the decode circuit receives and decodes 441 a first output signal VOUT, a second output signal VOUTM, a third output signal VOUTLM, and a fourth output signal VOUTHM to generate multibit data stored in the MLC are stored to output. For example, when two-bit data is stored in the MLC, the decode circuit 441A Multibit MSB data and LSB data off.

Referring to the table which is in 18B 1, a first MSB datum has a value corresponding to a level of the first output signal VOUT. In other words, when the first output signal VOUT has a logical low level L, the first MSB data stored in the MLC has a logical low value "0", and when the first output signal VOUT is a logic high Level H, the first MSB date has a logical high value of "1".

Furthermore, a second LSB datum has a value which varies according to levels of other output signals. For example, the value of the second LSB datum may be determined by the second to fourth output signals VOUTM, VOUTLM and VOUTHM which undergo a logic operation. For example, an XOR operation may be used to determine the value of the second LSB date. For this purpose, the decoder circuit 441 the first and second XOR gate 451 and 452 exhibit. The first XOR gate 451 receives the third and fourth output signals VOUTLM and VOUTHM and outputs a result of the XOR of the third and fourth output signals VOUTLM and VOUTHM. The second XOR gate 452 receives a signal output from the first XOR gate 451 and the second output signal VOUTM and outputs a result of the XOR of the signal coming from the first XOR gate 451 and the second output signal VOUTM as the second LSB data. Here, the second LSB datum may be the result of the XOR of the third output signal VOUTLM and the fourth output signal VOUTHM.

Referring to the 18B and 19A when the XOR of the third output signal VOUTLM and the fourth output signal VOUTHM has a logical low value "0", the second LSB datum has a value corresponding to a level of the first output signal VOUT and if the XOR of the third output signal VOUTLM and of the fourth output signal VOUTHM has a logical high value "1", the second LSB data has a value corresponding to an opposite level of the first output signal VOUT.

The configuration of an output decoder 441A , which with reference to the 19A is merely an example, and the number of configurations of the logic gates described above may vary to achieve the same goals, and may also be partially modified according to timing characteristics of a semiconductor memory device.

Furthermore is 19B a circuit diagram showing the decoder circuit 441 of the 18A illustrated in accordance with an exemplary embodiment of the inventive concept. A decoder circuit 441B of the 19B It decodes and receives a first output signal VOUT, a third output signal VOUTLM and a fourth output signal VOUTHM to output multi-bit data stored in the MLC. A first XOR gate 453 receives the third output signal VOUTLM and the fourth output signal VOUTHM, and outputs a result of the XOR of the third output signal VOUTLM and the fourth output signal VOUTHM. In addition, in the table, which in 18B is illustrated, since the first output signal VOUT is the same as the second output signal VOUTM, the first output signal VOUT instead of the second output signal VOUTM for a second XOR gate 454 be provided. The second XOR gate 454 receives a signal output from the first XOR gate 453 and the first output signal VOUT and outputs a result of the XOR of the signal output from the first XOR gate 453 and the first output signal VOUT as second LSB data. Here, the second LSB data may be the result of the XOR of the third output signal VOUTLM and the fourth output signal VOUTHM.

20 FIG. 12 is a block diagram illustrating a nonvolatile memory device including the data read circuit. FIG 4300 of the 15 according to an exemplary embodiment of the inventive concept. In 20 It is assumed that a decode circuit is configured as a block separate from a sense amplification circuit block. To simplify the description illustrated 20 only the read-amplification circuit block and a decoder block.

A nonvolatile storage device 4100A has a read-amplification circuit block 4110A and a decoder block 4120A to read data from a cell array (not shown). The read-amplification circuit block 4110A includes a plurality of read-amplification circuit units 4111A . 4112A . 4113 , ..., and the read amplification circuit unit 4111A . 4112A . 4113 , ... may be arranged to correspond to data read circuits. For example, n read-amplification circuit units may be arranged to correspond to n data-read circuits, and each read-amplification circuit unit may comprise a plurality of read-amplification circuits.

As in 20 is illustrated, the decoder block 4120A outside the read-amplification circuit block 4110A can be arranged and it can a plurality of decoder circuits 4121A . 4122A . 4123A ... which correspond to the read amplification circuit units 4111A . 4112A . 4113 , ... correspond. In addition, each decode circuit may include a plurality of bit generation units to generate multi-bit data. For example, as in 20 is illustrated when storing the MLC data of two bits, each of the decode circuits 4121A . 4122A . 4123A LSB and MSB units have. The LSB and MSB generation units may exchange an operation result and / or an intermediate operation result.

As described above, a plurality of reference voltages VREF are used to read out the MLC, and the reference voltages VREF are generally applied to the sense amplification circuit units 4111A . 4112A . 4113 , ... intended. In addition, the reference voltages VREF may be classified as a plurality of reference voltage combinations. For example, when each of the read-amplification circuit units 4111A . 4112A . 4113A four read amplification circuits, the reference voltages VREF are classified as four reference voltage combinations Ref_comb1 to Ref_comb4.

The read-amplification circuit units 4111A . 4112A . 4113A , ... perform sampling and amplification operations by using the data voltage VSA and the reference voltage combinations Ref_comb1 to Ref_comb4 and generate the first to fourth output signals VOUT, VOUTM, VOUTLM and VOUTHM. In addition, the LSB and MSB generating units decode the first to fourth output signals VOUT, VOUTM, VOUTLM, and VOUTHM, and output output LSB data and MSB data, respectively.

The reference voltages VREF can be combined in various ways. For example, the reference voltages VREF may vary on a path different from the table shown in FIG 18B is illustrated, combined. In this case, levels of the first to fourth output signals VOUT, VOUTM, VOUTLM, and VOUTHM, which may be outputs from the sense amplification circuit units 4111A . 4112A . 4113A , ... are, have different values.

The decoder circuits 4121A . 4122A . 4123A , ... can be designed taking into account level characteristics of the first to fourth output signals VOUT, VOUTM, VOUTLM and VOUTHM. In other words, a method for determining multi-bit data may vary according to the level characteristics of the first through fourth output signals VOUT, VOUTM, VOUTLM, and VOUTHM, and the LSB and MSB generating units may be different in route from that of FIG 19A and 19B according to the method for determining multi-bit data.

The 21 and 22 FIG. 11 are block diagrams of nonvolatile memory devices having different layouts in accordance with exemplary embodiments of the inventive concept. In 21 an example is shown in which a read-amplification circuit block is arranged for each cell array, and in FIG 22 For example, an example in which a plurality of cell arrays share a read amplification circuit block is shown.

As in 21 can be shown, a non-volatile memory device 5000 a cell arrangement 5100 which comprises a plurality of memory cells 5110 comprising a row decoder 5200 for selecting a word line WL of the cell arrangement 5100 and a column selection area 5300 for selecting a bit line BL of the cell array 5100 exhibit. The column selection area 5300 may include a sense amplification circuit block (eg, a plurality of sense amplifying circuits 5310 from a data read circuit according to an exemplary embodiment of the inventive concept) and column selection lines CSL, and the column selection area 5300 controls a connection between a bit line BL and a sense amplification circuit 5310 in response to a column select signal from a column decoder.

The cell arrangement 5100 may comprise a plurality of reference cells for generating reference voltages VREFH and VREFL and, for example, a first reference cell 5121 for generating a first reference voltage VREFH and a second reference cell 5122 for generating a second reference voltage VREFL. The majority of memory cells 5110 and the first and second reference cells 5121 and 5122 may be connected for a single word line WL, and data voltages from the plurality of memory cells 5110 are for an input terminal of the read amplification circuit 5130 provided by respective bit lines BL.

The voltages developed on the bitlines BL associated with the first and second reference cells 5121 and 5122 are connected as the first reference voltage VREFH and the second reference voltage VREF for the column selection area 5300 intended. The majority of read amplification circuits 5310 can in the column selection area 5300 and the first and second reference voltages VREFH and VREFL may generally be for the plurality of sense amplifying circuits 5310 be provided. In other words, the first and second reference voltages VREFH and VREFL, which are the first and second reference cells 5121 and 5122 generated locally for the read amplification circuit 5310 provided, and read data, which from the read-amplification circuit 5310 are supplied to an input / output circuit via a global line.

22 Fig. 10 is a block diagram of an example of a nonvolatile memory device having a different layout from that of the nonvolatile memory device 5000 , what a 21 shown has. As in 22 can be shown, a non-volatile memory device 6000 a cell arrangement 6100 comprising a plurality of memory cells 6110 , a row decoder 6200 for selecting a word line WL of the cell arrangement 6100 and a column selection area 6300 for selecting a bit line BL of the cell array 6100 using a column select line CSL. The cell arrangement 6100 can be a first reference cell 6121 for generating the first reference voltage VREFH and a second reference cell 6122 for generating the second reference voltage VREFL.

The nonvolatile storage device 6000 can still have a column decode area 6400 which generates a column select signal by decoding a column address. The column decoder area 6400 may be disposed on one side to a plurality of cell assemblies 6100 and a column select signal of. the column decoder area 6400 can be delivered globally and generally for at least two cell arrays 6100 be provided. At or on the column decoder area 6400 For example, a sense-amplifying circuit block (e.g., a plurality of sense-amplifying circuits) may be used 6410 from a data read circuit according to an exemplary embodiment of the inventive concept).

A local supply line LIO for locally providing the first and second reference voltages VREFH and VREFL may be in the column selection area 6300 and the first and second reference voltages VREFH and VREFL from the first and second reference cells 6121 and 6122 are for the column decoder area 6400 provided by the local supply management LIO and a global supply management GIO. The first and second reference voltages VREFH and VREFL provided by the global supply line GIO may be general to the plurality of sense-amplifying circuits 6410 be provided.

According to the structure of the nonvolatile memory device 6000 , what a 22 is shown, the read amplification circuits 6410 between a plurality of cell arrays 6100 shared, which reduces an area or area covered by the sense amplification circuits 6410 is claimed. On the other hand, since a data voltage and reference voltages are supplied through the global supply line GIO before reaching a full digital level, a variation in the voltage level according to resistance components of the global supply line GIO may occur, but the data read circuit according to the above embodiments may have an influence of Reduce variation, thereby improving the reliability of read data.

23 FIG. 12 is a circuit diagram of a data read circuit which may be included in a nonvolatile memory device according to an exemplary embodiment of the inventive concept. In 23 For example, a memory other than an MRAM described in the foregoing embodiments is applied.

As in 23 shows a data-reading circuit 7100 various circuits for reading data stored in a memory cell 7110 are stored, such as a read-amplification circuit 7120 for receiving and sampling / amplifying a data voltage VSA and at least two reference voltages VREFH and VREFL. The data read circuit 7100 can continue a precharge circuit 7130 for precharging a bit line to a predetermined level, a bit line selection circuit 7140 for selecting a bit line, a clamping circuit 7150 for clamping a bit line and a current source 7160 for providing a current for a bit line.

The memory cell 7110 may comprise a resistive memory such as a Programmable Random Access Memory (PRAM) cell or an RRAM cell as a nonvolatile memory cell. As in 23 As shown, each of the PRAM cells and the RRAM cells may be configured or shaped with a diode and a resistive element connected in series. Data is stored in accordance with variable resistance characteristics of the resistive element, a node of the resistive element is connected to a bit line, and a node of a diode (For example, a cathode electrode) is connected to a word line WL. Although in 23 not shown, the resistive element may be replaced by a ferroelectric capacitor which uses a thin ferroelectric film when implementing the nonvolatile memory cell with a FRAM cell.

As in the previous embodiments, the reference voltages VREFH and VREFL may be generated by reference cells having the same structure as the memory cell 7110 , For example, by performing a data-writing operation on the reference cells, once, resistance elements of some reference cells may have a high resistance value and resistive elements of some other reference cells may have a low resistance value. In a subsequent data read operation, a reference cell is selected to develop a voltage of a bit line connected to the reference cell to one of the reference voltages VREFH and VREFL. The read-amplification circuit 7120 receives the data voltage VSA and the reference voltages VREFH and VREFL, generates a differential output signal by performing an integrating operation according to a voltage level difference between the data voltage VSA and the reference voltages VREFH and VREFL, and samples / amplifies the differential output signal to a predetermined one Time, whereby an amplified output signal VOUT is generated.

24 FIG. 10 is a block diagram of an electronic system including a non-volatile memory device according to an exemplary embodiment of the inventive concept. Referring to 24 can be an electronic system 8100 an input device or input device 8110 , an output device or output device 8120 , a storage device 8140 and a processor device 8130 exhibit. The storage device 8140 may comprise a cell array having a plurality of nonvolatile memory cells and a peripheral circuit for performing operations such as read / write, or may include a nonvolatile memory device and a memory controller as a system. For example, assume that the storage device 8140 a memory controller and a nonvolatile memory device; then a memory 8141 which is in 24 is shown using a non-volatile memory device according to an exemplary embodiment of the inventive concept. The processor device 8130 can with the input device 8110 , the output device 8120 and the storage device 8140 be connected through appropriate interfaces, thereby reducing the overall operation of the electronic system 8100 controls.

25 FIG. 10 is a block diagram of a single chip microcomputer including a nonvolatile memory device according to an exemplary embodiment of the inventive concept. Referring to 25 can be a microcomputer 8200 in the form of a circuit module a central processing unit (CPU = Central Processing Unit) 8290 , a memory which serves as the working area of the CPU 8290 is used, for example, a RAM 8280 , a bus controller 8270 , an oscillator 8220 , Frequency divider circuits 8230 , a non-volatile memory 8240 , a power circuit 8250 , an input / output port 8260 and other peripheral circuits 8210 which have a timer counter, etc., which are electrically connected to an internal bus BUS.

The CPU 8290 may include an instruction control part and an execution part, decodes a fetched instruction by the instruction control part, and performs a processing operation according to a result of decoding by the execution part. The non-volatile memory 8240 stores an operation program or data of the CPU 8290 and different types of data. The power circuit 8250 generates a voltage which is required for read / write operations with respect to the nonvolatile memory 8240 necessary is. The frequency divider circuits 8230 share a source frequency, which is from the oscillator 8220 is provided in a plurality of frequencies to provide reference clock signals and other internal clock signals.

The internal bus BUS may include an address bus, a data bus and a control bus. The bus controller 8270 controls access to the BUS in response to an access request from the CPU 8290 , If the microcomputer 8200 is located in a system, the CPU controls 8290 Read / write operations with respect to the nonvolatile memory 8240 , In an apparatus test or a manufacturing stage, an external recording apparatus can directly read / write operations with respect to the nonvolatile memory 8240 through the input / output port 8260 Taxes.

At least one of the non-volatile memory 8240 or the RAM 8280 may use a nonvolatile memory device according to an exemplary embodiment of the inventive concept. In other words, the nonvolatile memory device according to an exemplary embodiment of the inventive concept can be used to store large-volume data, and the nonvolatile memory device according to an exemplary embodiment of the inventive concept can also be used instead of the RAM 8280 which requires fast read / write operations.

26 FIG. 10 is a block diagram of an information processing system having a nonvolatile memory device / system according to an exemplary embodiment of the inventive concept.

Referring to 26 can be a non-volatile storage system 8310 According to an exemplary embodiment of the inventive concept be included in a mobile device or a computer system such as a desktop computer. A computer system 8300 (For example, an information processing system), the non-volatile memory system 8310 , a modem 8320 , a CPU 8330 , a ram 8340 and a user interface (UI) 8350 which are electrically connected to a system bus. The non-volatile storage system 8310 can be a memory controller 8312 and a nonvolatile memory device 8311 exhibit. In 26 For example, an MRAM is referred to as the nonvolatile memory device 8311 used. The nonvolatile storage device 8311 however, it may comprise a flash memory or a nonvolatile memory such as a PRAM, an RRAM, an FRAM or the like.

Data generated by the CPU 8330 or data entered from outside are stored in the nonvolatile storage system 8310 saved. At least one of the non-volatile storage system 8310 and the RAM 8340 may include a nonvolatile memory device according to an exemplary embodiment of the inventive concept. In other words, according to an exemplary embodiment of the inventive concept, the nonvolatile memory device may be based on a memory for storing large volume data available to the computer system 8300 or memory requiring data which requires quick access thereto, such as system data. An application chipset, a camera image processor (CIS), an input / output device, etc. may continue to be in the computer system 8300 be provided.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept, as illustrated by the following Claims is defined, depart.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• KR 10-2011-0085146 [0001]
• KR 10-2011-0110719 [0001]

Claims (20)

Method for reading data from a nonvolatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 comprising: receiving a data voltage (VSA), a first reference voltage (VREFH), and a second reference voltage (VREFL) at a first sense amplifier (14); 2100 ), wherein the data voltage (VSA) corresponds to data stored in a memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ) are stored; sampling a voltage level difference between the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL) at the first sense amplifier (16) 2100 ) to generate first and second differential output signals (VOUT, VOUTb); and amplifying the first and second differential output signals (VOUT, VOUTb) at a second sense amplifier ( 2200 ) to read data for the memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ) to create. Method according to claim 1, wherein the second sense amplifier ( 2200 ) amplifies the first and second differential output signals (VOUT, VOUTb) after a first delay. Method according to claim 2, wherein the first delay is a time from when the first sense amplifier ( 2100 ) is activated until when the second sense amplifier ( 2200 ) is activated. The method of claim 1, further comprising: precharging a first and a second differential output terminal of the first sense amplifier ( 2100 ) to first level voltages in response to a control signal (Ctrl11) prior to receiving the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL). The method of claim 4, wherein the sampling performed on the first sense amplifier ( 2100 ), comprising: storing two voltage levels (VOUT, VOUTb) applied to the first and second differential output terminals, the two voltage levels (VOUT, VOUTb) being based on the voltage level difference between the data voltage (VSA ) and the first and second reference voltages (VREFH, VREFL). The method of claim 5, wherein the sampling performed on the first sense amplifier ( 2100 ), comprising: providing the two voltage levels from the first sense amplifier ( 2100 ) as the first and second differential output signals (VOUT, VOUTb) for the second sense amplifier ( 2200 ) in response to a version of the control signal (Ctrl12) delayed by the first delay, the gain being applied to the second sense amplifier (Ctrl12). 2200 ), comprising: amplifying the first and second differential output signals (VOUT, VOUTb); and outputting the amplified first and second differential output signals (VOUT, VOUTb) as the read data. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ), comprising: a cell assembly ( 1110 . 4110 . 5100 . 6100 ), which are a plurality of memory cells ( 1111 . 4111 . 5110 . 6110 . 7110 ) having; and a read-amplification circuit ( 431 - 434 ; 1151 ; 3160 . 3170 ; 4310 . 4320 ; 5310 ; 6410 ; 7120 ) which is configured to store a data voltage (VSA) of a memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ), a first reference voltage (VREFH) and a second reference voltage (VREFL) during a data read operation of the memory cell (FIG. 1111 . 4111 . 5110 . 6110 . 7110 ) to generate differential output signals (VOUT, VOUTb) based on a voltage level difference between the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL) and the differential output signals (VOUT, VOUTb ) as data coming from the memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ) were output. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 7, wherein the read-amplification circuit ( 431 - 434 ; 1151 ; 3160 . 3170 ; 4310 . 4320 ; 5310 ; 6410 ; 7120 ) Comprises: a first sense amplifier ( 2100 ) in response to a control signal (Ctrl11), the first sense amplifier ( 2100 ) is configured to receive the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL) and the differential output signals (VOUT, VOUTb) based on the voltage level difference between the data voltage (VSA) and the generate first and second reference voltages (VREFH, VREFL); a delay unit ( 2300 ) configured to receive the control signal (Ctrl11) and to generate a delayed control signal (Ctrl12); and a second sense amplifier ( 2200 ) in response to the delayed control signal (Ctrl12), the second sense amplifier ( 2200 ) is configured to amplify the differential output signals (VOUT, VOUTb) and the amplified differential output signals as the data received from the memory cell (12). 1111 . 4111 . 5110 . 6110 . 7110 ) are output. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 7, further comprising: a first reference voltage generation unit ( 1171 ) configured to generate the first reference voltage (VREFH); and a second reference voltage generation unit ( 1172 ) configured to generate the second reference voltage (VREFL), the first and second reference voltage generating units (14) 1171 . 1172 ) of the cell arrangement ( 1110 . 4110 . 5100 . 6100 ) are separated. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 7, further comprising a reference cell arrangement ( 1180 . 4180 ), wherein the reference cell arrangement ( 1180 . 4180 ) Comprises: a first reference cell ( 1181 . 4881 . 5121 . 6121 ) configured to generate the first reference voltage (VREFH); and a second reference cell ( 1182 . 4882 . 5122 . 6122 ) configured to generate the second reference voltage (VREFL). Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 10, wherein the first and second reference cells ( 1181 . 4881 . 5121 . 6121 ; 1182 . 4882 . 5122 . 6122 ) the same structure as the memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ) to have. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 7, wherein the data voltage (VSA) has a high voltage level or a low voltage level. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 12, wherein the first reference voltage (VREFH) has the same voltage level as the data voltage (VSA), and the second reference voltage (VREFL) has a different voltage level than the data voltage (VSA). Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 12, wherein the second reference voltage (VREFL) has the same voltage level as the data voltage (VSA), and the first reference voltage (VREFH) has a different voltage level than the data voltage (VSA). Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 7, wherein the memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ) is a magnetic random access memory (MRAM), a phase change random access memory (PRAM), a resistance random access memory (RRAM) or a ferroelectric random access memory (FRAM). Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ), comprising: a cell assembly ( 1110 . 4110 . 5100 . 6100 ; 1180 . 4180 ), which a memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ), a first reference cell and a second reference cell ( 1181 . 4881 . 5121 . 6121 ; 1182 . 4882 . 5122 . 6122 ), wherein the memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ) is connected to a first bit line (BL0), the first reference cell (BL0) 1181 . 4881 . 5121 . 6121 ) is connected to a second bit line (BL1) and the second reference cell (BL1) 1182 . 4882 . 5122 . 6122 ) is connected to a third bit line (BL2); and a sense amplifier ( 2100 . 2200 ) which is configured to store a data voltage (VSA) of the memory cell (FIG. 1111 . 4111 . 5110 . 6110 . 7110 ), which is provided by the first bit line (BL0), a first reference voltage (VREFH) of the first reference cell ( 1181 . 4881 . 5121 . 6121 ) provided by the second bit line (BL1) and a second reference voltage (VREFL) of the second reference cell (FIG. 1182 . 4882 . 5122 . 6122 ) provided by the third bit line (BL2), and in response to the reception of the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL) of the sense amplifier (FIG. 2100 . 2200 ) is configured to determine a difference between the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL) and this difference as data output from the memory cell (14). 1111 . 4111 . 5110 . 6110 . 7110 ) are output. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 16, wherein the difference between the data voltage (VSA) and the first and the second reference voltage (VREFH, VREFL) is determined after a time delay which is measured from when a first part of the sense amplifier ( 2100 . 2200 ) is activated by a control signal (Ctrl11) until a delayed version of the control signal (Ctrl12) activates a second part of the sense amplifier (Ctrl11). 2100 . 2200 ) is activated. Non-volatile memory device ( 1100 . 4100 . 4100A . 5000 . 6000 . 8140 . 8311 ) according to claim 16, wherein the data voltage (VSA) is generated by a data voltage generating unit which stores the memory cell (16). 1111 . 4111 . 5110 . 6110 . 7110 ) is generated, wherein the first reference voltage (VREFH) is generated by a first reference voltage generating unit, which the first reference cell ( 1181 . 4881 . 5121 . 6121 ), and the second reference voltage (VREFL) is generated by a second reference voltage generation unit which generates the second reference cell (VREFL). 1182 . 4882 . 5122 . 6122 ), wherein the data voltage generation unit, the first reference voltage generation unit and the second reference voltage generation unit each have the same structure. A Spin Torque Transfer (STT) Magnetic Random Access Memory (MRAM) device, comprising: a sense amplifier (16); 2100 . 2200 ), which has a first node which receives a data voltage (VSA) which is generated by a memory cell ( 1111 . 4111 . 5110 . 6110 . 7110 ), a second node receiving a first reference voltage (VREFH), a third node receiving a second reference voltage (VREFL), and a fourth node receiving a signal as data from the memory cell (VREFH). 1111 . 4111 . 5110 . 6110 . 7110 ), the signal being based on a voltage level difference between the data voltage (VSA) and the first and second reference voltages (VREFH, VREFL). The STT MRAM device according to claim 19, wherein the first reference voltage (VREFH) is provided by a first reference voltage generating unit, and the second reference voltage (VREFL) is provided by a second reference voltage generating unit.

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