DE102010003739B4 - Circuit arrangement for operating a plurality of LEDs - Google Patents

Abstract

Circuit arrangement for operating a plurality of LEDs with - a supply voltage connection (UV) for coupling with a DC supply voltage (Ua); - a reference potential connection for coupling to a reference potential; - A current source (I0), which is coupled to the reference potential connection; - The series connection of at least one first (LED1) and at least one second LED (LED2), wherein the at least one first LED (LED1) a first bypass device (BP1a) and the at least one second LED (LED2) a second bypass device (BP2a) connected in parallel The first (BP1a) and the second bypass device (BP2a) each have a control connection, the parallel connection of the at least one first LED (LED1) and the first bypass device (BP1a), the parallel connection of the at least one second LED (LED2) and the second bypass device (BP2a) and the current source (I0) are serially coupled between the supply voltage connection (UV) and the reference potential connection; - A PWM generator (12) with at least one first output (A1), which with the control connection of the first bypass device ...

Description

Technical area

The present invention relates to a circuit arrangement for operating a plurality of LEDs having a supply voltage terminal for coupling to a DC supply voltage, a reference potential terminal for coupling to a reference potential, a current source coupled to the reference potential terminal, the series connection of at least one first and at least one second LED, wherein the at least one first LED, a first bypass device and the at least one second LED, a second bypass device is connected in parallel, wherein the first and the second bypass device each having a control terminal, wherein the parallel connection of the at least one first LED and the first bypass device, the parallel circuit of at least one second LED and the second bypass device and the current source is serially coupled between the supply voltage terminal and the reference potential terminal, a PWM (Pulse Width Modulation) generator at least one first output coupled to the control port of the first bypass device and at least one second output coupled to the control port of the second bypass device and a level converter device having at least one first level converter connected between the first output of the PWM generator and the control terminal of the first bypass device, and a second level converter coupled between the second output of the PWM generator and the control terminal of the second bypass device.

State of the art

The present invention relates to a problem, as occurs for example in car headlights, which use a plurality of LEDs as the light source. In order to realize selective illumination functions, such as cornering light, illumination of persons, animals or traffic signs on the roadside, switching from high beam to low beam, etc., it is desirable to selectively switch individual LEDs or groups of LEDs off and on.

From the DE 101 03 611 A1 a circuit arrangement for operating a plurality of light sources is known, which operates these serially, wherein the light-emitting diodes can each be bridged with a switch.

From the GB 2 278 717 A is also known a circuit arrangement for the serial operation of light-emitting diodes, which are bridged by means of transistors.

The US 2008/0191642 Finally, shows the serial operation of high-power LEDs, which can also be bridged individually with transistors, the transistors are driven with different pulse width modulation to produce different emission rates of the light-emitting diodes.

To solve this problem, it is known from the prior art, to control the respective bypass device via a respective ohmic resistance, which is coupled between the respective level converter and the respective bypass device. If the respective level converter comprises a transistor, for example an npn transistor, then the respective ohmic resistance is arranged in the base line. In practice, however, this leads to LEDs, which are arranged closer to the reference potential within the LED string, emitting a different brightness than LEDs, which are arranged closer to the supply voltage terminal.

Presentation of the invention

The object of the present invention is therefore to develop a circuit arrangement mentioned in such a way that the brightness output of an LED is largely independent of where it is arranged between the supply voltage terminal and reference potential terminal.

These objects are achieved by a circuit arrangement having the features of patent claim 1.

The present invention is based on the finding that, in the prior art, brightness differences therefore occur between LEDs located at a higher potential and at a lower potential, since a relevant current component of the current that should actually flow through the LEDs is transmitted via the base device via the bypass device is deducted. The lower the potential of the respective LED, the more current has already been diverted from higher-potential LEDs, so that the LEDs lying at lower potential only deliver a lower brightness compared to the brightness emitted by the LEDs located at a higher potential ,

Moreover, in the case of the procedure known from the prior art, there is a further disadvantage: when using an ohmic resistance in the base line - when the level converter comprises a bipolar transistor; other realizations, eg. B. with a field effect transistor Of course possible - the current flowing through the ohmic resistance proportional to the voltage flowing through chip resistor is proportional to the voltage applied to the ohmic resistance, that is essentially the voltage at the output point in the LED strand is for the lower potential LEDs to dimension the ohmic resistance so that the transistor, which acts as a bypass device, receives sufficient control current. However, this results in a higher current than necessary for the higher potential LEDs. This results in undesirably high losses. Moreover, the above-mentioned disadvantage, that is to say that due to the removal of current from the LED string due to the LEDs lying at a higher potential, brightness fluctuations are amplified.

To avoid these problems, the present invention makes the way to form the first and second level converter as a constant current source. For this purpose, in the prior art in the collector line (on the example of npn bipolar transistor) provided ohmic resistance in the emitter line, that is, the connection between the emitter of the transistor of the level converter and the reference potential terminal coupled. As a result of the measure according to the invention, the voltage at the output of the PWM generator is converted by a level converter into a current for controlling the bypass device. In the prior art, however, the bypass device is controlled by a voltage, wherein the voltage required for control depends on how many LEDs are on or off, which are at a higher potential than the current LED.

By the simple measure of the present invention, only a minimal current is removed from the LED string, which is only a fraction of the current that was diverted from the LED string in the prior art. Although the current supplied to the lower potential drops minimally in relation to the LEDs located at a higher potential, the current difference is now so small that brightness differences can no longer be detected by a human eye. The fact that only a minimum current is drawn from the LED string, that is, only the current flowing out of the control connection of the bypass device, the losses of the circuit arrangement are minimized.

A particularly preferred embodiment is characterized in that the PWM generator is designed to temporally coordinate a rising edge at at least one first output with a falling edge at at least one second output, and vice versa. This measure ensures that the voltage drop across the current source changes as little as possible. While in uncoordinated switching on and off of LEDs, the voltage drop across the current source in extreme cases between a minimum value that is needed to switch the lowest potential LED still safe, and the potential lying at the supply voltage potential, it succeeds by this measure, to minimize the variation in the voltage drop across the current source at least in a variety of operating conditions of the circuit, for example, when all LEDs are operated with a PWM signal having a duty cycle of 50%. This results in a reduction in the EMC and line noise emitted by the circuitry.

The temporal coordination preferably takes place in such a way that the rise of the flank and the falling of the flank, and vice versa, occur in opposite directions. If one considers the series connection of two LEDs, one being operated instantaneously with a rising edge and the other with a falling edge, the voltage drop across the series circuit does not change.

Particularly preferably, the temporal coordination takes place in such a way that the change in the voltage drop across the current source during operation of the circuit remains below a predefinable threshold, the threshold being in particular at most 10%, preferably at most 5%, more preferably at most 2%, of the supply voltage connection during operation connected voltage is.

According to the invention, the first level converter comprises a first electronic switch with a control electrode, a reference electrode and a working electrode, wherein its working electrode with the control terminal of the first bypass device, the control electrode to the first output of the PWM generator and the reference electrode via a first resistor to the reference potential terminal wherein the second level converter comprises a second electronic switch having a control electrode, a reference electrode and a working electrode, wherein the working electrode with the control terminal of the second bypass device, the control electrode to the second output of the PWM generator and the reference electrode via a second resistor is coupled to the reference potential terminal. By this measure, the level converter can be realized by the least possible effort as a constant current source.

Efindungsgemäß is at least the first and the second bypass device as adjustable Bypass device formed, that is, for example, as a variable resistor, in particular as a transistor. In addition, a first low-pass filter is coupled between the first output of the PWM generator and the control electrode of the first electronic switch, wherein a second low-pass filter is coupled between the second output of the PWM generator and the control electrode of the second electronic switch. This measure results in softer switching edges, which significantly simplifies the synchronization of a rising edge with a falling edge. Thereby, the controller for the power source can be realized with significantly reduced effort, since it no longer needs to be designed for the case that it must respond to very spontaneous large voltage fluctuations in spite of synchronization of rising with falling edges. This configuration results in less sudden change of the current to be provided by the current source.

According to the invention, the first and / or the second low-pass filter is designed as an RC low-pass filter. As a result, softer edges can be achieved with relatively little effort. According to the invention, the RC low-pass filter comprises the series connection of a third and a fourth ohmic resistor, wherein the third ohmic resistor is coupled between the capacitor of the RC low-pass filter and the fourth ohmic resistor and wherein the third ohmic resistor is coupled to a current limiting device. The current-limiting device ensures that the current to be provided by the PWM generator to the electronic switch of the respective level converter does not exceed a predefinable threshold value. This ensures a constant charge and discharge current of the capacitor. In contrast to the exponential course of the capacitor voltage in the RC solution, this results in a linear progression over time.

In this case, a current-limiting device preferably comprises a first transistor and a complementary second transistor, the control electrodes of the first and second transistors being coupled to the pole of the third ohmic resistor facing the capacitor of the RC low-pass filter, the reference electrodes of the first and second transistors are coupled to the output of the PMW generator facing pole of the third ohmic resistor, wherein the working electrode of the first transistor is coupled to a supply voltage terminal and the working electrode of the second transistor to the reference potential terminal.

The first and / or the second bypass device are / is preferably realized as a pnp transistor, as a Darlington circuit, as a complementary Darlington circuit or as an n-channel transistor with a built-in protective diode. In this case, pnp transistors, which are more cost-effective than field-effect transistors, but in their conducting state have higher losses than field-effect transistors, are particularly advantageous in driving. However, the additional losses are insignificant and represent no additional problem in terms of heat dissipation, since this is designed anyway on the heat generated during operation of the LEDs and this is a multiple of what is implemented in a pnp transistor having an LED shorts. With regard to a particularly uniform light distribution, the Darlington circuit or the complementary Darlington circuit is preferred because then only a very small control current has to be diverted from the LED string.

Particularly preferably, the first and / or the second bypass device comprises an npn transistor, wherein the collector of the npn transistor is coupled to the anode of the associated LED and the emitter to the cathode of the associated LED, wherein the first and / or the second bypass device Furthermore, at least one current mirror device, wherein the output of the current mirror device is coupled to the emitter of the npn transistor, wherein the current mirror device is designed such that the output current of the current mirror device corresponds in amplitude to the base current of the npn transistor and in its direction opposite to the base current of the npn transistor is poled. This embodiment of the bypass device is preferably realized as an integrated circuit. It offers the advantage that the base current required for controlling the npn transistor is not introduced into the LED string, but is subtracted from the current mirror device again. This makes it possible to ensure that regardless of the switching state of the respective bypass device, the current flow in the LED string, that is, the series connection of the plurality of LEDs, is unaffected, whereby brightness fluctuations can be avoided particularly reliably.

Further advantageous embodiments of the invention will become apparent from the dependent claims.

The preferred embodiments presented with reference to the circuit arrangement according to the invention and their advantages apply correspondingly, as far as applicable, to the method according to the invention.

Short description of the drawing (s)

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Show it:

1 a schematic representation of an embodiment of a circuit arrangement according to the invention;

2 in a schematic representation of various embodiments of a bypass device, as shown in the in 1 shown circuit arrangement can be used;

3 a first embodiment of a arranged between the PWM generator and the level converter low-pass filter;

4 a second embodiment of a arranged between the PWM generator and the level converter low-pass filter; and

5 the time course of two coordinated, "soft" running switching edges of the currents I ₁ and I ₂ of in 1 illustrated circuit arrangement.

Preferred embodiment of the invention

1 shows a schematic representation of an embodiment of a circuit arrangement according to the invention. To provide a supply voltage U _a , which may be, for example, 48 V, a voltage converter is used whose input is coupled to an input voltage U _e , which may be 12 V, for example. The voltage converter in the present case comprises an inductance L1, a diode D1, a switch S1 and a capacitor C1. The switch S1 is in a known manner via a control device 10 controlled. For regulating the voltage U _a feedback can be provided. The output voltage U _a is used to supply a strand having a plurality of LEDs, in the present case the LEDs LED1, LED2, LED3, LEDi, LEDn are shown as examples. Each of the LEDs may in turn comprise a plurality of LEDs, in particular in parallel or series arrangement. Between the supply voltage terminal U _V , to which the supply voltage U _a is applied, and a reference potential terminal, in this case the ground potential, a current source is arranged in series with the LED string, which comprises an inductance L2, a switch S2, a resistor R and a freewheeling diode D2 includes. The current source is designated I ₀ and is characterized by a high output impedance and a very low output capacitance. As in 1 shown below, controls the control device 10 also the switch S2 of the current source I ₀ , which is presently arranged as a current sink, wherein the current source I _{0 is operated} in continuous mode with a fluctuation range of the amplitude of 10 to 15%. Although the current source I ₀ is realized here as a switching regulator, it can also be realized as a linear regulator. The voltage drop across the current source during operation of the circuit is designated U ₀ . The current flowing through the LED string is denoted by I.

Parallel to each LED - or parallel to a plurality of LEDs - is in each case an adjustable bypass device connected, which are referred to in the present case with BP1a, BP2a, BP3a, BPia, BPna. In the embodiment of 1 the respective bypass devices are realized as pnp transistors, wherein, for example, the LED LEDi, the emitter of the corresponding bypass device is coupled to a node N _i in the LED string, which is at a higher potential than the LEDi, the collector with a Node N _{i + 1} , which is at a lower potential than the LEDi, and wherein the base is coupled to a node N _pi connected to an output of a level converter PW _{i of} a level converter device 14 is coupled. Accordingly, each of LED (or a plurality of LEDs) associated with a level converter, in this case the LED1 of the level converter PW _1, the LED2 of the level converter PW _2, the LED3 of the level converter PW _3, the LEDi the level converter PW _i and the LEDn the level converter PW _n .

The level converter PW in the present case in each case comprise an npn transistor. In this case, the collector of each level converter PW is coupled to the control electrode of the associated bypass device BP, and the emitter of each level converter PW via a respective ohmic resistor R _i to the reference potential. The level converter PW are therefore realized as a constant current sources. The control electrode, that is to say the base of the respective NPN transistor in the present case, is connected via a respective low-pass filter TP1 to TPn to a respective output A ₁ to A _{n of} a PWM generator 12 coupled. The PWM generator is also supplied from the voltage source U _e .

The 2 shows various embodiments of bypass devices BP, each by the example of the bypass device BP _i for the LED LEDi. 2a are already in 1 illustrated embodiment again, in which the bypass device BPia is realized as a PNP transistor. According to the in 2 B illustrated embodiment, the bypass device BPib is implemented as a Darlington circuit. In the 2c illustrated embodiment shows a bypass device BPic, which includes a complementary Darlington circuit. According to the in 2d illustrated embodiment, a bypass device BPid can also be implemented as an n-channel transistor with built-in protection diode. In this case, the control electrode via a resistor R _{id is} coupled to the voltage U _a .

A particularly preferred embodiment of a bypass device is in 2e illustrated by the example of the bypass device BPie, which is preferably realized as an integrated circuit. This comprises a first SP ₁ and a second SP ₂ current mirror device and, as an essential element, an npn transistor T _d . The collector of the npn transistor T _d is coupled to the node N _i , the emitter of the transistor T _d to the node N _{i + 1} . The output of the current mirror device SP ₂ is coupled to the emitter of the transistor T _{d in} such a way that the output current I _{SP2 of} the current mirror device SP ₂ corresponds in amplitude to the base current I _{b of} the transistor T _d and with respect to its direction to the base current I _{b of} the transistor T _d opposite poled. This measure ensures that the current flowing from the LED string at the node N _i exactly corresponds to the current which is fed back to the LED string at the node N _{i + 1} .

3 shows a schematic representation of a first embodiment of a low pass TP _i of 1 , This comprises, in a manner known per se, an RC element with an ohmic resistance R _T and a capacitor C.

4 shows a particularly preferred embodiment for a low pass TP _i . This includes the series connection of two ohmic resistors R _T1 , R _T2 and again a capacitor C _T. To limit the current, two electronic switches S _T1 , S _{T2 are} provided, wherein the transistor S _{T2 is formed} complementary to the transistor S _T1 . The control electrodes of the transistors S _T1 , S _T2 are coupled to a pole P1, via which the resistor R _T2 is coupled to the capacitor C _T. The reference electrodes of the transistors S _T1 , S _T2 are coupled to a pole P2, via which the resistor R _T2 is coupled to the resistor R _T1 . While the collector of the transistor S _T1 is coupled to the input voltage U _e , the collector of the transistor S _{T2 is} coupled to the reference potential.

5 shows a schematic representation of two coordinated switching operations within the LED string. In the present example, the LED1 is turned on while the LED2 is turned off. As a result of the low-passes TP1, TP2, the respective switching operation is extended to the time duration Δt, that is, within the period Δt, the current I ₁ goes from its nominal value I _N back to zero, while at the same time the current I ₂ rises from zero to its nominal value I _N , Due to the temporal coordination of these two switching operations, the voltage U ₀ remains substantially constant throughout the switching process.

Claims (7)

Circuit arrangement for operating a plurality of LEDs with - a supply voltage terminal (U _V ) for coupling to a DC supply voltage (U _a ); A reference potential terminal for coupling to a reference potential; - A current source (I ₀ ), which is coupled to the reference potential terminal; - The series circuit of at least a first (LED1) and at least one second LED (LED2), wherein the at least one first LED (LED1) a first bypass device (BP1a) and the at least one second LED (LED2) a second bypass device (BP2a) connected in parallel wherein the first (BP1a) and the second bypass device (BP2a) each have a control terminal, the parallel connection of the at least one first LED (LED1) and the first bypass device (BP1a), the parallel connection of the at least one second LED (LED2) and the second bypass device (BP2a) and the current source (I ₀₎ in series between the supply voltage terminal (U _V) and said reference potential terminal is coupled; A PWM generator ( 12 ) having at least a first output (A1) coupled to the control port of the first bypass device (BP1a) and at least one second output (A2) coupled to the control port of the second bypass device (BP2a); and a level converter device ( 14 ) with at least one first level converter (PW1) connected between the first output (A1) of the PWM generator ( 12 ) and the control terminal of the first bypass device (BP1a), and a second level converter (PW2) connected between the second output (A2) of the PWM generator ( 12 ) and the control port of the second bypass device (BP2a); - Wherein the first (PW1) and the second level converter (PW2) are designed as Konstantstromsenke, - and the first level converter (PW1) comprises a first electronic switch having a control electrode, a reference electrode and a working electrode, wherein the working electrode with the control terminal of the first Bypass device (BP1a) whose control electrode is connected to the first output (A1) of the PWM generator ( 12 ) and whose reference electrode is coupled to the reference potential terminal via a first ohmic resistor (R ₁ ), the second level converter (PW 2) comprising a second electronic switch having a control electrode, a reference electrode and a working electrode, the working electrode thereof being connected to the control terminal of the second bypass device (BP2a) whose control electrode is connected to the second output (A2) of the PWM generator ( 12 ) and whose reference electrode is coupled to the reference potential terminal via a second ohmic resistor (R ₂ ); - wherein the first (BP1a) and the second bypass device (BP2a) is designed as an adjustable bypass device, wherein between the first output (A1) of the PWM generator ( 12 ) and the control electrode of the first electronic switch first low pass (TP1) is coupled, wherein between the second output (A2) of the PWM generator ( 12 ) and the control electrode of the second electronic switch is coupled to a second low-pass filter (TP2); - Wherein the first (TP1) and / or the second low-pass filter (TP2) is designed as RC low-pass filter; - wherein the RC low-pass filter comprises the series connection of a third (R _T2 ) and a fourth ohmic resistance (R _T1 ), wherein the third ohmic resistance (R _T2 ) between the capacitor (C _T ) of the RC low-pass and the fourth ohmic resistance (R _T1 ) is coupled and wherein the third ohmic resistor (R _T2 ) is coupled to a current limiting device. Circuit arrangement according to Claim 1, characterized in that the PWM generator ( 12 ) is designed to temporally coordinate a rising edge at at least one first output (A1) with a falling edge at at least one second output (A2), and vice versa. Circuit arrangement according to claim 2, characterized in that the temporal coordination takes place in such a way that the rise of the flank and the falling of the flank, and vice versa, proceed in opposite directions. Circuit arrangement according to one of claims 2 or 3, characterized in that the temporal coordination takes place in such a way that the change of the voltage (U ₀ ) dropping across the current source (I ₀ ) during operation of the circuit arrangement remains below a predefinable threshold value, the threshold value in particular a maximum of 10%, preferably a maximum of 5%, more preferably a maximum of 2% of the voltage connected during operation to the supply voltage terminal (U _V ). Circuit arrangement according to one of the preceding claims, characterized in that the current limiting device comprises a first transistor (S _T1 ) and a complementary second transistor (S _T2 ), wherein the control electrodes of the first (S _T1 ) and the second transistor (S _T2 ) with the pole of the third ohmic resistor (R _T2 ) facing the capacitor (C _T ) of the RC low-pass filter, the reference electrodes of the first (S _T1 ) and the second transistor (S _T2 ) being coupled to the output (A1; A2) of the PWM generator ( 12 ) facing the pole of the third ohmic resistor (R _T2 ) are coupled, wherein the working electrode of the first transistor (S _T1 ) with a supply voltage terminal (U _e ) and the working electrode of the second transistor (S _T2 ) is coupled to the reference potential terminal. Circuit arrangement according to one of the preceding claims, characterized in that the first (BP1a) and / or the second bypass device (BP2a) as pnp transistor (BPia), as Darlington circuit (BPib), as complementary Darlington circuit (BPic) or realized as an n-channel transistor (BPid) with built-in protection diode. Circuit arrangement according to one of claims 1 to 5, characterized in that the first (BP1a) and / or the second bypass device (BP2a) comprises an npn transistor (T _d ), wherein the collector of the npn transistor (T _d ) with the Anode of the associated LED (LEDi) and the emitter is coupled to the cathode of the associated LED (LEDi), wherein the first (BP1a) and / or the second bypass device (BP2a) further comprises at least one current mirror device (S _P2 ), wherein the output the current mirror device (S _P2 ) _is coupled to the emitter of the npn transistor (T _d ), the current mirror device (S _P2 ) being designed such that the output current (I _SP2 ) of the current mirror device (S _P2 ) is proportional to the base current ( I _b ) of the npn transistor (T _d ) corresponds and with respect to its direction against the base current (I _b ) of the npn transistor (T _d ) is poled.

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