DE102018108598A1 - Semiconductor device and method - Google Patents

Abstract

In a first and a second region of a substrate nanowire and ridge components are formed. To form the devices, alternating layers of a first and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then without simultaneously removing the layers of the first material in the second region, the layers of the first material removed to form nanowires. In the first and second regions, gate structures of gate dielectrics and gate electrodes are formed, so that the nanowire devices are formed in the first region and the ridge devices in the second region.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the priority of provisional U.S. Patent Application No. 62 / 552,737 entitled "Semiconductor Device and Method", filed on Aug. 31, 2017, and incorporated herein by reference in its entirety.

GENERAL PRIOR ART

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

The semiconductor industry further improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by further reducing the minimum feature size, thereby allowing more components to be integrated into a particular area. However, reducing the minimum feature size involves additional problems that must be solved.

list of figures

• Die 1A und 1B stellen eine Ausbildung abwechselnder Schichten aus einem ersten und einem zweiten Halbleitermaterial gemäß einigen Ausführungsformen dar.
• 2 stellt eine Ausbildung erster und zweiter Ausnehmungen gemäß einigen Ausführungsformen dar.
• 3 stellt eine Ausbildung von E/A-Öffnungen gemäß einigen Ausführungsformen dar.
• 4 stellt eine Ausbildung eines gemeinsamen Spacers gemäß einigen Ausführungsformen dar.
• 5 stellt eine Ausbildung von ersten und zweiten Innenspacern gemäß einigen Ausführungsformen dar.
• 6 stellt eine Ausbildung von Source/Drain-Gebieten gemäß einigen Ausführungsformen dar.
• 7 stellt eine Ausbildung eines Zwischenschichtdielektrikums gemäß einigen Ausführungsformen dar.
• 8 stellt ein Entfernen einer Dummy-Gate-Elektrode gemäß einigen Ausführungsformen dar.
• Die 9A und 9B stellen ein Entfernen eines ersten Materials gemäß einigen Ausführungsformen dar.
• Die 10A und 10B stellen ein Entfernen eines zweiten Materials gemäß einigen Ausführungsformen dar.
• 11 stellt eine Ausbildung einer Gate-Struktur gemäß einigen Ausführungsformen dar.
• 12 stellt ein Bauelement gemäß einigen Ausführungsformen dar, das ein einziges erstes Material für einen Grat (engl. „fin“) benutzt.

Aspects of the present disclosure are best understood when the following detailed description is studied in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with industry standard practice. Rather, the dimensions of the various features may be arbitrarily increased or decreased for purposes of illustration.

• The 1A and 1B illustrate formation of alternating layers of first and second semiconductor materials according to some embodiments.
• 2 FIG. 12 illustrates a formation of first and second recesses according to some embodiments. FIG.
• 3 FIG. 12 illustrates a configuration of I / O openings according to some embodiments. FIG.
• 4 FIG. 12 illustrates a formation of a common spacer according to some embodiments. FIG.
• 5 FIG. 12 illustrates a configuration of first and second inner spacers according to some embodiments. FIG.
• 6 FIG. 12 illustrates a formation of source / drain regions according to some embodiments. FIG.
• 7 FIG. 12 illustrates a formation of an interlayer dielectric according to some embodiments. FIG.
• 8th FIG. 10 illustrates removal of a dummy gate electrode according to some embodiments. FIG.
• The 9A and 9B illustrate removal of a first material according to some embodiments.
• The 10A and 10B illustrate a removal of a second material according to some embodiments.
• 11 FIG. 12 illustrates a formation of a gate structure according to some embodiments. FIG.
• 12 FIG. 12 illustrates a device according to some embodiments that uses a single first material for a fin.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various features of the invention. Hereinafter, to simplify the present disclosure, specific examples of components and arrangements will be described. These are of course only examples that should not be limiting. In the following description, to form a first feature on or at a second feature may include, for example, embodiments in which the first and second features are formed in direct contact, and embodiments in which additional features are formed between the first and second features so that the first and second features are not in direct contact. Additionally, in the present disclosure, reference numerals and / or reference numbers may be repeated in the various examples. This repetition is for simplicity and clarity and as such does not dictate any relationship between the various illustrated embodiments and / or configurations.

Spatially related terms such as "below", "below", "lower", "above", "above", "upper" r "and the like may also be used herein to simplify the description for purposes of describing the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. The spatial reference terms are intended to include, in addition to the orientation depicted in the figures, various orientations of the device in use or operation. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially related descriptors used herein may also be interpreted accordingly.

Embodiments relating to the integration of short channel horizontal gate all-around nanowire transistors and long channel non-nanowire fin long channel transistors will now be described Transistor) for use in the design and operation of integrated circuits. Such embodiments contribute to avoiding performance degradation of long channel devices due to the problems associated with filling limited space. However, embodiments may be used in various ways and are not intended to be limited to the embodiments described herein.

In 1 an embodiment is shown in which a first semiconductor layer 103 , a second semiconductor layer 105 , a third semiconductor layer 107 , a fourth semiconductor layer 109 , a fifth semiconductor layer 111 , a sixth semiconductor layer 113 , a seventh semiconductor layer 115 and an eighth semiconductor layer 117 on a semiconductor substrate 101 are formed. In an embodiment, the semiconductor substrate may be 101 for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, a III-V material substrate, or a substrate formed of other semiconductor materials, for example, with strong band-to-band tunneling (BTBT). In some embodiments, the semiconductor substrate is 101 around a bulk substrate. In another embodiment, the semiconductor substrate may be 101 to act a semiconductor-on-insulator (semiconductor-on-insulator) substrate.

In one embodiment, the semiconductor substrate 101 a number of different areas. In one embodiment, the semiconductor substrate 101 for example, a core area 102 and an I / O area 104. In the core area 102 become a first component 106 and a second component 108 designed so that the first component 106 one of the second component 108 having opposite conductivity. For example, in one embodiment, the first device may be 106 to act as an n-type device while the second device 108 can be a p-type device. However, any combination of components may be used.

In addition, in the I / O area 104, a third device may be included 110 be educated. In one embodiment, the third device may be 110 to act a FinFET device, which is formed so that it has a similar conductivity as the first device 106 , The third component 110 For example, in other embodiments it may be a p-type FinFET or may be both an n- and a p-type device. Any suitable combination of components may be used, and all such combinations are intended to be within the scope of the embodiment. The first component 106 , the second component 108 and the third component 110 are described as "devices" in this fabrication step, but this is not intended to imply that they are finished devices, but rather that the structures in said devices are used to form the finally finished devices.

The first semiconductor layer 103 is both on the core substrate and on the I / O area 104 on the semiconductor substrate 101 educated. In an embodiment, the first semiconductor layer is 103 formed of a semiconductor material, which is connected to the semiconductor substrate 101 together to form a ridge 122 or first nanowires 901 and second nanowires 1001 can contribute (in 1A not shown, but below with reference to the 9 and 10 shown and described). The first semiconductor layer 103 For example, silicon germanium (Si _x Ge _1-x , where x is in the range of about 0.01 to about 0.99), silicon, silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, an II- VI compound semiconductor or the like may be formed. Among the available materials for forming the III-V compound semiconductor include, for example, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

To form the first nanowires 901 and the second nanowires 1001 to support, there is the first semiconductor layer 103 however, of a different material than the semiconductor substrate 101 with a different etch selectivity. In an embodiment in which the semiconductor substrate 101 is silicon, is the first Semiconductor layer 103 is formed of a material other than silicon, such as silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, a III-V compound semiconductor, a II-VI compound semiconductor or the like. However, any suitable combination may be used.

The first semiconductor layer 103 can be formed using a growth process such as epitaxial growth. In an embodiment, the material for the first semiconductor layer 103 for example, on the exposed material of the semiconductor substrate 101 to be raised. The growth process can be continued until the first semiconductor layer 103 has a first thickness T ₁ of about 5 nm to about 15 nm. However, any suitable forming process and thickness may be used.

When the first semiconductor layer 103 on the semiconductor substrate 101 may be formed on the first semiconductor layer 103 the second semiconductor layer 105 be formed. In one embodiment, the second semiconductor layer is 105 formed of a semiconductor material, with the first semiconductor layer 103 and the semiconductor substrate 101 together to make the ridge 122 or the first nanowires 901 and the second nanowires 1001 can contribute. The second semiconductor layer 105 For example, silicon, silicon germanium (Si _x Ge _1-x , where x is in the range of from about 0.01 to about 0.99), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, an II- VI compound semiconductor or the like may be formed. Among the available materials for forming the III-V compound semiconductor include, for example, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

To form the first nanowires 901 and the second nanowires 1001 to support, there is the second semiconductor layer 105 however, of a different material than the first semiconductor layer 103 with a different etch selectivity. In an embodiment in which the first semiconductor layer 103 silicon germanium is the second semiconductor layer 105 for example, formed of the same material as the semiconductor substrate 101 by being made of silicon, for example. The second semiconductor layer 105 however, may also be of a different material than both the first semiconductor layer 103 as well as the semiconductor substrate 101 be formed, and any suitable combination can be used.

The second semiconductor layer 105 can be formed using a growth process such as epitaxial growth. In an embodiment, the material for the second semiconductor layer 105 for example, on the exposed material of the first semiconductor layer 103 to be raised. The growth process can be continued until the second semiconductor layer 105 has a second thickness T _{2 of} from about 5 nm to about 15 nm, such as about 10 nm. However, any suitable forming process and thickness may be used.

The third semiconductor layer 107 can be done using a similar material and process as in the first semiconductor layer 103 on the second semiconductor layer 105 be formed. In the third semiconductor layer 107 For example, it may be a material such as silicon germanium formed using an epitaxial growth process having a thickness of about 5 nm to about 15 nm. However, any suitable process, material, and thickness may be used.

The fourth semiconductor layer 109 can be done using a similar material and process as the second semiconductor layer 105 on the third semiconductor layer 107 be formed. In the fourth semiconductor layer 109 For example, it may be a material such as silicon that is formed using an epitaxial growth process having a thickness of about 5 nm to about 15 nm. However, any suitable process, material, and thickness may be used.

The fifth semiconductor layer 111 can be done using a similar material and process as in the first semiconductor layer 103 on the fourth semiconductor layer 109 be formed. In the fifth semiconductor layer 111 For example, it may be a material such as silicon germanium formed using an epitaxial growth process having a thickness of about 5 nm to about 15 nm. However, any suitable process, material, and thickness may be used.

The sixth semiconductor layer 113 can be done using a similar material and process as the second semiconductor layer 105 on the fifth semiconductor layer 111 be formed. In the sixth semiconductor layer 113 For example, it may be a material such as silicon that is formed using an epitaxial growth process having a thickness of about 5 nm to about 15 nm. However, any suitable process, material, and thickness may be used.

The seventh semiconductor layer 115 can be done using a similar material and process as in the first semiconductor layer 103 on the sixth semiconductor layer 113 be formed. In the seventh semiconductor layer 115 For example, it may be a material such as silicon germanium formed using an epitaxial growth process having a thickness of about 5 nm to about 15 nm. However, any suitable process, material, and thickness may be used.

The eighth semiconductor layer 117 can be done using a similar material and process as the second semiconductor layer 105 on the seventh semiconductor layer 115 be formed. At the eighth semiconductor layer 117 For example, it may be a material such as silicon that is formed using an epitaxial growth process having a thickness of about 5 nm to about 15 nm. However, any suitable process, material, and thickness may be used.

By forming the first semiconductor layer 103 , the second semiconductor layer 105 , the third semiconductor layer 107 , the fourth semiconductor layer 109 , the fifth semiconductor layer 111 , the sixth semiconductor layer 113 , the seventh semiconductor layer 115 and the eighth semiconductor layer 117 on the semiconductor substrate 101 Alternate layers of semiconductor material are formed, with layers of a first material (eg, silicon) being formed between layers of a second material (eg, silicon germanium). Such a stack of semiconductor materials may be used to form a burr 122 in the I / O area 104 and for forming the first nanowires 901 and the second nanowires 1001 in the core area 102 be used.

When the first semiconductor layer 103 , the second semiconductor layer 105 , the third semiconductor layer 107 , the fourth semiconductor layer 109 , the fifth semiconductor layer 111 , the sixth semiconductor layer 113 , the seventh semiconductor layer 115 and the eighth semiconductor layer 117 on the semiconductor substrate 101 have been formed, each of these semiconductor layers and the semiconductor substrate 101 for forming the ridge 122 structured. In one embodiment, the layers may be formed by applying a second photoresist (in 1A not shown individually) on the eighth semiconductor layer 117 be structured. The second photoresist is then patterned and developed so that on the eighth semiconductor layer 117 a mask is formed, and the mask is then subjected to an etching process such as an anisotropic etching process for transferring the structure of the second photoresist to the underlying layers and forming the ridge 122 used.

After forming the ridge 122 can first isolation areas 135 be formed. In one embodiment, the first isolation regions may be 135 to shallow trench isolation regions, which are formed by depositing a dielectric material such as an oxide material, a HDP (HDP high-density plasma) oxide or the like. The dielectric material, after optional cleaning and coating, may be formed by either a chemical vapor deposition (CVD) process, a high-density plasma CVD process, or other suitable formation process.

In addition, the dielectric material may be used to fill and overfill the spaces between the ridges 122 then deposited and then the excess material removed by a suitable process such as chemical mechanical polishing (CMP), an etch, a combination thereof, or the like. In one embodiment, the removal process also removes the burrs 122 Dielectric material so that by removing the dielectric material, the surface of the burrs 122 is exposed for further processing steps.

If the dielectric material has been deposited, it may then be on the surface of the ridges 122 be exempted. The evisceration may be to expose at least a portion of the to the upper surface of the ridges 122 adjacent sidewalls of the ridges 122 serve. The dielectric material can be wet etched by dipping the top surface of the ridges 122 however, other methods such as reactive ion etch, dry etch, dry oxide removal, or dry chemical cleaning may also be used to exclude material specific etchant with respect to the dielectric material.

However, those of ordinary skill in the art will appreciate that the steps described above may represent only a portion of the overall process flow used to fill and empty the dielectric material. Coating, cleaning, annealing, gap filling steps, combinations thereof and the like may also be used to form the dielectric material. All potential process steps are intended to be within the scope of the present embodiment. In addition, forming the first isolation regions 135 at other times in the manufacturing process, such as before Forming the first semiconductor layer 103 , All such steps and timings are intended to be within the scope of the embodiments.

1A also provides the formation of a dummy gate dielectric 119 and a dummy gate electrode 121 on the eighth semiconductor layer 117 In one embodiment, the dummy gate dielectric 119 by thermal oxidation, chemical vapor deposition, sputtering, or any other method of forming a gate dielectric that is known and used in the art. Depending on the technique for forming the gate dielectric, the thickness of the dummy gate dielectric may increase 119 differ above from the thickness of the dummy dielectric on the sidewall.

The dummy gate dielectric 119 may comprise a material such as silica or silicon oxynitride having a thickness of from about 3 angstroms to about 100 angstroms, such as 10 angstroms. The dummy gate dielectric 119 can be made of a material with high permittivity (high-k material, eg with a relative permittivity of more than 5) such as lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride ( HfON) or zirconia (ZrO ₂ ) or combinations thereof having an equivalent oxide thickness of from about 0.5 angstroms to about 100 angstroms, such as 10 angstroms or less. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials for the dummy gate dielectric may be used 119 be used.

The dummy gate electrode 121 may comprise a conductive material and be selected from a group consisting of polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof or the like. The dummy gate electrode 121 can be deposited by chemical vapor deposition (CVD), sputtering, or other techniques for depositing conductive materials known and used in the art. The thickness of the dummy gate electrode 121 may range from about 5 Å to about 500 Å. The upper surface of the dummy gate electrode 121 may be uneven and prior to patterning the dummy gate electrode 121 or the gate etching can be planarized. At this point, ions can enter the dummy gate electrode 121 be introduced. Ions may be introduced, for example, by ion implantation techniques.

If the dummy gate dielectric 119 and the dummy gate electrode 121 have been trained, they can be structured. In one embodiment, the structuring may be performed by first forming a first hardmask 123 and on the first hardmask 123 a second hard mask 125 is trained. The first hard mask 123 includes a dielectric material such as silicon oxide, silicon nitride, titanium nitride, silicon oxynitride, combinations thereof, or the like. The first hard mask 123 can be formed by a process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable material and method of formation may be used. The first hard mask 123 can be formed in a thickness of about 20 Å to about 3000 Å, such as 20 Å.

The second hard mask 125 includes another dielectric material such as silicon nitride, silicon oxide, titanium nitride, silicon oxynitride, combinations thereof, or the like. The second hard mask 125 can be formed by a process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable material and method of formation may be used. The second hard mask 125 can be formed in a thickness of about 20 Å to about 3000 Å, such as 20 Å.

If the first hard mask 123 and the second hardmask 125 have been trained, they can be structured. In one embodiment, the first hard mask 123 and the second hardmask 125 be structured by first a first photoresist (not shown individually) on the first hard mask 123 and the second hardmask 125 and exposed to a structured energy source (eg, light) to initiate a chemical reaction that alters the physical properties of the exposed portions of the first photoresist. The first photoresist may then be developed by applying a first developer (also not shown individually) to utilize the altered physical properties between the exposed and unexposed areas to selectively remove the exposed or unexposed area.

When the first photoresist has been patterned, it may serve as a mask for patterning the underlying first hardmask 123 and the second hardmask 125 be used. In one embodiment, the first hard mask 123 and the second hardmask 125 For example, be structured with the first photoresist as a mask using one or more reactive Ionenätzprozesse. The structuring process can be continued until the dummy gate electrode 121 under the first hard mask 123 exposed.

If the first hard mask 123 and the second hardmask 125 have been patterned, the first photoresist can be removed thereon. For example, in one embodiment, the first photoresist may be removed by an ashing process in which a temperature of the first photoresist is increased until it thermally decomposes and is easily removed by one or more cleaning processes. However, any other suitable removal process may be used.

If the first hard mask 123 and the second hardmask 125 can be structured to form a series of stacks 129 the dummy gate electrode 121 and the dummy gate dielectric 119 be structured. In one embodiment, the dummy gate electrode becomes 121 and the dummy gate dielectric 119 however, using any anisotropic etching process, such as reactive ion etching, any suitable process can be used.

1A also provides for forming a first spacer layer 127 on the dummy gate electrode 121 and the dummy gate dielectric 119 dar. The first spacer layer 127 can be on opposite sides of the stack 129 be formed. The first spacer layer 127 can be formed by blanket deposition on the already formed structure. The first spacer layer 127 For example, SiN, oxynitride, SiC, SiON, SiOCN, SiOC, oxide, and the like can be included and formed by methods used to form such a layer, such as chemical vapor deposition (CVD), plasma assisted CVD, sputtering, and others in the art known methods.

After forming, a third photoresist (in 1A not shown individually), which forms the first spacer layer 127 in the I / O area 104 while the first spacer layer 127 in the core area 102 exposed. When the first spacer layer 127 is protected in the I / O area 104, it may be in the core area 102 for forming the first spacer 131 at the stacks 129 in the core area 102 be etched. In one embodiment, the first spacers 131 be formed using an anisotropic etching process such as a reactive Ionenätzprozesses.

In addition, when training the first spacer 131 the eighth semiconductor layer 117 in the core area 102 exposed (without the eighth semiconductor layer 117 in the I / O area 104 is exposed). 1A In addition, an etching of the eighth semiconductor layer is provided 117 , the seventh semiconductor layer 115 , the sixth semiconductor layer 113 , the fifth semiconductor layer 111 , the fourth semiconductor layer 109 , the third semiconductor layer 107 , the second semiconductor layer 105 , the first semiconductor layer 103 and the semiconductor substrate 101 to make core openings 133 In one embodiment, the etching of the semiconductor substrate 101 using one or more anisotropic etches such as reactive ion etchings, however, any suitable processes may be used.

In one embodiment, the core openings 133 be formed to have a first width W ₁ of about 10 nm to about 40 nm, such as 20 nm. In addition to this, the core openings 133 be formed so that they to a first depth D ₁ of about 5 nm to about 20 nm, such as 10 nm, in the semiconductor substrate 101 into it. However, any suitable dimensions can be used.

If the core openings 133 have been formed, the third photoresist can be removed. For example, in one embodiment, the third photoresist may be removed by an ashing process in which a temperature of the third photoresist is increased until the second photoresist thermally decomposes and is easily removed by one or more cleaning processes. However, any other suitable removal process may be used.

1B illustrates a cross-sectional view of the structure 1A along the line BB 'dar. As can be seen, the burr 122 on three sides so from the dummy gate dielectric 119 covered that the three sides of the ridge are protected in the manufacturing process at this time. 1B additionally shows that several burrs 122 formed and of the dummy gate dielectric 119 and the dummy gate electrode 121 can be covered.

2 represents a structuring of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 for forming the first inner spacer 501 in this 2 not shown individually, but in relation to 5 shown and explained below). In one embodiment, the structuring of the first semiconductor layer takes place 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 by means of a wet etching with respect to the material of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 (Eg silicon germanium) material-specific etchant without significant removal of the material of the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 (eg silicon). In one embodiment, which is in the first semiconductor layer 103 around silicon germanium and at the second semiconductor layer 105 [Lakune], for example, an etchant such as hydrochloric acid (HCl) can be used for wet etching.

In another embodiment, the patterning of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 using a dry etching process or a combination of a dry and a wet etching process. There may be any suitable process for patterning the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 are used, and all such processes are intended to be within the scope of the embodiments.

In an embodiment, the wet etching process may be a dipping process, a spraying process, a spin-on process, or the like. In addition, the wet etching process may occur at a temperature of from about 400 ° C to about 600 ° C and for a period of from about 100 seconds to about 1000 seconds, such as about 300 seconds. However, any suitable process conditions and parameters may be used.

The etching process may be used to exclude the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 be continued so that ( 111 ) faceted surfaces of first recesses 201 in each layer between the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 be formed. In one embodiment, the first recesses 201 at a first length L ₁ of about 3 nm to about 8 nm, such as 5 nm. However, any suitable measure can be used.

In addition, the first spacer layer protects 127 the structures within the I / O area 104 during the etching process to form the first recesses 201 in the core area 102 is used. In itself, none of the first recesses 201 formed in the I / O area 104. This allows the burr 122 still suitable for use as a FinFET device.

In addition, if the first recesses 201 have been formed, second recesses 203 in the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 be formed. In one embodiment, the second recesses 203 be formed in a similar manner as the first recesses 201 , The second recesses 203 For example, they may be formed by a wet etching process that is one with respect to the material of the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 (eg silicon) material-specific etchant such as TMAH or NH ₃ (in solution) used.

In one embodiment, the wet etching process using TMAH or NH ₃ may be a dipping process, a spraying process, a spin-on process, or the like. In addition, the wet etching process may be performed at a temperature of about 25 ° C to about 100 ° C and for a period of about 10 seconds to about 200 seconds, such as about 30 seconds. However, any suitable process conditions and parameters may be used.

In another embodiment, the first recesses 201 and the second recesses 203 instead of being formed by a single wet etching process using a dry etching process. In yet another embodiment, a combination of wet and dry etching processes may be used to form the first recesses 201 or the second recesses 203 to be used.

3 5 illustrates that I / O openings 303 may be formed in the I / O area 104 when the first recesses 201 and the second recesses 203 in the core area 102 have been trained. In one embodiment, a fourth photoresist (in 3 not shown individually), which are the components in the core area 102 protects while the first spacer layer 127 is exposed in the I / O area 104. When the first spacer layer 127 has been exposed in the I / O area 104, it may be there to form second spacers 301 at the stacks 129 etched in the I / O area 104. In one embodiment, the second spacers 301 be formed using an anisotropic etching process such as a reactive Ionenätzprozesses.

In addition, in the formation of the second spacer 301 the eighth semiconductor layer 117 in the I / O area 104 exposed. 3 In addition, an etching of the eighth semiconductor layer is provided 117 , the seventh semiconductor layer 115 , the sixth semiconductor layer 113 , the fifth semiconductor layer 111 , the fourth semiconductor layer 109 , the third semiconductor layer 107 , the second semiconductor layer 105 , the first semiconductor layer 103 and the semiconductor substrate 101 for forming I / O openings 303. In one embodiment the etching of the semiconductor substrate 101 using one or more anisotropic etches such as reactive ion etching, however, any suitable processes may be used.

In one embodiment, the I / O openings 303 be formed to have a second width W ₂ of about 10 nm to about 100 nm, such as about 30 nm. In addition to this, the I / O openings 303 be formed to penetrate to a second depth D _{2 of} from about 5 nm to about 30 nm, such as 15 nm, into the semiconductor substrate 101 into it. However, any suitable dimensions can be used.

If the I / O openings 303 have been formed, the third photoresist can be removed. For example, in one embodiment, the fourth photoresist may be removed by an ashing process in which a temperature of the fourth photoresist is increased until it thermally decomposes and is easily removed using one or more cleaning processes. However, any other suitable removal process may be used.

4 represents a deposition of a common spacer 401 on the core area 102 as well as the I / O area 104 In one embodiment, the common spacer 401 of a material such as silicon nitride, silicon oxynitride, however, any suitable material such as low k material having a k value of less than about 3.5 may be used. The common spacer 401 can be deposited by a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition at a thickness of about 3 nm to about 10 nm, such as 5 nm. However, any suitable thickness or any suitable deposition process may be used.

Because the common spacer 401 both on the core area 102 As well as being deposited on the I / O area 104, it not only covers the sidewalls of the core openings 133 and the I / O openings 303, but also fills the first recesses 201 and the second recesses 203 that in the core area 102 were trained. The filling of the first recesses 201 and the second recesses 203 supports the formation of the first nanowires 901 and the second nanowires 1001 what's below with reference to the 9A and 10A is described.

5 represents a removal of the common spacer 401 from the core area 102 and the I / O area 104, at the first Innenspacer 501 that the first recesses 201 fill, as well as second Innenspacer 503 stay behind, the second recesses 203 to fill. In one embodiment, removal of the common spacer 401 by using an etching process such as an anisotropic dry etching process such as reactive ion etching. However, any suitable etching process may be used in which the common spacer 401 is removed while the first interior spacer 501 and the second interior spacers 503 remain.

If the common spacer 401 both from the core area 102 has also been removed from the I / O area 104, by means of a wet etching process, residual material from the common spacer 401 (For example, silicon nitride) from the layers (eg, the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 ) are removed.

In addition to this, stay while the common spacer 401 completely removed from the I / O area 104, the first interior spacer 501 back and fill the first recesses 201 in the core area 102 , and the second interior spacer 503 stay behind and fill in the second recesses 203 in the core area 102 , The first interior spacers 501 take on the form of the first recesses 201 and the second interior spacers 503 the shape of the second recesses 203 at. The first interior spacers 501 may be formed so as to have the first length L ₁ and the first thickness T ₁ . In addition to this, the second interior spacers 503 be formed so that they have the first length L ₁ and the second thickness T ₂ . However, any suitable dimensions can be used.

6 provides an education of first epitaxial source / drain regions 601 both in the core area 102 as well as in the I / O area 104 as well as second epitaxial source / drain areas 603 in the core area 102 In one embodiment, the first epitaxial source / drain regions 601 be formed by the second component 108 initially protected for example with a photoresist or other masking material. If the second component 108 Protected, the first epitaxial source / drain regions 601 be formed using a growth process such as a targeted epitaxy process with a material such as silicon. For the epitaxial growth process, precursors such as monosilane, dichlorosilane, monogermin and the like may be used and may take from about 5 minutes to about 120 minutes, such as about 30 minutes.

When the first epitaxial source / drain regions 601 have been formed, by implanting corresponding dopants to supplement the dopants in the rest of the first device 106 and the third device 110 Dopants in the first epitaxial source / drain regions 601 be implanted in it. For example, to form NMOS devices, n-type dopants such as phosphorous (to form SiP), arsenic, antimony or the like may be implanted. These dopants can be made using the stacks 129 , the first spacer 131 and the second spacer 301 be implanted as masks. It should be appreciated that those of ordinary skill in the art will appreciate that many other processes, steps or the like may be used to implant the dopants. For example, one of ordinary skill in the art will appreciate that multiple implants may be made using various combinations of spacers and coatings to form source / drain regions having a specific shape or characteristic suitable for a particular purpose. Any of these processes may be used to implant the dopants, and the above description is not intended to limit the present invention to the steps presented above.

In another embodiment, the dopants of the first epitaxial source / drain regions 601 growing the first epitaxial source / drain regions 601 be introduced. For example, phosphorus may be introduced in place when the first epitaxial source / drain regions 601 be formed. There may be any suitable process for introducing the dopants into the first epitaxial source / drain regions 601 are used, and all such processes are intended to be within the scope of the embodiments.

When the first epitaxial source / drain regions 601 may be formed by removing the protection from the second component 108 (eg by a process such as ashing) and protecting the first device 106 and the third device 110 For example, with a photoresist or other masking material, the second epitaxial source / drain regions 603 be formed. If the first component 106 and the third component 110 protected by a process such as epitaxial growth, the second epitaxial source / drain region 603 may be formed of a material such as silicon germanium, however, any suitable material or process may be used. In addition, either at or after the growth process, dopants such as boron (for a p-type device) may be introduced into the second epitaxial source / drain region 603 be introduced. When the second epitaxial source / drain regions 603 can be formed using a process such as ashing the protection for the first component 106 and the third component 110 be removed.

7 illustrates a formation of an Inter Layer Dielectric (ILD) layer. 701 on the first component 106 , the second component 108 and the third component 110 dar. The ILD layer 701 may comprise a material such as borophosphosilicate glass (BPSG), but any suitable dielectrics may be used. The ILD layer 701 can be formed using a process such as PECVD, but other processes such as LPCVD can alternatively be used. The ILD layer 701 can be formed in a thickness of about 100 Å to about 3,000 Å. If the ILD layer 701 is formed, for example, by using a planarization process such as a chemical-mechanical polishing process with the first spacer 131 and the second spacers 301 can be planarized, however, any suitable process can be used. In addition, the planarization process may also include the second hardmask 125 remove while he's at the first hardmask 123 stops.

8th represents a removal of the first hardmask 123 and removing the dummy gate electrode 121 In one embodiment, the first hardmask 123 using a planarization process such as a chemical mechanical polishing process to remove the material of the first hardmask 123 and planarizing the material of the dummy gate electrode 121 up to the material of the first spacer 131 and the second spacer 301 be removed. However, any suitable method of removing the first hardmask may be used 123 to expose the material of the dummy gate electrode 121 to be used.

If the dummy gate electrode 121 it may be exposed to expose the underlying dummy gate dielectric 119 be removed. In one embodiment, the dummy gate electrode 121 eg, by one or more wet or dry etch processes, which are in view of the material of the dummy gate electrode 121 use material-specific etchant. However, any suitable removal process may be used.

9A represents that the dummy gate dielectric 119 when exposed in the first component 106 (For example, the n-type device) can be removed without it in the second component 108 or the third component 110 Will get removed. In one embodiment, the dummy gate dielectric 119 of the first component 106 by removing a protective material such as a photoresist or other suitable masking material on the second device 108 and the third component 110 is attached. If the second component 108 and the third component 110 are protected, the dummy gate dielectric 119 in the first component 106 For example, using a wet etching process, however, any suitable etching process may be used.

If the dummy gate dielectric 119 from the first component 106 has been removed, the protective material on the second component 108 and the third component 110 be removed. In one embodiment, where the protective material is a photoresist, it may be removed by an ashing process (in which the temperature of the photoresist is increased until decomposition of the photoresist material occurs) or a stripping process. However, any suitable method of removing the protective material may be used.

9A also shows that after removing the dummy gate dielectric 119 from the first component 106 (whereby, as in the cross-sectional view in FIG 9B it is also possible to see the sides of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 exposed) the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 between the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 in the first component 106 can be removed. In one embodiment, the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 be removed by means of a wet etching process, which specifically the material of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 (eg silicon germanium), without the material of the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 (eg silicon) to remove significantly. However, any suitable removal process may be used.

In an embodiment in which the material of the first semiconductor layer 103 around silicon germanium and at the second semiconductor layer 105 is silicon, the removal of the first semiconductor layer 103 For example, by using an etchant, which specifically the material of the first semiconductor layer 103 (eg, silicon germanium) without the material of the second semiconductor layer 105 (eg silicon) to remove significantly. In one embodiment, the etchant may be hot HCl. In addition, the wet etching process may occur at a temperature of from about 400 ° C to about 600 ° C, such as 560 ° C, and for a period of from about 100 seconds to about 1000 seconds, such as about 300 seconds. However, any suitable etchant, any suitable process parameters, and any suitable period of time may be used.

By removing the material of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 are made of the material of the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 in the first component 106 first nanowires 901 in the first component 106 formed by the first interior spacer 501 are separated from each other. The first nanowires 901 include the channel regions of the first device 106 extending between opposing the first epitaxial source / drain regions 601 in the first component 106 extend when this is completed.

9B FIG. 12 illustrates a cross-sectional view of the first component. FIG 106 along the line BB 'in 9A As can be seen, when the dummy gate dielectric 119 has been removed, the sides of the first semiconductor layer 103 , the second semiconductor layer 105 , the third semiconductor layer 107 , the fourth semiconductor layer 109 , the fifth semiconductor layer 111 , the sixth semiconductor layer 113 , the seventh semiconductor layer 115 and the eighth semiconductor layer 117 free. The first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 can themselves be exposed to the etchant and to form the first nanowires 901 be removed between the other layers.

10A represents that when the first nanowires 901 in the first component 106 are formed by removing a portion of the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 between the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 in the second component 108 second nanowires 1001 in the second component 108 can be trained.

In one embodiment, the dummy gate dielectric 119 from the first component 108 be removed by applying a protective material such as a photoresist or other suitable masking material to the first device 106 and the third component 110 is attached. If the first component 106 and the third component 110 are protected, the dummy gate dielectric 119 in the second component 108 For example, using a wet etching process, however, any suitable etching process may be used.

If the dummy gate dielectric 119 from the second component 108 has been removed, the protective material on the first component 106 and the third component 110 be removed. In one embodiment, where the protective material is a photoresist, it may be removed by an ashing process (in which the temperature of the photoresist is increased until decomposition of the photoresist material occurs) or a stripping process. However, any suitable method of removing the protective material may be used.

10A also shows that after removing the dummy gate dielectric 119 from the second component 108 (and, as in 10B is shown, also from the sides of the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 ) the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 between the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 can be removed.

In an embodiment, the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 be removed by means of a wet etching process, which specifically the material of the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 (eg, silicon) without the material of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 (eg silicon germanium) to remove significantly. However, any suitable process can be used.

In an embodiment in which the material of the first semiconductor layer 103 around silicon germanium and at the second semiconductor layer 105 is silicon, the removal of the second semiconductor layer 105 For example, by using an etchant, which specifically the material of the second semiconductor layer 105 (eg, silicon) without the material of the first semiconductor layer 103 (eg silicon germanium) to remove significantly. In one embodiment, the etchant may be for removing the second semiconductor layer 105 to act an etchant such as tetramethylammonium hydroxide (TMAH) or ammonium hydroxide solution. In addition, the wet etching process may be carried out at a temperature of from about 25 ° C to about 100 ° C, such as 30 ° C, and for a period of from about 10 seconds to about 200 seconds, such as about 60 seconds. However, any suitable etchant, any suitable process parameters, and any suitable period of time may be used.

By removing the material of the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 are made of the material of the first semiconductor layer 103 , the third semiconductor layer 107 , the fifth semiconductor layer 111 and the seventh semiconductor layer 115 the second nanowires 1001 in the second component 108 formed by the second interior spacer 503 are separated from each other. The second nanowires 1001 include the channel regions of the second device 108 extending between opposing the second epitaxial source / drain regions 603 in the second component 108 extend when this is completed.

As in 10A can also be seen in the formation of the first nanowires 901 and the second nanowires 1001 within the core area 102 in the first component 106 and the second component 108 the ridge 122 in the third component 110 within the I / O area 104 is unstructured and extends from the semiconductor substrate 101 from consistently between the first epitaxial source / drain regions 601 ,

10B FIG. 3 illustrates a cross-sectional view of the second component. FIG 108 along the line BB 'in 10A As can be seen, when the dummy gate dielectric 119 has been removed, the sides of the semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 free. The semiconductor substrate 101 , the second semiconductor layer 105 , the fourth semiconductor layer 109 , the sixth semiconductor layer 113 and the eighth semiconductor layer 117 can themselves be exposed to the etchant and to form the second nanowires 1001 be removed between the other layers.

11A represents a removal of the dummy gate dielectric 119 in the third component 110 in the I / O area 104 and forming a gate dielectric, respectively 1101 in the first component 106 , the second component 108 and the third component 110 In one embodiment, the dummy gate dielectric 119 in the third component 110 For example, using a wet etching process, however, any suitable etching process may be used.

If the dummy gate dielectric 119 from the third component 110 has been removed, the gate dielectric 1101 be formed. Optionally, prior to forming the gate dielectric, first and second barrier layers (not shown individually) may be formed. In one embodiment, the first barrier may be an interface material such as silicon, but any suitable material may be used. The interfacial material may be deposited by a deposition process such as atomic layer deposition or chemical vapor deposition in a non-zero thickness of less than 20 Å, such as 10 Å. However, any suitable method and thickness may be used.

In one embodiment, the second interface comprises a buffer material such as silicon oxide, but any suitable material may be used. The second barrier layer may be formed by a process such as CVD, PVD, or oxidation in a thickness of about 1 Å to about 20 Å, such as 9 Å. However, any suitable process or thickness may be used.

In one embodiment, the gate dielectric is 1101 a high-k material such as HfO ₂ , HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta ₂ O ₅ , combinations thereof or the like deposited by a process such as atomic layer deposition, chemical vapor deposition or the like. The gate dielectric 1101 can be deposited in a thickness of about 5 Å to about 200 Å, but any suitable material and thickness can be used. As shown, the gate dielectric surrounds 1101 the first nanowires 901 and the second nanowires 1001 and thus forms channel regions of the first component 106 or of the second component 108 ,

When the gate dielectric 1101 is formed, the gate electrode 1103 designed so that they not only cover both the first nanowires 901 (in the first component 106 ) as well as over the second nanowire 1001 (in the second component 108 ) and the eighth semiconductor layer 117 (in the third component 110 ), but the first nanowires 901 (in the first component 106 ) and the second nanowires 1001 (in the second component 108 ) also surrounds. In one embodiment, the gate electrode becomes 1103 formed by a conformal deposition method such as Atomic Layer Deposition (ALD), which fills the gap between the first nanowires 901 and the second nanowires 1001 allows. However, any suitable material or method of formation may be used.

In a further embodiment, the gate electrode 1103 a plurality of layers, each deposited sequentially adjacent to each other, such as a first metal-containing material, a second metal-containing material, a blocking material and a first nucleation layer. The first metal-containing material may be attached to the gate dielectric 1101 may be formed adjacent to a metal material such as silicon doped titanium nitride (TSN), but other suitable materials such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, Metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. In an embodiment where the first metal-containing material is TSN, it may be deposited by a deposition process such as atomic layer deposition, but other suitable processes such as chemical vapor deposition, sputtering or the like may be used. The first metal-containing material may be deposited in a thickness of about 5 Å to about 200 Å, but any suitable thickness may be used.

When the first metal-containing material has been formed, the second metal-containing material may be formed adjacent thereto. In one embodiment, the second metal-containing material may be a workfunction metal such as TiAl, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates , Oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. In addition, the second metal-containing material may be deposited by a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering or the like in a thickness of about 5 Å to about 200 Å, but it may be any one suitable process or any suitable thickness can be used.

The blocking material may be used to block the transition of materials from the third metal-containing material to other regions. In one embodiment, the blocking material may be a material such as titanium nitride, but any other suitable material may be used. The blocking material may be deposited by a process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to a thickness of about 15 Å, however, any suitable deposition process or thickness may be used.

After depositing the blocking material, the first nucleation layer is formed to facilitate a first nucleation of the third metal-containing material. In addition, in one embodiment, the first nucleation layer is formed as a fluorine-free material, which helps to prevent fluorine from transferring to other portions of the structure. In a particular embodiment, where the third metal-containing material is tungsten, the first nucleation layer may be made of a material such as fluorine-free tungsten (FFW).

The third metal-containing material fills a remainder of the opening caused by the removal of the dummy gate electrode 121 arises. In one embodiment, the third metal-containing material is a metal material such as W, Al, Cu, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni However, any suitable process such as atomic layer deposition, sputtering or the like may be used to fill or overfill by removing the dummy gate electrode 121 incurred opening can be used. In a particular embodiment, the third metal-containing material may be deposited to a thickness of about 5 Å to about 500 Å, however, any suitable material, any suitable deposition process, and any suitable thickness may be used. In a particular embodiment, the third metal-containing material may be formed by a chemical vapor deposition process. Any suitable process conditions may be used.

If by removing the dummy gate electrode 121 When the resulting opening has been filled, the materials used to remove the material can be removed by removing the dummy gate electrode 121 resulting opening is planarized. In a particular embodiment, the removal may be accomplished by a planarization process such as chemical mechanical polishing. However, any suitable planarization and removal process may be used.

11A also illustrates that after forming the gate electrode 1103 through the ILD layer 701 passing silicide contacts 1105 and contacts 1107 can be formed, which for electrical connection to the first epitaxial source / drain regions 601 and the second epitaxial source / drain region 603 to care. In one embodiment, the silicide contacts 1105 and the contacts 1107 be formed by first by the ILD layer 701 extending openings (in 11A not shown individually) to the first epitaxial source / drain regions 601 and the second epitaxial source / drain region 603 expose. The openings may be formed, for example, by means of a suitable photolithographic masking and etching process.

The silicide contacts 1105 may include titanium, nickel, cobalt or erbium to reduce the height of the contact's Schottky barrier. However, other metals such as platinum, palladium and the like can also be used. The silicidation can be accomplished by blanketing a suitable metal layer, followed by an annealing step that causes the metal to react with the underlying exposed silicon. Unreacted metal is then removed, for example, with a targeted etching process. The thickness of the silicide contacts 1105 may be about 5 nm to about 50 nm.

In one embodiment, the contacts 1107 may consist of a conductive material such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations thereof, or the like, but it may be formed by a deposition process such as sputtering, chemical vapor deposition Plating, electroless plating or the like for filling and / or overfilling the openings, any suitable material is deposited therein. When filled, material deposited outside the openings may be removed by a planarization process such as chemical mechanical polishing (CMP). However, any suitable material and process may be used to form it.

By forming and using the first nanowires 901 and the second nanowires 1001 in the core area 102 can be achieved with short channel Devices in which the channel can be shorter than 100 nm, achieve high performance. Additionally, by using the embodiments described herein, the disadvantages of forming nanowires (eg, a worse process window for filling the gate structure) can be avoided for long channel devices in the I / O region 104 where the channel is longer than about 100 nm can be.

12 represents a further embodiment, in which, instead of that the third component 110 the stack layer of alternating materials comprises a single material for the burr 122 in the third component 110 is used. In this embodiment, prior to deposition of the gate dielectric 1101 the eighth semiconductor layer 117 , the seventh semiconductor layer 115 , the sixth semiconductor layer 113 , the fifth semiconductor layer 111 , the fourth semiconductor layer 109 , the third semiconductor layer 107 , the second semiconductor layer 105 and the first semiconductor layer 103 be removed using one or more etching processes when the first device 106 and the second component 108 Eg protected with a protective material such as a photoresist.

When the eighth semiconductor layer 117 , the seventh semiconductor layer 115 , the sixth semiconductor layer 113 , the fifth semiconductor layer 111 , the fourth semiconductor layer 109 , the third semiconductor layer 107 , the second semiconductor layer 105 and the first semiconductor layer 103 can be removed using a single material 1201 the ridge 122 to be raised again. In one embodiment, the one material may be a semiconductor material such as silicon, silicon germanium, a III-V material, or the like, which may be doped either during or after formation, eg, in an implantation process. If the burr 122 has regrown, can the gate dielectric 1101 and the gate electrode 1103 be formed as described above.

In one embodiment, a method of fabricating a semiconductor device includes forming a first semiconductor layer on both first and second regions of a semiconductor substrate, the first semiconductor layer comprising a first material, forming a second semiconductor layer on the first and second regions, removing the first semiconductor layer on the first region to form a nanowire channel from the second semiconductor layer, wherein removing the first semiconductor layer from the first region does not remove the first semiconductor layer on the second region, and forming a first gate electrode around the nanowire channel and forming a second gate electrode on the first semiconductor layer and the second semiconductor layer in the second region. In one embodiment, the removal of the first semiconductor layer takes place at least partially by a wet etching process. In one embodiment, prior to removing the first semiconductor layer, the method comprises forming a source / drain region adjacent to the second semiconductor layer. In one embodiment, prior to removing the first semiconductor layer, the method comprises forming a spacer in the first semiconductor layer and between the second semiconductor layer and the semiconductor substrate. In one embodiment, the first and second semiconductor layers in the second region form a semiconductor ridge of a FinFET. In one embodiment, the first semiconductor layer is silicon germanium. In one embodiment, the second semiconductor layer is silicon.

In one embodiment, the method of fabricating a semiconductor device comprises forming a first layer of silicon germanium on a silicon substrate, forming a first layer of silicon on the first layer of silicon germanium, patterning an opening through the first layer of silicon germanium, and the first layer Silicon for dividing the first layer of silicon germanium into a first and a second region, forming a first recess in the first layer of silicon germanium after patterning the opening by the first layer of silicon germanium, filling the first recess with a dielectric material; Removing the first portion of the first layer of silicon germanium without removing the second portion of the first layer of silicon germanium; and simultaneously forming a first dielectric material about the first portion of the first layer of silicon and a second dielectric material on both the second region of the first layer of silicon germanium and the first layer of silicon. In one embodiment, the method includes forming a first dummy gate dielectric on the first layer of silicon germanium and a second dummy gate dielectric on the first layer of silicon germanium. In one embodiment, the method includes removing the first dummy gate dielectric adjacent to the first region of the first silicon germanium layer without removing the second dummy gate dielectric simultaneously. In one embodiment, the method includes forming a first gate electrode around the first layer of silicon and a second gate electrode on both the second region of the first layer of silicon germanium and the first layer of silicon. In one embodiment, forming the first gate electrode and the second gate electrode occurs simultaneously. at In one embodiment, the second region of the first layer of silicon germanium is in an I / O region. In one embodiment, the first dielectric material around the first layer of silicon is in a core region.

In one embodiment, a semiconductor device comprises: a semiconductor substrate having a core region and an I / O region, a first nanowire on a second nanowire in the core region, a first inner spacer separating the first nanowire from the second nanowire, a gate Material located between the first and second nanowires, a channel located in the I / O region, the channel comprising: a first material that is in a first plane with the first nanowire, wherein the first nanowire comprises the first material and a second material located in a second plane with the gate material, wherein the first plane is parallel to the second plane, wherein the second material is different from the first material. In one embodiment, the device comprises a third nanowire on a fourth nanowire in the core region, wherein the third and fourth nanowires are in the second plane and comprise the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is silicon germanium. In one embodiment, the inner spacer comprises silicon nitride. In one embodiment, the inner spacer has a thickness that decreases in a first direction.

The above text provides an overview of features of various embodiments so that the aspects of the present disclosure will be better understood by those skilled in the art. Those skilled in the art will appreciate that they may readily use the present disclosure as a starting point for designing or modifying other processes and structures for the same purposes and / or for achieving the same advantages as the embodiments presented herein. It should also be apparent to those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDE IN THE DESCRIPTION

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Cited patent literature

• US 62552737 [0001]

Claims (20)

A method of fabricating a semiconductor device, the method comprising: Forming a first semiconductor layer on both first and second regions of a semiconductor substrate, the first semiconductor layer comprising a first material, Forming a second semiconductor layer on the first and second regions, Removing the first semiconductor layer on the first region to form a nanowire channel from the second semiconductor layer, wherein removing the first semiconductor layer from the first region does not remove the first semiconductor layer on the second region, and Forming a first gate electrode around the nanowire channel and Forming a second gate electrode on the first semiconductor layer and the second semiconductor layer in the second region. Method according to Claim 1 wherein the removal of the first semiconductor layer is at least partially carried out by a wet etching process. Method according to Claim 1 or 2 further comprising, prior to removal of the first semiconductor layer, forming a source / drain region adjacent to the second semiconductor layer. The method of claim 1, further comprising forming a spacer in the first semiconductor layer and between the second semiconductor layer and the semiconductor substrate before removing the first semiconductor layer. The method of any one of the preceding claims, wherein the first and second semiconductor layers in the second region form a semiconductor ridge of a FinFET. Method according to one of the preceding claims, wherein the first semiconductor layer consists of silicon germanium. Method according to Claim 6 wherein the second semiconductor layer is silicon. A method of fabricating a semiconductor device, the method comprising: Forming a first layer of silicon germanium on a silicon substrate, Forming a first layer of silicon on the first layer of silicon germanium, Patterning an opening through the first layer of silicon germanium and the first layer of silicon for dividing the first layer of silicon germanium into a first and a second area; Forming a first recess in the first layer of silicon germanium after patterning the opening through the first layer of silicon germanium, Filling the first recess with a dielectric material, Removing the first portion of the first layer of silicon germanium without removing the second portion of the first layer of silicon germanium, and simultaneously forming a first dielectric material around the first region of the first layer of silicon and a second dielectric material on both the second region of the first layer of silicon germanium and the first layer of silicon. Method according to Claim 8 further comprising forming a first dummy gate dielectric on the first layer of silicon germanium and forming a second dummy gate dielectric on the first layer of silicon germanium. Method according to Claim 9 further comprising removing the first dummy gate dielectric adjacent the first region of the first silicon germanium layer without simultaneously removing the second dummy gate dielectric. Method according to one of the preceding Claims 8 to 10 further comprising forming a first gate electrode around the first layer of silicon and forming a second gate electrode on both the second region of the first layer of silicon germanium and the first layer of silicon. Method according to Claim 11 wherein the formation of the first gate electrode and the second gate electrode occurs simultaneously. Method according to one of the preceding Claims 8 to 12 , wherein the second region of the first layer of silicon germanium is in an I / O region. Method according to one of the preceding Claims 8 to 13 , wherein the first dielectric material lying around the first layer of silicon is located in a core region. A semiconductor device comprising: a semiconductor substrate having a core region and an I / O region, a first nanowire on a second nanowire in the core region, a first inner spacer separating the first nanowire from the second nanowire, a gate material located between the first and second nanowires, a channel located in the I / O region, the channel comprising: a first material that is in a first plane with the first nanowire, the first nanowire comprising the first material, and a second material that is in a second plane with the gate material, the first plane being parallel to the second Level, wherein the second material is different from the first material. Semiconductor device according to Claim 15 further comprising a third nanowire on a fourth nanowire in the core region, wherein the third and fourth nanowires are in the second plane and comprise the second material. Semiconductor device according to Claim 15 or 16 wherein the first material is silicon. Semiconductor device according to Claim 17 wherein the second material is silicon germanium. Semiconductor component according to one of the preceding Claims 15 to 18 wherein the first inner spacer comprises silicon nitride. Semiconductor component according to one of the preceding Claims 15 to 19 wherein the first inner spacer has a thickness that decreases in a first direction.

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