DE102017103347B4 - PROCESSING OF DATA IN MEMORY CELLS OF A MEMORY - Google Patents

Abstract

Method for reading memory cells from a memory,- in which physical values are determined from a number of n memory cells, where n is at least three, the physical values being points in time,- in which the physical values are at least partially compared with one another,- in which the n memory cells are assigned K different digital memory cell values on the basis of the compared physical values,- in which the digital memory cell values obtained in this way are assigned a code word of an n1, ..., nK-of-n code,- in which the physical values are at least partially among one another are compared, so that an order of at least some of the physical values is determined, in which the K different digital memory cell values are assigned to the n memory cells on the basis of the order.

Description

Various approaches are known for storing data (e.g. binary data) in memory cells of a memory and reading them out from the memory cells of the memory for further processing.

DE 10 2014 112 947 A1 relates to estimating threshold values for state levels in memory cells.

US 2011/0296274 A1 refers to the storage of data in solid state memory. Multi-level memory cells can be used to determine cell rank.

US2013/0176780A1 relates to the detection of errors in data read from memory cells of a flash memory. For error detection, error correlations between multiple bits falling within a sliding window are determined.

The object of the invention consists in improving the handling of the memory and, in particular, in making the storage and/or reading out more efficient.

This object is solved according to the features of the independent claims. Preferred embodiments can be found in particular in the dependent claims.

• - bei dem physikalische Werte aus einer Anzahl von n Speicherzellen bestimmt werden, wobei n mindestens drei ist, wobei die physikalischen Werte Zeitpunkte sind,
• - bei dem die physikalischen Werte zumindest teilweise untereinander verglichen werden,
• - bei dem anhand der verglichenen physikalischen Werte den n Speicherzellen K unterschiedliche digitale Speicherzellenwerte zugeordnet werden,
• - bei dem den so erhaltenen digitalen Speicherzellenwerten ein Codewort eines n₁-, ..., n_K-aus-n-Codes zugeordnet wird,
• - bei dem die physikalischen Werte zumindest teilweise untereinander verglichen werden, so dass eine Reihenfolge zumindest eines Teils der physikalischen Werte bestimmt wird,
• - bei dem anhand der Reihenfolge den n Speicherzellen die K unterschiedlichen digitalen Speicherzellenwerte zugeordnet werden.

To solve the task, a method is specified for reading memory cells from a memory,

• - in which physical values are determined from a number of n memory cells, where n is at least three, the physical values being points in time,
• - in which the physical values are at least partially compared with each other,
• - in which, on the basis of the compared physical values, the n memory cells are assigned K different digital memory cell values,
• - in which a code word of an n ₁ -, ..., n _K -out of n code is assigned to the digital memory cell values obtained in this way,
• - in which the physical values are at least partially compared with one another, so that a sequence of at least some of the physical values is determined,
• - in which the K different digital memory cell values are assigned to the n memory cells based on the sequence.

The following applies in particular: n ≥ 3, n ₁ ≥ 1 to n _K ≥ 1, K ≥ 2 and m ≥ 1.

The number of memory cell values is n, with only K different digital values occurring.

The following also applies: n ₁ +... + n _K = n.

The comparison of the physical values can include a comparison of analog values.

The comparison can be based on the physical values themselves or based on the physical values. In particular, values derived from the physical values can be compared. In this respect, the comparison of the physical values mentioned here also covers comparisons that relate to values that can be derived from the physical values.

Due to the fact that the assignment of digital values to physical values is based on the physical values determined from a number of n memory cells being compared with one another, incorrect assignment of the digital values only rarely occurs. Such an erroneous assignment of the digital values can only occur if the physical values to be compared lie in an overlapping area of the frequency distributions of their values and their order changes during the comparison.

In this case, a first digital memory cell value is determined for n ₁ first memory cells in the sequence and a Kth digital memory cell value is determined for n _K last memory cells in the sequence.

In particular, a digital memory cell value can be assigned depending on the position of the physical values of the sequence.

If a first digital memory cell value is determined for n ₁ first memory cells in the order and n ₁ ≧2, then it may not be necessary to determine an order of the first n ₁ memory cells. In this case, it may be sufficient to determine that a memory cell belongs to the first n ₁ memory cells without having to determine at which position in the order of the first n ₁ memory cells a memory cell is positioned. For example, the same digital value 1 can be assigned to all n ₁ first memory cells.

Corresponding statements apply to further memory cells up to the n _K K-th memory cells. It may be sufficient to determine a partially determined order or an order for a subset of the memory cell values.

In one development, the physical values are determined by reading out the n memory cells.

It is a further development that all physical values are compared with one another.

It is a refinement that K=2, so that the n ₁ ,...,n _K -of-n code is an n ₁ -,n ₂ -of-n code, where n ₁ first memory cell values have the same first value among one another and n ₂ second memory cell values have the same second value among one another, the first value being different from the second value.

The n ₁ -, n ₂ -of-n code can also be referred to as n ₁ -of-n code. Here n ₂ = n - n ₁ applies.

It is a refinement that K=3, so that the n ₁ ,...,n _K -of-n code is an n ₁ -,n ₂ -,n ₃ -of-n code, where n ₁ first memory cell values have the same first value among each other, n ₂ second memory cell values have the same second value among each other and n ₃ third memory cell values have the same third value among each other, the first value, the second value and the third value being different from one another.

It is a further development that K>3 applies.

In this example, more than three values per memory cell, i.e. more than three digital memory cell values, can be determined.

In a development, the memory cell values determined from the memory cells are determined by a uniquely reversible transformation.

In this case, the number n of memory cell values is preferably less than twice the number of bits stored in the memory cells.

It is a further development that the physical values are points in time.

In one development, a point in time is determined in each case by means of a time integration of the physical value of the memory cell.

In one development, the physical value is a read current of a memory cell.

In a further development, if the digital memory cell values obtained represent a code word of an n ₁ -, . . . , n _K -out of n code, a number of m bits are determined from the code word by means of an inverse transformation.

In a further development, error detection and/or error correction of the m bits is carried out using an error code.

In a further development, the error detection and/or error correction is carried out based on check bits, the check bits being determined from the data bits in accordance with the error code.

In one development, the error detection and/or error correction is performed on the basis of check bits, the check bits being determined from the memory cell values in accordance with the error code.

In one development, the error code is a byte error-correcting and/or a byte error-detecting code.

In one development, a byte comprises m bits when error correction of data bits takes place and in which a byte comprises n bits when error correction of memory cells takes place.

In one development, the error code is a bit error-correcting and/or bit error-detecting code.

In a development, at least one reference value is used to determine the digital memory cell values.

• - einen Cache-Speicher,
• - ein Register oder ein Register-Array,
• - einen Flash-Speicher,
• - ein MRAM,
• - ein SRAM,
• - ein RE-RAM,
• - ein PC-RAM,
• - ein FE-RAM,
• - ein CB-RAM,
• - einen Multibit-Speicher,
• - einen Multilevel-Speicher.

In a further development, the memory comprises at least one of the following memory types:

• - a cache memory,
• - a register or a register array,
• - a flash memory,
• - an MRAM,
• - a SRAM,
• - a RE RAM,
• - a PC RAM,
• - a FE RAM,
• - a CB RAM,
• - a multibit memory,
• - a multilevel memory.

• - physikalische Werte aus einer Anzahl von n Speicherzellen zu bestimmen, wobei n mindestens drei ist, wobei die physikalischen Werte Zeitpunkte sind,
• - die physikalischen Werte zumindest teilweise untereinander zu vergleichen,
• - anhand der verglichenen physikalischen Werte den n Speicherzellen K unterschiedliche digitale Speicherzellenwerte zuzuordnen,
• - den so erhaltenen digitalen Speicherzellenwerten ein Codewort eines n₁-, ..., n_K-aus-n-Codes zuzuordnen,
• - die physikalischen Werte zumindest teilweise untereinander zu vergleichen und so eine Reihenfolge der physikalischen Werte zu bestimmen,
• - anhand der Reihenfolge der physikalischen Werte den n Speicherzellen die K unterschiedlichen digitalen Speicherzellenwerte zuzuordnen.

Furthermore, a device is proposed for processing memory cells from a memory, in which the device has a processing unit that is set up

• - to determine physical values from a number of n memory cells, where n is at least three, the physical values being points in time,
• - compare the physical values at least partially with each other,
• - assign different digital memory cell values to the n memory cells K on the basis of the compared physical values,
• - to assign a code word of an n ₁ -, ..., n _K -out of n code to the digital memory cell values obtained in this way,
• - compare the physical values at least partially with each other and thus determine a sequence of the physical values,
• - to assign the K different digital memory cell values to the n memory cells on the basis of the sequence of the physical values.

The processing unit mentioned here can in particular be embodied as a processor unit and/or an at least partially hardwired or logical circuit arrangement which is set up, for example, in such a way that the method can be carried out as described herein. Said processing unit can be or comprise any type of processor or calculator or computer with the necessary peripherals (memory, input/output interfaces, input/output devices, etc.).

The above explanations regarding the method apply accordingly to the device. The device can be embodied in one component or distributed in several components.

The above-mentioned object is also achieved by means of a system comprising at least one of the devices described here.

A computer program product is also proposed which can be loaded directly into a memory of a digital computer, comprising program code parts which are suitable for carrying out the steps of the method described here.

A computer-readable storage medium is provided comprising computer-executable instructions suitable for the computer to perform the steps of the method described herein.

The properties, features and advantages of this invention described above and the manner in which they are achieved are described below in connection with a schematic description of exemplary embodiments which are explained in more detail in connection with the drawings. For the sake of clarity, elements that are the same or have the same effect can be provided with the same reference symbols.

• 1a eine Häufigkeitsverteilung für ausgelesene physikalische Werte, wobei ein Referenzwert zwischen den Häufigkeitsverteilungen dargestellt ist;
• 1b eine Häufigkeitsverteilung für ausgelesene physikalische Werte, wobei sich im Gegensatz zu 1a die Häufigkeitsverteilungen überlappen;
• 2a ein Schaubild umfassend mehrere physikalische Werte, die aus den Speicherzellen ausgelesen wurden;
• 2b ein Schaubild mit mehreren Zeitpunkten, wobei je ein Zeitpunkt einem der in 2a dargestellten physikalischen Werte entspricht;
• 3 ein Diagramm, das die Häufigkeitsverteilungen von physikalischen Werten W_G einer Speicherzelle veranschaulicht.
• 4 ein Diagramm, das Häufigkeitsverteilungen von aus dem Speicher gelesenen Werten veranschaulicht;
• 5 ein Diagramm, das vier Häufigkeitsverteilungen von aus dem Speicher gelesenen Werten 0, 1, 2 und 3 veranschaulicht, wobei es für die vier Häufigkeitsverteilungen drei Überlappungsbereiche gibt;
• 6 einen Speicher mit vier Speicherzellen, wobei aus den Speicherzellen physikalische Werte ausgelesen und unter Verwendung von mehreren Vergleichern paarweise verglichen werden;
• 7 eine Schaltungsanordnung anhand derer aus den von der Vergleichern aus der Schaltung gemäß 6 die entsprechenden Belegungen der Speicherzellen bestimmt werden mittels mehrerer Logikgatter;
• 8 ein schematisches Diagramm, bei dem Datenbits transformiert, in Speicherzellen eines Speichers gespeichert, die Speicherzellen gelesen und mittels einer inversen Transformation in Datenbits zurück transformiert werden;
• 9 ein schematisches Schaubild, bei dem mehrere Gruppen von Datenbits transformiert, gespeichert und nach dem Lesen in Datenbits zurück transformiert werden;
• 10 eine beispielhafte Schaltungsanordnung, die eine Fehlererkennung oder eine kombinierte Fehlererkennung mit Fehlerkorrektur ermöglicht, wobei die Datenbits durch eine Transformationsschaltung in Speicherbits transformiert werden, die in Speicherzellen eines Speichers gespeichert werden;
• 11 eine alternative Schaltungsanordnung, die eine Fehlerkorrektur oder eine Fehlererkennung ggf. mit Fehlerkorrektur ermöglicht;
• 12 ein weiteres Beispiel einer Variante der in 11 angedeuteten Schaltungsanordnung mit Rücktransformation und Bestimmung gegebenenfalls korrigierter Datenbits;
• 13 eine beispielhafte Schaltungsanordnung umfassend mehrere Logikgatter zur Bestimmung eines Hold-Signals für mehrere Latches;
• 14 eine beispielhafte Schaltungsanordnung zur Bestimmung der ersten drei schnellsten Nullen beim Auslesen von sechs Speicherzellen, wobei zur Ansteuerung mehrerer Latches das mittels der Schaltungsanordnung aus 13 erzeugte Hold-Signal genutzt wird;
• 15 eine schematische Anordnung zur Veranschaulichung wie Datenbits mittels einer Transformationsschaltung transformiert und als Speicherzellenwerte in Speicherzellen eines Speichers gespeichert werden;
• 16 eine schematische Umsetzung der Anordnung von 15, wobei in 16 beispielhaft n = k = 6, K = 3 und n₁ = n₂ = n₃ = 2 gelten;
• 17 eine schematische Anordnung zur Transformation von vier Datenbits x₁, x₂, x₃, x₄ in vier Speicherzellenwerte z₁, z₂, z₃, z₄.

Show it:

• 1a a frequency distribution for read physical values, wherein a reference value is shown between the frequency distributions;
• 1b a frequency distribution for physical values read out, in contrast to 1a the frequency distributions overlap;
• 2a a chart including a plurality of physical values read from the memory cells;
• 2 B a diagram with several points in time, each point in time corresponding to one of the in 2a corresponds to the physical values shown;
• 3 a diagram that illustrates the frequency distributions of physical values W _G of a memory cell.
• 4 a diagram illustrating frequency distributions of values read from the memory;
• 5 a diagram illustrating four frequency distributions of values 0, 1, 2 and 3 read from the memory, where there are three areas of overlap for the four frequency distributions;
• 6 a memory with four memory cells, physical values being read from the memory cells and compared in pairs using a plurality of comparators;
• 7 a circuit arrangement based on those from the comparators from the circuit according to FIG 6 the corresponding assignments of the memory cells are determined using a plurality of logic gates;
• 8th a schematic diagram in which data bits are transformed, stored in memory cells of a memory, the memory cells are read and transformed back into data bits by means of an inverse transformation;
• 9 a schematic diagram in which several groups of data bits are transformed, stored and transformed back into data bits after reading;
• 10 an exemplary circuit arrangement that enables error detection or combined error detection with error correction, the data bits being transformed by a transformation circuit into memory bits, which are stored in memory cells of a memory;
• 11 an alternative circuit arrangement that enables error correction or error detection, if necessary with error correction;
• 12 Another example of a variant of the in 11 indicated circuit arrangement with inverse transformation and determination of possibly corrected data bits;
• 13 an exemplary circuit arrangement comprising a plurality of logic gates for determining a hold signal for a plurality of latches;
• 14 an exemplary circuit arrangement for determining the first three fastest zeros when reading six memory cells, with the circuit arrangement being used to control a plurality of latches 13 generated hold signal is used;
• 15 a schematic arrangement to illustrate how data bits are transformed by means of a transformation circuit and stored as memory cell values in memory cells of a memory;
• 16 a schematic implementation of the arrangement of 15 , where in 16 by way of example, n=k=6, K=3 and _n1 = _n2 = _n3 =2;
• 17 a schematic arrangement for the transformation of four data bits x ₁ , x ₂ , x ₃ , x ₄ into four memory cell values z ₁ , z ₂ , z ₃ , z ₄ .

A memory cell can assume different physical values or states corresponding to different digital values.

A value of a physical quantity G of a memory cell S is denoted by W _G and a digital value of the memory cell S is denoted by W _D .

The digital value W _D can be binary and thus can assume one of two values, which can be denoted by 0 and 1. A digital value is in particular one of a finite number of values.

It is also possible that the digital value W _D can assume more than two different values. For example, a digital value can take on three different values; in this case these different digital values can be denoted by 0,1,2. In general, a digital value K with K≧2 can assume different values. These K different values can be denoted by 0,1,...,K-1. A memory that has memory cells that can store more than two digital memory cell values is also referred to herein as a multi-valued memory or multi-level memory. The associated memory cells can be referred to as multi-valued or multi-level memory cells.

Correspondingly, a memory with memory cells that store two digital values can be referred to as a binary memory and the corresponding memory cells can be referred to as binary memory cells.

A physical value read from the memory cell S is denoted by W _A .

For example, the physical value or state of a memory cell can be an electrical resistance value. Accordingly, two resistance values can be differentiated in binary: For example, a larger resistance value can correspond to the digital value 0 and a smaller resistance value to the digital value 1. In another example, the larger resistance value can correspond to the digital value 1 and the smaller resistance value can correspond to the digital value 0.

If more than two digital values are stored in a memory cell, they can be scaled accordingly (in the direction of the larger or smaller resistance values): For example, a largest resistance value can have the digital value 0, a second-largest resistance value the digital value 1, and a third-largest resistance value the digital value 2, etc. and finally a smallest resistance value can be assigned to the digital value K−1 (here again K digital values can be stored in the memory cell S).

When a memory cell S is read, an analog physical value W _A is determined, which depends on the physical value W _G that was generated when the digital value W _D was written or stored.

If there are no errors, the corresponding digital value W _D can be determined from the physical value W _A that has been read out.

If different electrical resistance values correspond to different states of the memory cell S, as is the case with an MRAM, for example, then the stored physical value W _G is a resistance value and the physical value W _A read can be a current or a voltage.

For example, when reading out memory cells, at least one reference value R can be used, which is the same for all or for a plurality of memory cells read out. Optionally, the (at least one) reference value can (also or partially) be made available externally. The value W _A read from a memory cell can be compared with the reference value R.

In the following, by way of example, reference is made in particular to binary memory cells which can store two different digital values 0 and 1. Correspondingly, however, memory cells can also be provided which can each store more than two digital values.

If a larger resistance value corresponds to the binary value 0 and a smaller resistance value to the binary value 1, then a smaller read value _WA of a current corresponds to the digital value 0 and a larger read value _WA of the current corresponds to the digital value 1.

Accordingly, it is an option that when a memory cell is read, a voltage is determined as the value W _A read out, the level of which depends on whether the binary value 0 or the binary value 1 was previously written into the memory cell.

If the digital value W _D is determined by comparing the read value W _A with a single corresponding reference value R, the digital value W _D can be: $$W_D=\{\begin{array}{ccc}0& \text{for}& W_A<\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">R</figure-callout>}\\ 1& \text{for}& W_A>R\end{array}$$

If a digital value 0 is written to several memory cells, the memory cells written to assume different physical values W _G , for example due to statistical fluctuations (e.g. process fluctuations in production), which all correspond to the digital value W _D = 0 in the error-free case and the can be described by a frequency distribution. Correspondingly, the values W _A that are read out also assume different values according to a frequency distribution.

This statement applies analogously to memory cells in which a digital value 1 or another value is written: If the digital value 1 is written to several memory cells, the memory cells written take on different values, for example due to statistical fluctuations (e.g. process fluctuations in production). physical values W _G , which all correspond to the digital value W _D =1 in the error-free case and which can be described by a frequency distribution. Correspondingly, the values W _A that are read out also assume different values according to a frequency distribution.

If it is possible to store more than one bit in a memory cell, then these statements apply accordingly to all digital values that can be stored in each of the memory cells.

1a FIG. 1 shows, by way of example, a frequency distribution 101 for the values W _A (1) read out, which correspond to the digital value 1, and a frequency distribution 102 for the values W _A (0) read out, which correspond to the digital value 0. The different values WA read out are shown on the x-axis and the frequencies of the values _WA read out are shown _on the y-axis. A reference value R between the frequency distributions 101 and 102 is also shown.

in the in 1a In the example shown, there is no overlap between the frequency distributions 101 and 102. There is therefore no erroneous assignment of the binary values 0 and 1. In other words, using the reference value R, there is a clear and error-free assignment of the read value W _A to the respective binary value 0 or 1 possible if no read error occurs.

In this example, it is assumed in simplified form that there are no incorrect assignments due to the effects of radiation or heating.

1b FIG. 1 shows an example of a frequency distribution 103 for the read values W _A (1), which correspond to the digital value 1, and a frequency distribution 104 for the read values W _A (0), which correspond to the digital value 0. A reference value R between the frequency distributions 103 and 104 is again shown.

In contrast to the in 1a In the frequency distributions 101 and 102 illustrated, the frequency distributions 103 and 104 overlap. Such an overlap can occur, for example, in the case of MRAM memory cells. In 1b an overlap area 105 is shown; this is also denoted by [0,1] _A.

If a read value _WA is assigned the binary value 0 if _WA < R and if the value _WA is assigned the binary value 1 if _WA ≥ R, this assignment may be incorrect if the read value _WA is in the overlap area 105 lies.

Furthermore, errors can occur which are based on the effects of radiation or heat or on permanent errors in memory cells.

Thus, due to the overlapping area 105 using the reference value R, an erroneous assignment can occur with a relevant probability: if a read value _WA that corresponds to a binary value 0 is in the overlapping area 105, W _A >R can apply in about half of the cases , which leads to an incorrect assignment. Correspondingly, the following applies: If a read value W _A , which corresponds to a binary value 1, is in the overlapping area 105, W _A <R can apply in about half of the cases, which also leads to an erroneous assignment.

Therefore, for values W _A that have been read out, if they lie in the overlapping area 105, an associated digital value can be assigned incorrectly. An area 106 shows a portion of the values W _A read out which are erroneously assigned to the binary value 1, although binary values 0 are involved. The frequency with which an erroneous digital value is assigned is therefore essentially determined by the frequency with which the value W _A that has been read lies in the overlapping area 105 . This is disadvantageous in particular for large overlapping areas, such as can occur with modern technologies, for example.

A digital binary value x, which can take the values 0 and 1, can be stored using two memory cells S ¹ and S ² . For example, for x=0 a value 0 can be written (stored) in memory cell ^S1 and a value 1 in memory cell ^S2 and for x=1 a value 1 can be written in memory cell ^S1 and a value 0 in memory cell ^S2 . Conversely, for x=0 a value 1 can be written into memory cell ^S1 and a value 0 into memory cell ^S2 and for x=1 a value 0 can be written into memory cell ^S1 and a value 1 into memory cell ^S2 .

The (physical) values read from the two memory cells S ¹ and S ² can be compared with one another, for example by means of a comparator, in order to determine, if there are no errors, whether the value 0 or the value 1 was stored.

und aus der Speicherzelle S² der physikalische Wert $W_A^2$

gelesen. Gilt $$W_A^1<W_A^2,$$

kann das bedeuten, dass der binäre Wert x = 0 in den beiden Speicherzellen S¹ und S² gespeichert wurde. Gilt $$W_A^1>W_A^2,$$

kann das bedeuten, dass der binäre Wert x = 1 in den beiden Speicherzellen S¹ und S² gespeichert wurde.For example, the storage cell S ¹ becomes the physical value $W_A^{}$${}_1^{}$

and from the storage cell S ² the physical value $W_A^{}$${}_2^{}$

had read. Is applicable $$W_A^1<W_A^2,$$

this can mean that the binary value x = 0 was stored in the two memory cells ^S1 and ^S2 . Is applicable $$W_A^1>W_A^2,$$

this can mean that the binary value x = 1 was stored in the two memory cells S ¹ and S ² .

miteinander und nicht mit einem Referenzwert verglichen. Dadurch kann die Wahrscheinlichkeit für das Auftreten eines Fehlers durch gegenseitigen Vergleich der ausgelesenen Werte deutlich reduziert werden.In this example, the read values stored in memory cells S ¹ and S ² become ${\mathrm{<figure-callout\; id="1"\; label="W\; A"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}\text{and}{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

compared with each other and not with a reference value. As a result, the probability of an error occurring can be significantly reduced by mutual comparison of the values read out.

der Zelle S¹ als auch der ausgelesene Wert $W_A^2$

der Zelle S² in dem Überlappungsbereich der Verteilungen W_A(0) und W_A(1) liegen. Dies wird wesentlich seltener der Fall sein, als dass nur einer der beiden ausgelesenen Werte in dem Überlappungsbereich liegt.An error can only occur if both the read value $W_A^{}$${}_1^{}$

of cell S ¹ as well as the read value $W_A^{}$${}_2^{}$

of cell S ² lie in the overlap region of the distributions W _A (0) and W _A (1). This will be the case much more rarely than only one of the two values read out being in the overlapping area.

If, on the other hand, the value read from a memory cell is compared with a reference value, an error can already occur if this one value that has been read lies in the overlapping area of the corresponding distributions.

The disadvantage here is that two memory cells are required for each bit to be stored, ie 2−n memory cells are required for the storage of n bits.

An advantage of the examples presented here is that it makes it possible to store digital values with high reliability using as few memory cells as possible. A further advantage is that an error code can also be used when storing, so that reading errors can be at least partially recognized and/or corrected.

Transformation of data bits into memory cell values

For example, 2 ^k possible assignments of k bits are transformed into n memory cell values. The memory cell values are stored in n memory cells, for example in memory cells of an addressable memory.

The n memory cell values stored in n memory cells can be read out from the n memory cells, and the read out n memory cell values can be transformed back into the k data bits when there is no error.

The memory cell values can be binary values (e.g. the values 0 and 1). In this case, binary values are stored in the memory cells of the memory. These memory cells can then be referred to as binary memory cells.

It is also possible that each of the memory cell values K can assume different values. In contrast to the binary memory cell values, each memory cell value can have more than two values. Thus: K > 2, where the K memory cell values are 0,1,...,K-1. If, for example, three-valued memory cells are provided which can store correspondingly three-valued memory cell values, one of the values 0, 1 or 2 can be assigned to each memory cell value.

It is also possible that i memory cells can store different K _i -valued values (binary or multi-valued, ie K _i ≧2). For example, at least two memory cells can be provided, of which one memory cell stores K ₁ -values and the other K ₂ -values, where K ₁ ≠K ₂ .

Binary memory cell values

First, the case where the memory cell values are binary is considered.

k data bits x ₁ , . . . , x _k are to be transformed into n memory cell values z ₁ , . . . , z _n and stored in n memory cells.

The possible 2 ^k assignments _of the k data bits x _i , . For this purpose, the transformation circuit provides a transformation that maps the 2 ^k assignments of the k data bits into n memory cell values.

The transformation is implemented in such a way that the memory cell values into which the data bits are transformed are code words of an n ₁ -of-n code. A code word of the n ₁ -of-n code has n ₁ first binary values and n ₂ = n - n ₁ second binary values. If the first binary values have the value 1 and the second binary values have the value 0, then a code word of the n ₁ out of n code has a number of n ₁ ones and a number of n ₂ =n−n ₁ zeros .

Accordingly, it is possible for the first binary values to have the value 0 and the second binary values to have the value 1.

Storing the data bits as code words of the n ₁ -out of n code is advantageous since, for example, when reading out the code words of the n ₁ -out of n code stored in the memory cells, greater reliability can be achieved than with data bits stored uncoded.

The n ₁ -of-n code can also be referred to as an n ₁ -,n ₂ -of-n code, where n ₁ denotes the number of first binary values and n ₂ denotes the number of second binary values. Here n ₂ = n - n ₁ . This designation shows that there are two different (here binary) values 0 and 1 in each code word.

$$n_2=n-n_1<n$$

$$n_1+n_2=n$$

$$n_1\ge 1$$

$$n_2\ge 1.$$

The following apply: $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1<n$$

$${\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2=n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1<n$$

$${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2=n$$

$${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1\ge 1$$

$${\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2\ge 1.$$

For example, the number n of memory cell values can be greater than or equal to 3.

If the number of memory cell values is 2 (i.e. if n=2), then the code words of the corresponding 1-of-2 code are 10 and 01. For example, the binary value 0 can be encoded as 10 and the binary value 1 as 01. The disadvantage here is that n=2 memory cells are required to store the information of an individual bit.

verschiedene Codewörter eines n₁-aus-n-Codes.As explained above, there are 2 ^k different assignments of the k data bits. There is also $$\left(\begin{array}{c}n\\ n_1\end{array}\right)$$

different code words of an n ₁ -out of n code.

Codewörter des n₁-aus-n-Codes kann eindeutig umkehrbar erfolgen, so dass auch anhand eines der Codewörter auf die entsprechende Belegung der Datenbits eindeutig rückgeschlossen werden kann, wenn eine Belegung der Datenbits einem der Codewörter zugeordnet ist.The transformation of the 2 ^k assignments of the k data bits into the $\left(\begin{array}{c}n\\ n_1\end{array}\right)$

Code words of the n ₁ -of-n code can be uniquely reversible, so that one of the code words can also be used to unambiguously infer the corresponding occupancy of the data bits if an occupancy of the data bits is assigned to one of the code words.

erfüllt, dann ist eine umkehrbar eindeutige Transformation aller Belegungen der k Datenbits in Codewörter des n₁-aus-n-Codes möglich.There are at least as many different code words as there are data bit assignments, ie is the condition $$2^k\le \left(\begin{array}{c}n\\ n_1\end{array}\right)$$

is met, then a reversible, unique transformation of all assignments of the k data bits into code words of the n ₁ -of-n code is possible.

erfüllt ist, um umkehrbar eindeutig den tatsächlich auftretenden Belegungen Codewörter zuzuordnen.It is also possible that, depending on the application, not all of the 2 ^k possible assignments of the k data bits occur. If this is the case and a value Anz < 2 ^k indicates the number of allocations that actually occur, all that is required is that the condition $$An\mathrm{e.g}\le \left(\begin{array}{c}n\\ n_1\end{array}\right)$$

is fulfilled in order to reversibly and uniquely assign code words to the assignments that actually occur.

In this way, advantageously less than 2−k memory cells can be used for storing k data bits.

Binary memory cell values: examples

verschiedene Codewörter eines 3-aus-6-Codes, wobei jedes der Codewörter drei Einsen und drei Nullen aufweist. Somit ist es möglich, die unterschiedlichen 16 Belegungen der 4 Datenbits in 16 ausgewählte Codewörter (der insgesamt 20 Codewörter) des 3-aus-6-Codes zu transformieren und in 6 Speicherzellen des Speichers zu speichern.As an example, k=4 data bits are assumed for which there are 2 ^k =2 ⁴ =16 different allocations. For example, if there are n=6 memory cells (n is the number of memory cell values, where each memory cell value is to be stored in a memory cell) and n ₁ =3, then there is $$\left(\begin{array}{c}n\\ n_1\end{array}\right)=\left(\begin{array}{l}6\\ 3\end{array}\right)=\frac{6\cdot 5\cdot 4}{3\cdot 2\cdot 1}=20$$

different codewords of a 3-of-6 code, each of the codewords having three 1's and three 0's. It is thus possible to transform the different 16 assignments of the 4 data bits into 16 selected code words (of the 20 code words in total) of the 3-out-of-6 code and to store them in 6 memory cells of the memory.

verschiedene Codewörter eines 2-aus-6-Codes, bei dem jedes Codewort genau zwei Einsen und vier Nullen aufweist. Eine umkehrbar eindeutige Transformation der 2⁴ = 16 Belegungen der 4 Datenbits in Codewörter des 2-aus-6-Codes ist damit nicht möglich.For n=6 memory cell values and n ₁ =2, only $$\left(\begin{array}{l}n\\ n_1\end{array}\right)=\left(\begin{array}{l}6\\ 2\end{array}\right)=\frac{6\cdot 5\cdot 4}{2\cdot 1}=15$$

different code words of a 2-of-6 code, where each code word has exactly two 1's and four 0's. A reversibly unambiguous transformation of the 2 ⁴ =16 assignments of the 4 data bits into code words of the 2-out-of-6 code is therefore not possible.

If the number of occupancies that actually occurred is, for example, less than or equal to 15, this 2-out-of-6 code can also be used.

Binary memory cell values: grouping of data bits

Codes umkehrbar eindeutig transformiert werden.It is explained below that N data bits are transformed into memory cell values, where N=M*k should apply and M is greater than 1. M groups of k data bits each can thus be formed, with the respective 2 ^k assignments of each group of k data bits in 2 ^k code words of one $\left(\begin{array}{c}n\\ n_1\end{array}\right)$

Codes can be uniquely transformed in an invertible manner.

If the occupancies of M groups of k data bits each are transformed into code words of a respectively identical n ₁ out of n code, this results in M×n memory cell values which can be stored correspondingly in M×n memory cells.

wobei

• - die ersten k₁ Datenbits in Codewörter eines ersten $n_1^1-\text{aus}-n^1-\text{Codes},$
  
• - die zweiten k₂ Datenbits in Codewörter eines zweiten $n_1^2-\text{aus}-n^2-\text{Codes},$
  
  ...
• - die M-ten k_M Datenbits in Codewörter eines M-ten $n_1^M-\text{aus}-n^M-\text{Codes}$
  

transformiert werden können. Dabei können die einzelnen Codes zumindest teilweise voneinander verschieden sein. Optional können unterschiedliche Codes auch dann verwendet werden, wenn die Anzahl der Datenbits pro Gruppe gleich ist.The case in which the M groups each comprise k data bits is described here as an example. Alternatively, it is possible for a first group of data bits to have k ₁ data bits, a second group of data bits to have k ₂ data bits, etc. until an Mth group has k _m data bits. The number of data bits per group k ₁ , k ₂ , . . . , _km can at least partially differ from one another. Thus applies $$N=k_1+k_2+...+k_M,$$

whereby

• - the first k ₁ data bits in code words of a first $n_1^1-\text{out of}-n^1-\text{codes},$
  
• - the second k ₂ data bits into code words of a second $n_1^2-\text{out of}-n^2-\text{codes},$
  
  ...
• - the Mth k _M data bits in codewords of an Mth $n_1^M-\text{out of}-n^M-\text{codes}$
  

can be transformed. The individual codes can be at least partially different from one another. Optionally, different codes can also be used if the number of data bits per group is the same.

For example, if the number of data bits k=3, there are 2 ^k =8 possible allocations of the 3 data bits. With n=5 memory cell values, both a 2-of-5 code and a 3-of-5 code can be used, since these two codes each have 10 code words and therefore more code words than possible bele provide services. For example, the 2-of-5 code can be used for a first group of 3 data bits and the 3-of-5 code can be used for a second group of 3 data bits.

As explained, it is an option that the groups of data bits do not all have the same number k of data bits. For example, 23 data bits are to be transformed into memory cell values: 5 groups each with 4 data bits and one group with 3 data bits can be formed from the 23 data bits. The 2 ⁴ =16 possible assignments of the respective group with 4 data bits can be transformed, for example, into code words of a 3-out-of-6 code, which has 20 different code words. The remaining group with 3 data bits has 2 ³ = 8 possible assignments. For example, these 3 data bits can be transformed into code words of a 3-of-5 code having 10 code words. As a result, one memory cell less is required than if the 2 ³ =8 possible assignments of the 3 data bits were also transformed into code words of the 3-out-of-6 code. It is also possible, for example, to supplement the group of 3 data bits with a constant bit, eg a bit with the value 0, resulting in 4 data bits, so that all groups have the same number of data bits and the same transformation can therefore be used . This can reduce circuit design effort.

Multivalued memory cell values

The case should now be considered in which memory cell values can assume more than two different values and that accordingly the memory cells can store multi-valued memory cell values.

A memory cell should be able to store K different memory cell values, where K > 2 (K=2 would be the special case of binary memory cell values). The different memory cell values per memory cell can be denoted by 0, 1, . . . , K-1.

• - n₁ erste Werte,
• - n₂ zweite Werte, ...
• - n_K K-te Werte

auf. Beispielsweise können

• - die ersten Werte mit 0,
• - die zweiten Werte mit 1, ...
• - die K-ten Werte mit K - 1

bezeichnet sein.Again k data bits are to be stored. The 2 ^k different assignments of the k data bits can be uniquely transformed into n memory cell values in a reversible manner. These n memory cell values have

• - n ₁ first values,
• - n ₂ second values, ...
• - n _K Kth values

on. For example, can

• - the first values with 0,
• - the second values with 1, ...
• - the Kth values with K - 1

be designated.

bezeichnet werden.The n memory cell values can also be referred to as an n-tuple of memory cell values. The n-tuple of n multi-value (here K-value) memory cell values, which have n ₁ first values, n ₂ second values, ...., n _K K-th values, can be used as a code word of a $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-,{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2-,...,n_K-\text{out of}-n-\text{codes}$$

be designated.

The n ₁ -, n ₂ -, ... , n _x - out - n - code has the following number of code words: $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot ...\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2-...-n_{K-1}\\ n_K\end{array}\right).$$

beziehungsweise wenn die Bedingung $$Anz\le \left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot \dots \cdot \left(\begin{array}{c}n-n_1-n_2-\dots -n_{K-1}\\ n_K\end{array}\right),$$

erfüllt ist, sofern der Wert Anz (mit Anz < 2^k) die Anzahl der tatsächlich auftretenden Belegungen der k Bits ist, wie dies in Bezug auf die binäre Speicherzellenwerte vorstehend beschrieben wurde.The 2 ^k occupancies of the k data bits are now to be transformed unambiguously into 2 ^k of these code words of the n ₁ -, n ₂ -, . . . , n _K -out of n codes. This is possible if the condition $$2^k\le \left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot ...\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2-...-n_{K-1}\\ n_K\end{array}\right).$$

respectively if the condition $$An\mathrm{e.g}\le \left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot ...\cdot \left(\begin{array}{c}n-n_1-n_2-...-n_{K-1}\\ n_K\end{array}\right),$$

is satisfied if the value Anz (with Anz<2 ^k ) is the number of occupancies of the k bits that actually occur, as was described above in relation to the binary memory cell values.

Multivalued memory cell values: examples

k = 6 data bits are to be stored. Thus there are 2 ^k = 2 ⁶ = 64 possible assignments of the 6 data bits. As described, the data bits are binary values and are previously subjected to a transformation for storage in the multi-value memory cells.

verschiedene Codewörter des hier beispielhaft verwendeten 2-,2-,2-aus-6-Codes. Diese 90 Codewörter reichen aus, um die 2⁶ = 64 möglichen Belegungen der 6 Datenbits abzubilden.For example, 3-valued memory cell values (K=3) are considered. Thus each memory cell can store three different values. A total of n=6 memory cell values (and thus 6 memory cells) are given and n ₁ = n ₂ = n ₃ = 2 is assumed. So there is $$\left(\begin{array}{l}6\\ 2\end{array}\right)\cdot \left(\begin{array}{l}4\\ 2\end{array}\right)\cdot \left(\begin{array}{l}2\\ 2\end{array}\right)=90$$

different code words of the 2, 2, 2 out of 6 code used here as an example. These 90 code words are sufficient to map the 2 ⁶ = 64 possible assignments of the 6 data bits.

The multi-value memory cells allow more efficient use compared to the binary memory cells since more than two values can be stored per memory cell. A small number of physical memory cells is therefore sufficient: In the present example, 90 code words of the 2, 2, 2-out-of-6 code can be formed with only 6 three-value memory cells, whereas only 20 code words of a 3-out code can be formed with 6 binary memory cells -6 codes can be formed.

In each code word of the 2, 2, 2 out of 6 code assumed here as an example, one of the values 0, 1 and 2 occurs twice. Examples of code words are: 001122, 101220, 021210.

Codewörter 012, 021, 102, 120, 201 und 210 auf. Sollen k = 2 Datenbits gespeichert werden, dann können 2² = 4 unterschiedliche Belegungen in den 3 Speicherzellen als Codewörter des 1-,1-,1-aus-3-Codes gespeichert werden.In another example, a 1, 1, 1 of 3 code is used for 3-valued memory cell values (K=3). This has n=3 memory cells $$\left(\begin{array}{l}3\\ 1\end{array}\right)\cdot \left(\begin{array}{l}2\\ 1\end{array}\right)\cdot \left(\begin{array}{l}1\\ 1\end{array}\right)=6$$

code words 012, 021, 102, 120, 201 and 210. If k=2 data bits are to be stored, then 2 ² =4 different allocations can be stored in the 3 memory cells as code words of the 1, 1, 1 out of 3 code.

verschiedene Codewörter eines 2-,2-,1-,1-aus-6-Codes. Mit diesen 180 Codewörtern können 7 Datenbits mit 2⁷ = 128 möglichen Belegungen in den 6 vierwertigen Speicherzellen gespeichert werden.In a further example, four-valued memory cell values K=4 are considered. Each memory cell can store one of the values 0, 1, 2 or 3, for example. There are a total of n=6 memory cells in this example and n ₁ =n ₂ =2 and n ₃ =n ₄ =1 are assumed. Thus there is $$\left(\begin{array}{l}6\\ 2\end{array}\right)\cdot \left(\begin{array}{l}4\\ 2\end{array}\right)\cdot \left(\begin{array}{l}2\\ 1\end{array}\right)\cdot \left(\begin{array}{l}1\\ 1\end{array}\right)=15\cdot 6\cdot 2\cdot 1=180$$

different code words of a 2,2,1,1 out of 6 code. With these 180 code words, 7 data bits with 2 ⁷ = 128 possible assignments can be stored in the 6 four-value memory cells.

Examples of code words of the 2, 2, 1, 1 out of 6 code used here are: 001123, 101320, 031210. Each of the code words has two zeros, two ones, a two and a three.

Multi-valued memory cell values: grouping of data bits

Again consider the case where N data bits are transformed into memory cell values, where N=M*k and M is greater than 1. Thus, M groups of k data bits each can be formed, with the respective 2 ^k assignments of each group of k data bits being reversibly uniquely transformed into 2 ^k code words of an n ₁ -, n ₂ -, . . . , n _x -out of n code become.

If the occupancies of M groups of k data bits each are transformed into code words of the n ₁ -, n ₂ -, ... , n _K -out of n code, this results in M · n K-valued memory cell values, which are correspondingly stored in M . n K-value memory cells are stored.

It can be advantageous to transform the assignments of all groups of k data bits into memory cell values by the same transformation. Then, for example, a transformation circuit can be used multiple times. However, it is also possible to transform the k data bits of the various groups into memory cell values using different transformations.

Writing and reading data bits

The k bits to be stored are also referred to as data bits. These data bits can have, for example, information bits and check bits of a separable error-detecting and/or error-correcting code. Information bits can be supplemented by check bits in a separable code. It is also possible that the data bits are bits of an inseparable code in which the bits of a code word are not divided into information bits and check bits. It is also an option that the data bits include information bits and address bits and/or bits derived from address bits and/or bits of a password.

The term "data bits" is used, for example, to denote the bits to be stored in memory. This can be program code, image data, measurement data or other useful data (payload) that are transformed into memory cell values and stored in memory cells. The memory cell values can be multi-valued or binary.

When reading the memory cells, the digital memory cell values stored in the memory cells are determined using a comparison of physical values output from the n memory cells. Alternatively, they can also be values that are derived from the physical values that are output.

If the n memory cells are binary, the sequence of k bits to be stored is transformed into a sequence of n binary memory cell values having n ₁ first binary values and n ₂ second binary values. If the first binary values are denoted by 1 and the second binary values by 0, then a sequence of k bits to be stored is transformed into a code word of an n ₁ -of-n code and n ₂ =n - n ₁ applies.

gilt.Given n and n _1, k is determined such that $$2^k\le \left(\begin{array}{c}n\\ n_1\end{array}\right)$$

is applicable.

If the memory cells are not binary and a memory cell is used to store K-value digital memory cell values, then a sequence of k bits is transformed into a sequence of n K-value memory cell values, which are stored in the n memory cells. The sequence of n memory cell values is determined such that it comprises a predetermined first number n ₁ of first, mutually identical first memory cell values, a predetermined second number n ₂ of second, mutually identical second memory cell values, etc. up to a predetermined K-th number n _K of Kth mutually identical Kth memory cell values.

und $$n_1+n_2+\dots +n_K=n.$$

applies $$1\le {\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}"><figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout></figure-callout>}}_1\mathrm{,1}\le {\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2,...\mathrm{,1}\le n_K$$

and $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2+...+n_K=n.$$

gilt.Furthermore, k is determined in such a way that $$2^k\le \left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot ...\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-...-n_{K-1}\\ n_K\end{array}\right)$$

is applicable.

A sequence of n K-value memory cell values comprising a predetermined first number n ₁ of first, mutually identical first memory cell values, a predetermined second number n ₂ of second, mutually identical second memory cell values, etc. up to a predetermined K-th number n _K of K-th mutually identical K-th memory cell values can be referred to as a code word of an (n ₁ -, n ₂ -,..., n _K -of-n) code.

bestimmt.The number n _K of mutually identical Kth memory cell values is increased $$n_K=n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2-...-n_{K-1}$$

certainly.

When the memory cells are read, the digital data stored in the memory cells of a group of n memory cells are determined by comparing physical values read from memory cells of the group. Alternatively, the digital data stored in the memory cells of a group of n memory cells are determined by means of a comparison using physical values read out or derived properties.

A temporal behavior of physical values read from different memory cells can also be considered as a property and (also) taken into account for a comparison.

an. Beispielsweise ist der in der Speicherzelle Sⁱ gespeicherte Wert $W_G^i$

ein elektrischer Widerstandswert und der aus der Speicherzelle Sⁱ zum Zeitpunkt τ erhaltene physikalische Wert $W_A^i\left(\tau \right)$

ist ein Lesestrom (eine Stromstärke).At a time τ, a value read from a memory cell S ⁱ takes an analog value $W_A^i\left(\tau \right)$

at. For example, the value stored in memory cell S is ⁱ $W_G^i$

an electrical resistance value and the physical value obtained from the memory cell ^Si at time τ $W_A^i\left(\tau \right)$

is a reading current (an amount of current).

der Speicherzelle Sⁱ kleiner als ein Widerstandswert $W_G^j$

einer anderen Speicherzelle S^j, ist der Lesestrom $W_A^i\left(\tau \right)$

größer als ein Lesestrom $W_A^j\left(\tau \right)$

der anderen Speicherzelle S^j, sofern eine vorgegebene (gleiche) Lesespannung zum Auslesen beider Speicherzellen verwendet wird.Is the resistance $W_G^i$

of the memory cell S ^{i is} less than a resistance value $W_G^j$

another memory cell S ^j , is the read current $W_A^i\left(\tau \right)$

larger than a read current $W_A^j\left(\tau \right)$

the other memory cell S ^j , provided that a predetermined (same) reading voltage is used to read both memory cells.

der Speicherzelle Sⁱ unter Verwendung einer Kapazität C über die Zeit integriert, so ist zu einem Zeitpunkt t_i ein vorgegebener Schwellwert Sw erreicht. Der aus der Speicherzelle Sⁱ erhaltene physikalische Wert ist hier beispielhaft der Lesestrom $W_A^i.$

Der aus dem ausgelesenen physikalischen Wert bestimmte abgeleitete Wert ist beispielhaft der Zeitpunkt t_i, zu dem das Zeitintegral über den Lesestrom den vorgegebenen Schwellwert Sw erreicht.Will the reading stream $W_A^i\left(\tau \right)$

of the memory cell S ⁱ using a capacitance C over time, a predetermined threshold value Sw is reached at a point in time t _i . The physical value obtained from the memory cell ^Si is the read current here, for example $W_A^i.$

The derived value determined from the physical value read is, for example, the point in time t _i at which the time integral over the read current reaches the predetermined threshold value Sw.

der Speicherzelle S^j unter Verwendung der Kapazität C über die Zeit integriert, so ist zu einem Zeitpunkt t_j der vorgegebene Schwellwert Sw erreicht.Will the reading stream $W_A^j\left(\tau \right)$

of the memory cell S ^j using the capacitance C over time, the predetermined threshold value Sw is reached at a point in time t _j .

gilt, gilt auch t_i < t_j und der Schwellwert Sw wird für die Speicherzelle Sⁱ früher erreicht als für die Speicherzelle S^j.Since for the read currents of the memory cells S ⁱ and S ^j $$W_A^i\left(\tau \right)>W_A^j\left(\tau \right)$$

applies, t _i <t _j also applies and the threshold value Sw is reached earlier for the memory cell S ⁱ than for the memory cell S ^j .

kleiner ist als der Widerstandswert $W_G^j.$

It can thus be compared for the memory cells S ⁱ and S ^j whether the integral of the read current of the memory cell S ⁱ reaches the threshold value Sw earlier than the integral of the read current of the memory cell S ^j . This is the case if (at the same voltage) the resistance value $W_G^i$

is less than the resistance value $W_G^j.$

und $W_G^j$

oder ihrer Zustände zu bestimmen. Durch die Zeitpunkte t_i und t_j, zu denen der Schwellwert Sw erreicht wird, können die Speicherzellen entsprechend ihrer Widerstände $W_G^i\text{ und }{W}_G^j$

sortiert werden, d.h. zuerst die Speicherzelle Sⁱ, dann die Speicherzelle S^j (oder umgekehrt).Thus, it is an option, an ordering (or "sequence") of the memory cells Si ^{and Sj} based on the physical values stored in them $W_G^i$

and $W_G^j$

or to determine their states. Due to the points in time t _i and t _j at which the threshold value Sw is reached, the memory cells can, according to their resistances $W_G^i\text{and}{W}_G^j$

are sorted, ie first the memory cell S ⁱ , then the memory cell S ^j (or vice versa).

This approach can be used to sort all memory cells in a group of n memory cells.

If, for example, a binary 0 is written to the first n ₁ memory cells and a binary 1 to the second n ₂ memory cells, the electrical resistance of the first n ₁ memory cells is lower than the electrical resistance of the second n ₂ memory cells if there are no errors, so that the read current of the first n ₁ memory cells is greater than the read current of the second n ₂ memory cells. For example, the following applies here: n ₁ + n ₂ = n.

zu denen für die ersten n₁ Speicherzellen der Schwellwert Sw erreicht wird vor den Zeitpunkten $t_1^2,t_2^2,\dots ,t_{n2}^2,$

zu denen für die zweiten n₂ Speicherzellen der Schwellwert Sw erreicht wird.The times are accordingly $t_1^1,t_2^1,...,t_{n1}^1,$

at which the threshold value Sw is reached for the first n ₁ memory cells before the times $t_1^2,t_2^2,...,t_{n2}^2,$

at which the threshold value Sw is reached for the second n ₂ memory cells.

In this way, the memory cells can be ordered according to the points in time at which the threshold value Sw is reached. For example, the first memory cell can be assigned to the earliest (first) point in time and the nth memory cell can be assigned to the latest (last) point in time. In this example, the first n ₁ memory cells would then just be the memory cells into which a binary 0 value was written, and the n ₂ remaining memory cells would be the memory cells into which a binary 1 value was written.

eine Spannung vⁱ(t) zu einem Zeitpunkt t an in Abhängigkeit der jeweiligen Leseströme $W_A^i$

(mit i = 1,... ,n) für die n Speicherzellen S¹ bis Sⁿ.For example, there is the integral $$v^i\left(t\right)=\frac{1}{C}{\displaystyle {\int }_0^t{W}_A^i\mathrm{i.e}\tau =\frac{t}{C}\cdot W_A^i}$$

a voltage v ⁱ (t) at a time t on depending on the respective read currents $W_A^i$

(with i = 1,...,n) for the n memory cells S ¹ to S ⁿ .

This voltage v ⁱ (t) can be compared to the threshold value Sw. Thus, the points in time at which the above integral reaches the threshold value Sw can be determined. The times obtained can be compared with one another. It is thus possible to determine whether the state of the memory cell corresponds to a binary value of 0 or 1.

und $$v^i\left(t\right)>Sw\text{ für }t>t_i$$

gilt, wobei hierbei beispielhaft der Lesestrom als konstant über die Zeit angenommen wird.The time t _i can be determined by the fact that $$v^i\left(t\right)<Sw\text{for}t<t_i$$

and $$v^i\left(t\right)>Sw\text{for}t>t_i$$

applies, in which case the read current is assumed to be constant over time, for example.

The resistance values or the states of the memory cells can be compared with one another via the read current or the time integral of the read current. Fluctuations in the resistance values within the first n ₁ cells advantageously do not affect the assignment of the binary value 0 to these memory cells as long as these resistance values are not greater than a resistance value of the second n ₂ memory cells are. Accordingly, fluctuations in the resistance values within the second n ₂ cells advantageously do not affect the assignment of the binary value 1 to these memory cells as long as their resistance values are not less than a resistance value of the first n ₁ memory cells.

subgroups of memory cells

For example, it may also not be necessary to determine an order of the n ₁ memory cells with the same first digital values or an order of the n ₂ memory cells with the same second digital values of a group of n memory cells. The n ₁ memory cells with the first digital values form a first subgroup and the n ₂ memory cells with the second digital values form a second subgroup. Each of the subgroups corresponds to a part of the group of n memory cells. An example of such subgroups is explained in more detail below.

In die n₁ Speicherzellen der ersten Teilgruppe wird jeweils ein erster digitaler Wert geschrieben und in die n₂ Speicherzellen der zweiten Teilgruppe wird jeweils ein zweiter digitaler Wert geschrieben, der von dem ersten digitalen Wert verschieden ist.For example, 2 subgroups are considered, where the number of memory cells n ₁ and n ₂ of the subgroups applies: $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2=n.$$

A first digital value is written to each of the n ₁ memory cells of the first subgroup, and a second digital value that differs from the first digital value is written to each of the n ₂ memory cells of the second subgroup.

When reading out the physical values from the memory cells, it can be advantageous not to determine an order between the n ₁ memory cells of the first subgroup, since the same digital value was written into them.

For example, n=6 memory cells S ¹ , . . . , S ⁶ are considered. The memory cells S ¹ , S ² , S ³ are the n ₁ = 3 memory cells of the first subgroup and the memory cells S ⁴ , S ⁵ , S ⁶ are the n ₂ = 3 memory cells of the second subgroup. The memory cells of the first subgroup are written with the value 0 and the memory cells of the second subgroup are written with the value 1.

$$

die aus den Speicherzellen S¹ bis S⁶ ausgelesen wurden. Bei dem physikalischen Wert W_A handelt es sich beispielsweise um einen Lesestrom. 2a shows a diagram comprising several physical values $W_A^1,W_A^2,W_A^3,W_A^4,W_A^5\text{and}{W}_A^6,$

$$

which have been read from the memory cells S ¹ to S ⁶ . The physical value W _A is a read current, for example.

entspricht mit m = 1,... , 6. 2 B shows a diagram with several points in time t ₁ to t ₆ , each point in time t _m corresponding to one of the physical values $W_A^m$

corresponds with m = 1,... , 6.

Time integration of the corresponding read currents can thus be used to determine times t ₁ , t ₂ , t ₃ , t ₄ , t ₅ and t ₆ at which the time integral of the respective read current reaches a predetermined threshold value. For example, according to 2 B : $$t_5>t_4>t_6>{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">t</figure-callout>}}_2>{\mathrm{<figure-callout\; id="3"\; label="t"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">t</figure-callout>}}_3>{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">t</figure-callout>}}_1.$$

gilt. Insbesondere ist es ein Vorteil, dass kein Unterschied zwischen den Zeitpunkten t₄, t₅, t₆ und den Zeitpunkten t₁, t₂, t₃ bestimmt werden muss.The assignment of the digital values 0 or 1 stored in the memory cells S ¹ to S ⁶ can be done by determining that for i = 4,5,6 and for j = 1, 2, 3 $$t_i>t_j.$$

is applicable. In particular, it is an advantage that no difference between the times t ₄ , t ₅ , t ₆ and the times t ₁ , t ₂ , t ₃ has to be determined.

It is thus possible to assign a first digital value to the n ₁ first memory cells whose time integral via the read current reaches the threshold value Sw, and to assign a second digital value to the n ₂ remaining memory cells. In this case it may be sufficient to determine whether one of the memory cells belongs to the n ₁ first memory cells.

It is also possible to form links from analog signals from memory cells and, based on these links, to determine whether memory cells are assigned a first digital value or another digital value.

unterschiedliche Möglichkeiten die n Speicherzellen mit n₁ Nullen und n₂ = n - n₁ Einsen zu beschreiben. Somit sind in den n Speicherzellen $\left(\begin{array}{c}n\\ n_1\end{array}\right)$

verschiedene Belegungen (auch bezeichnet als Zustände) möglich, so dass k Datenbits (auch bezeichnet als ein k-Bit-Byte) in den n Speicherzellen gespeichert werden können, wenn $$2^k\le \left(\begin{array}{c}n\\ n_1\end{array}\right)$$

gilt. Ist n eine gerade Zahl, so ergibt sich für n₁ = n/2 die größte Anzahl möglicher Zustände.For a group of n memory cells and n ₁ first memory cells result $$\left(\begin{array}{c}n\\ n_1\end{array}\right)$$

different possibilities to describe the n memory cells with n ₁ zeros and n ₂ = n - n ₁ ones. Thus, in the n memory cells $\left(\begin{array}{c}n\\ n_1\end{array}\right)$

different assignments (also referred to as states) are possible, so that k data bits (also referred to as a k-bit byte) can be stored in the n memory cells if $$2^k\le \left(\begin{array}{c}n\\ n_1\end{array}\right)$$

is applicable. If n is an even number, then n ₁ = n/2 results in the largest number of possible states.

For example, let n=6 memory cells be given, each with n ₁ =n ₂ =3 first and second memory cells. The n=6 memory cells form a group of memory cells S ₁ to S ₆ in which a code word of a 3-of-6 code can be stored.

den Schwellwert Sw erreicht.First, the case where no error occurs will be described. When reading the memory cells, the times t ₁ to t ₆ are compared, at which the value of the integral over the read currents $W_A^1\left(\tau \right)\text{until}{W}_A^6\left(\tau \right)$

reaches the threshold value Sw.

ergibt sich die Reihenfolge der Speicherzellen zu $$S_1,S_3,S_4,S_2,S_5,S_6.$$

Valid for example $$t_1<t_3<t_4<t_2<t_5<t_6,$$

results in the order of the memory cells $$S_{}$$$${}_1,{\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">S</figure-callout>}}_3,S_4,{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,S_5,S_6.$$

The code word 101100 of the 3-of-6 code, for example, is stored in the memory cells S ₁ to S ₆ and read from these memory cells. The value 1 is determined as the read value for the first three memory cells S ₁ , S ₃ and S ₄ of the ordered memory cells and the value 0 is determined for the following three memory cells S ₂ , S ₅ and S ₆ of the ordered memory cells.

so folgt hieraus die Reihenfolge der Speicherzellen zu $$S_3,S_4,S_1,S_2,S_6,S_5.$$

However, for example $$t_3^{\text{'}}<t_4^{\text{'}}<t_1^{\text{'}}<t_2^{\text{'}}<t_6^{\text{'}}<t_5^{\text{'}},$$

so the order of the memory cells follows from this $${\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">S</figure-callout>}}_3,S_4,{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">S</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,S_6,S_5.$$

Thus, the same code word 101100 of the 3-of-6 code is read from the memory cells S ₁ to S ₆ . Reversing the order within the memory cells S ₁ , S ₃ and S ₄ storing the binary value 1 or reversing the order within the memory cells S ₂ , S ₅ and S ₆ storing the binary value 0 has no effect read out the code word of the 3-of-6 code.

This property is advantageous because smaller fluctuations in the physical values read out, which correspond to the same digital values, do not affect the associated digital values when they are read out.

geschrieben, die jeweils den binären Wert 1 repräsentieren sollen. Untereinander unterscheiden sich diese Werte $W_G^1,W_G^3,W_G^4$

wenig, sie können aber insbesondere durch zufällige Einflüsse leicht variieren.In this example, the memory cells S ₁ , S ₃ and S ₄ are provided for storing the value 1. The values were stored in these memory cells $W_G^{}$${}_1^{},{\mathrm{<figure-callout\; id="3"\; label="W\; G"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_G^{},W_G^4$

written, each of which should represent the binary value 1. These values differ from each other $W_G^{}$${}_1^{},{\mathrm{<figure-callout\; id="3"\; label="W\; G"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_G^{},W_G^4$

little, but they can vary slightly, particularly due to random influences.

geschrieben, die jeweils den binären Wert 0 repräsentieren. Untereinander unterscheiden sich diese Werte $W_G^2,W_G^5\text{ und }{W}_G^6$

wenig, sie können aber ebenfalls aufgrund von zufälligen Einflüssen leicht variieren.Correspondingly, the storage cells S ₂ , S ₅ and S ₆ are provided for storing the value 0. The values were stored in these memory cells $W_G^{}$${}_2^{},W_G^5\text{and}{W}_G^6$

written, each representing the binary value 0. These values differ from each other $W_G^{}$${}_2^{},W_G^5\text{and}{W}_G^6$

little, but they can also vary slightly due to random influences.

eine zeitliche Ordnung $$t_1^{\text{'}}<t_3^{\text{'}}<t_2^{\text{'}}<t_4^{\text{'}}<t_5^{\text{'}}<t_6^{\text{'}}$$

bestimmt worden, sind die Speicherzellen wie folgt geordnet $$S_1,S_3,S_2,S_4,S_5,S_6$$

und es wird aus den Speicherzellen S₁ bis S₆ das Codewort 111000 des 3-aus-6 Codes ausgelesen, das sich von dem fehlerfreien Codewort 101100 dadurch unterscheidet, dass die zeitlich erste Speicherzelle S₂, der in der Reihenfolge der Speicherzellen im fehlerfreien Fall der Wert 0 zugeordnet und die zeitlich letzte Speicherzelle S₄, der im fehlerfreien Fall in der Reihenfolge der Speicherzellen der Wert 1 zugeordnet ist, vertauscht sind.For example, instead of $${\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">t</figure-callout>}}_1<{\mathrm{<figure-callout\; id="3"\; label="t"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">t</figure-callout>}}_3<t_4<{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">t</figure-callout>}}_2<t_5<t_6$$

a temporal order $$t_1^{\text{'}}<t_3^{\text{'}}<t_2^{\text{'}}<t_4^{\text{'}}<t_5^{\text{'}}<t_6^{\text{'}}$$

has been determined, the memory cells are ordered as follows $${\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">S</figure-callout>}}_1,{\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">S</figure-callout>}}_3,{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,S_4,S_5,S_6$$

and the code word 111000 of the 3-out-of-6 code is read from the memory cells S ₁ to S ₆ , which differs from the error-free code word 101100 in that the first memory cell S ₂ in time, which is in the order of the memory cells in the error-free case assigned the value 0 and the temporally last memory cell S ₄ , to which the value 1 is assigned in the error-free case in the sequence of the memory cells, are swapped over.

Example: 3-value memory cells

A scenario is considered below by way of example, in which three different digital values 0, 1 and 2 can be stored per memory cell.

3 FIG. 12 shows a diagram illustrating frequency distributions of physical values W _G of a memory cell.

3 shows a frequency distribution 301 for stored values 0, a frequency distribution 302 for stored values 1 and a frequency distribution 303 for stored values 2. Frequency distribution 301 is also denoted by W _G (0), frequency distribution 302 is also denoted by W _G (1) and the Frequency distribution 303 is also denoted by W _G (2).

Frequency distributions 301 and 302 have an overlap area 304 and frequency distributions 302 and 303 have an overlap area 305 .

According to an embodiment, the physical value can be a resistance value.

4 shows an example of a frequency distribution 401 for the value 2 read from the memory, a frequency distribution 402 for the value 1 read from the memory and a frequency distribution 403 for the value 0 read from the memory. The frequency distribution 401 is also denoted by W _A (2), the frequency distribution 402 is also denoted by W _A (1) and the frequency distribution 403 is also denoted by W _A (0).

Frequency distributions 401 and 402 have an overlap area 404 and frequency distributions 402 and 403 have an overlap area 405 .

According to one embodiment, the physical value read may be a current strength.

des Lesestroms der Speicherzelle Sⁱ über die Zeit t integriert, dann wird ein vorgegebener Schwellwert Sw zu einem Zeitpunkt t_i erreicht.becomes an amperage $W_A^i\left(\tau \right)$

of the read current of the memory cell S ⁱ is integrated over time t, then a predefined threshold value Sw is reached at a time t _i .

des Lesestromes der Speicherzelle S^j über die Zeit t integriert, dann wird der vorgegebene Schwellwert Sw zu einem Zeitpunkt t_j erreicht.becomes an amperage $W_A^j\left(\tau \right)$

of the read current of the memory cell S ^j is integrated over time t, then the predefined threshold value Sw is reached at a point in time t _j .

auf und beim Auslesen dieser Speicherzelle Sⁱ ist der Lesestrom $W_A^i$

relativ gering. Dementsprechend ist der Zeitpunkt t_i zu dem das Zeitintegral des Lesestroms den vorgegebenen Schwellwert Sw erreicht, groß.If the digital value 2 is written into the memory cell S ⁱ , then the memory cell S ⁱ has a relatively high resistance value $\left(W_G^i\right)$

on and when reading this memory cell S ⁱ is the read current $W_A^i$

relatively low. Accordingly, the point in time t _i at which the time integral of the read current reaches the predetermined threshold value Sw is large.

auf, der geringer ist als der Widerstandswert $W_G^i$

der Speicherzelle Sⁱ. Entsprechend ist der Lesestrom $W_A^j$

beim Auslesen der Speicherzelle S^j größer als der Lesestrom $W_A^i$

beim Auslesen der Speicherzelle Sⁱ. Somit liegt der Zeitpunkt t_j, zu dem das Zeitintegral des Lesestroms den vorgegebenen Schwellwert Sw erreicht, vor dem Zeitpunkt t_i, d.h. es gilt t_j < t_i.If the digital value 1 is written into the memory cell S ^j , then the memory cell S ^j has a resistance value $W_G^j$

which is less than the resistance value $W_G^i$

of the memory cell S ⁱ . The read current is corresponding $W_A^j$

when reading the memory cell S ^j greater than the read current $W_A^i$

when reading the memory cell S ⁱ . The point in time t _j at which the time integral of the read current reaches the predetermined threshold value Sw therefore lies before the point in time t _i , ie t _j <t _i applies.

W_G auf, der sowohl geringer als der Widerstandswert W_G der Speicherzelle Sⁱ als auch geringer als der Widerstandswert $W_G^j$

der Speicherzelle S^j ist. Entsprechend ist der Lesestrom $W_A^k$

der Speicherzelle S^k größer als der Lesestrom $W_A^j$

oder der Lesestrom $W_A^i$

der Speicherzellen S^j, Sⁱ. Somit liegt der Zeitpunkt t_k, zu dem das Zeitintegral des Lesestroms den vorgegebenen Schwellwert Sw erreicht, vor den Zeitpunkten t_i und t_j, d.h. es gilt t_k < t_j < t_i.If the digital value 0 is written into the memory cell S ^k , then the memory cell S ^k has a resistance value $W_G^k$

W _G which is both less than the resistance value W _G of the memory cell S ⁱ and less than the resistance value $W_G^j$

of memory cell S ^j . The read current is corresponding $W_A^k$

of the memory cell S ^k is greater than the read current $W_A^j$

or the reading stream $W_A^i$

of the memory cells S ^j , S ⁱ . The point in time t _k at which the time integral of the read current reaches the predetermined threshold value Sw therefore lies before the points in time t _i and t _j , ie t _k <t _j <t _i applies.

der Speicherzelle Sⁱ größer oder kleiner sein als der Widerstandswert $W_G^j$

der Speicherzelle S^j.If the same digital value has been written into a memory cell S ⁱ as into a memory cell S ⁱ , the resistance value can $W_G^i$

of the memory cell S ⁱ can be larger or smaller than the resistance value $W_G^j$

of the memory cell S ^j .

der Speicherzelle Sⁱ größer oder kleiner ist als der Lesestrom $W_A^j$

der Speicherzelle S^j.It is also possible that the read current $W_A^i$

of the memory cell S ⁱ is larger or smaller than the reading current $W_A^j$

of the memory cell S ^j .

Furthermore, it is possible that the point in time t _i at which the time integral over the read current of the memory cell S ⁱ reaches the predetermined threshold value Sw is before or after the point in time t _j at which the time integral over the read current of the memory cell S ^j reaches the predetermined Threshold Sw reached.

In this case it remains undetermined whether t _i < t _j or t _i < t _j . The value "undetermined" is also described here by the symbol "—".

Example

• - in n₁ = 2 ersten Speicherzellen der digitale Speicherzellenwert 2,
• - in n₂ = 2 zweiten Speicherzellen der digitale Speicherzellenwert 1 und
• - in n₃ = 2 dritten Speicherzellen der digitale Speicherzellenwert 0

gespeichert wird. Es gibt somit $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-n_2\\ n_3\end{array}\right)=\left(\begin{array}{c}6\\ 2\end{array}\right)\cdot \left(\begin{array}{c}4\\ 2\end{array}\right)\cdot \left(\begin{array}{c}2\\ 2\end{array}\right)=15\cdot 6\cdot 1=90$$

A group of n=6 memory cells S ¹ to S ⁶ is considered as an example. There are three subgroups, each with two memory cells, ie n ₁ =n ₂ =n ₃ =2, where

• - in n ₁ = 2 first memory cells the digital memory cell value 2,
• - in n ₂ = 2 second memory cells the digital memory cell value 1 and
• - in n ₃ = 2 third memory cells the digital memory cell value 0

is saved. So there is $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-n_2\\ n_3\end{array}\right)=\left(\begin{array}{c}6\\ 2\end{array}\right)\cdot \left(\begin{array}{c}4\\ 2\end{array}\right)\cdot \left(\begin{array}{c}2\\ 2\end{array}\right)=15\cdot 6\cdot 1=90$$

Ways to distribute two twos, two ones and two zeros to 6 positions and store them in 6 memory cells with three digital (ternary) memory cell values.

In contrast, for n = 6 and n ₁ = n ₂ = 3 only $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_1\end{array}\right)=\left(\begin{array}{c}6\\ 3\end{array}\right)\cdot \left(\begin{array}{c}3\\ 3\end{array}\right)=20$$

Possibilities to distribute three ones and three zeros in 6 positions and store them in 6 memory cells with binary memory cell values, so that by using the three ternary digital values 0, 1 and 2 compared to using only binary memory cell values 0 and 1 there is considerably more information in a group can be stored by n memory cells.

• - n₁ = 2 erste digitale Werte 2,
• - n₂ = 2 zweite digitale Werte 1 und
• - n₃ = 2 dritte digitale Werte 0 auf.

In this example, in which each of the memory cells can assume the value 0, 1 or 2, a number of k=6 data bits (with 2 ⁶ =64 possible assignments) can be transformed into n=6 digital memory cell values and into n=6 memory cells get saved. The 6 memory cell values each have

• - n ₁ = 2 first digital values 2,
• - n ₂ = 2 second digital values 1 and
• - n ₃ = 2 third digital values 0 on.

bei dem jedes Codewort zwei erste digitale Werte, zwei zweite digitale Werte und zwei dritte digitale Werte aufweist.The 6 memory cell values form a code word of a $$2-\mathrm{,2}-\mathrm{,2}-\text{out of}-6-\text{codes}\text{,}$$

in which each code word has two first digital values, two second digital values and two third digital values.

Codewörter.The code has $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-n_2\\ n_3\end{array}\right)=15\cdot 6\cdot 1=90$$

code words.

With k=6 bits, ^2k = ²⁶ =64 binary words of length 6 can be uniquely transformed into 64 of the code words of the 2, 2, 2 out of n code.

15 shows a schematic arrangement to illustrate how k data bits x ₁ to x _k are transformed by means of a transformation circuit 1501 and stored as n memory cell values in n memory cells of a memory 1502. Here k≧2 and n≧3 is assumed as an example. The k data bits x ₁ to x _k are present at the input of the transformation circuit 1501 .

The n memory cell values are provided by the transformation circuit 1501 at data inputs of the memory cells of the memory 1502. These n memory cell values form a code word of a $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-,{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">n</figure-callout>}}_2-,...,n_K-\text{out of}-n-\text{codes}\text{.}$$

The memory cell values are, for example, K-value digital values.

16 shows a schematic implementation of the arrangement of 15 , where in 16 for example n = k = 6, K = 3 and n ₁ = n ₂ = n ₃ = 2 apply. According to the 16 In the example shown, 6 data bits x ₁ to x ₆ are transformed into 6 three-valued memory cell values by a transformation circuit 1601 and stored in a memory 1602 . The 6 memory cell values have two 2 values, two 1 values and two 0 values and form (in the error-free case) a code word of a 2, 2, 2 out of 6 code. In this case, each of the memory cells is capable of storing three-valued (K=3) memory cell values.

dann können die Speicherzellen S¹ bis S⁶ in der Reihenfolge $$S^{i_1},S^{i_2},S^{i_3},S^{i_4},S^{i_5},S^{i_6}$$

geordnet werden. Dabei ist die Menge der Werte i₁, ... , i₆ gleich der Menge der Werte 1,...,6. Gilt beispielsweise z₁ = 5, i₂ = 4, i₃ = 2, i₄ = 1, i₅ = 6 und i₆ = 3, so ergibt sich $$t_5<t_4<t_2<t_1<t_6<t_3$$

und damit die Reihenfolge der Speicherzellen zu $$S^5,S^4,S^2,S^1,S^6,S^3.$$

As described, the times t ¹ to t ⁶ are determined for the memory cells S ₁ to S ₆ during reading, when the time integral of the read current reaches (or exceeds) the predetermined threshold value Sw. Valid for example $$t_{i_1}<t_{i_2}<t_{i_3}<t_{i_4}<t_{i_5}<t_{i_6},$$

then the memory cells S ¹ to S ⁶ in order $$S^{i_{}}$$$${{}_1}^{},{\mathrm{<figure-callout\; id="2"\; label="S\; i"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">S</figure-callout>}}^{i_{}},{\mathrm{<figure-callout\; id="3"\; label="S\; i"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">S</figure-callout>}}^{i_{}},S^{i_4},S^{i_5},S^{i_6}$$

to be sorted. The set of values i ₁ ,..., i ₆ is equal to the set of values 1,...,6. For example, if z ₁ = 5, i ₂ = 4, i ₃ = 2, i ₄ = 1, i ₅ = 6 and i ₆ = 3, the result is $$t_5<t_4<{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">t</figure-callout>}}_2<{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">t</figure-callout>}}_1<t_6<{\mathrm{<figure-callout\; id="3"\; label="t"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">t</figure-callout>}}_3$$

and thus the order of the memory cells $$S^5,S^4,{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">S</figure-callout>}}^2,{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">S</figure-callout>}}^1,S^6,{\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">S</figure-callout>}}^3.$$

It can be specified that the first two memory cells S ^{i 1} and S ^{i 2} in the sequence of the memory cells the digital memory cell value 0, the following two memory cells S ^{i 3} and S ^{i 4} in the order of the digital memory cell value 1 and the other two memory cells S ^{i 5} and S ^{i 6} in which order the digital memory cell value 2 is assigned.

It can also be specified that the first two memory cells S ^{i 1} and S ^{i 2} the digital memory cell value 2, the following two memory cells S ^{i 3} and S ^{i 4} the digital memory cell value 1 and the other two memory cells S ^{i 5} and S ^{1 6} the digital memory cell value 0 is assigned. Correspondingly, further assignment variants are also possible.

• - wenn sowohl der Lesestrom ${\mathrm{<figure-callout\; id="2"\; label="W\; A\; i"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_{A{i}_{}}^{{}_2}$
  
  der Speicherzelle Sⁱ² als auch der Lesestrom ${\mathrm{<figure-callout\; id="3"\; label="W\; A\; i"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_{A{i}_{}}^{{}_3}$
  
  der Speicherzelle Zelle Sⁱ³ in einem Überlappungsbereich liegen, in dem sowohl ein Lesestrom für den Wert 0 als auch für den Wert 1 vorkommt oder
• - wenn sowohl der Lesestrom $W_A^{i_4}$
  
  der Speicherzelle Sⁱ⁴ als auch der Lesestrom $W_A^{i_5}$
  
  der Speicherzelle $S^{i_5}$
  
  Sⁱ⁵ in einem Überlappungsbereich liegen, in dem sowohl ein Lesestrom für den Wert 1 als auch ein Lesestrom für den Wert 2 vorkommt.

An incorrect assignment of digital values only occurs

• - if both the reading current $W_A^{{\mathrm{<figure-callout\; id="2"\; label="i"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">i</figure-callout>}}_2}$
  
  of the memory cell S ^{i 2} as well as the read stream ${\mathrm{<figure-callout\; id="3"\; label="W\; A\; i"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_{A{i}_{}}^{{}_3}$
  
  of the memory cell cell S ^{i 3} lie in an overlapping area in which both a read current for the value 0 and for the value 1 occurs or
• - if both the reading current $W_A^{i_4}$
  
  of the memory cell S ⁱ⁴ as well as the read current $W_A^{i_5}$
  
  the storage cell $S^{i_5}$
  
  S ⁱ⁵ lie in an overlap region in which both a read current for the value 1 and a read current for the value 2 occur.

Thus, there is advantageously an error-free assignment of digital values with a high degree of probability, even for multi-value digital memories, because, based on the 6 memory cells, an incorrect assignment is only possible for a small part of the memory cells and because for this purpose the read currents of two memory cells in each case are in an overlapping area at the same time have to lie.

It is therefore advantageous that read errors only rarely occur when the stored memory cell values are read out. When reading out, the physical values read out or the values of different memory cells determined from the physical values read out can be compared with one another, which as a result can then correspond to an effective reduction in the read errors. An erroneous result of a comparison can only occur if the two values to be compared are in an overlapping area at the same time.

It is also possible to read out the values stored as K-value memory cell values in n memory cells using reference values if code words stored in corresponding n memory cells have a (n ₁ -, n ₂ -, ..., n _K -out of n) -form code.

Example: Four-valued memory cell values

17 shows a schematic arrangement for the transformation of four data bits x ₁ , x ₂ , x ₃ , x ₄ into four memory cell values z ₁ , z ₂ , z ₃ , z ₄ .

The four data bits x ₁ , x ₂ , x ₃ , x ₄ are present at the input of a transformation circuit 1701 . These four data bits are transformed into the four memory cell values z ₁ , z ₂ , z ₃ , z ₄ using the transformation circuit 1701 and stored in memory cells S ¹ , S ² , S ³ , S ⁴ of a memory 1702 .

In this example, the memory 1702 comprises the group of the n=4 memory cells S ¹ , S ² , S ³ , S ⁴ , four different values 0, 1, 2, 3 and 4 being able to be stored in each of the memory cells, for example. There is thus one memory cell per subgroup, ie n ₁ = n ₂ = n ₃ = n ₄ = 1.

In the error-free case, the memory cell values z ₁ , z ₂ , z ₃ , z ₄ form a code word of a 1, 1, 1, 1 out of 4 code with 4×3×2×1=24 possible code words. 24 different digital values can thus be stored in the group with n=4 memory cells.

5 shows an example of a frequency distribution 501 for the values 3 read from the memory 1702, a frequency distribution 502 for the values 2 read from the memory 1702, a frequency distribution 503 for the values 1 read from the memory 1702 and a frequency distribution 504 for the values 1 read from the memory 1702 read values 0. Frequency distribution 501 is also denoted by W _A (3), frequency distribution 502 is also denoted by W _A (2), frequency distribution 503 is also denoted by W _A (1) and frequency distribution 504 is also denoted by W _A (0 ) designated.

Each of the values 0, 1, 2, 3, and 4 can be stored in one of the plurality of quad-valued memory cells of memory 1702.

For example, the value read from the memory 1702 can be a current (a read current), with one of the values 0, 1, 2, 3 or 4 resulting depending on the magnitude of this current.

Frequency distributions 501 and 502 have an overlap area 505, frequency distributions 502 and 503 have an overlap area 506, and frequency distributions 503 and 504 have an overlap area 507.

If the current strength W _A (τ) ⁱ of the read current of the memory cell S ⁱ is integrated over time t, then the predefined threshold value Sw is reached at a specific point in time t _i .

If the current strength W _A (τ) ^j of the read current of the memory cell S ^j is integrated over time t, then the predefined threshold value Sw is reached at a specific point in time t _j .

der Speicherzelle Sⁱ kleiner ist als der Lesestrom $W_A^j$

der Speicherzelle S^j.If, for example, the value 3 is stored in the memory cell S ⁱ and one of the digital values 0, 1 or 2 is stored in the memory cell S ^j , then t _j <t _i da the read current applies $W_A^i$

of the memory cell S ⁱ is smaller than the read current $W_A^j$

of the memory cell S ^j .

der Speicherzelle Sⁱ größer ist als der Lesestrom $W_A^j$

der Speicherzelle S^j.If, for example, the value 1 is stored in the memory cell S ⁱ and one of the values 3 or 2 is stored in the memory cell S ^j , then t _j >t _i da the read current applies $W_A^i$

of the memory cell S ⁱ is greater than the read current $W_A^j$

of the memory cell S ^j .

For example, if t ₁ <t ₃ <t ₂ <t ₄ , the sequence of the memory cells is: S ¹ , S ³ , S ² , S ⁴ . The value 0 can be assigned to the memory cell S ¹ , the value 1 to the memory cell S ³ , the value ² to the memory cell S 2 and the value 3 to the memory cell S ⁴ .

The four data bits x ₁ , x ₂ , x ₃ , x ₄ are present at the input of the transformation circuit 1701, and the memory cell values z ₁ , z ₂ , z ₃ , z ₄ are output at the output of the transformation circuit 1701. This transformation performed in the transformation circuit 1701 can be determined according to Table 1, for example. Table 1 Line × ₁ x2 _{_} × ₃ x ₄ z ₁ z ₂ z ₃ z ₄ 1 0 0 0 0 3 2 1 0 2 0 0 0 1 3 2 0 1 3 0 0 1 0 3 1 2 0 4 0 0 1 1 3 1 0 2 5 0 1 0 0 3 0 1 2 6 0 1 0 1 3 0 2 1 7 0 1 1 0 2 3 1 0 8th 0 1 1 1 2 3 0 1 9 1 0 0 0 2 1 3 0 10 1 0 0 1 2 1 0 3 11 1 0 1 0 2 0 3 1 12 1 0 1 1 2 0 1 3 13 1 1 0 0 1 3 2 0 14 1 1 0 1 1 3 0 2 15 1 1 1 0 1 2 3 0 16 1 1 1 1 1 2 0 3

The four data bits x ₁ , x ₂ , x ₃ , x ₄ can take on 16 different binary values 0000,...,1111, all of which are shown in Table 1 above. In this case, each row corresponds to a transformation, which can be carried out by the transformation circuit 1701, of data bits x _i into a code word z _i of the 1, 1, 1, 1 out of 4 code.

For example, the third row of Table 1 shows that the code word 3120 is assigned to the data bits 0010.

As already stated, there are 24 different code words of the 1,1,1,1 out of 4 code. These 24 code words face 16 different values for x ₁ , x ₂ , x ₃ , x ₄ . According to Table 1, only 16 of the 24 possible code words are used.

If, when reading out the memory cells S ¹ , S ² , S ³ , S ^{4 ,} four memory cell values z ₁ , z ₂ , z ₃ , z ₄ are determined which, in the error-free case, contain a code word of 1-,1-,1-,1-out -4 codes, then these memory cell values are transformed according to Table 1 into the corresponding data bits x ₁ , x ₂ , x ₃ , x ₄ .

A possible inverse transformation is shown in Table 2. Table 2 Line z ₁ z ₂ z ₃ z ₄ × ₁ x2 _{_} × ₃ x ₄ 1 3 2 1 0 0 0 0 0 2 3 2 0 1 0 0 0 1 3 3 1 2 0 0 0 1 0 4 3 1 0 2 0 0 1 1 5 3 0 1 2 0 1 0 0 6 3 0 2 1 0 1 0 1 7 2 3 1 0 0 1 1 0 8th 2 3 0 1 0 1 1 1 9 2 1 3 0 1 0 0 0 10 2 1 0 3 1 0 0 1 11 2 0 3 1 1 0 1 0 12 2 0 1 3 1 0 1 1 13 1 3 2 0 1 1 0 0 14 1 3 0 2 1 1 0 1 15 1 2 3 0 1 1 1 0 16 1 2 0 3 1 1 1 1 17 1 0 3 2 - - - - 18 1 0 2 3 - - - - 19 0 3 2 1 - - - - 20 0 3 1 2 - - - - 21 0 2 3 1 - - - - 22 0 2 1 3 - - - - 23 0 1 3 2 - - - - 24 0 1 2 3 - - - -

In Table 2, the 24 code words are assigned the 16 possible assignments of the data bits, with some of the code words (lines 17 to 24 in Table 2) having no data bits or the data bits for these code words being undefined. Table 2 thus shows the inverse transformation of Table 1.

For example, row 5 of Table 1 shows that data bits 0100 are assigned the code word 3012. Correspondingly, line 5 of Table 2 shows that code word 3012 is assigned data bits 0100.

For rows 17 through 24 of Table 2, the data bits are undetermined. In a synthesis of an inverse transformation circuit, undetermined data bits can be used as so-called "don't care" values for circuit optimization.

The indefinite data bits can also be set to any value, e.g. to 0.

Example: 11 data bits in 8 memory cells

For example, k=11 data bits x ₁ , . . . , x ₁₁ can be transformed into 8 memory cells with memory cell values z ₁ , . . . , z ₈ . The memory cell values are code words of a 2, 2, 2, 2 out of 8 code. Each memory cell value has four values (K=4), ie one of four different values can be stored per memory cell.

The 11 data bits can represent 2 ¹¹ = 2048 different values. The 2,2,2,2 out of 8 code includes $$\left(\begin{array}{c}\mathrm{8th}\\ 2\end{array}\right)\cdot \left(\begin{array}{c}6\\ 2\end{array}\right)\cdot \left(\begin{array}{c}4\\ 2\end{array}\right)\cdot \left(\begin{array}{c}2\\ 2\end{array}\right)=28\cdot 15\cdot 6\cdot 1=2520$$

code words. These 2520 code words are enough to transform all 2048 binary values into code words of the 2,2,2,2 out of 8 code.

Example: 9 data bits in 7 memory cells

Also, k=9 data bits x ₁ ,...,x ₉ can be transformed into n=7 memory cells with memory cell values z ₁ ,...,z ₇ . The memory cell values are codewords of a 2,2,2,1 of 7 code. Each memory cell value is, for example, four-valued (K=4).

The 9 data bits can represent 2 ⁹ = 512 different values. The 2,2,2,1 of 7 code includes $$\left(\begin{array}{c}7\\ 2\end{array}\right)\cdot \left(\begin{array}{c}5\\ 2\end{array}\right)\cdot \left(\begin{array}{c}3\\ 2\end{array}\right)\cdot \left(\begin{array}{c}1\\ 1\end{array}\right)=21\cdot 10\cdot 3\cdot 1=630$$

code words. These 630 code words are enough to transform all 512 binary values into code words of the 2,2,2,2 out of 7 code.

bilden, kein Referenzwert erforderlich ist. Das Bestimmen der ausgelesenen digitalen Speicherzellenwerte kann unter Verwendung eines gegenseitigen Vergleichs der aus Speicherzellen ausgelesenen physikalischen Werte oder eines Vergleichs von aus ausgelesenen physikalischen Werten abgeleiteten Werten erfolgen, wodurch die Wahrscheinlichkeit von Lesefehlern auch dann gering ist, wenn die Häufigkeitsverteilungen für die verschiedenen Speicherzellenwerte Überlappungsbereiche aufweisen.It is advantageous, for example, that when reading out and determining digital memory cell values, the code words of a $${\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-,...,n_K-\text{out of}-n-\text{codes}$$

form, no reference value is required. The digital memory cell values read can be determined using a mutual comparison of the physical values read from memory cells or a comparison of values derived from physical values read out, which means that the probability of reading errors is low even if the frequency distributions for the different memory cell values have overlapping areas.

Reading out the memory using a comparator

ausgelesen und unter Verwendung von $\left(\begin{array}{c}4\\ 2\end{array}\right)=6$

Vergleichern 602 bis 607 paarweise verglichen. Ein Vergleicher kann z.B. als ein Komparator ausgeführt sein. 6 Figure 12 shows a memory 601 comprising n=4 memory cells S ¹ , S ² , S ³ and S ⁴ . At the outputs of the memory cells, the values $W_A^{}$${}_1^{},{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{},{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}{\text{and w}}_A^4$

read and using $\left(\begin{array}{c}4\\ 2\end{array}\right)=6$

Comparators 602 to 607 compared in pairs. A comparator can be implemented as a comparator, for example.

der Speicherzellen S¹ und S². Der Vergleicher 602 ist so konfiguriert, dass er an seinem Ausgang einen binären Wert y₁₂ = 1 ausgibt, falls für die ausgelesenen Werte $W_A^1>W_A^2$

gilt, und den binären Wert y₁₂ = 0 ausgibt, falls für die ausgelesenen Werte $W_A^1<W_A^2$

gilt.The comparator 602 compares the read values $W_A^{}$${}_1^{}\text{and}{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

of memory cells S ¹ and S ² . The comparator 602 is configured to provide a binary value y ₁₂ =1 at its output if for the values read $W_A^1>{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

applies, and outputs the binary value y ₁₂ =0 if for the values read out ${\mathrm{<figure-callout\; id="1"\; label="W\; A"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}<{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

is applicable.

der Speicherzellen S¹ und S³. Der Vergleicher 603 ist so konfiguriert, dass er an seinem Ausgang einen binären Wert y₁₃ = 1 ausgibt, falls für die ausgelesenen Werte $W_A^1>W_A^3$

gilt, und den binären Wert y₁₃ = 0 ausgibt, falls für die ausgelesenen Werte $W_A^1<W_A^3$

gilt.The comparator 603 compares the read values $W_A^{}$${}_1^{}\text{and}{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

of memory cells S ¹ and S ³ . The comparator 603 is configured to provide a binary value y ₁₃ =1 at its output if for the values read $W_A^1>{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

applies, and outputs the binary value y ₁₃ =0 if for the values read out ${\mathrm{<figure-callout\; id="1"\; label="W\; A"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}<{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

is applicable.

der Speicherzellen S¹ und S⁴. Der Vergleicher 604 ist so konfiguriert, dass er an seinem Ausgang einen binären Wert y₁₄ = 1 ausgibt, falls für die ausgelesenen Werte $W_A^1>W_A^4$

gilt, und den binären Wert y₁₄ = 0 ausgibt, falls für die ausgelesenen Werte $W_A^1<W_A^4$

gilt.The comparator 604 compares the read values $W_A^{}$${}_1^{}\text{and}{W}_A^4$

of memory cells S ¹ and S ⁴ . The comparator 604 is configured to provide a binary value y ₁₄ =1 at its output if for the values read $W_A^1>W_A^4$

applies, and outputs the binary value y ₁₄ =0 if for the values read out ${\mathrm{<figure-callout\; id="1"\; label="W\; A"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}<W_A^4$

is applicable.

der Speicherzellen S² und S³. Der Vergleicher 605 ist so konfiguriert, dass er an seinem Ausgang einen binären Wert y₂₃ = 1 ausgibt, falls für die ausgelesenen Werte $W_A^2>W_A^3$

gilt, und den binären Wert y₂₃ = 0 ausgibt, falls für die ausgelesenen Werte $W_A^2<W_A^3$

gilt.The comparator 605 compares the read values $W_A^{}$${}_2^{}\text{and}{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

of memory cells S ² and S ³ . The comparator 605 is configured to provide a binary value y ₂₃ =1 at its output if for the values read $W_A^2>{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

applies, and outputs the binary value y ₂₃ =0 if for the values read out ${\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}<{\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

is applicable.

der Speicherzellen S² und S⁴. Der Vergleicher 606 ist so konfiguriert, dass er an seinem Ausgang einen binären Wert y₂₄ = 1 ausgibt, falls für die ausgelesenen Werte $W_A^2>W_A^4$

gilt, und den binären Wert y₂₄ = 0 ausgibt, falls für die ausgelesenen Werte $W_A^2<W_A^4$

gilt.The comparator 606 compares the read values $W_A^{}$${}_2^{}\text{and}{W}_A^4$

of memory cells S ² and S ⁴ . The comparator 606 is configured to provide a binary value y ₂₄ =1 at its output if for the values read $W_A^2>W_A^4$

applies, and outputs the binary value y ₂₄ =0 if for the values read out ${\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}<W_A^4$

is applicable.

der Speicherzellen S³ und S⁴. Der Vergleicher 607 ist so konfiguriert, dass er an seinem Ausgang einen binären Wert y₃₄ = 1 ausgibt, falls für die ausgelesenen Werte $W_A^3>W_A^4$

gilt, und den binären Wert y₃₄ = 0 ausgibt, falls für die ausgelesenen Werte $W_A^3<W_A^4$

gilt.The comparator 607 compares the read values $W_A^{}$${}_3^{}\text{and}{W}_A^4$

of memory cells S ³ and S ⁴ . The comparator 607 is configured to provide a binary value y ₃₄ =1 at its output if for the values read $W_A^3>W_A^4$

applies, and outputs the binary value y ₃₄ =0 if for the values read out ${\mathrm{<figure-callout\; id="3"\; label="W\; A"\; filenames="DE102017103347B4\_0234.png,DE102017103347B4\_0243.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}<W_A^4$

is applicable.

If two subgroups have a size of n ₁ = n ₂ = 2, then in the group with n = 4 memory cells S ¹ to S ⁴ $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)=\left(\begin{array}{l}4\\ 2\end{array}\right)\cdot \left(\begin{array}{c}4-2\\ 2\end{array}\right)=6\cdot 1=6$$

assignments are saved.

Table 3 shows the output values y ₁₂ , y ₁₃ , y ₁₄ , y ₂₃ , y ₂₄ , y ₃₄ of the 6 comparators 602 to 607 for these 6 assignments. Table 3 p ¹ S ² p3 ^_ p4 ^_ y ₁₂ y ₁₃ y ₁₄ y ₂₃ y ₂₄ y ₃₄ function 1 1 0 0 - 1 1 1 1 - y ₁₃ Λ y ₁₄ Λ y ₂₃ Λ y ₂₄ 1 0 1 0 1 - 1 0 - 1 y _12Λ y _14Λ y _23Λy 34 _{_} 1 0 0 1 1 1 - - 0 0 y _12Λ y _13Λ y ₂₄ Λ y ₃₄ 0 1 1 0 0 0 - - 1 1 y _12Λ y _13Λy 24Λyyy 34 _{_ _} 0 1 0 1 0 - 0 1 - 0 y _12Λ y _14Λ and _23Λ y ₃₄ 0 0 1 1 - 0 0 0 0 - y ₁₃ Λ y ₁₄ Λ y ₂₃ Λ y ₂₄

miteinander verglichen, die beide einem gespeicherten binären Wert 1 zugeordnet sind. Es ist in diesem Fall nicht vorhersehbar, ob $W_A^1<W_A^2$

oder $W_A^1>W_A^2$

gilt, so dass der Ausgabewert y₁₂ des Vergleichers 602 unbestimmt ist. Auch ist der Ausgang y₃₄ des Vergleichers 607 unbestimmt, da die Werte $W_A^3$

und $W_A^4$

der Speicherzellen S³ und S⁴ beide den binären Wert 0 aufweisen.For example, the first row of Table 3 describes that the memory cells S ¹ to S ⁴ are occupied with the binary values 1100. The comparators 602 to 607 then output the binary values y ₁₃ =y ₁₄ =y ₂₃ =y ₂₄ =1. Since the memory cells S ¹ and S ² are both occupied with the binary value 1, the values from the comparator 602 are ${\mathrm{<figure-callout\; id="1"\; label="W\; A"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}\text{and}{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

compared with each other, both associated with a stored binary value 1. In this case, it is not foreseeable whether $W_A^1<{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

or ${\mathrm{<figure-callout\; id="1"\; label="W\; A"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}>{\mathrm{<figure-callout\; id="2"\; label="W\; A"\; filenames="DE102017103347B4\_0232.png,DE102017103347B4\_0233.png"\; state="\{\{state\}\}">W</figure-callout>}}_A^{}$

holds, so that the output value y ₁₂ of the comparator 602 is undetermined. The output y ₃₄ of the comparator 607 is also undetermined since the values $W_A^{}$${}_3^{}$

and $W_A^4$

of memory cells S ³ and S ⁴ both have the binary value 0.

Thus, in Table 3, the output values of a comparator are undetermined if the output values of the associated memory cells to be compared have the same values.

In the “Function” column, Boolean expressions are assigned to the rows of Table 3 as a conjunction of negated or non-negated output values of the corresponding comparators: If the output value y _ij is equal to 1, the output value appears in the conjunction; if, on the other hand, the output value y _ij is 0, the negated output value appears y _ij in the conjunction. If the output value is indefinite ("-"), it does not appear in the conjunction. In particular, this reduces the outlay for the implementation of the circuitry.

Exactly one of the 6 conjunctions assumes the value 1 for each of the 6 allocations of the memory cells S ¹ to S ⁴ with bits of a 2-out-of-4 code: For example, the allocation 1001 of the memory cells according to the third row in Table 3 corresponds to the conjunction $$y_{}$$$${}_{12}\wedge y_{13}\wedge {\overline{y}}_{24}\wedge {\overline{y}}_{34}=1\wedge 1\wedge 1\wedge 1=1.$$

The comparators 602, 603, 606 and 607 output the values _y12 =1, _y13 =1, _y24 =0 and _y34 =0. All other conjunctions shown in Table 3 have the value 0 in this case.

Thus, by making the conjunction y ₁₂ Λ y ₁₃ Λ y ₂₄ Λ y ₃₄ has the value 1, clearly determines that the occupancy 1001 was read from the memory cells S ¹ to S ⁴ .

Determination of the occupancy of the memory cells

7 FIG. 1 shows a circuit arrangement by means of which the values y ₁₂ , y ₁₃ , y ₁₄ , y ₂₃ , y ₂₄ and y ₃₄ of the comparators 602 to 607 are used to determine the corresponding assignments of the memory cells S ¹ to S ⁴ . Six AND gates 701 to 706, each with four inputs, and four OR gates 708 to 711, each with three inputs, are used for this purpose.

The values y ₁₃ , y ₁₄ , y ₂₃ and y ₂₄ are applied to the inputs of AND gate 701 . The values y ₁₂ , y ₁₄ , y ₂₃ and y ₂₄ are applied to the inputs of AND gate 702 . The values y ₁₂ , y ₁₃ , y ₂₄ and y ₃₄ are fed to the inputs of the AND gate 703. The values y ₁₂ , y ₁₃ , y ₂₄ and y ₃₄ are fed to the inputs of AND gate 704 . The values y ₁₂ , _y14 , _y23 and y ₃₄ are fed to the inputs of the AND gate 705. The values y ₁₃ , y ₁₄ , y ₂₃ and y ₂₄ are fed to the inputs of AND gate 706.

Furthermore, the outputs of the AND gates 701 to 706 are connected to the inputs of the OR gates 708 to 711 as follows: The output of the AND gate 701 is connected to one of the inputs of the OR gates 708 and 709, respectively. The output of AND gate 702 is connected to one of the inputs of OR gates 708 and 710, respectively. The output of AND gate 703 is connected to one of the inputs of OR gates 708 and 711, respectively. The output of AND gate 704 is connected to one of the inputs of OR gates 709 and 710, respectively. The output of AND gate 705 is connected to one of the inputs of OR gates 709 and 711, respectively. The output of AND gate 706 is connected to one of the inputs of OR gates 710 and 711, respectively.

At the output of the OR gate 708 is the occupancy of the memory cell S ¹ , at the output of the OR gate 709 is the occupancy of the memory cell S ² , at the output of the OR gate 710 is the occupancy of the memory cell S ³ and at the The assignment of the memory cell S ⁴ is provided at the output of the OR gate 711 .

The circuit arrangement thus visualizes according to FIG 7 Table 3 above as follows: The functions of Table 3 are mapped to the outputs of AND gates 701 to 706, with AND gate 701 corresponding to the function of the first row and AND gate 706 corresponding to the function of the last row of Table 3 is equivalent to. The occupancy of the memory cell S ⁱ according to 7 results from the column of the memory cell S ⁱ as follows: In that row of the table in which this column has the value 1, there is a logical OR link to the function (conjunction). For example, the memory cell S ¹ in the first three rows of Table 3 has the value 1, ie there is an OR link with the outputs of AND gates 701, 702 and 703, which stand for the conjunctions of the first three rows of Table 3 . This applies correspondingly to the other memory cells.

Example: Trivalent memory cells

An example with three-value memory cells is considered below, i.e. each of the memory cells can assume one of the values 0, 1 or 2, with 2 > 1 > 0 as an example.

The case is considered in which the group has n=6 memory cells and the subgroups have n ₁ =n ₂ =n ₃ =2 memory cells. Thus, the value 2 can be stored twice, the value 1 twice and the value 0 twice per group of 6 memory cells. There is with $$\left(\begin{array}{l}6\\ 2\end{array}\right)\cdot \left(\begin{array}{l}4\\ 2\end{array}\right)\cdot \left(\begin{array}{l}2\\ 2\end{array}\right)=15\cdot 6\cdot 1=90$$

Possibilities of assigning two twos, two ones and two zeros to a group of 6 memory cells S ¹ to S ⁶ .

$$VG{L}_{23},VG{L}_{24},VG{L}_{25},VG{L}_{26},$$

$$VG{L}_{34},VG{L}_{35},VG{L}_{36},$$

$$VG{L}_{45},VG{L}_{46},$$

und $$VG{L}_{56}.$$

If the read value of all memory cells is compared in pairs when reading data from the memory cells, then 15 comparators VGL _ij are used to compare all physical output values of the memory cells S ¹ to S ⁶ , with i, j = 1... 6 indices , each of which designates one of the memory cells. Thus, the comparator VGL _ij compares the memory cell S ⁱ with the memory cell S ^j . The 15 comparators are therefore: $$VG{L}_{12},VG{L}_{13},VG{L}_{14},VG{L}_{15},VG{L}_{16},$$

$$VG{L}_{23},VG{L}_{24},VG{L}_{25},VG{L}_{26},$$

$$VG{L}_{34},VG{L}_{35},VG{L}_{36},$$

$$VG{L}_{45},VG{L}_{46},$$

and $$VG{L}_{56}.$$

$$y_{23},y_{24},y_{25},y_{26},$$

$$y_{34},y_{35},y_{36},$$

$$y_{45},y_{46}$$

und $$y_{56}.$$

A binary output value of the comparator VGL _ij is denoted by y _ij , so that there are the following 15 binary output values: $$y_{12},y_{13},y_{14},y_{15},y_{16},$$

$$y_{23},y_{24},y_{25},y_{26},$$

$$y_{34},y_{35},y_{36},$$

$$y_{45},y_{46}$$

and $$y_{56}.$$

Table 4 shows the output values of these 15 comparators for the assignment 221100 of the memory cells S ¹ to S ⁶ .

y₁₃ The following conjunction results: $$y_{13}\wedge {\mathrm{<figure-callout\; id="14"\; label="y"\; filenames="DE102017103347B4\_0236.png"\; state="\{\{state\}\}">y</figure-callout>}}_{14}\wedge y_{15}\wedge y_{16}\wedge y_{23}\wedge y_{24}\wedge y_{25}\wedge {\mathrm{<figure-callout\; id="26"\; label="y"\; filenames="DE102017103347B4\_0238.png"\; state="\{\{state\}\}">y</figure-callout>}}_{26}\wedge y_{35}\wedge y_{36}\wedge y_{45}\wedge y_{46}.$$

y ₁₃

This conjunction has 12 values of the 15 comparators. These are the values that are not indeterminate.

In principle, the following applies: A value of 1 indicates a non-inverted or non-negated value y _ij and a value of 0 indicates an inverted or negated value y _ij of the respective comparator.

Table 5 shows the output values of the 15 comparators for the assignment 212100 of the memory cells S ¹ to S ⁶ .

The following conjunction results: $${\mathrm{<figure-callout\; id="12"\; label="y"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0231.png"\; state="\{\{state\}\}">y</figure-callout>}}_{12}\wedge {\mathrm{<figure-callout\; id="14"\; label="y"\; filenames="DE102017103347B4\_0236.png"\; state="\{\{state\}\}">y</figure-callout>}}_{14}\wedge y_{15}\wedge y_{16}\wedge {\overline{y}}_{23}\wedge y_{25}\wedge {\mathrm{<figure-callout\; id="26"\; label="y"\; filenames="DE102017103347B4\_0238.png"\; state="\{\{state\}\}">y</figure-callout>}}_{26}\wedge y_{35}\wedge y_{36}\wedge y_{45}\wedge y_{46}.$$

The conjunction has 12 output values from the 15 comparators.

Table 6 shows the output values of the 15 comparators for the assignment 001122 of the memory cells ^S1 to ^S6 .

The following conjunction results: $${\overline{y}}_{13}\wedge {\overline{y}}_{14}\wedge {\overline{y}}_{15}\wedge {\overline{y}}_{16}\wedge {\overline{y}}_{23}\wedge {\overline{y}}_{24}\wedge {\overline{y}}_{25}\wedge {\overline{y}}_{26}\wedge {\overline{y}}_{35}\wedge {\overline{y}}_{36}\wedge {\overline{y}}_{45}\wedge {\overline{y}}_{46}.$$

The conjunction has 12 output values from the 15 comparators.

in den Vergleichern VGL_ij paarweise verglichen werden.The associated conjunctions result accordingly for the remaining assignments of the memory cells with two twos, two ones and two zeros. 12 of the 15 output values (inverted or not) that are not indefinite form the corresponding conjunctions. These conjunctions assume the value 1 precisely when the allocations corresponding to them and the values read from the memory cells are stored in the memory cells S ¹ to S ⁶ ${\text{W}}_A^1\text{until}{W}_A^6$

be compared in pairs in the comparators VGL _ij .

Example: Transformation and Inverse Transformation

• - in n₁ Speicherzellen n₁ erste Werte,
• - in n₂ Speicherzellen n₂ zweite Werte, ⋮
• - in n_K Speicherzellen n_K K-te Werte

gespeichert werden. Mit anderen Worten, es gibt eine Anzahl von K Teilgruppen. In jeder Teilgruppe wird eine bestimmte Anzahl gleicher Werte gespeichert. In unterschiedlichen Teilgruppe werden unterschiedliche Werte gespeichert. 8th FIG. 12 shows an embodiment in which m data bits are stored in memory cells S ¹ to S ⁿ of a memory 803. FIG. A group of n memory cells S ¹ to S ⁿ is shown, where

• - in n ₁ memory cells n ₁ first values,
• - in n ₂ memory cells n ₂ second values, ⋮
• - in n _K memory cells n _K Kth values

get saved. In other words, there are K number of subgroups. A certain number of identical values are stored in each subgroup. Different values are stored in different subgroups.

The m bits of data stored in the group of n memory cells may also be referred to as an m-bit byte or simply a byte. The letters m or k are used as variables for the number of data bits.

mit $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot \dots \cdot \left(\begin{array}{c}n-n_1-\dots -n_{K-1}\\ n_K\end{array}\right)=N.$$

und m < n. Hierbei bezeichnet N die Anzahl der Möglichkeiten, die Gruppe von n Speicherzellen mit n₁ ersten Werten, n₂ zweiten Werten, usw. bis n_K K-ten Werten zu belegen.applies $$2^m\le N$$

with $$\left(\begin{array}{c}n\\ n_1\end{array}\right)\cdot \left(\begin{array}{c}n-n_1\\ n_2\end{array}\right)\cdot ...\cdot \left(\begin{array}{c}n-{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">n</figure-callout>}}_1-...-n_{K-1}\\ n_K\end{array}\right)=N.$$

and m<n. In this case, N designates the number of possibilities for occupying the group of n memory cells with n ₁ first values, n ₂ second values, etc. up to n _K K th values.

• - eine Anzahl n₁ der Werte von z₁, z₂, ..., z_n gleich 0 sind,
• - eine Anzahl n₂ der Werte von z₁, z₂, ..., z_n gleich 1 sind, ... ⋮
• - eine Anzahl n_K der Werte von z₁, z₂, ... ,z_n gleich K - 1 sind.

A transformation circuit 801 performs a transformation T _S (m,n) which transforms 2 ^m data bits of word length m into 2 ^m of the N values z ₁ , z ₂ , ..., z _n , where

• - a number n ₁ of the values of z ₁ , z ₂ , ..., z _n are equal to 0,
• - a number n ₂ of the values of z ₁ , z ₂ , ..., z _n are equal to 1, ... ⋮
• - a number n _K of the values of z ₁ , z ₂ , ... , z _n are equal to K-1.

If not all 2 ^m of the data bits of word length m are required, it is possible to transform only the required data bits and store them in the memory cells.

• - n₁ der Werte von z₁,... ,z_n den Wert 0,
• - n₂ der Werte von z₁,... ,z_n den Wert 1, ... ⋮
• - n_K der Werte von z₁,... , z_n den Wert (K - 1)

aufweisen.The transformation circuit 801 is configured, for example, to map the transformation T(m,n) of bit values x ₁ ,...,x _m of word width m into values z ₁ ,...,z _n of word width n contained in the memory cells S ¹ to S ⁿ are to be stored, where

• - n ₁ of the values of z ₁ ,... ,z _n the value 0,
• - n ₂ of the values of z ₁ ,... ,z _n the value 1, ... ⋮
• - n _K of the values of z ₁ ,... , z _n the value (K - 1)

exhibit.

The m bits x ₁ ,...,x _m can be referred to as data bits, for example. In particular, it is possible to distinguish such data bits from values that are written into the memory cells of the memory. If the bits x ₁ to x _m are, for example, bits of a code word of an error code for error detection or error correction, these bits can also include at least one check bit of the error code or just be check bits of the error code.

bis $z_n^{\text{'}}$

werden mittels einer Transformationsschaltung 802, die eine Transformation $T_S^{-1}\left(n,m\right)$

bereitstellt, in Datenbits $x_1^{\text{'}}\text{ bis }{x}_m^{\text{'}}$

tranformiert, wobei im fehlerfreien Fall gilt: $$x_1^{\text{'}},\dots ,x_m^{\text{'}}=x_1,\dots ,x_m.$$

The memory cells S ¹ to S ⁿ are read out and the values read out ${\mathrm{e.g}}_1^{\text{'}}$

until ${\mathrm{e.g}}_n^{\text{'}}$

are made by a transform circuit 802 performing a transform $T_S^{-1}\left(n,m\right)$

provides, in data bits $x_1^{\text{'}}\text{until}{x}_m^{\text{'}}$

transformed, whereby in the error-free case the following applies: $$x_1^{\text{'}},...,x_m^{\text{'}}=x_1,...,x_m.$$

The transformation circuit 801 and the transformation circuit 802 are preferably set up in such a way that the following applies to the transformation T (m, n) and the inverse transformation T ⁻¹ (n, m): $$T^{-1}\left(n,m\right)\left\{T\left(m,n\right)\left[{\mathrm{<figure-callout\; id="1"\; label="x"\; filenames="DE102017103347B4\_0230.png,DE102017103347B4\_0232.png"\; state="\{\{state\}\}">x</figure-callout>}}_1,...,x_m\right]\right\}=x_1,...,x_m.$$

If the bits x ₁ to x _m are referred to as m-bit bytes, an m-bit byte is stored as a word z ₁ to z _n in n memory cells of the memory, with a predetermined number of n ₁ first memory cells having a first value, a predetermined number of n ₂ second memory cells store a second value, etc. and a predetermined number n _K of K th memory cells store a K th value.

Example: With K=2, n ₁ first memory cells store a first value 0 and n ₂ second memory cells store a second value 1. Code words of an n ₂ -of-n code are then stored in the memory cells S ¹ to S ⁿ .

Another example: If four values can be stored in each of the memory cells S ¹ to S ⁿ , it is possible to store the first value in n ₁ memory cells, the second value in n ₂ memory cells, the third value in n ₃ memory cells and the third value in n ₄ memory cells store fourth value. Where: n ₁ + n ₂ + n ₃ + n ₄ = n.

As described, it is possible to compare physical properties (e.g. physical values) of different read memory cells with one another. As a result, error probabilities can be at least partially reduced. An error can only occur if both of the values compared in pairs during reading out are simultaneously in the overlapping area of frequency distributions of the physical values, and not when only a single value is in such an overlapping area.

Example: Fig.9

9 Figure 12 shows an example of storing m-bit bytes in n memory cells each, where m=4, n=6 and n ₁ =n ₂ =3. A first digital value 0 is stored in n ₁ =3 memory cells and a second digital value 1 is stored in n ₂ =3 second memory cells. The 4-bit byte is stored in 6 memory cells as a 6-bit word of a 3-of-6 code.

9 shows the storage of three 4-bit bytes in 6 memory cells each of a memory 901, the memory cells being able to store digital binary values by way of example. A transformation circuit 902 transforms 4-bit bytes x ₁ , x ₂ , x ₃ , x ₄ into binary values z ₁ to z ₆ , which are stored in memory cells S ¹ to S ⁶ of memory 901 . Furthermore, 4-bit bytes x ₃ , x ₆ , x ₇ , x ₈ are transformed by a transformation circuit 903 into binary values z ₇ to z ₁₂ , which are stored in memory cells S ⁷ to S ¹² of memory 901 . Also, 4-bit bytes x ₉ , x ₁₀ , x ₁₁ , x ₁₂ are transformed by a transformation circuit 904 into binary values z ₁₃ to z ₁₈ , which are stored in memory cells S ¹³ to S ¹⁸ of memory 901 .

Each of the transform circuits 902 through 904 performs a transform T(4,6). The transformation T(4,6) can be described in the form of a table that associates a different codeword of a 3-of-6 code with each of the 16 possible 4-bit values. An example is shown in Table 7. Table 7 × ₁ x2 _{_} × ₃ x ₄ z ₁ z ₂ z ₃ z ₄ z ₅ z ₆ 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 1

Such a table can be implemented, for example, in the form of a combinatorial (logical) circuit or in the form of a read-only memory.

If the values or the memory cell values that are stored in the memory cells are binary values, then these values can also be referred to as memory bits.

In the example described, the inversion of the data bits results in an inversion of the memory bits.

Optionally, different 4-bit bytes can be transformed into storage values, in particular storage bits, with a functionally identical transformation or a transformation circuit having the same effect. It is also possible to transform different 4-bit bytes into memory bits or generally into memory values with functionally different transformations or transformation circuits. For example, at least two of the transformation circuits 902-904 may implement different transformations. Correspondingly, the transformation circuits 905 to 907 then provide the appropriate inverse transformations.

For example, transformations can be provided in which an inversion of the 4-bit byte x leads to an inversion of the digital values z.

gelesen und durch die Transformationsschaltung 905 in 4-Bit Bytes $x_1^{\text{'}},x_2^{\text{'}},x_3^{\text{'}},x_4^{\text{'}}$

x₁, transformiert. Entsprechend werden Speicherbits $z_7^{\text{'}},z_8^{\text{'}},z_9^{\text{'}},z_{10}^{\text{'}},z_{11}^{\text{'}},z_{12}^{\text{'}}$

z₂, gelesen und durch die Transformationsschaltung 906 in 4-Bit Bytes $x_5^{\text{'}},x_6^{\text{'}},x_7^{\text{'}},x_8^{\text{'}}$

x₃, transformiert. Auch werden Speicherbits $z_{13}^{\text{'}},z_{14}^{\text{'}},z_{15}^{\text{'}},z_{16}^{\text{'}},z_{17}^{\text{'}},z_{18}^{\text{'}}$

gelesen und durch die Transformationsschaltung 907 in 4-Bit Bytes $x_9^{\text{'}},x_{10}^{\text{'}},x_{11}^{\text{'}},x_{12}^{\text{'}}$

transformiert.When read from memory 901, memory bits ${\mathrm{e.g}}_1^{\text{'}},{\mathrm{e.g}}_2^{\text{'}},{\mathrm{e.g}}_3^{\text{'}},{\mathrm{e.g}}_4^{\text{'}},{\mathrm{e.g}}_5^{\text{'}},{\mathrm{e.g}}_6^{\text{'}}$

read and converted to 4-bit bytes by transform circuit 905 $x_1^{\text{'}},x_2^{\text{'}},x_3^{\text{'}},x_4^{\text{'}}$

x ₁ , transformed. Accordingly, memory bits ${\mathrm{e.g}}_7^{\text{'}},{\mathrm{e.g}}_{\mathrm{8th}}^{\text{'}},{\mathrm{e.g}}_9^{\text{'}},{\mathrm{e.g}}_{10}^{\text{'}},{\mathrm{e.g}}_{11}^{\text{'}},{\mathrm{e.g}}_{12}^{\text{'}}$

z ₂ , read and transformed by transform circuit 906 into 4-bit bytes $x_5^{\text{'}},x_6^{\text{'}},x_7^{\text{'}},x_{\mathrm{8th}}^{\text{'}}$

x ₃ , transformed. Also, memory bits ${\mathrm{e.g}}_{13}^{\text{'}},{\mathrm{e.g}}_{14}^{\text{'}},{\mathrm{e.g}}_{15}^{\text{'}},{\mathrm{e.g}}_{16}^{\text{'}},{\mathrm{e.g}}_{17}^{\text{'}},{\mathrm{e.g}}_{18}^{\text{'}}$

read and converted to 4-bit bytes by transform circuit 907 $x_9^{\text{'}},x_{10}^{\text{'}},x_{11}^{\text{'}},x_{12}^{\text{'}}$

transformed.

die eine inverse Transformation der in Tabelle 7 gezeigten Transformation ist, wonach jeweils n = 6 Zustandsbits $z_{\left(i\cdot n\right)}^{\text{'}}$

(i = 1...3 und n = 1...6) in jeweils m = 4 Datenbits $x_{\left(i\cdot m\right)}^{\text{'}}$

(i = 1...3 und m = 1... 4) transformiert werden.Each of the transform circuits 905, 906 and 907 realizes a transform $T_S^{-1}\left(6.4\right),$

which is an inverse transform of the transform shown in Table 7, where each n = 6 state bits ${\mathrm{e.g}}_{\left(i\cdot n\right)}^{\text{'}}$

(i = 1...3 and n = 1...6) in m = 4 data bits each $x_{\left(i\cdot m\right)}^{\text{'}}$

(i = 1...3 and m = 1...4).

von den ursprünglich gespeicherten Bits z(_i·n) unterscheiden. Somit können sich auch die gelesenen Datenbits $x_{i\cdot m}^{\text{'}}$

von den geschriebenen Datenbits x_i·m unterscheiden.The memory bits read from the memory 901 may differ due to errors ${\mathrm{e.g}}_{\left(i\cdot n\right)}^{\text{'}}$

differ from the originally stored bits z( _i·n ). This means that the data bits read can also change $x_{i\cdot m}^{\text{'}}$

differ from the written data bits x _i·m .

und die ersten 4 sich hieraus ergebenden Datenbits $x_1^{\text{'}}\text{ bis }{x}_4^{\text{'}}:$

$$z_1,z_2,z_3,z_4,z_5,z_6=z_1^{\text{'}},z_2^{\text{'}},z_3^{\text{'}},z_4^{\text{'}},z_5^{\text{'}},z_6^{\text{'}}$$

$$x_1,x_2,x_3,x_4=x_1^{\text{'}},x_2^{\text{'}},x_3^{\text{'}},x_4^{\text{'}}.$$

If no error has occurred, then the first 4 data bits x ₁ to x ₄ , the first 6 transformed bits z ₁ to z ₆ , the first 6 bits to be transformed back apply ${\mathrm{e.g}}_1^{\text{'}}\text{until}{\mathrm{e.g}}_6^{\text{'}}$

and the first 4 resulting data bits $x_1^{\text{'}}\text{until}{x}_4^{\text{'}}:$

$${\mathrm{e.g}}_1,{\mathrm{e.g}}_2,{\mathrm{e.g}}_3,{\mathrm{e.g}}_4,{\mathrm{e.g}}_5,{\mathrm{e.g}}_6={\mathrm{e.g}}_1^{\text{'}},{\mathrm{e.g}}_2^{\text{'}},{\mathrm{e.g}}_3^{\text{'}},{\mathrm{e.g}}_4^{\text{'}},{\mathrm{e.g}}_5^{\text{'}},{\mathrm{e.g}}_6^{\text{'}}$$

$$x_1,x_2,x_3,x_4=x_1^{\text{'}},x_2^{\text{'}},x_3^{\text{'}},x_4^{\text{'}}.$$

This applies accordingly to the second 4 data bits and the third 4 data bits.

veranschaulicht. Hierbei handelt es sich um die inverse Abbildung der in der Tabelle 7 gezeigten Zuordnungen. Tabelle 8 $z_1^{\text{'}}$

$z_2^{\text{'}}$

$z_3^{\text{'}}$

$z_4^{\text{'}}$

$z_5^{\text{'}}$

$z_6^{\text{'}}$

$x_1^{\text{'}}$

$x_2^{\text{'}}$

$x_3^{\text{'}}$

$x_4^{\text{'}}$

1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 For the sake of completeness, a table 8 is shown showing a transformation $T_S^{-1}\left(6.4\right)$

illustrated. This is the inverse mapping of the mappings shown in Table 7. Table 8 ${\mathrm{e.g}}_1^{\text{'}}$

${\mathrm{e.g}}_2^{\text{'}}$

${\mathrm{e.g}}_3^{\text{'}}$

${\mathrm{e.g}}_4^{\text{'}}$

${\mathrm{e.g}}_5^{\text{'}}$

${\mathrm{e.g}}_6^{\text{'}}$

$x_1^{\text{'}}$

$x_2^{\text{'}}$

$x_3^{\text{'}}$

$x_4^{\text{'}}$

1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0

können zugehörige beliebige Werte der Datenbits $x_1^{\text{'}}\text{ bis }{x}_4^{\text{'}}$

x₁ für die Synthese der inversen Transformationsschaltung 905 vorgegeben werden. Es ist beispielsweise möglich, solche beliebigen Werte als unbestimmte Werte, die auch als „Don't-care“ Werte bezeichnet werden, bei der Optimierung durch ein Synthesetool festlegen zu lassen. Auch ist es eine Option, diese Werte zu 0 zu setzen.For memory bit values not listed in Table 8 ${\mathrm{e.g}}_1^{\text{'}}\text{until}{\mathrm{e.g}}_6^{\text{'}}$

can associated arbitrary values of the data bits $x_1^{\text{'}}\text{until}{x}_4^{\text{'}}$

x ₁ for the synthesis of the inverse transform circuit 905 are given. It is possible, for example, to have such arbitrary values specified as indeterminate values, which are also referred to as "don't care" values, during the optimization by a synthesis tool. It is also an option to set these values to 0.

Error detection and/or error correction

If erroneous memory bits are associated with erroneous data bits by the inverse transformation circuit 905, then an erroneous 4-bit byte can be recognized and/or corrected by an error code. This is explained below by way of example.

10 shows an exemplary circuit arrangement that enables error detection or combined error detection with error correction, the data bits being transformed by a transformation circuit into memory bits, which are stored in memory cells of a memory.

Data bits x are present at the input of a coder 1001, at the output of which bits y=Cod(x) coded according to an error code C ₁ are provided.

It is possible that the error code C ₁ is a byte error correcting and/or detecting code, for example a Reed-Solomon code. It is also possible that the error code C ₁ is a code that corrects and/or detects bit errors, for example a BCH code, a Hsiao code, a Hamming code, a low-density parity code or another code.

The bits (or bytes) y=Cod(x) output at the output of the coder 1001 are transformed into digital values z(y) by means of a transformation circuit 1002, which values are written into memory cells of a memory 1003. The transformation circuit 1002 provides a transformation T _S .

In a group of n memory cells each, n ₁ first values are stored in n ₁ first memory cells, n ₂ second values in n ₂ second memory cells, etc. up to n _K K th values in n _K K th memory cells. The following applies: n ₁ + n ₂ + ... + n _K = n.

In a next step, values z′(y) are read from the corresponding memory cells of memory 1003 . It is possible that the values z'(y) differ from the written values z(y) due to at least one error. If no error has occurred, z(y) = z'(y) applies.

bereitstellt, in binäre Werte y' transformiert.The z'(y) values read from the memory 1003 are transformed by an inverse transform circuit 1004, which performs a transform $T_S^{-1}$

provides, transformed into binary values y'.

Ist ein Fehler aufgetreten, gilt $$y\text{'}\ne y=Cod\left(x\right).$$

If no error has occurred, $$y\text{'}=y=CO\mathrm{i.e}\left(x\right).$$

If an error has occurred, $$y\text{'}\ne y=CO\mathrm{i.e}\left(x\right).$$

A correction value generator 1005 forms a correction value e of corresponding word length in accordance with the error code C ₁ , the components of the correction value e being XORed with the values y′ in an XOR circuit 1007 component by component. The XOR circuit is a circuit that performs an exclusive OR operation on the input signals and provides the result of this operation at the output. The XOR circuit supplies the logical value 1 at the output if the signals at the inputs are the same. If the signals at the inputs are different, the XOR circuit supplies the logical value 0 at the output.

A corrected value y ^cor is provided at the output of the XOR circuit 1007 . If an error that can be corrected by the code C ₁ using the correction value generator 1005 has occurred, the corrected bits are equal to the coded bits, ie $$y^{cO\mathrm{right}}=y=CO\mathrm{i.e}\left(x\right).$$

Furthermore, an error detection circuit 1006 is shown, which can be used to determine whether an error and/or a specific type of error that can be identified using the error code C ₁ is present. The error detection circuit 1006 is supplied with the value y′ and the error detection circuit 1006 outputs error information 1008 .

If the error code is, for example, a 1-byte error-correcting code and 2-byte error-detecting code, then the error detection circuit 1006 can output different error information 1008 depending on whether no error, a 1-byte error or a 2-byte error has occurred. For example, the error information 1008 can be encoded as a bit sequence 00, 01 or 10 (ie a bit sequence with two bits in this example).

Optionally, the error detection circuit 1006 and the correction value generator 1005 can be implemented jointly or partially jointly.

If the error code C ₁ is a separable code in which the data bits are not changed during coding by the encoder 1001, then if no error has occurred or if an error which can be corrected by the error code C ₁ has occurred, from the XOR circuit 1006 bits output equal to the corresponding data bits input to encoder 1001 and stored in memory 1003 after being transformed by transform circuit 1002.

11 shows an alternative circuit arrangement that enables error correction or error detection, possibly with error correction.

Data bits x are present at the input of a transformation circuit 1101 and are transformed into values z(x). The values z(x) of the transformation circuit 1101 are present at the input of a coder 1102, which is set up in such a way that data Cod(z(x)) coded using an error code C ₂ are provided at its output.

The encoder 1102 can provide an encoding function and a check bit transforming function.

As an example, it should be assumed that the error code C ₂ is a separable code, so that the values z(x) that are present at the input of the coder 1102 contain unchanged in the output data Cod(z(x)) determined by the coder and um Check bits corresponding to error code C ₂ have been added.

In this example, the coder 1102 is designed in such a way that it outputs the values z(x) present at its input unchanged at its output (in this case, the input and the output can each have a plurality of lines, with each line being assigned to a bit) and additionally forms check bits corresponding to the error code C ₂ from the bits z(x) and transforms these check bits before storing them in a memory 1103.

For example, the values z(x) form groups of n bits consisting of code words of an n ₁ -of-n code. The transformed check bits provided by the coder 1102 can likewise be or include n ₁ out of n code words.

It is possible, for example, for the check bits determined from the bits z(x) by the error code C ₂ to be provided by the coder 1102 as bits in which two bits are complementary to one another. Each check bit is transformed into two bits and stored in two memory cells. For example, a check bit 1 can be transformed into bits 10 and a check bit 0 can be transformed into bits 01 and stored in two memory cells each.

Other transformations of the check bits into memory cell values are also possible. It is thus conceivable, for example, to write the check bits into the memory 1103 in triplicate or twice and/or in some other way in an error-tolerant manner.

In a group of n memory cells of the memory 1103, n ₁ first values in a first number of n ₁ first memory cells become n ₂ second values in a second number of n ₂ second memories cells, etc. up to n _KK th values are stored in a predetermined K th number of n _KK th memory cells. The following applies: n ₁ +n ₂ +... +n _K = n.

in the in 10 In the circuit arrangement shown, the error processing is carried out using the data bits. In contrast, in the in 11 circuit arrangement shown, the error processing based on the memory cell values, which are determined from the data bits by the transformation circuit 1101. The memory cell values are memory bits, for example. Error processing is understood here as error detection and/or error correction.

12 shows another example of a variant of the in 11 circuit arrangement shown.

Data bits x are present at the input of a transformation circuit 1201 and are transformed into code words [3-of-6] ₁ , with each 4 bits of the data bits being transformed into a 3-of-6 code word. These 3-of-6 codewords [3 - out - 6] ₁ are provided at the output of transform circuit 1201 . A code word of the 3-of-6 code is reversibly assigned to each of the 16 4-bit values by the transformation circuit 1201 .

The output of the transformation circuit 1201 is connected to the input of a check bit generator 1202 which determines check bits Pr for the bits of the 3-out-of-6 code words corresponding to an error code and makes them available at its output.

For example, the check bit generator 1202 generates check bits of a BCH code. The bits that are output by the transformation circuit 1201 and the check bits that are output by the check bit generator 1202 then form a code word of the BCH code if there are no errors.

Accordingly, another error code can also be used instead of the BCH code. Several error codes can also be used in combination with one another.

The output of the transformation circuit 1201 is also connected to the input of a memory 1204, so that the 3-out-of-6 code words obtained from the data bits by means of the transformation circuit 1201 (also without check bits) can be stored in the memory 1204.

The output of the check bit generator 1202 is connected to the input of a check bit transformer 1203, which transforms the check bits provided into 3-of-6 code words [3-of-6] ₂ and makes them available at its output.

The output of check bit transformer 1203 is connected to the input of memory 1204 . For example, separate data inputs of the memory can be used for this. Thus, the 3-of-6 codewords [3-of-6] ₂ generated by the check bit transformer 1203 based on the check bits Pr can be stored in the memory 1204. FIG.

In the error-free case, those bits are stored in the memory 1204 which are 3-of-6 code words. These bits are also referred to as memory cell values.

From the data bits x, the transformation circuit 1201 forms code words [3-of-6] ₁ of the 3-of-6 code, which are written into the memory 1204. These code words [3 - out - 6] ₁ form memory cell values for memory cells of memory 1204.

From the bits of the code words [3-out-6] ₁ , check bits Pr are determined by a check bit generator 1202 according to the error code used and are output at its output. The check bit transformer 1203 transforms the check bits Pr into codewords [3-of-61 ₂ of the 3-of-6 code. These code words [3 - out - 6] ₂ form memory cell values for memory cells of the memory 1204, which were formed from the check bits Pr.

Thus, in the memory 1204, the code words [3 - out - 6] ₁ and the code words [3 - out - 6] ₂ are stored. Bit errors can occur during storage or reading, which falsify code words [3 - off - 6] ₁ and code words [3 - off - 6] ₂ into erroneous bits.

die den Datenbits zugeordnet sind und Bits ${\left[3-aus-6\right]}_2^{\text{'}},$

die den Prüfbits der transformierten Datenbits zugeordnet sind, aus dem Speicher 1204 ausgegeben. Die Bits ${\left[3-aus-6\right]}_1^{\text{'}}$

als auch die Bits ${\left[3-aus-6\right]}_2^{\text{'}}$

können Bitfehler enthalten. Im fehlerfreien Fall gilt: $${\left[3-aus-6\right]}_1^{\text{'}}={\left[3-aus-6\right]}_1$$

$${\left[3-aus-6\right]}_2^{\text{'}}={\left[3-aus-6\right]}_2.$$

When reading, bits ${\left[3-a\mathrm{and}s-6\right]}_1^{\text{'}},$

associated with the data bits and bits ${\left[3-a\mathrm{and}s-6\right]}_2^{\text{'}},$

associated with the check bits of the transformed data bits are output from memory 1204. the bits ${\left[3-a\mathrm{and}s-6\right]}_1^{\text{'}}$

as well as the bits ${\left[3-a\mathrm{and}s-6\right]}_2^{\text{'}}$

may contain bit errors. In the error-free case: $${\left[3-a\mathrm{and}s-6\right]}_1^{\text{'}}={\left[3-a\mathrm{and}s-6\right]}_1$$

$${\left[3-a\mathrm{and}s-6\right]}_2^{\text{'}}={\left[3-a\mathrm{and}s-6\right]}_2.$$

ausgegeben werden, ist mit dem Eingang eines inversen Prüfbittransformierers 1205 verbunden, der basierend auf den Bits ${\left[3-aus-6\right]}_2^{\text{'}}$

eventuell fehlerhaften Prüfbits Pr' bestimmt und sie an seinem Ausgang bereitstellt. Der inverse Prüfbittransformierer 1205 implementiert eine inverse Transformation zu der Transformation, die der Prüfbittransformierer 1203 umsetzt.The output of memory 1204, where the bits ${\left[3-a\mathrm{and}s-6\right]}_2^{\text{'}}$

is connected to the input of a check bit inverse transformer 1205 which is calculated based on the bits ${\left[3-a\mathrm{and}s-6\right]}_2^{\text{'}}$

any faulty check bits Pr' and makes them available at its output. Inverse check bit transformer 1205 implements an inverse transform to the transform that check bit transformer 1203 implements.

If there are no errors, the inverse check bit transformer 1205 outputs the same check bits Pr that were formed by the check bit generator 1202 at its output.

die den Datenbits entsprechen. Somit können diese eventuell fehlerhaften Prüfbits Pr' zur Fehlerkorrektur der eventueller Bitfehler der Bits ${\left[3-aus-6\right]}_1^{\text{'}}$

entsprechend dem verwendeten 3-aus-6-Codes genutzt werden.The possibly erroneous check bits Pr' are the check bits of the bits ${\left[3-a\mathrm{and}s-6\right]}_1^{\text{'}},$

corresponding to the data bits. Thus, these possibly erroneous check bits Pr' can be used for error correction of the possible bit errors of the bits ${\left[3-a\mathrm{and}s-6\right]}_1^{\text{'}}$

according to the 3-of-6 code used.

in korrigierte Bits ${\left[3-aus-6\right]}_1^{cor}$

entsprechend dem verwendeten Fehlercode.The output of the memory 1204 and the output of the inverse check bit transformer 1205 are each connected to an input of a corrector 1206 . Corrector 1206 corrects the bits ${\left[3-a\mathrm{and}s-6\right]}_1^{\text{'}}$

into corrected bits ${\left[3-a\mathrm{and}s-6\right]}_1^{cO\mathrm{right}}$

according to the error code used.

If any errors that have occurred can be corrected by the error code used, the following applies: $${\left[3-a\mathrm{and}s-6\right]}_1^{cO\mathrm{right}}={\left[3-a\mathrm{and}s-6\right]}_1.$$

bereitgestellt. Der Ausgang des Korrektors 1206 ist mit dem Eingang einer inversen Transformationsschaltung 1207 verbunden, die eine Transformation durchführt, die invers zu der von der Transformationsschaltung 1201 durchgeführten Transformation ist. An dem Ausgang der inversen Transformationsschaltung 1207 werden die Datenbits x^cor bereitgestellt. Dabei handelt es sich ggf. um korrigierte Datenbits oder - falls kein Fehler aufgetreten ist - um die Datenbits x.At the output of the corrector 1206 these bits ${\left[3-a\mathrm{and}s-6\right]}_1^{cO\mathrm{right}}$

provided. The output of the corrector 1206 is connected to the input of an inverse transform circuit 1207 which performs a transform which is the inverse of the transform performed by the transform circuit 1201 . The data bits x ^cor are provided at the output of the inverse transformation circuit 1207 . These may be corrected data bits or - if no error has occurred - the data bits x.

If there is no error or if an error that has occurred can be corrected by error code C, the following applies $$x^{cO\mathrm{right}}=x.$$

The circuit arrangement described is an exemplary embodiment in which the error correction of memory cell values takes place using an error code. In this exemplary embodiment, the binary memory cell values are code words of a 3-of-6 code. The 3-of-6 code is used to form memory cell values. The memory cell values can be error-corrected using an error code, for example a Hamming code, a Hsiao code, a BCH code or another code.

Thus, data bits are transformed into memory cell values and check bits of an error code are determined for the bits of the memory cell values. These check bits are now also transformed into memory cell values. The memory cell values of the transformed bits and the transformed check bits are stored in memory. When reading from the memory, the memory cell values that correspond to the check bits are then first transformed back into check bits. The memory cell values corresponding to the data bits are corrected to corrected memory cell values in a conventional corrector using the retransformed check bits and using the error code. The corrected memory cell values, which correspond to the data bits, can then be transformed back into corrected data bits by an inverse transformation.

In addition to the described memory cell values and the described 3-out-of-6 code, other memory cell values, for example code words of a 4-out-of-8 code, can also be used accordingly.

In contrast to the in 12 The exemplary embodiment described takes place in the 10 described embodiment, an error correction of the data bits. Check bits of an error code are determined from the data bits. The data bits and the check bits so determined are transformed together into memory cell values and stored in the memory. When reading out from the memory, any incorrect memory cell values are first transformed back into possibly incorrect data bits and possibly incorrect check bits, and the possibly incorrect data bits are corrected using the error code used.

Example: 3 out of 6 code

A group of n=6 memory cells is assumed below by way of example, with two subgroups each having n ₁ =n ₂ =3 memory cells. Thus, 3-out-of-6 code words, each with three times the binary value 0 and three times the binary value 1, can be stored in the n=6 memory cells.

verschiedene Codewörter mit drei Nullen und drei Einsen, so dass es 20 unterschiedliche Werte gibt, die als 3-aus-6-Codewörter in 6 Speicherzellen gespeichert werden können. Da 2⁴ = 16 < 20 gilt, können in den 6 Speicherzellen 4 Datenbits gespeichert werden.There are $\left(\begin{array}{l}6\\ 3\end{array}\right)=20$

different codewords with three zeros and three ones, so there are 20 different values that can be stored as 3 out of 6 codewords in 6 memory cells. Since 2 ⁴ = 16 < 20, 4 bits of data can be stored in the 6 memory cells.

Table 9 shows a possible assignment of binary 4-bit values stored in 6 memory cells S ¹ to S ⁶ as 3-of-6 code words. The last column of Table 9 is titled “4-bit”; there the 4-bit values are incremented bit-by-bit from 0 to 16 (compare the penultimate column). For each 4-bit value there is exactly one code word of the 3-out-of-6 code used here as an example. The 3-out-of-6 code is characterized by the fact that the value 1 (or the value 0) occurs exactly three times in each code word. For the n = 6 memory cells there are 20 - 16 = 4 code words that are "left over", ie have no associated 4-bit value. Here in the example in Table 9, these are the last four rows of the table, in which the “4-Bit” column contains the symbol “-” four times.

Detection of the fastest read current

13 shows an exemplary circuit arrangement comprising four NOR gates 1301 to 1304 each with three inputs, two NOR gates 1305, 1306 each with two inputs and one NAND gate 1307 with a large number of inputs.

This circuit configuration makes it possible to determine those three memory cells whose time integral over the read current reaches the predetermined threshold value Sw the fastest.

verschiedene Möglichkeiten, drei der 6 Speicherzellen S¹ bis S⁶ mit drei Nullen und drei Einsen zu belegen.There are $\left(\begin{array}{l}6\\ 3\end{array}\right)=20$

different ways to assign three of the 6 memory cells S ¹ to S ⁶ with three zeros and three ones.

The three outputs of the memory cells, which are assigned 0 in the first 16 rows of Table 9, are connected to the inputs of a NOR gate Table 9 p ¹ S ² p3 ^_ p4 ^_ p ⁵ S S ⁶ Value 4 bit 1 1 1 0 0 0 0 0000 1 1 0 1 0 0 1 0001 1 0 1 1 0 0 2 0010 0 1 1 1 0 0 3 0011 1 1 0 0 1 0 4 0100 1 0 1 0 1 0 5 0101 0 1 1 0 1 0 6 0110 1 0 0 1 1 0 7 0111 0 1 0 1 1 0 8th 1000 0 0 1 1 1 0 9 1001 1 1 0 0 0 1 10 1010 1 0 1 0 0 1 11 1011 0 1 1 0 0 1 12 1100 1 0 0 1 0 1 13 1101 0 1 0 1 0 1 14 1110 0 0 1 1 0 1 15 1111 1 0 0 0 1 1 16 ---- 0 1 0 0 1 1 17 ---- 0 0 1 0 1 1 18 ---- 0 0 0 1 1 1 19 ---- tied together. The output of a NOR gate is 1 only if all of its inputs are 0.

The three outputs of the memory cells S ⁴ , S ⁵ and S ⁶ , which have the value 0 according to the first row of Table 9, are routed to the three inputs of the NOR gate 1301 . The three outputs of the memory cells S ³ , S ⁵ and S ⁶ which have the value 0 according to the second row of Table 9 are fed to the three inputs of the NOR gate 1302 . The three outputs of the memory cells S ¹ , S ³ and S ⁵ , which have the value 0 according to row 14 of Table 9, are fed to the three inputs of the NOR gate 1303 . The three outputs of the memory cells S ¹ , S ² and S ⁵ which have the value 0 according to row 15 of Table 9 are fed to the three inputs of the NOR gate 1304 .

This approach is also applied correspondingly to rows 3 to 13, according to which a separate NOR gate is provided for each row, the three inputs of which are connected to those memory cells of the row which have the value 0.

The value 1 is present only at the output of that NOR gate 1301 to 1304 whose inputs all have the value 0. In other words, only that NOR gate 1301 to 1304 supplies the value 1 at its output which is linked to the associated code word according to Table 9. Since the combinations of connections of the inputs to memory cells on all of the NOR gates 1301 to 1304 are different (each code word contains a different arrangement of three zeros), the value 1 is present only once at the outputs of the NOR gates 1301 through 1304.

The NOR gates 1305 and 1306 exemplify a second level of linking of logic signals in 13 : The output of NOR gate 1301 and the output of NOR gate 1302 are connected to the inputs of NOR gate 1305 . The output of NOR gate 1303 and the output of NOR gate 1304 are connected to the inputs of NOR gate 1306 . Thus, in each case two of the outputs of the NOR gates 1301 to 1304 are connected to the inputs of a NOR gate of this second level.

The outputs of the second level NOR gates 1305 to 1306 are connected to one input of the NAND gate 1307 each. At the output of the NAND gate 1307 a signal 1308 is provided.

The NAND gate only supplies the value 0 at its output if all of its inputs have the value 1. As soon as one of the inputs has the value 0, the signal 1308 has the value 1. As stated above, if there are three zeros in the memory cells, only one of the NOT- OR gates 1301 to 1304 change from the value 0 to the value 1 at its output. Correspondingly, the NOR gate 1305 to 1306 connected to the output of the affected NOR gate 1301 to 1304 changes from the value 1 to the value 0. This value 0 causes the signal 1308 to change to the value 1.

in the in 13 In the example shown, there are 16 different ways of distributing three zeros to 6 memory cells (compare Table 9). Correspondingly, there are 16 NOR gates 1301-1304. The outputs of every two of these NOR gates are fed to the inputs of one of the second level NOR gates 1305-1306. Thus, there are 8 second level NOR gates 1305-1306 and the NAND gate 1307 has 8 inputs accordingly.

The signal 1308 at the output of the NAND gate 1307 can be sampled in time.

If the value 1 is determined for the signal 1308 for the first time during sampling, then the signal 1308 can be used as a “hold signal” for 6 latches, which are connected downstream of the respective storage elements S ¹ to S ⁶ . This is in terms of 14 explained in more detail.

(hier mit i = 1...6) aus (hier beispielhaft 6) Speicherzellen des Speichers ausgelesen. Je einer der ausgelesenen physikalischen Werte $W_A^i$

wird einem der Signalverstärker 1401 bis 1406 zugeführt. Bei dem physikalischen Wert $W_A^i$

kann es sich um einen Lesestrom handeln. 14 shows an exemplary circuit arrangement comprising six signal amplifiers (also referred to as sense amplifiers or sense amplifiers) 1401 to 1406. As already explained above, physical values $W_A^i$

(here with i=1 . . . 6) read from (here for example 6) memory cells of the memory. One of the physical values read out $W_A^i$

is supplied to one of the signal amplifiers 1401 to 1406. At the physical value $W_A^i$

it can be a read stream.

Ist das Zeitintegral zu einem Zeitpunkt t kleiner als ein Schwellwert Sw, dann liegt zum Zeitpunkt t am Ausgang des Signalverstärkers 1401 der digitale Wert 1 an. Ist das Zeitintegral zu dem Zeitpunkt t größer als der Schwellwert Sw, dann liegt am Ausgang des Signalverstärkers 1401 der digitale Wert 0 an. Der Ausgang des Signalverstärkers 1401 ist mit dem ersten Eingang eines Latches 1407 verbunden, an dessen zweitem Eingang ein Hold-Signal 1413 anliegt. Ist der Wert des Hold-Signales gleich 0, dann ist das Latch 1407 transparent geschaltet, d.h. der an dem Ausgang des Signalverstärkers 1401 bereitgestellte binäre Wert liegt an dem ersten Eingang einer Logikschaltung 1414 an. Ist der Wert des Hold-Signals gleich 1, dann ist das Latch 1407 eingefroren, d.h. der zu diesem Zeitpunkt an dem ersten Eingang des Latches 1407 anliegende Wert bleibt solange auch an dem Ausgang des Latches 1407 bestehen wie der Wert des Hold-Signals gleich 1 ist.The signal amplifier 1401 determines a time integral of the physical value $W_A^{}$${}_1^{}.$

If the time integral is less than a threshold value Sw at a time t, then the digital value 1 is present at the output of the signal amplifier 1401 at the time t. If the time integral at time t is greater than the threshold value Sw, then the digital value 0 is present at the output of the signal amplifier 1401 . The output of the signal amplifier 1401 is connected to the first input of a latch 1407, at the second input of which a hold signal 1413 is present. If the value of the hold signal is equal to 0, then the latch 1407 is switched to be transparent, ie the binary value provided at the output of the signal amplifier 1401 is present at the first input of a logic circuit 1414 . If the value of the hold signal is 1, then latch 1407 is frozen, i.e. the value present at the first input of latch 1407 at this point in time also remains at the output of latch 1407 for as long as the value of the hold signal is 1 is.

For the function of the latch, which is also referred to as a catch register or state-controlled flip-flop, see “de.wikipedia.org/wiki/Latch”, for example.

The logic circuit 1414 determines the first three zeros, i.e. the fastest three zeros, which appear at the outputs of the latches 1407 to 1412 and then sets the hold signal 1413 to the value 1.

Ist das Zeitintegral zu dem Zeitpunkt t kleiner als derAccordingly, the following apply: The signal amplifier 1402 determines a time integral of the physical value $W_A^{}$${}_2^{}.$

If the time integral at time t is less than

Ist das Zeitintegral zu dem Zeitpunkt t kleiner als der Schwellwert Sw, dann liegt zu dem Zeitpunkt t am Ausgang des Signalverstärkers 1403 der digitale Wert 1 an. Ist das Zeitintegral zu dem Zeitpunkt t größer als der Schwellwert Sw, dann liegt am Ausgang des Signalverstärkers 1403 der digitale Wert 0 an. Der Ausgang des Signalverstärkers 1403 ist mit dem ersten Eingang eines Latches 1409 verbunden, an dessen zweitem Eingang das Hold-Signal 1413 anliegt. Der Ausgang des Latches 1409 ist mit dem dritten Eingang der Logikschaltung 1414 verbunden. Der Signalverstärker 1404 bestimmt ein Zeitintegral des physikalischen Werts $W_A^4.$

Ist das Zeitintegral zu dem Zeitpunkt t kleiner als der Schwellwert Sw, dann liegt zu dem Zeitpunkt t am Ausgang des Signalverstärkers 1404 der digitale Wert 1 an. Ist das Zeitintegral zu dem Zeitpunkt t größer als der Schwellwert Sw, dann liegt am Ausgang des Signalverstärkers 1404 der digitale Wert 0 an. Der Ausgang des Signalverstärkers 1404 ist mit dem ersten Eingang eines Latches 1410 verbunden, an dessen zweitem Eingang das Hold-Signal 1413 anliegt. Der Ausgang des Latches 1410 ist mit dem vierten Eingang der Logikschaltung 1414 verbunden. Der Signalverstärker 1405 bestimmt ein Zeitintegral des physikalischen Werts $W_A^5.$

Ist das Zeitintegral zu dem Zeitpunkt t kleiner als der Schwellwert Sw, dann liegt zu dem Zeitpunkt t am Ausgang des Signalverstärkers 1405 der digitale Wert 1 an. Ist das Zeitintegral zu dem Zeitpunkt t größer als der Schwellwert Sw, dann liegt am Ausgang des Signalverstärkers 1405 der digitale Wert 0 an. Der Ausgang des Signalverstärkers 1405 ist mit dem ersten Eingang eines Latches 1411 verbunden, an dessen zweitem Eingang das Hold-Signal 1413 anliegt. Der Ausgang des Latches 1411 ist mit dem fünften Eingang der Logikschaltung 1414 verbunden. Der Signalverstärker 1406 bestimmt ein Zeitintegral des physikalischen Werts $W_A^6.$

Ist das Zeitintegral zu dem Zeitpunkt t kleiner als der Schwellwert Sw, dann liegt zu dem Zeitpunkt t am Ausgang des Signalverstärkers 1406 der digitale Wert 1 an. Ist das Zeitintegral zu dem Zeitpunkt t größer als der Schwellwert Sw, dann liegt am Ausgang des Signalverstärkers 1406 der digitale Wert 0 an. Der Ausgang des Signalverstärkers 1406 ist mit dem ersten Eingang eines Latches 1412 verbunden, an dessen zweitem Eingang das Hold-Signal 1413 anliegt. Der Ausgang des Latches 1412 ist mit dem sechsten Eingang der Logikschaltung 1414 verbunden.threshold value Sw, then the digital value 1 is present at the time t at the output of the signal amplifier 1402 . If the time integral at time t is greater than the threshold value Sw, then the digital value 0 is present at the output of the signal amplifier 1402 . The output of the signal amplifier 1402 is connected to the first input of a latch 1408, at the second input of which the hold signal 1413 is present. The output of latch 1408 is connected to the second input of logic circuit 1414 . The signal amplifier 1403 determines a time integral of the physical value $W_A^{}$${}_3^{}.$

If the time integral at time t is less than the threshold value Sw, then the digital value 1 is present at the output of the signal amplifier 1403 at time t. If the time integral at time t is greater than the threshold value Sw, then the digital value 0 is present at the output of the signal amplifier 1403 . The output of the signal amplifier 1403 is connected to the first input of a latch 1409, at the second input of which the hold signal 1413 is present. The output of latch 1409 is connected to the third input of logic circuit 1414 . The signal amplifier 1404 determines a time integral of the physical value $W_A^4.$

If the time integral at time t is less than the threshold value Sw, then the digital value 1 is present at the output of the signal amplifier 1404 at time t. If the time integral at time t is greater than the threshold value Sw, then the digital value 0 is present at the output of the signal amplifier 1404 . The output of the signal amplifier 1404 is connected to the first input of a latch 1410, at the second input of which the hold signal 1413 is present. The output of latch 1410 is connected to the fourth input of logic circuit 1414 . The signal amplifier 1405 determines a time integral of the physical value $W_A^5.$

If the time integral at time t is less than the threshold value Sw, then the digital value 1 is present at the output of the signal amplifier 1405 at time t. If the time integral at time t is greater than the threshold value Sw, then the digital value 0 is present at the output of the signal amplifier 1405 . The output of the signal amplifier 1405 is connected to the first input of a latch 1411, at the second input of which the hold signal 1413 is present. The output of latch 1411 is connected to the fifth input of logic circuit 1414 . The signal amplifier 1406 determines a time integral of the physical value $W_A^6.$

If the time integral at time t is less than the threshold value Sw, then the digital value 1 is present at the output of the signal amplifier 1406 at time t. If the time integral at time t is greater than the threshold value Sw, then the digital value 0 is present at the output of the signal amplifier 1406 . The output of the signal amplifier 1406 is connected to the first input of a latch 1412, at the second input of which the hold signal 1413 is present. The output of latch 1412 is connected to the sixth input of logic circuit 1414 .

By way of example, a diagram 1415 shows a read current over time for signal amplifier 1401. The read current at signal amplifier 1401 then reaches the threshold value Sw at a point in time t ₁ . Accordingly, in 14 also shows diagrams 1416 to 1420 for the signal amplifiers 1402 to 1406, according to which a point in time t _i indicates when the i-th signal amplifier 1401 to 1406 reaches the threshold value Sw.

As long as the integral of the read current is less than the threshold value Sw up to the point in time t _i , the respective signal amplifier outputs the value 1; If the integral of the read current from time t _i is greater than the threshold value Sw, the respective signal amplifier outputs the value 0.

bestimmt, wobei t größer ist als t₁, t₃ und t₅ und wobei t kleiner ist als t₂, t₄ und t₆. Damit liegt zum Zeitpunkt t an den Ausgängen der Signalverstärker 1401, 1403 und 1405 jeweils der Wert 0 an, während an den Ausgängen der Signalverstärker 1402, 1404 und 1406 noch der Wert 1 anliegt. Die Logikschaltung 1414 erkennt diese ersten drei Nullen und setzt das Hold-Signal 1413 von 0 auf 1, daraufhin werden die Latches 1407 bis 1412 „eingefroren“.in the in 14 example shown is at a time t the physical values $W_A^{}$${}_1^{}\text{until}{W}_A^6$

where t is greater than t ₁ , t ₃ and t ₅ and where t is less than t ₂ , t ₄ and t ₆ . The value 0 is thus present at the time t at the outputs of the signal amplifiers 1401, 1403 and 1405, while the value 1 is still present at the outputs of the signal amplifiers 1402, 1404 and 1406. The logic circuit 1414 recognizes these first three zeros and sets the hold signal 1413 from 0 to 1, after which the latches 1407 to 1412 are “frozen”.

The logic circuit 1414 can be implemented, for example, by the in 13 circuit arrangement shown can be implemented.

Claims (21)

Method for reading memory cells from a memory, - in which physical values are determined from a number of n memory cells, where n is at least three, the physical values being points in time, - in which the physical values are at least partially compared with one another, - in in which the n memory cells K are assigned different digital memory cell values on the basis of the compared physical values, - in which the digital memory cell values obtained in this way are assigned a code word of an n ₁ -, ..., n _K -out of n code, - in which the physical values are at least partially compared with one another, so that an order of at least some of the physical values is determined, - in which the K different digital memory cell values are assigned to the n memory cells on the basis of the order. Method according to one of the preceding claims, in which the physical values are determined by reading out the n memory cells. Method according to one of the preceding claims, in which all physical values are compared with one another. A method according to any one of the preceding claims, wherein K = 2 such that the n ₁ , ..., n _K -of-n code is an n ₁ -,n ₂ -of-n code, where n ₁ first memory cell values have the same first value among one another and n ₂ second memory cell values have the same second value among one another, the first value being different from the second value. Procedure according to one of Claims 1 until 3 , where K = 3 such that the n ₁ -,...,n _K -of-n code is an n ₁ -,n ₂ -,n ₃ -of-n code, where n ₁ first Memory cell values have the same first value among one another, n ₂ second memory cell values have the same second value among one another and n ₃ third memory cell values have the same third value among one another, the first value, the second value and the third value each being different from one another. Procedure according to one of Claims 1 until 3 , where K > 3 holds. Method according to one of the preceding claims, in which the memory cell values determined from the memory cells are determined by a uniquely reversible transformation. Method according to one of the preceding claims, in which a point in time is determined in each case by means of a time integration of the physical value of the memory cell. Method according to one of the preceding claims, in which the physical value is a read current of a memory cell. Method according to one of the preceding claims, in which, if the digital memory cell values obtained represent a code word of an n ₁ -, ..., n _K out of n code, a number of m bits are determined from the code word by means of an inverse transformation. procedure after claim 10 , in which error detection and/or error correction of the m bits is carried out using an error code. procedure after claim 10 , in which the error detection and/or error correction is carried out based on check bits, the check bits being determined from the data bits according to the error code. procedure after claim 10 , in which the error detection and/or error correction is performed based on check bits, the check bits being determined from the memory cell values in accordance with the error code. Procedure according to one of Claims 11 until 13 , in which the error code is a byte error-correcting and/or a byte error-detecting code. procedure after Claim 14 in which a byte comprises m bits when error correction of data bits is performed and in which a byte comprises n bits when error correction of memory cells is performed. Procedure according to one of Claims 11 until 15 , in which the error code is a bit error-correcting and/or a bit error-detecting code. Method according to one of the preceding claims, in which at least one reference value is used to determine the digital memory cell values. Method according to one of the preceding claims, in which the memory comprises at least one of the following memory types: - a cache memory, - a register or a register array, - a flash memory, - an MRAM, - a SRAM, - a RE RAM, - a PC RAM, - a FE RAM, - a CB RAM, - a multibit memory, - a multilevel memory. Device for processing memory cells from a memory, in which the device has a processing unit that is set up - to determine physical values from a number of n memory cells, where n is at least three, with the physical values being points in time, - to compare the physical values at least partially with one another, - to assign K different digital memory cell values to the n memory cells on the basis of the compared physical values, - to assign a code word of an n ₁ -, ..., n _K -out of n code to the digital memory cell values obtained in this way. - compare the physical values at least partially with one another and thus determine a sequence of the physical values, - assign the K different digital memory cell values to the n memory cells on the basis of the sequence of the physical values. Computer program product that can be loaded directly into a memory of a digital computer, comprising program code parts that are suitable for carrying out the steps of the method according to one of Claims 1 until 18 to perform. Computer-readable storage medium comprising computer-executable instructions suitable for the computer to carry out the steps of the method according to any one of Claims 1 until 18 performs.

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