DE102016118063B4 - PROCEDURE FOR ELECTROMIGRATION ACCEPTANCE - Google Patents

Abstract

A method (500) for electromigration abatement, comprising the steps of:determining a plurality of actual temperatures (TACT_1, TACT_2, TACT_3) each of which corresponds to one or more components (218a, 218b, 218c) in an electrical circuit (201a, 201b , 201c) of a plurality of electrical circuits (201a, 201b, 201c) in an integrated chip design (226);determining an electromigration limit for a component (218a) in a selected electrical circuit (201a) of the plurality of electrical circuits (201a, 201b , 201c), wherein the electromigration limit is determined at one (TACT_1) of the plurality of actual temperatures (TACT_1, TACT_2, TACT_3) corresponding to the component (218a) in the selected electrical circuit (201a); and comparing the electromigration limit to an electromigration metric to determine whether there is electromigration damage to the component (218a) in the selected electrical circuit (201a),wherein determining the plurality of actual temperatures (TACT_1, TACT_2, TACT_3) comprises:determining a Plurality of real temperature changes (ΔTreal_1, ΔTreal_2, ΔTreal_3) each of the one or more components (218a, 218b, 218c) in the one (201a, 201b, 201c) of the plurality of electrical circuits (201a, 201b, 201c ) correspond to; andadding one (ΔTreal_1) of the plurality of real temperature changes (ΔTreal_1, ΔTreal_2, ΔTreal_3) to an ambient temperature (TE) that is the same for the plurality of electrical circuits (201a, 201b, 201c) by one (TACT_1) of the plurality of actual temperatures (TACT_1, TACT_2, TACT_3),wherein determining the plurality of real temperature changes (ΔTreal_1, ΔTreal 2, ΔTreal_3) comprises:determining a temperature change by Joule heat evolution (ΔTjoule) using an effective current (IRMS ) in the component (218a) in the selected electrical circuit (201a); andadding the temperature change due to Joule heating (ΔTjoule) to a temperature change due to device self-heating (ΔTchannel) to determine one (ΔTreal_1) of the plurality of real temperature changes (ΔTreal_1, ΔTreal_2, ΔTreal_3), the temperature change due to device self-heating ( ΔTchannel) is caused by charge carriers in a channel region (206) of a transistor device (204) in the selected electrical circuit (201a).

Description

Background of the Invention

Electromigration is the transport of atoms in a conductive material caused by collisions that transfer momentum between conductive electrons and the atoms of the conductive material. Electromigration in metal interconnect layers often occurs in modern integrated chips. For example, when electrons conduct a current to a semiconductor device, the electrons collide with metal atoms in the metal compound layers. The collisions cause metal atoms in the metal interconnect layers to move (i.e., undergo electromigration), resulting in voids in the metal interconnect layers that can result in integrated chip failure.

the U.S. 2013/0 298 101 A1 describes a simulation method for calculating a temperature distribution in connecting wires of a semiconductor chip package, in which areas are determined in which connecting wires are particularly thermally coupled. From the U.S. 2013/0 212 544 A1 a method for avoiding electromigration damage in packages made of stacked integrated circuits is known. A limit value for a current at different points in the package is scaled with a previously determined temperature and then compared with a current at the respective point in order to identify possible electromigration damage.
the U.S. 2006/0 066 337 A1 discloses a test device for measuring temperatures in semiconductor structures based on the temperature-dependent resistance of conductive elements.
From the WO 2007/070 879 A1 a method for the computer-aided design of integrated circuits is known in which a temperature distribution in the integrated circuit is simulated and based on the simulated temperature distribution aspects of the design are modified depending on one or more predetermined criteria, the method using an electromigration analysis may include.

character list

• 1 zeigt ein Ablaufdiagramm einiger Ausführungsformen eines Verfahrens zur Durchführung einer Elektromigrations-Abnahme (EM-Abnahme), bei dem verschiedene Temperaturen zum Ermitteln von EM-Schäden an Komponenten in verschiedenen elektrischen Schaltungen verwendet werden.
• Die 2A und 2B zeigen einige Ausführungsformen eines integrierten Chips, der eine Vielzahl von verschiedenen elektrischen Schaltungen aufweist.
• Die 3A bis 3C zeigen einige Ausführungsformen von Diagrammen, die Beispiele zum Ermitteln von EM-Schäden über einen mittleren EM-Strom unter Verwendung verschiedener Ist-Temperaturen für Komponenten in den verschiedenen elektrischen Schaltungen der 2A und 2B zeigen.
• 4 zeigt eine Draufsicht einiger Ausführungsformen, die Anpassungen einer Designschicht für elektrischen Schaltungen auf Grund der EM-Schäden zeigt, die in den 3A bis 3C identifiziert worden sind.
• 5 zeigt ein Ablaufdiagramm einiger weiterer Ausführungsformen eines Verfahrens zur Durchführung der EM-Abnahme, das der Bauelement-Eigenerwärmung und der resistiven Erwärmung Rechnung trägt.
• Die 6A zeigt eine Schnittansicht einiger Ausführungsformen eines integrierten Chips, bei dem eine Bauelement-Eigenerwärmung und eine resistive Erwärmung auftreten. Die 6B zeigt beispielhafte grafische Darstellungen, die den Strom als Funktion der Zeit für zwei elektrische Schaltungen des integrierten Chips aus 6A zeigen.
• 7 zeigt ein Blockdiagramm einiger Ausführungsformen eines Systems zur Durchführung der EM-Abnahme.

Aspects of the present invention are best understood by considering the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

• 1 FIG. 12 shows a flowchart of some embodiments of a method for performing electromigration (EM) degradation using different temperatures to determine EM damage to components in different electrical circuits.
• the 2A and 2 B show some embodiments of an integrated chip having a variety of different electrical circuits.
• the 3A until 3C FIG. 12 shows some embodiments of graphs that provide examples for determining EM damage versus mean EM current using different actual temperatures for components in the different electrical circuits of FIG 2A and 2 B demonstrate.
• 4 12 shows a top view of some embodiments showing adjustments of a design layer for electrical circuits due to the EM damage shown in FIGS 3A until 3C have been identified.
• 5 FIG. 12 shows a flowchart of some other embodiments of a method for performing EM decay that accounts for device self-heating and resistive heating.
• the 6A Figure 12 shows a cross-sectional view of some embodiments of an integrated chip where device self-heating and resistive heating occur. the 6B FIG. 12 shows exemplary plots showing current versus time for two electrical circuits of the integrated chip 6A demonstrate.
• 7 Figure 12 shows a block diagram of some embodiments of a system for performing EM collection.

Detailed description

The invention relates to a method for electromigration removal with the features of claim 1, a method for electromigration removal with the features of claim 11 and a system for electromigration removal with the features of claim 16. Preferred embodiments are given in the dependent claims . The description below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first member over or on a second member in the description below may include embodiments where the first and second members are formed in direct contact, and may also include embodiments where additional members are formed between the first and the second element can be formed such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numbers and/or letters may be repeated in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like may be used herein for ease of reference describing the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation) and the spatially relative descriptors used herein interpreted accordingly as well.

As metal interconnect layers have decreased in size through miniaturization, electromigration has become a growing reliability issue for integrated chips. This is because the smaller size of the metal interconnect layers increases the current density of signals carried by the metal interconnect layers. Since the electromigration is proportional to the current density, the higher current density also increases the electromigration.

To ensure that integrated chips meet a minimum reliability standard, they undergo an EM acceptance process. Normally an EM acceptance is carried out in two phases. In the first phase of EM mitigation, a global effective temperature change (determined from the RMS current value of multiple electrical circuits on an integrated chip) is compared to a specified temperature limit to identify EM damage (to ensure that the temperature generated generated by the effective current is below a selected level). Violations of the specified temperature limit indicate that EM damage is present because higher temperatures lead to greater electromigration by providing thermal energy that increases the frequency of collisions between electrons and metal atoms in metal compound layers. In the second phase of EM removal, an average current is compared to a specified average current limit to identify EM damage based on current density (since EM is proportional to current density).

Both phases of EM decay are performed on a variety of electrical circuits of an integrated chip and depend on the global effective temperature change. For example, if an ambient temperature is 110°C and a global effective temperature change is 10°C, average current limits can be calculated for the plurality of electrical circuits at an elevated temperature of 120°C. However, it has been recognized that using one and the same elevated temperature for the plurality of electrical circuits may be too pessimistic for certain electrical circuits and therefore may incur additional design costs in identifying spurious EM damage. In addition, the individual phases of EM acceptance make area optimization difficult, as the individual phases can produce different results, which lead to further costs. In addition, both phases do not take into account the self-heating of the transistor components.

The present invention relates to an electromigration (EM) acceptance method for determining EM damage to components (e.g., metal bond wires) in various electrical circuits of an integrated chip design by performing a single EM test on various components is performed using different temperatures. In some embodiments, the method determines a plurality of actual temperatures, each corresponding to one or more components in an electrical circuit of a plurality of electrical circuits in an integrated chip design. An electromigration boundary is determined for a component in a selected electrical circuit of the plurality of electrical circuits. The electromigration limit is determined at one of the plurality of actual temperatures corresponding to the component in the selected electrical circuit. The electromigration limit is compared to an electromigration metric to determine if there is EM damage to the component in the selected electrical circuit. By using different Lower actual temperatures for components in various electrical circuits mitigate spurious EM damage, reducing design cost loss. In addition, using only one EM test on a component eliminates variability between different EM acceptance procedures.

1 10 shows a flowchart of some embodiments of a method 100 for performing electromigration (EM) degradation in which EM damage is determined in different electrical circuits using different temperatures.

In step 102, an integrated chip design (ie, layout) is obtained having a plurality of electrical circuits. The plurality of electrical circuits each have one or more components in the integrated chip design that are electrically connected to one another. For example, the plurality of electrical circuits may each include individual sets of metal interconnect layers (e.g., metal bond wires and metal vias) electrically connected to different power bus lines (e.g., a wire held at Vss or V _DD ) that configured to power circuit elements. In some embodiments, components in different electrical circuits may be electrically isolated from one another.

At step 104, a change in real temperature (ΔT _real ) for one or more components (e.g., metal bond wires) in a selected one of the plurality of electrical circuits is determined. The change in real temperature (ΔT _real ) includes a change in temperature of the one or more components in the selected electrical circuit due to heat generated in the selected electrical circuit. For example, in various embodiments, the change in real temperature (ΔT _real ) may arise from Joule heating in a metal bond wire in the selected electrical circuit and/or from heat generated by one or more transistor devices (ie, self-heating) in the selected electrical circuit is generated (ie, heat generated by the collision of charge carriers with semiconductor molecules in a channel region of a transistor device). In some embodiments, the change in real temperature (ΔT _real ) may be different for different ones of the plurality of electrical circuits and/or for different components in the same electrical circuit.

At step 106, the change in real temperature (ΔT _real ) is added to an ambient temperature (T _E ) to obtain an actual temperature (T _ACT ) for the one or more components in the selected electrical circuit. The ambient temperature (T _E ) can be adjusted to have the same value for different electrical circuits of the integrated chip design. In some embodiments, the ambient temperature (T _E ) may have a value chosen to be greater than that of a substrate or metal bond wire to speed up EM testing and generate EM failures in each short period of time ( since the real lifetime of an integrated chip is in practice longer than the time allotted for EM decay). For example, the ambient temperature may have a value chosen such that the integrated chip will fail within a specified period of time. In some embodiments, the ambient temperature (T _E ) may be a variable determined by a process engineer (e.g., based on on-chip data).

At step 108, an electromigration limit is established for the one or more components in a selected electrical circuit at the actual temperature (T _ACT ). The electromigration limit is an acceptable upper limit of a value of an electromigration metric for the one or more components in an electrical circuit. If the value of the electromigration metric exceeds the electromigration limit, the one or more components in the selected electrical circuit are at risk of electromigration and EM damage is identified. In some embodiments, the EM limit may be an average current limit set at the actual temperature. In other embodiments, the EM metric/boundary may be an average lifetime boundary set at the actual temperature.

At step 110, an electromigration metric is determined for the one or more components in the selected electrical circuit. In some embodiments, the electromigration metric may be an average current in the one or more components in the selected electrical circuit. In other embodiments, the electromigration metric may be an average lifetime. The electromigration metric can be determined from a simulation of the integrated chip design.

At step 112, the electromigration metric is compared to the electromigration limit to determine if there is EM damage in the one or more components.

At step 114, one or more design layers corresponding to the one or more components in the selected electrical circuit are adjusted if EM damage has been identified. For example, if an average electromigration current violates a current limit, one or more design layers corresponding to the one or more components in the chosen electrical circuit of the integrated chip design are adjusted to mitigate EM damage in the chosen electrical circuit .

It should be appreciated that steps 102-114 may be iteratively repeated to determine and eliminate EM damage to various components in an electrical circuit and/or to components in various circuits of the plurality of electrical circuits. For example, steps 102-114 may be performed a first time to determine EM damage to one or more components in a first electrical circuit, a second time to determine EM damage to one or more components in a second electrical circuit determine, etc. Since the components in each electrical circuit can have different temperatures, the EM limit of the components in each electrical circuit can be different. Therefore, EM damage can be determined on a circuit-by-circuit basis, which can reduce unnecessary redesign of electrical circuits that do not have EM damage.

After the EM damage has been determined in a variety of electrical circuits and the EM acceptance is complete, in step 116 an integrated chip design can be manufactured on a semiconductor substrate based on the adapted integrated chip design.

the 2A and 2 B show some embodiments of an integrated circuit having a plurality of electrical circuits.

2A 1 shows a sectional view of some embodiments of an integrated chip 200 having a plurality of electrical circuits 201a-201c. The integrated chip 200 has a plurality of transistor devices 204 arranged in a substrate 202 . In various embodiments, the substrate 202 may include some type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer.

The individual transistor components 204 each have a source area 203a and a drain area 203b which are separated by a channel area 206 . The source region 203a and the drain region 203b comprise heavily doped regions (e.g. having a doping concentration higher than that of the surrounding substrate 202). In some embodiments, the source region 203a and the drain region 203b may be arranged in a well region 208 that has a different doping type than the substrate 202 (e.g., an n-type well region may be in a p-type conductive substrate be arranged). A gate structure is arranged over the channel region 206 . The gate structure is configured to control the flow of charge carriers (e.g., holes or electrons) in the channel region 206 during operation of a transistor device 204 . The gate structure has a gate electrode 207 which is separated from the channel region 206 by a gate dielectric 205 . In some embodiments, the gate structure is surrounded by a dielectric layer 210 (e.g., phosphosilicate glass).

A back-end-of-line (BEOL) metallization stack 212 is disposed over the substrate 202 . The BEOL metallization stack 212 includes a plurality of metal interconnect layers arranged in a dielectric structure having one or more dielectric layers 214a-214e. In various embodiments, the one or more dielectric layers 214a-214e may comprise an oxide, an ultra-low-k dielectric material, and/or a low-k dielectric material (e.g., SiCO). In some embodiments, the plurality of metal interconnect layers may include conductive contacts 216, metal interconnect wires 218a-218c, and/or metal vias 220. FIG. Conductive contacts 216 electrically connect transistor devices 204 to metal bond wires 218a - 218c separated by metal vias 220 .

The individual electrical circuits 201a to 201c each have a plurality of metal interconnection layers which are electrically connected to one another. For example, in some embodiments, a first electrical circuit 201a may include a plurality of metal interconnect layers connected to a first power bus line 222a configured to carry current (e.g., maintained at Vss) for transistor devices in of the first electrical circuit 201a, while a second electrical circuit 201b may include a plurality of metal interconnection layers connected to a second power bus line 222b configured to carry current (e.g., maintained at Vss) for transistor -Components in the second electrical circuit 201b provides. In some embodiments, the metal ver Bonding layers in various electrical circuits are electrically isolated from each other.

The metal bond wires in the various electrical circuits 201a-201c have different actual temperatures due to different changes in real temperature (ΔT _real ) due to resistive heating and/or self-heating of the components. For example, in some embodiments, the changes in real temperature (ΔT _real ) in metal bonding wires in a desired electrical circuit may depend on an rms current in the metal bonding wires in the selected electrical circuit. Since the metal bonding wires in different electric circuits 201a to 201c have different effective currents, the metal bonding wires in different electric circuits 201a to 201c have different real temperature changes. In some embodiments, one and the same electrical circuit 201a-201c may have different real temperature changes (ΔT _real ) in different segments of the electrical circuit, since the electrical circuit may have different branches of metal bonding wires carrying different effective currents.

In some embodiments, the first electrical circuit 201a may have a first metal bond wire carrying a first effective current corresponding to a first real temperature change (ΔT _{real_1} ), the second electrical circuit 201b may have a second metal bond wire carrying a second effective current carries that corresponds to a second real temperature change (ΔT _{real_2} ), and the third electric circuit 201c may have a third metal bonding wire that carries a third effective current that corresponds to a third real temperature change (ΔT _{real_3} ). In various embodiments, two or more of the first real temperature change (ΔT _{real_1} ), the second real temperature change (ΔT _{real_2} ), and the third real temperature change (ΔT _{real_3} ) may be different.

2 B FIG. 22 shows a top view 224 of an integrated chip design 226 associated with integrated chip 200. FIG. As shown in plan view 224, first electrical circuit 201a includes a first metal wire 218a having a first width w ₁ , second electrical circuit 201b includes a second metal wire 218b having a second width w ₂ , and third electrical circuit 201c has a third metal wire 218c with a third width w ₃ . In some embodiments, the first width w ₁ may be equal to the second width w ₂ and the third width w ₃ . In other embodiments, the first width w ₁ , the second width w ₂ and/or the third width w ₃ can be different.

the 3A until 3C 12 show some embodiments of diagrams 300 through 304 showing examples of a disclosed EM mitigation process in which EM damage is detected using individual real temperature changes (ΔT _{real_x} ) for the metal bond wires in the various electrical circuits (e.g., 201a through 201c) the 2A and 2 B be determined. The EM pickup process is configured to determine an average EM current (I _{AVG_x} ) of the metal bond wires in each electrical circuit at different actual temperatures (ΔT _{ACT_x} ). As the actual temperature (ΔT _{ACT_x} ) increases, a corresponding EM current limit (I _{EM_LIMx} ) decreases since higher temperatures increase electromigration. Therefore, using different actual temperatures for the metal bonding wires in different electrical circuits allows treating the metal bonding wires differently in the different electrical circuits, thereby avoiding the need to match the metal bonding wires in electrical circuits of an integrated chip design that are not likely to cause EM problems.

As in the diagram 300 of 3A shown, a first metal bonding wire in a first electrical circuit (e.g., 201a of 2A ) a first actual temperature (T _{ACT_1} ) equal to a sum of an ambient temperature (T _E ) and a change in real temperature of the first metal bonding wire in the first electrical circuit (ΔT _{real_1} ) (ie T _{ACT_1} = T _E + ΔT _{real_1} ) is. For example, if the ambient temperature (T _E ) is 110°C and the change in real temperature of the first circuit (ΔT _real1 ) is 10°C, the first actual temperature (T _{ACT_1} ) is 120°C. An average EM current limit of the first metal bond wire in the first electrical circuit (I _{EM_LIM1} ) is calculated at the first actual temperature (T _{ACT_} i ) and is compared to an average current of the first metal bond wire in the first electrical circuit (I _{AVG_1} ). Because the average current of the first metal bonding wire in the first electrical circuit (I _{AVG_1} ) is greater than the average EM current limit of the first metal bonding wire in the first electrical circuit (I _{BM_LIM1} ), the first metal bonding wire in the first electrical circuit is reconfigured to reduce electromigration (e.g., increase the width of the first metal bonding wire in the first electrical circuit to reduce current density).

As in diagram 302 of 3B shown, a second metal bonding wire in a second electrical circuit (e.g., 201b of 2A ) a second actual temperature (T _{ACT_2} ) equal to a sum of the ambient temperature (T _E ) and a change in the real temperature of the second metal bonding wire in the second electrical circuit (ΔT _{real_2} ) (ie T _{ACT_2} = T _E + ΔT _{real_2} ) is. For example, when the ambient temperature (T _E ) is 110°C and the change in real temperature of the second metal bonding wire in the second circuit (ΔT _{real_2} ) is 3°C, the second actual temperature (T _{ACT_2} ) is 113° C An average EM current limit of the second metal bond wire in the second electrical circuit (I _{EM LIM2} ) is calculated at the second actual temperature (T _{ACT_2} ) and is compared to an average current of the second metal bond wire in the second electrical circuit (I _{AVG 2} ). . Because the average current of the second metal bonding wire in the second electrical circuit (I _AVG2 ) is less than the average EM current limit of the second metal bonding wire in the second electrical circuit (I _{EM LIM2} ), the second metal bonding wire in the second electrical circuit is not reconfigured to reduce electromigration (e.g., the width of the second metal bonding wire is not increased in the second electrical circuit). Rather, the second metal bonding wire in the second electrical circuit can remain unchanged or can be reconfigured to make the integrated circuit design more compact.

As in diagram 304 of 3C shown, a third metal bonding wire in a third electrical circuit (e.g., 201c of 2A ) a third actual temperature (T _{ACT__3} ) equal to a sum of the ambient temperature (T _E ) and a change in the real temperature of the third metal bonding wire in the third electrical circuit (ΔT _{real_3} ) (ie T _{ACT_3} = T _E + ΔT _{real_3} ) is. For example, when the ambient temperature (T _E ) is 110°C and the change in real temperature of the third metal bonding wire in the third circuit (ΔT _{real_3} ) is 5°C, the third actual temperature (T _{ACT_3} ) is 115° C An average EM current limit of the third metal bonding wire in the third electrical circuit (I _{EM LIM3} ) is calculated at the third actual temperature (T _{ACT_3} ) and is compared to an average current of the third metal bonding wire in the third electrical circuit (I _AVG _ ₃ ) compared. Because the mean current of the third metal bonding wire in the third electrical circuit (I _{AVG_3} ) is less than the mean EM current limit of the third metal bonding wire in the third electrical circuit (I _{EM LIM3} ), the third metal bonding wire in the third electrical circuit is not reconfigured to reduce electromigration. Rather, the third metal bonding wire in the third electrical circuit may remain unchanged or the width may be reconfigured to make the integrated circuit design more compact.

4 FIG. 400 shows a top view 400 of some embodiments showing adjustments of an integrated chip design on a circuit-by-circuit basis to avoid violations of EM limits in the 3A until 3C to take into account. Since the integrated chip design is adjusted on a circuit-by-circuit basis, an unnecessary increase in design cost can be mitigated.

The top view 400 shows an adapted integrated chip design 226'. In the customized integrated chip design 226', a first metal bond wire 218a' associated with the first electrical circuit 201a has been customized to account for EM damage by reducing the width of the first metal bond wire 218a' from a first width w ₁ has been enlarged to an adjusted first width w ₁ ' that is greater than the first width w ₁ . The width of the first metal bond wire 218a' associated with the first electrical circuit 201a is increased because the average current of the first metal bond wire in the first electrical circuit (I _{AVG_1} ) is greater than the average EM current limit of the first metal bond wire in the first electrical circuit (I _{EM _LiM1} ). Increasing the width of the first metal bonding wire 218a' reduces EM damage in the first electrical circuit 201a since the average EM current limit of the first metal bonding wire in the first electrical circuit 201a is thus increased.

In the adjusted integrated chip design 226', a second metal bond wire 218b' associated with the second electrical circuit 201b has been adjusted by reducing the width of the second metal bond wire 218b' from a second width w ₂ to an adjusted second width w ₂ ' has been reduced, which is smaller than the second width w ₂ . Since the average current in the second metal bonding wire in the second electrical circuit (I _{AVG_2} ) is less than the average EM current limit of the second metal bonding wire in the second electrical circuit (I _{EM LIM2} ), the width of the second metal bonding wire 218b', which is associated with the second electrical circuit 201b can be reduced to the adjusted second width w ₂ ' without causing EM damage. In some alternative embodiments, the second width w ₂ of the second metal bonding wire 218b' is not adjusted.

In the custom integrated chip design 226' is a third metal bond wire 218c' associated with the third electrical circuit 201c has been adjusted by reducing the width of the third metal bonding wire 218c' from a third width w ₃ to an adjusted third width w ₃ ' that is less than the third width w ₃ is. Because the mean current in the third metal bond wire in the third electrical circuit (I _{AVG_3} ) is less than the mean EM current limit of the third metal bond wire in the third electrical circuit (I _{EM LIM3} ), the width of the third metal bond wire 218c', which is associated with the third electrical circuit 201c can be reduced to the adjusted third width w ₃ ' without causing EM damage. In some alternative embodiments, the third width w ₃ of the third metal bonding wire 218c' is not adjusted.

5 FIG. 5 shows a flowchart of a more detailed embodiment of a method 500 for performing EM decay that accounts for self-heating and resistive heating of devices.

While the foregoing methods (e.g., methods 100 and 500) have been illustrated and described herein as a series of operations or events, it should be understood that the presented order of these operations or events is not intended to be construed in a limiting sense . For example, some operations may be performed in different orders and/or concurrently with operations or events other than those illustrated and/or described herein. In addition, not all operations presented may be required to implement one or more aspects or embodiments of the present description. Additionally, one or more of the operations described herein may be performed in a single operation or in multiple separate operations and/or phases.

In step 502, an integrated chip design (i.e., layout) is obtained having a plurality of electrical circuits.

In step 504, a change in real temperature (ΔT _real ) for a metal bond wire in a selected circuit is determined. In some embodiments, the real temperature change may include a real temperature change due to device self-heating and Joule heating, which is determined in steps 506-510.

At step 506, the change in Joule temperature (ΔT _joule ) for a metal bond wire in a selected electrical circuit is determined. The change in temperature due to Joule heating (ΔT _joule ) (ie resistive heating) is proportional to the effective current ( _IRMS ) of the metal bonding wire in the chosen electrical circuit. For example, an RMS current of 5 mA can result in a 5 °C change in Joule temperature. In some embodiments, the change in Joule temperature (ΔT _joule ) may depend on the process and/or the size of features in a technology node. In these embodiments, the change in temperature by Joule heat evolution (ΔT _joule ) can be found using a formula given in a design rule book. In other embodiments, the change in temperature may be determined by Joule heat evolution (ΔT _joule ) based on a simulation run with the integrated chip design.

At step 508, a change in device self-heating temperature (ΔT _channel ) for the metal bond wire in a selected electrical circuit is determined. In some embodiments, the change in temperature due to device self-heating (ΔT _channel ) can be calculated by measuring the self-heating temperature of a device using a separate simulation (e.g., a SPICE simulation) (SPICE: simulation program with integrated circuit emphasis; simulation program with a focus on integrated circuits) is determined and then the influence of the component self-heating on the metal connecting wire is determined.

At step 510, a change in real temperature (ΔT _real ) for the metal bond wire due to the change in temperature due to Joule heating (ΔT _joule ) and the change in temperature due to device self heating (ΔT _channel ) is determined. In some embodiments, the change in real temperature (ΔT _real ) may be determined by adding the change in temperature due to Joule heating (ΔT _joule ) to the change in temperature due to device self-heating (ΔT _channel ) (ie, ΔT _real = ΔT _joule + coefficient ΔT _channel ). In some embodiments, device self-heating (ΔT _channel ) of a first electrical circuit may affect the actual temperature of one or more metal bonding wires in an adjacent electrical circuit, such that the change in real temperature (ΔT _real ) may be determined by measuring the change in Temperature due to joule heating (ΔT _joule ) is added to the change in temperature due to device self-heating in multiple channels (ie, ΔT _real = ΔT _joule + coefficient 1 * ΔT _{channel_1} + coefficient_2 * ΔT _{channel_2} ).

In step 512, an average current limit (I _AVGLIM ) for the metal bond wire in the selected electrical circuit is calculated at an actual temperature (T _ACT ) equal to a sum of the ambient temperature (T _E ) and the change in real temperature (ΔT _real ) is. In some embodiments, the average current limit (I _{AVG_LIM} ) for a metal bond wire may be a function of the actual temperature (T _ACT ) of the electrical circuit and the width of the metal bond wire [ie, I _{AVG_LIM} = f(T _ACT , width)].

In step 514, an average current (I _AVG ) in a metal bond wire is compared to the average current limit (I _AVGLIM ) for the metal bond wire. If the average current (I _AVG ) is greater than the average current limit (I _{AVG_LIM} ), then there is EM damage in the metal bond wire (at 516) and the process proceeds to modifying the integrated chip design (e.g. width of the metal bonding wire) to reduce the average current in the selected electrical circuit (step 518).

Steps 512 through 518 of method 500 may be iteratively performed for a plurality of metal bond wires in an electrical circuit. For example, steps 512-518 may be performed a first time for a first metal bond wire in a first electrical circuit, performed a second time for a second metal bond wire in the first electrical circuit, and so on a variety of electrical circuits can be executed in the integrated chip design in order to determine EM damage in the individual electrical circuits separately.

the 6A and 6B show some embodiments for determining a change in real temperature (ΔT _real ) through device self-heating and through resistive heating in a variety of electrical circuits.

6A FIG. 6 shows a sectional view 600 of an integrated chip having a first electrical circuit 602a and a second electrical circuit 602b. The first electrical circuit 602a includes a first plurality of metal bonding wires 604a and 606a disposed over a first transistor device 204a. A first current I _net1 is provided across the first plurality of metal bonding wires 604a and 606a in the first electrical circuit 602a. The second electrical circuit 602b includes a second plurality of metal bonding wires 604b and 606b disposed over a second transistor device 204b. A second current I _net2 is provided across the second plurality of metal bonding wires 604b and 606b in the second electrical circuit 602b.

6B 12 shows some example embodiments of a first plot 608 showing current (x-axis) as a function of time (y-axis) for first electrical circuit 602a, and a second plot 614 showing current (x-axis ) as a function of time (y-axis) for the second electrical circuit 602b.

In the first electrical circuit 602a, the change in real temperature of a metal bond wire 604a or 606a through self-heating depends on a first change in Joule temperature (ΔT _joule1 ) of the metal bond wire and/or on a first change in temperature through device self-heating (ΔT _channel1 ) caused in the metal bonding wire by the underlying first transistor device 204a (e.g., by the collision of charge carriers in semiconductor molecules in a channel of the first transistor device 204a). In some embodiments, the first joule temperature change (ΔT _joule1 ) can be calculated from the effective current of the first electrical circuit 602a since the first joule temperature change (ΔT _joule1 ) is a process in which the flow of a electric current through a conductor releases heat. As shown in the first plot 608, a current 610 in the first electrical circuit 602a is an alternating current that varies between a peak value I _p and a minimum value I _m , resulting in an effective current 612 that has a first value (the e.g., about equal to I _p /√2).

A first average EM current limit (I _{AVG_LIM1} ) may be determined for metal interconnect 604a based on a first real temperature change (ΔT _{real_1} ) due to self-heating and a first width w ₁ of metal interconnect 604a [ie, I _{AVG_LIM1} = f(T _E + ΔT _{real_1} , _w1 )]. An average current in the metal bond wire 604a is then determined and compared to the first average EM current limit (I _{AVG_LIM1} ) to determine EM damage to the metal bond wire 604a. When there is EM damage, the width of metal bonding wire 604a is increased from w ₁ to a larger width. By increasing the width of the metal bond wire 604a, the first average EM current limit (I _{AVG_LIM1} ), which is a function of the width, can be increased and thereby eliminating the EM damage. A second average EM current limit (I _{AVG_LIM2} ) may occur for metal bond wire 606a due to the first real temperature change (ΔT _real1 ). self-heating and a second width w ₂ of the metal bond wire 606a [ie, I _{AVG_LIM2} = f( _{TE + ΔT real_1 ,} w ₂ )]. An average current in the metal bond wire 606a is then determined and compared to the second average EM current limit (I _AVGLIM2 ) to determine EM damage to the metal bond wire 606a. When there is EM damage, the width of the metal bonding wire 606a is increased from w ₂ to a larger width.

In some embodiments, the self-heating (ΔT _channel ) of a second electrical circuit (e.g., 602b) may affect the actual temperature of one or more metal bonding wires in a first electrical circuit (e.g., 602a). if in 6A For example, if metal bond wire 604a is intended to pass over second transistor device 204b (but not be connected to second electrical circuit 602b), metal bond wire 604a is protected from self-heating of first transistor device 204a as well as from self-heating of second transistor device 204b affected.

After the EM tests have been completed on the metal bond wires 604a and 606a in the first electrical circuit 602a, EM tests can be performed on the metal bond wires 604b and 606b in the second electrical circuit 602b. In the second electrical circuit 602b, a second real temperature change (ΔT _{real_2} ) of a metal bond wire 604b or 606b by self-heating is compensated by a second Joule temperature change (ΔT _joule2 ) of the metal bond wire and/or a temperature change by device self-heating (ΔT _channel2 ) caused in the metal bonding wire by the underlying second transistor device 204b. In some embodiments, the second temperature change may be calculated by Joule heat evolution (ΔT _joule2 ) from the rms current of the second electrical circuit 602b. As shown in the second plot 614, a current 616 in the second electrical circuit 602b is a direct current, resulting in an rms current having a second value equal to the dc value and less than the first rms current value 612 is. The second value causes the self-heating of the metal bonding wires 604b and 606b in the second electrical circuit 602b to be lower than that of the metal bonding wires 604a and 606a in the first electrical circuit 602a, resulting in higher EM limits.

A third average EM current limit (I _AVGLIM3 ) can be determined for the third metal interconnect wire 604b due to the second real temperature change (ΔT _{real_2} ) through self-heating and a third width w ₃ of the third metal interconnect wire 604b [ie, I _{AVG_LIM3} = f( T _E + ΔT _{real_2} , w ₃ )]. Then, an average current in the third metal bond wire 604b is determined and compared to the third average EM current limit (I _{AVG_LIM3} ) to determine EM damage of the third metal bond wire 604b. When there is EM damage, the width of the third metal bonding wire 604b is increased from w ₃ to a larger width. A fourth average EM current limit (I _{AVG_LIM4} ) may be determined for the fourth metal interconnect wire 606b due to the second real temperature change (ΔT _{real_2} ) through self-heating and a fourth width w ₄ of the fourth metal interconnect wire 606b [ie, I _{AVG_LIM4} = f( T _E + ΔT _{real_2} , w ₄ )]. Then, an average current in the fourth metal bond wire 606b is determined and compared to the fourth average EM current limit (I _AVGLIM4 ) to determine EM damage of the fourth metal bond wire 606b. When there is EM damage, the width of the fourth metal bonding wire 606b is increased from w ₄ to a larger width.

In some embodiments, the self-heating (ΔT _channel ) of a first electrical circuit (e.g., 602a) may affect the actual temperature of one or more metal bonding wires in a second electrical circuit (e.g., 602b). if in 6A For example, if metal bond wire 604b is to pass over first transistor device 204a (but not be connected to first electrical circuit 602a), then metal bond wire 604b will benefit from the self-heating of second transistor device 204b as well as from the self-heating of first transistor device 204a affected.

7 FIG. 7 shows a block diagram of some embodiments of a system 700 for performing EM collection. In some embodiments, one or more components of the system 700 may be part of an electronic design automation (EDA) system.

The system 700 includes a first memory element 702 configured to store an integrated chip design 704 (ie, layout). The first storage element 702 includes electronic memory (e.g., RAM, read-only memory, etc.) configured to store digital data. The integrated chip design 704 includes a variety of different design layers (e.g., metal bond wire layers, metal via layers, etc.) that are arranged in a plurality of electrical circuits 704a to 704n.

An electromigration limit determination element 705 is configured to determine electromigration limits for one or more components in the plurality of electrical circuits 704a-704n. In some embodiments, the electromigration limit determination element 705 includes a current sensing element 706 configured to measure a current (I _n ) in one or more components in each of the plurality of electrical circuits 704a-704n and a plurality of effective Currents (I _{RMS_x} , where x=1 to n) for the one or more components in the plurality of electrical circuits 704a to 704n in the integrated chip design 704 are determined. Each of the plurality of RMS currents ( _{IRMS_x} ) corresponds to one or more components in one of the plurality of electrical circuits 704a-704n in the integrated chip design 704. For example, a first RMS current I _{RMS_1 corresponds} to one or more components in a first electrical circuit 704a , a second effective current I _{RMS_2} corresponds to _one or more components in a second electrical circuit 704b, and so on , which is used to calculate the plurality of effective currents (I _{RMS_x} ). In some embodiments, the first formula (f ₁ ) depends on a technology node and/or a manufacturing process for the integrated chip design 704 .

A change in real temperature calculation element 708 is configured to calculate a change in real temperature (ΔT _{real_x} ) for the one or more components in the plurality of electrical circuits 704a through 704n due to the plurality of effective currents ( I _{RMS_x} ) determined. The change in real temperature (ΔT _{real_x} ) is added to an ambient temperature (T _E ) with a summing element 710 to derive actual temperatures (T _{ACT_x} ) for the one or more components in each of the plurality of electrical circuits 704a-704n determine. In some embodiments, the ambient temperature (T _E ) can be stored in a second storage element 712 . In various embodiments, the second storage element 712 may be the same physical storage as the first storage element 702 , or it may be different physical storage than the first storage element 702 .

The actual temperatures (T _{ACT_x} ) for the one or more components in the plurality of electrical circuits 704a-704n are provided to an average current limit calculation element 714 configured to calculate an average current limit (I _AVGLIMx ) for calculates the one or more components in the plurality of electrical circuits 704a-704n at an actual temperature (T _{ACT_x} ) corresponding to the one or more components of a selected electrical circuit 704a-704n. For example, the average current limit calculation element 714 may calculate a first average current limit (I _AVGLIM1 ) for a first metal bond wire in a first electrical circuit 704a at a first actual temperature (T _{ACT_1} ), a second average current limit (I _{AVG_LIM2} ) for one calculate a second metal bonding wire in a second electrical circuit 704b at a second actual temperature (T _{ACT_2} ), etc. In some embodiments, the average current limit calculation element 714 may be configured to calculate a second formula (f ₂ ) from the design rule Database 716 receives to calculate the average current limit (I _AVGLIMx ). The second formula (f ₂ ) may depend on a technology node and/or a manufacturing process for the integrated chip design 704 .

A simulation tool 718 is configured to determine average currents (I _AVGx ) for the one or more components in the plurality of electrical circuits 704a - 704n based on the integrated chip design 704 . The average currents (I _AVGx ) and the average current limit (I _{AVG_LIMx} ) are provided to a comparator 720 configured to identify EM damage by comparing the average currents (I _AVGx ) to the average current limit (I _{AVG_LIMx} ). . For example, when the average current (I _AVGx ) of a metal bonding wire in an electrical circuit violates the average current limit (I _{AVG_LIMx} ) of that electrical circuit, EM damage is identified. In some embodiments, the simulation tool may include a SPICE simulator (SPICE: Integrated Circuits-focused Simulation Program).

A design layout tool 722 is configured to adjust one or more design layers corresponding to the one or more components in one of the plurality of electrical circuits 704a - 704n based on an output of the comparison element 720 . The one or more design layers may be adjusted to increase the width of a metal bond wire when it is determined that there is EM damage in the electrical circuit. Alternatively, the one or more design layers may be adjusted to reduce the width of a metal bond wire, when the average current is determined to be below the average current limit.

Thus, the present invention relates to an electromigration (EM) degradation method for detecting EM damage in various electrical circuits by performing a single EM test on each circuit. The individual EM tests are performed by comparing an electromigration metric (e.g., an average current) to an EM limit of the various electrical circuits determined using different temperatures.

In some embodiments, the present invention relates to a method for electromigration loss. The method includes determining a plurality of actual temperatures, each corresponding to one or more components in a plurality of electrical circuits in an integrated chip design. The method further comprises determining an electromigration limit for a component in a selected electrical circuit of the plurality of electrical circuits, wherein the EM limit is determined at one of the plurality of actual temperatures corresponding to the component in the selected electrical circuit. The method further includes comparing the electromigration limit to an electromigration metric to determine whether there is electromigration damage to the component in the selected electrical circuit.

In further embodiments, the present invention relates to a method for electromigration loss. The method includes the steps of: determining a first actual temperature corresponding to a first metal bonding wire in a first electrical circuit of an integrated chip design; and determining a second actual temperature corresponding to a second metal bond wire in a second electrical circuit of the integrated chip design. The method further includes the steps of: determining a first average current limit for the first metal bonding wire using the first actual temperature; and determining a second average current limit for the second metal bond wire using the second actual temperature. The method further comprises the steps of: comparing a first average current in the first metal bond wire to the first average current limit to determine electromigration damage in the first metal bond wire; and comparing a second average current in the second metal bond wire to the second average current limit to determine electromigration damage in the second metal bond wire.

In still other embodiments, the present invention relates to a system for electromigration abatement. The system includes a memory element configured to store an integrated chip design that includes a plurality of electrical circuits. The system further includes an electromigration limit determination element configured to determine a plurality of actual temperatures, each corresponding to one or more components in one of the plurality of electrical circuits in the integrated chip design, and to determine an electromigration limit for determining a component in a selected electrical circuit of the plurality of electrical circuits, wherein the electromigration limit is determined at one of the plurality of actual temperatures corresponding to the component in the selected electrical circuit. The system further includes a comparator configured to compare the electromigration limit to an electromigration metric to determine whether there is electromigration damage to the component in the selected electrical circuit.

Claims (17)

Method (500) for electromigration acceptance, with the following steps: determining a plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ) each of which corresponds to one or more components (218a, 218b, 218c) in an electrical circuit ( 201a, 201b, 201c) corresponding to a plurality of electrical circuits (201a, 201b, 201c) in an integrated chip design (226); Determining an electromigration limit for a component (218a) in a selected electrical circuit (201a) of the plurality of electrical circuits (201a, 201b, 201c), the electromigration limit being at one (T _{ACT_1} ) of the plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ) corresponding to the component (218a) in the selected electrical circuit (201a); and comparing the electromigration limit to an electromigration metric to determine if there is electromigration damage to the component (218a) in the selected electrical circuit (201a), wherein determining the plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ) does the following comprises: determining a plurality of real temperature changes (ΔT _{real_1} , ΔT _{real_2} , ΔT _{real_3} ) corresponding to the one or more components (218a, 218b, 218c) in the one (201a, 201b, 201c) of the plurality of electrical correspond to circuits (201a, 201b, 201c); and adding one (ΔT _{real_1} ) of the plurality of real temperature changes (ΔT _{real_1} , ΔT _{real_2} , ΔT _{real_3} ) to an ambient temperature (T _E ) required for the plurality of electrical circuits (201a, 201b, 201c) is the same to determine one (T _{ACT_1} ) of the plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ), wherein determining the plurality of changes in real temperature (ΔT _{real_1} , ΔT _{real 2} , ΔT _{real_3} ) comprises: determining a joule temperature change (ΔT joule ) from an effective current ( _IRMS ) in the component ( _218a ) in the selected electrical circuit (201a); and adding the joule temperature change (ΔT _joule ) to a device self-heating temperature change (ΔT _channel ) to determine one (ΔT _{real_1} ) of the plurality of real temperature changes (ΔT _{real_1} , ΔT _{real_2} , ΔT _{real_3} ), where the temperature change due to device self-heating (ΔT _channel ) is caused by charge carriers in a channel region (206) of a transistor device (204) in the selected electrical circuit (201a). Method (500) according to claim 1 , further comprising: adjusting one or more design layers in the selected electrical circuit (201a) when electromigration damage is determined to be present. Method (500) according to claim 2 wherein the component (218a) comprises a metal bond wire (218a) and the one or more design layers comprise a metal bond wire design layer. Method (500) according to any one of the preceding claims, wherein the electromigration metric is an average current (I _{AVG_1} ) in the component (218a) in the selected electrical circuit (201a) and the electromigration limit is an average current limit (IAVG _LIM1 ) of the component (218a) is. The method (500) of any preceding claim, further comprising: calculating an average current limit (I _{AVG_LIM} ) based on the one (T _{ACT_1} ) of the plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ) and a width (w ₁ ) of component (218a). A method (500) according to any one of the preceding claims, further comprising: Manufacturing an integrated chip (200) in a semiconductor substrate (202) based on the integrated chip design (226') after the electromigration damage has been determined. The method (500) of any preceding claim, further comprising: determining a first electromigration limit for a first metal bond wire (218a) in a first electrical circuit (201a) at a first actual temperature (T _{ACT_1} ); and comparing the first electromigration limit to a first electromigration metric calculated for the first metal bond wire (218a). Method (500) according to claim 7 The further comprising: determining a second electromigration limit for a second metal bond wire in the first electrical circuit (201a) at a second actual temperature; and comparing the second electromigration limit to a second electromigration metric calculated for the second metal bond wire. Method (500) according to claim 8 The further comprising: determining a third electromigration limit for a third metal bond wire (218c) in a second electrical circuit (201c) at a third actual temperature (T _{ACT_3} ); and comparing the third electromigration limit to a third electromigration metric calculated for the third metal bond wire (218c). The method (500) of any preceding claim, further comprising determining the device self-heating temperature change (ΔT _channel ) by: determining a self-heating temperature of the transistor device (204) in the selected electrical circuit (201a); and determining the effect of device self-heating of the transistor device (204) in the selected electrical circuit (201a) on the component (218a) in the selected electrical circuit (201a). A method (500) for electromigration abatement, comprising the steps of: determining a first actual temperature (T _{ACT_1} ) corresponding to a first metal bonding wire (218a) in a first electrical circuit (201a) of an integrated chip design (226); determining a second actual temperature (T _{ACT_2} ) corresponding to a second metal bonding wire (218b) in a second electrical circuit (201b) of the integrated chip design (226); determining a first average current limit (I _{AVG_LIM1} ) for the first metal bond wire (218a) using the first actual temperature (T _{ACT_1} ); determining a second average current limit (I _{AVG_LIM2} ) for the second metal bonding wire (218b) using the second actual temperature (T _{ACT_2} ), comparing a first average current (I _{AVG_1} ) in the first metal interconnect (218a) to the first average current limit (L _{AVG_LIM1} ) to determine electromigration damage in the first metal interconnect (218a); and comparing a second average current (I _{AVG_2} ) in the second metal interconnect (218b) to the second average current limit (I _{AVGL_IM2} ) to determine electromigration damage in the second metal interconnect (218b), wherein determining the first actual temperature (T _{ACT_1} ) comprises: determining a first change in real temperature (ΔT _{real_1} ) corresponding to the first metal bonding wire (218a); and adding the first real temperature change (ΔT _{real_1} ) to an ambient temperature (T _E ) that is the same for the first (201a) and second electrical circuit (201b) to determine the first actual temperature (T _{ACT_1} ). wherein determining the first real temperature change (ΔT _{real_1} ) comprises: determining a Joule heat evolution temperature change (ΔT joule ) from an effective current ( _IRMS ) in the first metal bonding _wire (218a); and adding the joule temperature change (ΔT _joule ) to a device self-heating temperature change (ΔT _channel ) to determine the first real temperature change (ΔT _{real_1} ), the device self-heating temperature change (ΔT _channel ) caused by carriers in a channel region (206) of a transistor device (204) in the first electrical circuit (201a). Method (500) according to claim 11 The further comprising: adjusting one or more design layers in the first electrical circuit (201a) when electromigration damage is determined to be present in the first metal bond wire (218a). Method (500) according to claim 11 or 12 , wherein the temperature change due to component self-heating (ΔT _channel ) is further caused by charge carriers in a channel region (206) of a second transistor component (204) in the second electrical circuit (201b). Method (500) according to any one of Claims 11 until 13 , further comprising: calculating the first average current limit (I _{AVG_LIM1} ) based on the first actual temperature (T _{ACT_1} ) and a width (w ₁ ) of the first metal bond wire (218a). Method (500) according to any one of Claims 11 until 14 The further comprising determining the device self-heating temperature change (ΔT _channel ) by: determining a self-heating temperature of the transistor device (204) in the first electrical circuit (201a); and determining the effect of device self-heating of the transistor device (204) in the first electrical circuit (201a) on the first metal bonding wire (218a). A system (700) for electromigration removal, comprising: a memory element (712) configured to store an integrated chip design (226) comprising a plurality of electrical circuits (201a, 201b, 201c); an electromigration limit determination element (705) configured to: determine a plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ) corresponding to one or more components (218a, 218b, 218c) in a ( 201a, 201b, 201c) of the plurality of electrical circuits (201a, 201b, 201c) in the integrated chip design (226), and an electromigration limit for a component (218a) in a selected electrical circuit (201a) of the plurality of electrical circuits ( 201a, 201b, 201c), the electromigration limit being determined at one (T _{ACT_1} ) of the plurality of actual temperatures (T _{ACT_1} , T _{ACT_2} , T _{ACT_3} ) which the component (218a) in the selected electrical circuit (201a) is equivalent to; a comparison element (720) configured to compare the electromigration limit to an electromigration metric to determine whether there is electromigration damage to the component (218a) in the selected electrical circuit (201a); a current sensing element (706) configured to measure a current of the component (218a) in the selected electrical circuit (201a); a change in real temperature calculation element (708) configured to determine a change in real temperature (ΔT _real1 ) of the component (218a), wherein determining the change in real temperature (ΔT _{real_1} ) of the The component (218a) comprising: determining a joule temperature change (ΔT joule ) from an effective current ( _IRMS ) in the component ( _218a ) in the selected electrical circuit (201a); and adding the Joule temperature change (ΔT _joule ) to a device self-heating temperature change (ΔT _channel ) to determine the real temperature change (ΔT _{real_1} ), where the device self-heating temperature change (ΔT _channel ) due to carriers in a canal area (206) a transistor device (204) in the selected electrical circuit (201a); and a summing element (710) configured to add the change in real temperature (ΔT _real1 ) to an ambient temperature (T _E ) that is the same for the plurality of electrical circuits (201a, 201b, 201c) to determine an actual temperature (T _{ACT_1} ) of the component (218a). system (700) after Claim 16 A design layout tool (722) configured to modify one or more design layers in the selected electrical circuit (201a) when electromigration is determined to be present.

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