DE102016100837B3 - Eindrahtlichtsteuerbus - Google Patents

Abstract

The invention relates to a data bus system having a single-wire data bus (b1, b2, b3) for transmitting data between a bus master (BM) and bus nodes (BS1, BS2, BS3). The bus master (BM) has a master single-wire data bus interface (OWM), which is intended to transmit data over the single-wire data bus (b1, b2, b3) bidirectionally by means of a data bus protocol with more than two physical voltage and / or current levels to receive from this. The considered single-wire data bus section (b1, b2, b3) comprises only a single signal line. To the considered single-wire data bus section (b1, b2, b3) are a single-wire data bus interface (OWS1, OWS2, OWS3) of a bus node (BS1, BS2, BS3) of the bus nodes (BS1, BS2, BS3) and a first transfer gate (TG1) of the considered one Bus node (BS1, BS2, BS3) electrically connected. The single-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration is intended to receive data from the single-wire data bus section under consideration (b1, b2, b3) by means of the data bus protocol. At the same time, the single-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration is intended to send data via the data bus protocol via the single-wire data bus section (b1, b2, b3) under consideration. The transfer gate (TG1, TG2, TG3) of the considered bus node is intended to separate and / or electrically connect the considered single wire data bus section (b1, b2) from an optional subsequent single wire data bus section (b2, b3). The considered bus accounts (BS1, BS2, BS3) has a first transfer gate control register which is designed to control the first transfer gate (TG1). The bus master can use the master single-wire data bus interface (OWM) and the single-wire data bus (b1, b2, b3) or the considered single-wire data bus section (b1, b2, b3) and the single-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration. Describe gate control registers (TGCR) of the considered bus node (BS1, BS2, BS3) and thus control the state of the transfer gate (TG1) of the considered bus node (BS1, BS2, BS3).

Description

introduction

In the automotive industry, light bands of light-emitting diodes (LEDs) with preferably several colors are to be used in the future. These LEDs are intended by means of the known pulse modulation methods such as Pulse Width Modulation (PWM), Pulse Code Modulation (PCM), Pulse Count Modulation (PCM), Phase Offset Modulation (POM), Pulse Width Modulation (POM). Density modulation (PDM), pulse-frequency modulation (PFM), etc. are controlled and energized. The corresponding types of modulation can be found by the person skilled in the relevant literature. In the following, when PWM is mentioned, it is meant within this disclosure all pulse modulation modes that are currently known in the art. Depending on the average voltage or current level, which is applied to the respective LED, the LED can be adjusted in brightness and, to a certain extent, also in the color temperature. Thus, for example, in the case of PWM modulation, duty cycle and level determine brightness appearance and perceived color temperature.

The LEDs of the light strip are usually uniformly distributed over the length of the light strip.

In the prior art, it is customary to use a plurality of integrated circuits, which are more or less equally distributed as bus node on the light strip, for driving the LEDs. Typically, each bus node is assigned a plurality of light sources, preferably LEDs, which are then respectively controlled by a bus node.

This activation takes place for the individual integrated circuit for a single LED or for a plurality of LEDs typically arranged one behind the other on the light strip, that is to say for a light strip section which is assigned to this integrated circuit.

In the prior art, it is now common to provide these integrated circuits each with a shift register with an input and an output. The input of a subsequent shift register of an integrated circuit following on the light strip is connected to the output of the shift register of the integrated circuit preceding on the light strip. The first integrated circuit of the light band is connected to a bus master (BM) instead of a preceding integrated circuit, which generates the data and the shift clock. Typically, it is a microcontroller.

The bus master (BM) supplies via a clock line (TCK) all the shift register segments of all the integrated circuits along such a compound shift register chain with the necessary shift clock and a transfer signal via a test data line (TDI) in the time division multiplex or a test mode signal line (TMS ) in the space division multiplex, with which the current values in the segments of the shift register chain are loaded into shadow registers of the integrated circuits.

In order to transmit the required information, the bus master (BM) thus generates a serial data stream which contains the information about brightness and / or color temperature, pushes these in bit-correct order into the shift register chain and signals the integrated circuits at the correct clock rate the acquisition, whereupon they load their shadow registers accordingly and adjust the PWM modulation of the LED driver in amplitude and duty cycle or fill factor according to the thus loaded brightness and color temperature values.

Here are several problems when used in the automobile, which are to be solved.

First, the prior art approach and arrangement known in the art for controlling such a luminous band requires a supply voltage line, a ground line, a clock line, a signaling line, and a data line, that is, a total of five lines. If necessary, the body of the car can be used as a ground line, if this is not made of non-conductive plastic or another insulator. There still remains the need for four wires. This leads to costs and weight gain.

Secondly, no return channel is provided in order to be able to detect, for example, faults, to be able to measure the temperature at the location of the LED, to carry out a self-test, etc.

So a solution is needed that allows programming and reading of the integrated circuits over a single data line.

The JTAG protocol is known from the prior art. The JTAG protocol has become one of the leading tools in the programming, testing, debugging, and emulation of integrated circuits. In a method called Boundary Scan, a host processor can control the state of an integrated circuit. In particular, the host processor as a bus master via a special interface, the JTAG interface according to IEEE 1149 standard, able to program the integrated circuit suitable as a bus node and, if necessary, to initialize. Furthermore, the host processor as a bus master is able to read the state of the integrated circuit after a predetermined number of system clock periods of the JTAG interface according to IEEE 1149 standard or upon detection of a predetermined event or during operation of the integrated circuit, ie of the bus node to modify. This also includes stopping the integrated circuit or forcibly changing to other states or changing memory contents. However, the JTAG protocol is a point-to-point connection and thus unsuitable for the control of automotive light strips. From the prior art, although a concatenation of JTAG test interfaces with the property right EP 0 503 117 B1 known for a long time. The EP 0 503 117 B1 but reveals the concatenation of 4-wire JTAG interfaces. Thus the technology of the EP 0 503 117 B1 the requirement of a single wire data bus for the control of automotive LED based light bands not.

• 1. mindestens einem seriellen Dateneingang (Testdateneingang) TDI,
• 2. mindestens einem seriellen Datenausgang (Testausgang) TDo,
• 3. mindestens einem Mode-Eingang (Testmode-Eingang) TMS,
• 4. mindestens einem Takteingang (Testtakteingang) TCK,
• 5. einem optionalen Rücksetzeingang (Testrücksetzeingang) TRST.

The invention described below thus relates to a device for concatenated control and / or for programming a plurality of integrated circuits, microsystems including microelectromechanical systems (MEMS) and integrated microelectro-optical systems (MEOS) by means of a single-wire data bus, wherein the controlled integrated circuits, microsystems incl microelectromechanical systems (MEMS) and integrated microelectro-optical systems (MEOS) each play the role of a bus node. With such systems, it is already common today to control them for the production test via a JTAG test bus according to IEEE 1149 standard in pure point-to-point configuration. This standard JTAG interface has a test data port with typically four test ports:

• 1. at least one serial data input (test data input) TDI,
• 2. at least one serial data output (test output) TDo,
• 3. at least one mode input (test mode input) TMS,
• 4. at least one clock input (test clock input) TCK,
• 5. an optional reset input (test reset input) TRST.

Since the method has been known for several decades, reference is made at this point to the corresponding technical literature and to the corresponding patent and disclosure documents (IEEE 1149 standards).

Here is just a brief description: The JTAG protocol according to IEEE 1149 standard comprises in the base standard five signal groups, which between the emulation unit, which contains the host processor and thus acts as a bus master, and the integrated circuit as a slave, below each designated with bus node, to be replaced. The TCK signal represents the system clock and temporally synchronizes the internal state machine of the test controller (TAPC) of the JTAG test interface to the IEEE 1149 integrated circuit standard. The TMS signal controls the state of this test controller (TAPC) of the JTAG interface of the bus node. Depending on the state of the test controller (TAPC), the JTAG test interface of the bus node performs different operations. The TDI input represents a serial data input. The TDo output represents a serial data output. The two inputs TMS and TDI are typically but not necessarily sampled with the rising TCK edge. The data output (TDo) typically changes its date with the falling edge of the TCK signal. The TCK, TMS and TDI single signals in the prior art form the test data input signals. In the context of this disclosure, they form the data input signals. The TDo signal represents the output signal. With the rising system clock edge (TCK edge) and with the appropriate setting of a test controller (TAPC) internal instruction register (IR), the data are sent serially via the serial data input TDI into different shift register chains, so-called scan register chains. Paths shifted into the integrated circuit as a bus node. At the same time, the original content of the relevant scan chain is output at the serial data output (TDo). In this case, state vectors of finite automata within the bus node can be part of the scan chain. Thus, a change in the contents and states or the control of these contents and states of the memory cells of the scan chains via this interface in the prior art is easily possible. Here is again referred to the literature.

Fig. 1 (prior art)

1 shows the standardized state diagram for a JTAG test controller (TAPC) according to the prior art and the relevant standards. After the system is reset, the test controller (TAPC) is in the Reset Test Logic (TLR) state. In this it remains as long as the test mode signal (TMS) is 1. If the test mode signal (TMS) is 0, the test controller (TAPC) changes to the "wait state" (RUN) in synchronism with the system clock (TCK). The test controller (TAPC) remains there until a 1 is present at the test mode signal (TMS). Then, the test controller (TAPC) changes to the "Data Register Move Start" (SDRS) state. If the test mode signal (TMS) also shows a 1 again the next time, the test controller (TAPC) then changes to the state "Start instruction register shift" (SIRS). If a 1 is then again present on the test mode signal (TMS) with the next cycle, the test controller (TAPC) returns to the state "reset test logic" (TLR) and resets the data interface logic.

However, if there is a 0 on the test mode signal (TMS) in the "Start of instruction register shift" (SIRS) state, the test controller (TAPC) changes to the state "load instruction register data" (CIR) in which the data is stored. which are available in an instruction shadow register into which the instruction register (IR) is loaded. In this respect, the instruction register (IR) is a two-stage register in which the foreground is formed by a shift register and the actual data is in a shadow register, which is read only in this state. The shift register of the instruction register (IR) serves to supply and remove the data, while the shadow register of the instruction register (IR) contains the actual, valid data. This two-stage validity applies to all registers, in particular also the data registers (DR), the JTAG interface, and also the registers of the interface according to the invention described below. Possibly. The Instruction Register (IR) shadow register may be partially or completely subdivided into one for reading and one for writing. Other visibility and accessibility changes depending on internal states are of course possible. If a 1 is present in the state "Load instruction register data" (CIR) at the next clock of the test mode signal (TMS), then the test controller (TAPC) jumps directly into the "instruction register Exit 1" (EIR1) described later. However, if a 0 is present, the test controller (TAPC) changes to the "shift instruction register" (SIR) state in which it remains as long as a 0 is present at the test mode signal (TMS). Only in this state, the shift register of the instruction register (IR) is operated in the function of a shift register and its data contents are shifted one bit towards the serial data output (TDI) with each clock of the system clock (TCK), with the last memory cell of the shift register of the instruction register (IR). Of course, the shadow register of the instruction register (IR) is not subjected to this shift operation. The data information applied to the data input (TDI) is loaded with each clock of the system clock (TCK) in the first cell of the shift register of the instruction register (IR) and from there while pushing forward with each further clock. If, however, a 1 is applied to the test mode signal at one clock, the test controller (TAPC) leaves the state "shift instruction register" (SIR) and changes to the already mentioned state "instruction register Exit 1" (EIR1). If a 1 is again present at the next clock of the system clock (TCK), the test controller (TAPC) changes to the state "write instruction register" (UIR2) in which the value of the shift register part of the instruction register (IR) in the shadow register of the instruction register (IR ) is written. However, if a 0 is present on the Test Mode Signal (TMS) in the "Instruction Register Exit 1" (EIR1) state, the Test Controller (TAPC) changes to the "Pause Instruction Register" (PIR) state, where it remains a 0 is applied to the test mode signal (TMS). If there is a 1 on the test mode signal (TMS) in the "Pause instruction register" (PIR) state, the test controller (TAPC) changes to the "Instruction register Exit 2" (EIR2) state. If a 0 is applied to the test mode signal (TMS) with the next system clock (TCK), the test controller (TAPC) returns to the previously described state "shift instruction register" (SIR). However, if in the state "instruction register Exit 2" (EIR2) with the next system clock (TCK) a 1 is present on the test mode signal (TMS), the test controller (TAPC) changes to the state "Write Instruction Register" (UIR2 ). In the following cycle, the Test Controller (TAPC) switches to the "Data Register Startup" (SDRS) state, if a 1 is present on the test mode signal (TMS) at this clock, and in the "wait" state (FIG. RUN), if a 0 is present.

If there is a 0 on the test mode signal (TMS) in the "Data Register Shift Start" state (SDRS), the test controller (TAPC) changes to the "Load Data Register Data" (CDR) state in which the data is being read are available in a data shadow register in which respective data registers (DR) are loaded. Which data register (DR) is selected by a plurality of data registers thereby determines by default at least part of the valid bits of the shadow register of the data register (DR). Again, typically, the data register (DR) is a two-level register in which the foreground is formed by a shift register and the actual data resides in a shadow register that is only in that state is read. The shift register of the data register (DR) also serves to supply and remove the data, while the shadow register of the data register (DR) contains the actual data. As already stated, this two-stage validity applies to all registers of the JTAG interface, including the inventive registers of the interface according to the invention described below, which are executed as standard as data registers (DR). Possibly. For example, the shadow register of the data register (DR) may again be subdivided in whole or in part into one for reading and one for writing operations. Other visibility and accessibility changes depending on internal conditions are of course also possible here. If a 1 is present in the state "load data register data" (CDR) at the next cycle of the test mode signal (TMS), then the test controller (TAPC) jumps directly into the state "data register exit 1" (EDR1) described later. However, if a 0 is present, the test controller (TAPC) changes to the "shift data register" (SDR) state in which it remains as long as a 0 is present at the test mode signal (TMS). Only in this state, and not otherwise, is the shift register of the data register (DR) operated in the function of a shift register and its data contents shifted one clock at each clock of the system clock (TCK) towards the serial data output (TDI), with the last one Memory cell of the shift register of the data register (DR) is connected. Of course, the shadow register of the data register (DR) is not subjected to this shift operation. The data information applied to the data input (TDI) is loaded into the first cell of the shift register of the data register (DR) with each clock of the system clock (TCK) and from there is conveyed during the shift with each further clock. If, however, a 1 is applied to the test mode signal (TMS) at one clock, the test controller (TAPC) leaves the state "data register shift" (SDR) and changes to the already mentioned state "data register exit 1" (FIG. EDR1). If a 1 is again present at the next clock of the system clock (TCK), the test controller (TAPC) changes to the state "write data register" (UIR2) in which the value of the shift register part of the data register (DR) in the shadow register of the data register (DR ) is written. However, if a 0 is applied to the test mode signal (TMS) in the "Data Register Exit 1" (EDR1) state, the test controller (TAPC) changes to the "Pause Data Register" (PDR) state, where it remains as long as a 0 is applied to the test mode signal (TMS). If a 1 on the test mode signal (TMS) is present in the "Pause Data Register" (PDR) state, the test controller (TAPC) changes to the "Data Register Exit 2" (EDR2) state. If a 0 is applied to the test mode signal (TMS) with the next system clock (TCK), the test controller (TAPC) switches back to the previously described state "Data register shift" (SDR). However, if in the state "Data Register Exit 2" (EDR2) with the next system clock (TCK) a 1 is present on the test mode signal (TMS), the test controller (TAPC) changes to the state "write data register" (UDR2 ). In the following cycle, the Test Controller (TAPC) switches to the "Data Register Startup" (SDRS) state, if a 1 is present on the test mode signal (TMS) at this clock, and in the "wait" state (FIG. RUN), if a 0 is present.

It is particularly useful to use this IEEE 1149 JTAG standard state scheme to stay compatible with the software-based standard that is already in widespread use. Of course, deviations from this JTAG standard are conceivable. In the description of the invention, however, we assume that this JTAG standard for the state diagram of the test controller (TAPC) is adhered to.

The semiconductor industry has tried several times in recent years to reduce the number of terminals to be used for such JTAG interfaces in order to limit the size of the required housing and thus the manufacturing costs. Various relevant documents have been disclosed. An exemplary document is US patent law US 2007/0 033 465 A1 , The technique disclosed therein does not permit consistent conversion of the data of the IEEE 1149.1 4-Wire JTAG protocol into the data of the method described therein and vice versa. The device arrangement described there and the method described there require synchronized time slots between the bus master, so the host processor and the bus node as a slave, so the integrated circuit to be tested, programmed or debuged. In the event of a lack of time synchronization of the bus master and bus node access to the test data bus, the TDo output driver of the bus node and the bus master output driver (typically a push-pull stage) may generate a short circuit while transmitting access to the test data line , In addition, it only discloses a point-to-point connection.

From the US 2007/0 033 465 A1 is a multi-level single-wire point-to-point arrangement is known, which already makes do with only one data line, but is not suitable for driving multiple bus nodes. The extension by in the EP 0 503 117 B1 is not possible because it does not disclose a suitable method for bidirectional forwarding of the intermediate levels.

From the US 2008/0 255 791 A1 For example, a method and configuration for the mixed operation of multiple single-wire and multi-wire JTAG test buses from a printed circuit is known. The topology the one of the US 2008/0 255 791 A1 The disclosed bus structure is essentially a star structure enabled via a special JTAG star coupler. Such a configuration is not autoaddressable because the position information of the single bus node is lost.

From the US 2009/0 252 210 A1 For example, a single wire data bus is known for a point-to-point connection with a multi-level data transmission. From the US 2014/0 281 076 A1 For example, a single wire data bus having a multi-level data transmission with a non-auto addressing star topology is known. From the DE 19 643 013 C1 is a unidirectional data bus system known that would be in principle autoadressierungsfähig. Due to the unidirectionality it always requires a return line compared to a real single wire data bus system, which increases the effort. From the DE 10 2007 060 441 B3 a data bus system is known in which information is transmitted by load modulation.

Object of the invention

It is the object of the invention to enable bidirectional, freely configurable transmission of illumination data with only one data line for more than one bus node (BS1, BS2, BS3) as a slave of a bus master (BM).

This object is achieved by a device according to claim 1.

Description of the invention

According to the invention it was recognized that a single-wire test bus, as with the associated operating method, for example, in the German patents DE 2015 004 434 B3 . DE 2015 004 433 B3 . DE 2015 004 435 B3 and DE 2015 004 436 B3 is described, especially for the transmission of such data, in particular for the control of the lighting means of light bands, is suitable if each bus node has a suitable sub-device for bidirectional handover. The disclosure of these German patent applications is thus a full part of this disclosure.

In contrast to the German patents DE 10 2015 004 434 B3 . DE 10 2015 004 433 B3 . DE 10 2015 004 435 B3 and DE 10 2015 004 436 B3 However, now no test data, but payload data are transmitted in particular for lighting control. Furthermore, also in the German patents DE 10 2015 004 434 B3 . DE 10 2015 004 433 B3 . DE 10 2015 004 435 B3 and DE 10 2015 004 436 B3 revealed test bus designed only for a point-to-point connection. It is therefore necessary to modify this test bus so that several bus slaves can be controlled and operated as bus nodes. According to the invention, the control data are written to or read from a special data register (DR) of a JTAG interface.

• 1. mindestens die Daten des seriellen Testdateneingangs TDI und
• 2. mindestens die Daten des einen seriellen Testausgangs TDo und
• 3. mindestens die Steuerdaten des Testmode-Eingangs TMS zur Steuerung des Test-Controllers der integrierten Schaltung und
• 4. mindestens den Testtakt zur Versorgung des Test-Controllers mit seinem Test-System-Takt TCK und
• 5. ein optionalen Testrücksetzsignal TRST

zu übertragenThe above and other objects are achieved according to the present invention by providing an interface unit having a JTAG interface capable of exchanging a temporal sequence of time multiplexed signals with the integrated circuit through an interface device. The signals are formatted in such a way that all information required by the JTAG interface for controlling the data flow and setting the lighting parameters of the connected lamps is transmitted serially via this interface. In this case, all data values of the JTAG Boundary Protocol are transmitted in designated time slots. In addition to the temporal multiplexing of the JTAG control signals, the interface device according to the invention uses three different voltage ranges (V _B1 , V _B2 , V _B3 ), see 2 , around

• 1. at least the data of the serial test data input TDI and
• 2. at least the data of the one serial test output TDo and
• 3. at least the control data of the test mode input TMS for controlling the test controller of the integrated circuit and
• 4. at least the test clock to supply the test controller with its test system clock TCK and
• 5. an optional test reset signal TRST

transferred to

The invention thus relates primarily to a bidirectional data bus between a first sub-device, the bus master (BM), and at least two further sub-devices, the bus node (BS1, BS2, BS3), see 6 , In this case, the bus node is identical to the aforementioned integrated circuit for controlling bulbs by means of PWM in the broadest sense, whose states are controlled or changed should be. Of course, the bi-directional data bus described in this disclosure is also suitable for controlling other consumers of electrical energy. This bidirectional data bus preferably has only one ground line (GND) and a single data line in the form of a single-wire data bus (b1, b2, b3) which is subdivided by the bus nodes (BS1, BS2, BS3) into different single-wire data bus sections (b1, b2, b3) becomes. As a result, the bus nodes require only two individual additional electrical connections. In order to be able to send in both data in one of the bus nodes (BS1, BS2, BS3), referred to below as the bus node, and also to be able to read out data from the relevant bus node, the data can be transmitted via the single-wire data bus (b1, b2, b3). be transmitted bidirectionally. The problem arises that in addition to the data transmission and a synchronization signal must be transmitted. For this purpose, the system clock is additionally transmitted via the single-wire data bus (b1, b2, b3) by a clock signal, the TCK signal, in particular from the bus master to the bus node. In order to enable this communication, the bus nodes (BS1, BS2, BS3) have a first device which determines the level on the single-wire data bus (b1, b2, b3) or on a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1 , b2, b3) compares with a first threshold. A realization of this first device is preferred as the first comparator (C _2H ), which compares the said level with that of a first threshold signal (V _2H ). Accordingly, the bus node furthermore has a second device which has the signal level in the form of a signal voltage on the single-wire data bus (b1, b2, b3) or on a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) compared to a second threshold. This is preferably done by a second comparator (C _2L ), which has the signal level in the form of a signal voltage on a single-wire data bus (b1, b2, b3) or on a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3). with the voltage level of a second threshold signal (V _2L ) compares. If the first threshold value (V _2H ) _differs from the second threshold value (V _2L ) and the threshold values lie within the supply voltage range, then these three threshold values (V _2H , V _2L ) define three voltage ranges (V _B1 , V _B2 , V _B3 ) and fixed. In this case, the first and second comparators (C _2H , C _2L ) measure on the bus node side in which voltage range (V _B1 , V _B2 , V _B3 ) the single-wire data bus (b1, b2, b3) or the respectively connected to the relevant bus node Single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) is currently located. The first and second threshold values thus define the three said signal voltage ranges (V _B1 , V _B2 , V _B3 ) between the operating voltage (V _IO ) and the reference potential (V ₀ ) of the reference potential line (GND). For clarity, we name the middle voltage range as the second voltage range (V _B2 ). This is limited by a first voltage range (V _B1 ) up or down. We consciously leave it open whether the first voltage range (V _B1 ) is a voltage range with more positive or negative voltages than the voltages of the middle, second voltage range (V _B2 ), since the system also works with reverse voltage polarities. At the same time, the second voltage range (V _B2 ) is correspondingly limited to the other voltage side, ie downwards or upwards, but the other way round than in the first voltage range (V _B1 ) is limited by a third voltage range (V _B3 ).

In order to now transfer the data from the bus master (BM), that is, the host processor, to a bus node (BS1, BS2, BS3), at least three consecutive time slots (TIN0, TIN1, TDO) are Master (BM) or the relevant bus node (BS1, BS2, BS3) data via the single-wire data bus (b1, b2, b3) or to the bus node (BS1, BS2, BS3) connected single-wire data bus section (b1, b2, b3) of the single-wire data bus ( b1, b2, b3), see 4 , Anyone who has a transmission authorization is determined by the time position of the respective time slot (TIN0, TIN1, TDO) and by the content of the bus node register (BKADR) of the bus node and the transmission address previously transmitted by the bus master (BM). Here, the bus master (BM) is typically allocated two timeslots (TIN0, TIN1) and the respective bus node (BS1, BS2, BS3) typically one time slot (TDO) in the packet of the three consecutive time slots (TIN0, TIN1, TDO). Which bus nodes (BS1, BS2, BS3) are allowed to transmit among the bus nodes (BS1, BS2, BS3) is determined according to the invention by a date, the transmission address of the relevant bus node (BS1, BS2, BS3), which is the bus master in all Transmitter registers (SR) of all accessible bus nodes transmitted and stored simultaneously, the Einzeldrahtdatenbusabschnitte just allow a connection to the bus master (BM). All bus nodes compare this transmit address in their respective transmit registers (SR) with their own bus node address stored in their bus node address registers (BKADR) during bus initialization and transmit only if the transmitted transmit address in their transmit register (SR) has its own stored bus node address in its bus node address register (BKADR) and then only at the predetermined times. The relative time slot position within the packet of at least three time slots (TIN0, TIN1, TDO) is preferably, but not necessarily, always the same for preferably all bus nodes. Particularly preferably, the first time slot (TIN0) and the second time slot (TIN1) contain a control data and / or a first data transmitted from the bus master (BM) to the bus nodes (BS1, BS2, BS3), the control data and the first date in particular, and preferably with the data of the IEEE 1149.1 4 wire Test data bus should be compatible, and the bus nodes receive the control date and the first date. In this way, for example, bus node addresses, transmission addresses and illumination values can be transmitted.

In contrast to the prior art, however, in the third time slot, the datum from the relevant bus node (BS _n ) to the bus master (BM) is now only in the second and third voltage range (V _B2 and V _B3 ) and not in the first voltage range (V _B1 ) transmitted when the transmitted and stored in the transmit register (SR) of the JTAG interface of the bus node transmit address matches the stored in the bus node address register (BKADR) of the bus node during the Businitialisierung stored bus node address. Thus, according to the invention, the third time slot contains a second datum which is transmitted from the relevant bus node (BS1, BS2, BS3) to the bus master (BM) and the bus master (BM) receives this second datum and wherein the second datum is received only in the second voltage range (V _B2 ) and in the third voltage range (V _B3 ) is transmitted. At the same time, the clock is transmitted by the bus master (BM) in each timeslot. The clock signal (TCK) is thereby signaled by a clock signal which occurs between the first voltage range (V _B1 ) in a first half-cycle period of the at least two half-clock periods (T _1H , T _2H ) of a system clock period (T) on the one side and the second voltage region ( V _B2 ) or third voltage range (V _B3 ) in the second half-clock period of the at least two half-clock periods (T _1H , T _2H ) of a system clock period (T) fluctuates. The clock signal can therefore be detected by measuring the voltage on the single-wire data bus (b1, b2, b3) or on a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) from the second voltage range (V _B2 ) or third voltage range (V _B3 ) in the first voltage range (V _B1 ) and vice versa. The crossing of the corresponding threshold voltage (V _2L ) can be detected by the associated comparator (C _2L ) or the corresponding device. Thus, it becomes possible to surely extract the system clock (TCK) on the bus node side, that is, the integrated circuit side. In this case, the construction of the clock impression in comparison to the construction of the impression of the other signals according to the invention chosen so that the clock transmitter on the side of the bus master (BM) can overwrite all other level sources that can be active in parallel on the data line. This is a significant difference from the prior art. In reality, therefore, it may be necessary to provide external larger transistors for imprinting the clock on the single wire data bus (b1, b2, b3) or on a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3). to be able to supply as many bus nodes as possible with one clock.

• • Es dominiert als erstes der Schaltzustand des dominierenden Schalters (S_1L) des Bus-Masters (BM), dann folgen
• • als zweites in der Hierarchie der spannungsbestimmenden Elemente für die Spannung auf dem Eindrahtdatenbus (b1, b2, b3) oder dem betreffenden, angeschlossener Eindrahtdatenbusabschnitt (b1, b2, b3) des Eindrahtdatenbusses (b1, b2, b3) die beiden geschalteten Stromquellen des Bus-Masters (I₁, S_1H) und des betreffenden Busknotens (I₂, S_2H), die typischerweise untereinander gleichberechtigt sind, und als
• • drittes und letztes mit niedrigster Priorität der Pull-Schaltkreis, hier in Form eines Spannungsteilers (R_0H, R_0L), der typischerweise nur einmal pro Eindrahtdatenbussystem vorgesehen wird.

In a particular embodiment of the invention, this is therefore characterized by the fact that three logical states in the bidirectional transmission of the data on the single-wire data bus (b1, b2, b3) or on a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2 , b3) are used by the bus master (B) and the bus nodes (BS1, BS2, BS3), these logical states having a hierarchy and a clock state, here the one in which the single-wire data bus (b1, b2, b3) or a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) is in the first voltage range (V _B1 ) which has the highest priority and can not be overwritten by other transmission devices. This ensures that the bus master and the bus nodes can always operate synchronously at least with regard to the basic clock. In order to establish this first logic state, in which the single-wire data bus (b1, b2, b3) or a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) is forced into the first voltage range (V _B1 ) For example, the master single wire data bus interface (OWM) of the bus master (BM) may comprise a dominant switch (S _1L ) including the single wire data bus (b1, b2, b3) or a connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3), for example, short-circuits against the reference potential (V ₀ ) of the reference potential line (GND) in the associated half-clock periods of the at least two half-clock periods (T _1H , T _2H ) of the respective system clock period (T), see 3 , This periodic short circuit can then no longer be overwritten by other transmitters if its internal resistance is higher according to the invention than that of the dominant switch (S _1L ). For example, by a voltage divider _comprising a first voltage divider resistor (R _0H ) against a voltage, for example the supply voltage (V _IO ), and a second voltage divider resistor (R _0L ) against another voltage, for example the reference potential (V ₀ ), the single-wire data bus (b1, b2, b3) or a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) is held or fed back into the second voltage range (V _B2 ) if none of the other transmitters (S _1L , S _1H , I ₁ , S _2H , I ₂ ) of the bus master (BM) or the bus node (BS1, BS2, BS3) sends. In order to transmit data now, the single-wire data bus (b1, b2, b3) or a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3), in contrast to the prior art, becomes out of this second voltage range (V _B2 ). is brought by the transmitters of the bus master (BM) and / or the bus nodes (BS1, BS2, BS3) into the third voltage range (V _B3 ) if a logical value opposite to the logical data value of the second voltage range (V _B2 ) is to be transmitted , For this purpose, the respective transmitting unit feeds, ie the bus master or the relevant bus node (BS1, BS2, BS3), a current into the single wire data bus (b1, b2, b3) or the respective connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3). This injected current leads to a changed voltage drop across the voltage divider resistors (R _0H , R _0L ). With a proper polarity of the injected current, the voltage level on the single wire data bus (b1, b2, b3) or on a connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3) from the second voltage range (V _B2 ) in the third voltage range (V _B3 ) shifted. Should it come to a simultaneous transmission by means of such a data stream, and the simultaneous closing of the dominant switch (S _1L ), then the dominant switch, if it is designed according to the invention low enough, dissipate the transmission current of the respective transmitter and thus this voltage level and, if necessary also _{override the} voltage level generated by the voltage divider (R _0H , R _0L ). However, it does not come to a short circuit as in the prior art. In particular, it does not come to that from the US 2007/0 033 465 A1 known short circuit between the bus node side and the bus master transmitter. It is thus a particular feature of the invention that a second of the three logic states on the data bus is provided by a first switchable current source (I ₁ , S _1H ) in the bus master and / or a second switchable current source (I ₂ , S _2H ). and not generated by a voltage source. At the same time, in one embodiment of the invention, a third of the three logic states on the data bus is generated by a pull circuit (R _0H , R _0L ) in the form of a voltage divider. Of course, other possibilities for such a pull circuit are conceivable. In principle, the pull circuit in the form of a voltage divider is a voltage source which places the data line at a second voltage which lies within the second voltage range (V _B2 ), and which voltage source has an internal resistance which is so great in that the possible input current is limited so that the switched current sources (I ₁ , S _H1 ) and (I ₂ , S _H2 ) deliver a larger current than this pull circuit (R _0H , R _0L ) can dissipate. This results in a clear hierarchy:

• It dominates first the switching state of the dominant switch (S _1L ) of the bus master (BM), then follow
• Second, in the hierarchy of the voltage-determining elements for the voltage on the single-wire data bus (b1, b2, b3) or the respective connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) the two switched current sources of the bus -Masters (I ₁ , S _1H ) and the relevant bus node (I ₂ , S _2H ), which are typically equal to each other, and as
• Third and last lowest priority of the pull circuit, here in the form of a voltage divider (R _0H , R _0L ), which is typically provided only once per single wire _data bus system.

The first logic state preferably corresponds to a voltage level (V ₀ ) in the first voltage range (V _B1 ) on the single-wire data bus (b1, b2, b3) or a connected single-wire data bus portion (b1, b2, b3) of the single-wire data bus (b1, b2, b3). , the second logic state having a voltage level (V _M ) in the second voltage range (V _B2 ) on the single wire data bus (b1, b2, b3) or a connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3) and the third logic state having a voltage level (V _IO ) in the third voltage range (V _B3 ) on the single wire data bus (b1, b2, b3) or a connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3), see 2 ,

According to the invention, the second logic state on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) for transmitting a first logical state, for example "low", of a data signal and the third logic state on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) for transmitting a second logical state, for example "high", of Data signal used. If the data line is in the first logical state, it is ignored for data transmission.

According to the invention, the first logic state on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) is used to transmit a first logical state, for example "low" of a system clock signal and the third or second logic state on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) for transmitting a second logical state, for example "high" of System clock signal used. The logic state on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) changes between the second or third logical state on the single wire data bus (b1, b2, b3 ) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3), this change is ignored for the transmission of the system clock and typically continues to be interpreted as a second logic state, for example "high".

According to the invention, the disclosed technology is thus in one embodiment a data bus system with a reference potential line (GND) and a single-wire data bus (b1, b2, b3) for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular to illuminant bus nodes. In this case, the single-wire data bus (b1, b2, b3) is subdivided by the bus nodes (BS1, BS2, BS3) into at least two single-wire data bus sections (b1, b2, b3). It is terminated by a bus node, the terminating bus node (BS3). Each of the bus nodes (BS1, BS2, BS3) is, except for a first bus node (BS1), a preceding single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3) with a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3). The one first bus node (BS1) is connected to the bus master (BM) through a preceding single-wire data bus section (b1) of the single-wire data bus sections (b1, b2, b3). Each bus node (BS1, BS2, BS3) is, with the exception of one terminating bus node (BS3), connected by a subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a subsequent bus node (BS3, BS4) of the bus nodes (BS1, BS3). BS2, BS3). This does not apply to the terminating bus node (B3). The bus master (BM) is provided with a master single wire data bus interface (OWM), wherein the master single wire data bus interface (OWM) is provided to bidirectionally over the single wire data bus via a data bus protocol with more than two physical voltage and / or current levels. b1, b2, b3) or at least one single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3), hereinafter referred to as the considered single-wire data bus section (b1, b2, b3), and to receive from this. The considered single-wire data bus section (b1, b2, b3) comprises only a single signal line. A single-wire data bus interface (OWS1, OWS2, OWS3) of a bus node (BS1, BS2, BS3) of the bus nodes (BS1, BS2, BS3), referred to below as the considered bus node, and a transfer are referred to the single-wire data bus section (b1, b2, b3) Gate (TG1, TG2, TG3) of the considered bus node (BS1, BS2, BS3) electrically connected. The single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node is intended to bidirectionally send and receive data via the considered single-wire data bus section (b1, b2, b3) by means of a data bus protocol with more than two physical voltage and / or current levels , The transfer gate (TG1, TG2, TG3) of the considered bus node is intended to separate and / or electrically connect the considered single wire data bus section (b1, b2) from an optional subsequent single wire data bus section (b2, b3). The considered bus node (BS1, BS2, BS3) has a transfer gate control register (TGCR) which is designed to connect the transfer gate (TG1, TG2, TG3) of the considered bus node (BS1, BS2, BS2). BS3). The bus master (BM) can use the master single-wire data bus interface (OWM) and the single-wire data bus (b1, b2, b3) or the considered single-wire data bus section (b1, b2, b3) and the single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node describe the transfer gate control register (TGCR) of the considered bus node (BS1, BS2, BS3). Thus, the bus master is able to control the state of the transfer gate (TG1, TG2, TG3) of the considered bus node (BS1, BS2, BS3).

In another embodiment, the considered bus node (BS1, BS2, BS3) internally at least one IEEE 1149 compliant interface, also known as JTAG interface, on the one-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node with the single-wire data bus ( b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) is connected so that the bus master (BM) over the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3 ) can serve this JTAG interface. In the context of this disclosure, a JTAG interface is characterized in that it has a test controller (TAPC) in the form of a finite state machine - also called a finite state machine - which complies with an IEEE 1149-compliant state diagram 1 and the introductory description.

In another embodiment, a data bus according to the invention is characterized in that the respective transfer gate control register (TGCR) of the considered bus node (BS1, BS2, BS3) by means of the at least one JTAG test interface of the considered bus node (BS1, BS2 , BS3) via the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) can be described by the bus master (BM).

In a further embodiment, a data bus system according to the invention is characterized in that at least the considered bus node, a light source bus node, is provided with light sources assigned to it, hereinafter referred to as light sources, in dependence on data transmitted via the single wire data bus (b1 , b2, b3) or the considered single-wire data bus section (b1, b2, b3) are transmitted from the bus master (BM) to the considered bus node (BS1, BS2, BS3).

In another embodiment, a data bus system according to the invention is characterized in that the JTAG interface of the considered bus node has at least one illumination register (ILR) as Data register (DR) of the JTAG interface of the considered bus node comprises, at least temporarily, the at least temporary control of the light source, in particular brightness and / or color temperature, by the considered bus node by means of the PWM units (PWM1, PWM2, PWM3). depends on the considered bus node.

In another embodiment, a data bus system according to the invention is characterized in that the JTAG interface of the considered bus node at least one lighting control register (ILCR) as a data register (DR) of the JTAG interface of the considered bus node and a lighting register (ILR) as a data register (DR) of the JTAG Interface of the considered bus node comprises. At least part of the contents of the lighting control register (ILCR) depends on whether the lighting register (ILR) is connected via the JTAG interface by means of the combined TMS TDI signal (TMS_TDI) of the JTAG interface of the considered bus node or a separate data input (SILDI) of the considered bus node receives the serial illumination data for controlling the control of the light source considered by the bus master (BM) or another bus node. From the at least temporary content of the lighting register (ILR) depends in this case, at least temporarily, the control of the light source considered by the considered bus node.

The data bus system according to the invention is provided with a reference potential line (GND) and a single-wire data bus (b1, b2, b3) for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular illuminant bus nodes , Mistake. In this case, the single-wire data bus (b1, b2, b3) is subdivided by the bus nodes (BS1, BS2, BS3) into at least two single-wire data bus sections (b1, b2, b3). It is terminated by a bus node, the terminating bus node (BS3). Each of the bus nodes (BS1, BS2, BS3) except for a first bus node (BS1) is connected by a preceding single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a preceding bus node (BS1, BS2) of the bus nodes (BS1 , BS2, BS3). The one first bus node (BS1) is connected to the bus master (BM) through a preceding single wire data bus section (b1) of the single wire data bus sections (b1, b2, b3). Each bus node (BS1, BS2, BS3) except for the terminating bus node (BS3) is connected by a subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a subsequent bus node (BS3, BS4) of the bus nodes (BS1, BS3). BS2, BS3). The data bus system has the bus master (BM) with a master single wire data bus interface (OWM). As described, the master single-wire data bus interface (OWM) is provided to bidirectionally over the single-wire data bus (b1, b2, b3) or at least one single-wire data bus section (b1, b2, b3) via a data bus protocol with more than two physical voltage and / or current levels ) of the single-wire data bus sections (b1, b2, b3), hereinafter referred to as the considered single-wire data bus section (b1, b2, b3), and to receive from this. The considered single-wire data bus section (b1, b2, b3) comprises only a single signal line. A single-wire data bus interface (OWS1, OWS2, OWS3) of a bus node (BS1, BS2, BS3) of the bus nodes (BS1, BS2, BS3), referred to below as the considered bus node, is electrically connected to the single-wire data bus section (b1, b2, b3) under consideration. The single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node is intended to receive data from the single-wire data bus section under consideration (b1, b2, b3) by means of a data bus protocol with more than two physical voltage and / or current levels. The considered bus node (BS1, BS2, BS3) comprises an address register (BKADR) as a data register (DR) of a JTAG interface, which can be described by the bus master (BM) preferably only when the transfer gate (TG) and opened by the content of which depends on the contents of the transmitter register (SR) of the JTAG interface of the bus node, whether the single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node data at designated times and / or after sending specific data, such as a transmission address for the transmit registers (SR) the bus node, by the bus master (BM) or another bus node of the bus nodes (BS1, BS2, BS3) on the single-wire data bus (b1, b2, b3) and / or the considered single-wire data bus section (b1, b2, b3) May output data. The single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node is intended to transmit data via the data wire bus section (b1, b2, b3) under consideration by means of a data bus protocol with at least two physical voltage and / or current levels.

In a further embodiment, a data bus system according to the invention is characterized in that the considered bus node (BS1, BS2, BS3) internally has at least one IEEE 1149-compliant interface, also known as JTAG interface, which communicates via the single-wire data bus interface (OWS1, OWS2, OWS3). of the considered bus node is connected to the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) so that the bus master (BM) looks over the single-wire data bus (b1, b2, b3) or at least the one Single wire data bus section (b1, b2, b3) can serve this JTAG interface. In this case, a JTAG interface in the sense of this disclosure is characterized in that it has a test controller (TAPC) in the form of a finite-state machine - also called a finite state machine - which complies with an IEEE 1149 compliant state diagram 1 has.

In a further embodiment, a data bus system according to the invention is characterized in that a transfer gate (TG1, TG2, TG3) of the considered bus node (BS1, BS2, BS3) is electrically connected to the considered single-wire data bus section (b1, b2, b3). The transfer gate (TG1, TG2, TG3) of the considered bus node is intended to separate and / or electrically connect the considered single wire data bus section (b1, b2) from the optional subsequent single wire data bus section (b2, b3). The considered bus node (BS1, BS2, BS3) has a transfer gate control register (TGCR) as a data register (DR) of the JTAG interface, which is designed to the transfer gate (TG1, TG2, TG3 ) to control. The respective transfer gate control register (TGCR) of the considered bus node (BS1, BS2, BS3) can be connected via the single-wire data bus (b1, b2, B3) via the at least one JTAG test interface of the considered bus node (BS1, BS2, BS3). b3) or at least the single-wire data bus section (b1, b2, b3) considered at least by the bus master (BM).

In a further embodiment, a data bus system according to the invention is characterized in that at least the considered bus node, a light source bus node, is provided with light sources (LM) assigned to it, referred to below as light sources (LM), depending on data. which are transmitted via the single-wire data bus (b1, b2, b3) or the single-wire data bus section (b1, b2, b3) considered by the bus master (BM) to the considered bus node (BS1, BS2, BS3).

In a further embodiment, a data bus system according to the invention is characterized in that the JTAG interface of the considered bus node comprises at least one illumination register (ILR) as data register (DR) of the JTAG interface of the considered bus node, at least temporarily controlling the control of the considered Illuminant (LM) depends on the considered bus node. This can be z. As the duty cycle, the amplitude, the frequency and other parameters of PWM control concern.

In a further embodiment, a data bus system according to the invention is characterized in that the JTAG interface of the considered bus node comprises at least one lighting control register (ILCR) as a data register of the JTAG interface of the considered bus node and a lighting register (ILR) as a data register of the JTAG interface of the considered bus node , At least part of the contents of the lighting control register (ILCR) depends on whether the lighting register (ILR) via the test data interface (TMS_TDI) of the JTAG interface of the considered bus node or a separate data input (SILDI) of the considered bus node, preferably the serial illumination data to control the control the considered light source receives from the bus master or another bus node. From the at least temporary content of the lighting register (ILR), the control of the light source (LM) under consideration by the considered bus node depends at least temporarily.

A JTAG interface according to the invention of a bus node (BS1, BS2, BS3) for controlling the activation of light sources (LM) by a bus node (BS1, BS2, BS3) of a light chain is characterized in that it comprises at least one illumination register (ILR) as data register ( DR) of this JTAG interface, whose at least temporary content at least temporarily depends on the control of the lighting means (LM) by the bus node (BS1, BS2, BS3). As before, a JTAG interface is characterized in that the test controller (TAPC) is a state diagram according to the IEEE 1149 standard (see also 1 ) and in particular one or more of its sub-standards IEEE 1149.1 to IEEE 1149.8 and their further developments. This definition of the tag of a JTAG interface applies to the entire document.

An inventive method for controlling a light source (LM) by means of an electrical control device within a bus node (BS1, BS2, BS3) of several bus nodes (BS1, BS2, BS3), the considered bus node, then comprises the following steps: transmission of control data for the setting of luminous values for at least one luminous means by controlling a JTAG controller (TAPC) of a JTAG interface within the considered bus node (BS _n ), which supplies at least one light source (LM) with controllable electrical energy as a function of this control data. The JTAG interface is again - as in this entire disclosure - characterized in that the test controller (TAPC) comprises a state diagram according to the IEEE 1149 standard and / or in particular one or more of the sub-standards IEEE 1149.1 to IEEE 1149.8 and their further developments ,

A JTAG interface according to the invention for controlling the activation of lighting means by a bus node (BS1, BS2, BS3) of a light chain can also be characterized by having at least one lighting control register (ILCR) as the data register of the JTAG interface and a lighting register (ILR) as Data register of the JTAG interface includes. According to the invention, at least parts of the content of the lighting control register (ILCR) depend on whether the lighting register (ILR) receives the illumination data for controlling the activation of the lighting means by the bus node via the test data interface (TMS_TDI) of the JTAG interface or a separate data input (SILDI) , These registers may also be sub-registers of the Instruction Register (IR) or other data register of the JTAG interface. The separate implementation is usually preferable. From at least temporary content of the lighting register (ILR) then depends at least temporarily the control of the lighting means by the bus node (BS1, BS2, BS3). As before, the JTAG interface is again characterized in that it comprises a test controller (TAPC) which has a state diagram according to the IEEE 1149 standard and in particular one or more of the substandards IEEE 1149.1 to IEEE 1149.8 and their further developments.

A data bus according to the invention between a first sub-device, the bus master (BM), and at least two further sub-devices, the bus node (BS1, BS2, BS3) has a reference potential line (GND) with a reference potential (V ₀ ) and a single-wire data bus (b1, b2, b3) for data transmission and system clock transmission between the bus master (BM) and the bus nodes (BS1, BS2, BS3). In this case, the single-wire data bus (b1, b2, b3) is subdivided by the bus nodes (BS1, BS2, BS3) into at least two single-wire data bus sections (b1, b2, b3). Each of these bus nodes (BS1, BS2, BS3) is connected, except for a first bus node (BS1), via a preceding single-wire data bus section (b1, b2, b3) to a preceding bus node (BS1, BS2) of the bus nodes (B1, B2, B3). The first bus node (BS1) is connected to the bus master (BM) via a preceding single wire data bus section (b1). Each of these bus nodes (BS1, BS2, BS3) is connected to a subsequent bus node (BS3) via a subsequent single-wire data bus section (b2, b3) to a subsequent bus node (BS2, BS3). This applies if the bus node is not the last bus node (B3) of the chain of bus nodes (BS1, BS2, BS3) from the bus master (BM) in the sequence of bus nodes (BS1, BS2, BS3). Via the single-wire data bus (b1, b2, b3) or at least via a single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3), referred to below as the single-wire data bus section (b1, b2, b3), data is bidirectionally interpolated between the Bus master (BM) and a bus node (BS1 BS2, BS3), hereinafter referred to as the bus node (BS1, BS2, BS3) called, transmitted or can be transmitted. Via the single-wire data bus (b1, b2, b3) or at least over the single-wire data bus section (b1, b2, b3) considered, a system clock having a system clock period (T) which is generated in at least a first half-clock period (T _1H ) and a second half-clock period (T _2H ), which may have a different duration, additionally transmitted from the bus master (M) to the considered bus node (BS1, BS2, BS3). At least the considered bus node (BS1, BS2, BS3) has a first device, in particular a first comparator (C _2H ), the signal level in the form of a signal voltage between the reference potential (V ₀ ) of the reference potential line (GND) and the potential of the considered Single wire data bus section (b1, b2, b3) with a first threshold, in particular that of a first threshold signal (V _2H ), compares. The considered bus node has a second device, in particular a second comparator (C _2L ), which has the signal level in the form of a signal voltage between the reference potential (V ₀ ) of the reference potential line (GND) and the potential of the considered single-wire data bus section (b1, b2, b3). with a second threshold, in particular that of a second threshold signal (V _2L ), compares. The first threshold is different from the second threshold. The first and second threshold values define between the operating voltage (V _IO , V _IO1 , V _IO2 ) and the reference potential (V ₀ ) of the reference potential line (GND) three signal voltage ranges (V _B1 , V _B2 , V _B3 ). In this case, a mean voltage range is limited as a second voltage range (V _B2 ) from a first voltage range (V _B1 ) upwards or downwards. The second voltage range (V _B2 ) is limited to the bottom or top but the other way around than the first voltage range (V _B1 ) by a third voltage range (V _B3 ). In this case, data on the single-wire data bus section (b2, b3) under consideration is transmitted in time-spaced or successive time-slot packets each having a duration of one system clock period (T) with at least three consecutive time slots (TIN0, TIN1, TDO). A first time slot (TIN0) and a second time slot (TIN1) contain at least one control data and / or a first data transmitted from the bus master (BM) to the considered bus node (BS1, BS2, BS3), the control data and in particular, the first datum may be compatible with the data of the IEEE 1149.14 wire test data bus or with another substandard of the IEEE 1149 standard, and wherein the considered bus node (BS1, BS2, BS3) receives the control datum and the first datum. A third time slot (TDO) contains a second datum which transmits the considered bus node (BS1, BS2, BS3) to the bus master (BM), the bus master (BM) receiving this second datum and the second datum only in the second voltage range (V _B2 ) and third voltage range (V _B3 ) is transmitted. The transmission of the data takes place in one Half-cycle period of the at least two half-clock periods (T _1H , T2 _H ) of a system clock period (T). The system clock is transmitted by a clock signal in the first voltage range (V _B1 ) during the respective other half-clock period of the at least two half-clock periods (T _1H , T _2H ) of the system clock period (T).

In another embodiment of the invention, the data bus according to the invention between a first subdevice, the bus master (BM), and further at least two subdevices, the bus node (BS1, BS2, BS3) characterized in that at least three logic states in bidirectional transmission of the data on the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) under consideration by the bus master (BM) and the bus nodes (BS1, BS2, BS3).

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that a first of the at least three logical states is generated on the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) considered by a first dominant switch (S _1L ) of the bus master (BM), which detects the potential of the single-wire data bus (b1, b2 , b3) or at least of the considered single-wire data bus section (b1, b2, b3) forces into the first voltage range (V _B1 ).

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that a second of the at least three logical states on the single wire data bus (b1, b2, b3) or at least the considered single wire data bus section (b1, b2, b3) by switching on a first switchable current source (I ₁ , S _1H ) in the bus master (BM) and / or by switching on a second one switchable current source (I ₂ , S _2H ) is generated in the bus node (BS1, BS2, BS3), see 3 ,

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that the switching of the first switchable current source ( I ₁ , S _1H ) in the bus master (BM) and / or turning on the second switchable current source (I ₂ , S _2H ) in the bus node (BS1, BS2, BS3) the potential on the single wire data bus or at least the considered single wire data bus section (b1, b2, b3) to a potential in the third voltage range (V _B3 ) forces unless the first dominant switch (S _1L ) of the bus master (BM) is turned on, the potential of the single wire data bus or at least the considered single wire data bus section (b1) forces into the first voltage range when switching on and overwrites the switchable current sources (I ₁ , S _1H , I ₂ , S _2H ).

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that a third of the at least three logic states on which the single-wire data bus (b1, b3, b3) or at least the single-wire data bus section (b1, b2, b3) considered is generated by a pull circuit (R _0H , R _0L ), if none of the other logical states are present, by the pull Circuit (R _0H , R _0L ) _brings the potential of the single wire _data bus or at least the considered single wire _data bus section (b1, b2, b3) to a mean potential (VM) in the second voltage range (V _B2 ).

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that the change from a second or a third logic state on the single wire data bus (b1, b3, b3) or at least the considered single wire data bus section (b1, b2, b3) on the one hand to a first logical state on the single wire data bus (b1, b3, b3) or at least the single wire data bus section (b1 , b2, b3) on the other side and changes in the reverse direction to transmit a clock signal.

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that the change from a first or a second logic state on the single wire data bus (b1, b3, b3) or at least the considered single wire data bus section (b1, b2, b3) on the one hand to a third logical state on the single wire data bus (b1, b3, b3) or at least the single wire data bus section (b1 , b2, b3) on the other side and changes in the reverse direction for transmitting a data signal from the bus master (BM) to the considered bus node and / or from the considered bus node to the bus master (BM).

In another embodiment of the invention, the data bus according to the invention between a first sub-device, the bus master (BM), and further at least two sub-devices, the bus node (BS1, BS2, BS3) characterized in that the data in a half-clock period of at least two half-clock periods (T _1H , T _2H ) of one time slot are transmitted and the system clock is transmitted in another half-clock period of the at least two half-clock periods (T _1H , T _2H ) of a time slot, wherein a time slot packet is one length of a system clock period (T) with at least two half-clock periods (T _1H , T _2H ).

A data bus according to the invention extends between a first subdevice, the bus master (BM), and at least two further subdevices, the bus node (BS1, BS2, BS3), the data bus having a reference potential line (GND) with a reference potential (V ₀ ) and a single wire data bus (b1, b2, b3) having a single data line divided by the bus nodes (BS1, BS2, BS3) into a plurality of single wire data bus sections (b1, b2, b3) and by a last bus node (BS3) of the bus nodes (BS1 , BS2, BS3), the terminating bus node (BS3), and may also be characterized as follows: The bus master (BM) has a master single wire data bus interface (OWM). The master single wire data bus interface (OWM) further comprises a first switchable voltage source (S _1L ) having a first internal resistance comprising the single wire data bus (b1, b2, b3) or at least one single wire data bus portion (b1, b2, b3), hereinafter referred to as single wire data bus portion (FIG. b1, b2, b3) can connect to a first potential (V0). The master single-wire data bus interface (OWM) has a second switchable voltage source (S _1H , I ₁ ) with a second internal resistance which comprises at least the considered single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) or the single-wire data bus ( b1, b2, b3) can connect to a second potential (V _IO1 ), the second switchable voltage source also having a current source (S _1H , I ₁ ) with a second internal resistance (R _1H ) and the current value (I ₁ = V _IO1 / R _1H ) can be. At least one of the bus nodes (BS1, BS2, BS3), referred to below as the considered bus node, has a single-wire data bus interface (OWS1, OWS2, OWS3), referred to below as the considered single-wire data bus interface. At least this considered single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node has a third switchable voltage source (S _2H , I ₂ ) with a third internal resistance which comprises at least the single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2 , b3) or the single _{- wire data} bus (b1, b2, b3) can connect to a third potential (V _IO2 ) which is preferably equal to the second potential (V _IO1 ) and wherein the third switchable voltage source also _comprises a current source (S _2H , I ₂ ) with a third internal resistance (R _2H ) and the current value (I ₂ = V _IO2 / R _2H ). At least the considered single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) or the single-wire data bus (b1, b2, b3) is _{interconnected} by a fourth voltage source, in particular a pull circuit (R _0H , R _0L ) fourth potential (V _IO ), which is preferably equal to the second and third potentials (V _IO1 , V _IO2 ), and the first potential (V ₀ ), with a fourth internal resistance maintained at a mean potential (V _M ). The value of the mean potential (V _M ) is between the value of the first potential (V ₀ ) and the value of the second potential (V _IO1 ) and / or between the value of the first potential (V ₀ ) and the value of the third potential s (V _IO2 ). The first internal resistance is smaller than the other internal resistances. The fourth internal resistance is greater than the other internal resistances.

Accordingly, a method according to the invention for operating a data bus between a first subdevice, the bus master (BM), and at least two further subdevices, the bus node (BS1, BS2, BS3) can be formulated. In this case, the data bus has a reference potential line (GND) with a reference potential (V0) and a single-wire data bus (b1, b2, b3), which is divided by the at least two bus nodes (BS1, BS2, BS3) into at least two single-wire data bus sections (b1, b2, b3 ) and is terminated by at least one bus node (BS3) of the bus node (BS1, BS2, BS3), the terminating bus node (BS3). The method comprises the steps: as a first step, a bidirectional transmission of data over the single-wire data bus (b1, b2, b3) or at least one single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3), referred to below as single-wire data bus section between the bus master (BM) and at least one bus node (BS1, BS2, BS3), referred to hereinafter as the bus node (BS1, BS2, BS3); As a second step, the simultaneous transmission of a clock signal via the single-wire data bus (b1, b2, b3) or at least the said single-wire data bus section (b1, b2, b3) from the bus master (BM) to at least the considered bus node (BS1, BS2, BS3) a system clock period (T) divided into at least a first half-clock period (T _1H ) and a second half-clock period (T _2H ); As a third step, the comparison of the signal level on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) in the form of a signal voltage between the reference potential (V0) of the reference potential line (GND) and the potential of the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) having a first threshold, in particular that of a first Threshold signal (V _2H ), by a first device of the considered bus node (BS1, BS2, BS3), in particular a first comparator (C _2H ); As a fourth step, the comparison of the signal level on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) in the form of a signal voltage between the reference potential (V ₀ ) on the reference potential line (GND) and the potential of the Single-wire data bus (b1, b2, b3) or at least of the considered single-wire data bus section (b1, b2, b3) with a second threshold value, in particular that of a second threshold signal (V _2L ), different from the first threshold value, by a second device of the considered bus node (BS1, BS2, BS3), in particular a second comparator (C _2L ). In this case, the first and second threshold values between an operating voltage (I _IO , V _IO1 , V _IO2 ) and the reference potential (V ₀ ) of the reference potential line (GND) _define three signal voltage ranges (V _B1 , V _B2 , V _B3 ). A middle voltage range is thereby bounded as a second voltage range (V _B2 ) from a first voltage range (V _B1 ) upwards or downwards, and wherein the second voltage range (V _B2 ) upwards or downwards but vice versa than the first voltage range (V _B1 ) is limited by a third voltage range (V _B3 ); As a fifth step, the transmission of the data on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) in time-slot packets each having a duration of a system clock period (T) with at least three consecutive time slots (TIN0, TIN1 , TDO), wherein the order of the time slots (TIN0, TIN1, TDO) within the sequence of these at least three time slots (TIN0, TIN1, TDO) can be selected system-specific; As a sixth step, transmitting at least one control datum and / or a first datum in a first time slot (TIN0) and in a second time slot (TIN1) from the bus master (BM) to the considered bus node (BS1, BS2, BS3), the control datum and the first datum may be particularly compatible with the data of the IEEE 1149 standard, and wherein the considered bus node (BS1, BS2, BS3) receives the control datum and the first datum; As a seventh step, transmitting a second data in a half-clock period of the at least two half-clock periods (T _1H , T _2H ) of the system clock period (T) in the second voltage range (V _B2 ) and in the third voltage range (V _B3 ) on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) from the considered bus node (BS1, BS2, BS3) to the bus master (BM) in a third time slot (TDO) of the at least three consecutive time slots (TIN0, TIN1, TDO) wherein the bus master (BM) receives this second datum; As the eighth step, transmitting another control data and / or another first data in a half-clock period of the at least two half-clock periods (T _1H , T _2H ) of the system clock period (T) of the respective time slot, in the second voltage range (V _B2 ) and third voltage range (V _B3 ) on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) from the bus master (BM) to the considered bus node (BS1, BS2, BS3) in the first and / or second timeslot ( TIN0, TIN1) of the at least three consecutive time slots (TIN0, TIN1, TDO), wherein the considered bus node (BS1, BS2, BS3) receives the further control data and the further first data, the transmission of the data by changing the potential on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) between the second voltage range (V _B2 ) on the one side and the third voltage range (V _B3 ) takes place on the other side over the first voltage range (V _B1 ) and over the first voltage range (V _B1 ) change in the opposite direction; The ninth step is to transmit a system clock in the other half-clock period of the at least two half-clock periods (T _1H , T _2H ) of the system clock period (T) of the respective timeslot, typically in each of the at least three time slots (TIN0, TIN1, TDO) Half clock period no data are sent and wherein the transmission of the system clock in the respective time slot by a change of the potential on the single wire data bus (b1, b2, b3) or at least the considered single wire data bus section (b1, b2, b3) between the first voltage range (V _B1 ) on the one hand and the second voltage range (V _B2 ) and / or third voltage range (V _B3 ) on the other side and change in the opposite direction.

A variant of this method is characterized in that three logical states in the bidirectional transmission of data on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) by the bus master (BM) and the considered bus node, each logical state of a, typically just one, voltage range (V _B1 , V _B2 , V _B3 ) of the potential of the single wire data bus (b1, b2, b3) or at least the considered single wire data bus section (b1, b2, b3) assigned is.

Another variant of this method is characterized by a temporary closing of a dominant switch (S _1L ) of the bus master (BM), which may also be a transistor or other semiconductor switch, for the temporary generation of a first of the three logical States on the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section under consideration (b1, b2, b3), wherein the potential of the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) in the first voltage range (V _B1 ) is forced.

A further variant of this method is characterized by a temporary switching on of a first switchable current source (I ₁ , S _1H ) in the bus master (BM) and / or by temporarily switching on a second switchable current source (I ₂ , S _2H ) in the considered one Bus node for generating a third of the three logic states on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3).

A further variant of this method is characterized in that the switching on of the first switchable current source (I ₁ , S _1H ) in the bus master (BM) and / or the switching on of the second switchable current source (I ₂ , S _2H ) in the considered bus node, the potential on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) to a third potential forces unless the first dominant switch (S _1L ) of the bus master (BM) is not turned on which forces the potential of the single wire data bus (b1, b2, b3) or at least the considered single wire data bus section (b1, b2, b3) into the first voltage range (V _B1 ) and overwrites the current sources.

Another variant of this method is characterized by the generation of a second of the three logic states on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3), in particular by a pull circuit (R _0H , R _0L ), if none of the other logic states _exist on the single wire _data bus (b1, b2, b3) or at least the single wire _{data bus portion} (b1, b2, b3) considered, in particular by the pull circuit (R _0H , R _0L ) _having the potential of the single-wire data bus (b1, b2, b3) or at least of the single-wire data bus section (b1, b2, b3) considered to be at a mean potential (V _M ) in the second voltage range (V _B2 ).

Another variant of this method is characterized by the transmission of a system clock by changing from the second or third logic state on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) on one side to a first logic state on the single wire data bus (b1, b2, b3) or at least the considered single wire data bus section (b1, b2, b3) on the other side and change in the reverse direction.

A further variant of this method is characterized by the transmission of data by changing from the second logic state on the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) on the one hand to a third logical state on the single wire data bus (b1, b2, b3) or at least the single wire data bus section (b1, b2, b3) on the other side under consideration and change in the reverse direction.

A further variant of this method is characterized in that a first or second datum or a control datum or other datum in a half-clock period of the at least two half-clock periods (T _1H , T _2H ) of a time slot of the at least three consecutive time slots (TIN0, TIN1, TDO ) and a system clock is transmitted in the other half-clock period of the at least two half-clock periods (T _1H , T _2H ) of this time slot of the at least three consecutive time slots (TIN0, TIN1, TDO), wherein a time slot packet having a length of one system clock period (T) has at least two half-clock periods (T _1H , T _2H ).

Another aspect of the invention relates to a method for operating a data bus between a first subdevice, the bus master (BM), and at least two further subdevices, the bus node (BS1, BS2, BS3), wherein the data bus has a reference potential line (GND) a reference potential (V ₀ ) and a single-wire data bus (b1, b2, b3) which is divided by the at least two bus nodes into at least two single-wire data bus sections (b1, b2, b3) and by at least one bus node (BS3) of the bus nodes (BS1, BS2 , BS3) completed by the terminating bus node (BS3). The method comprises, as a first step, the temporary connection of the single-wire data bus (b1, b2, b3) or at least one single-wire data bus section of the single-wire data bus sections (b1, b2, b3), referred to below as the considered single-wire data bus section (b1, b2, b3), with a first connectable one Voltage source (S _1L ) of the bus master (BM), which has a first internal resistance, with a first potential (V ₀ ). As a second step, it comprises temporarily connecting the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) to a second connectable voltage source (S _1H , I ₁ ) of the bus master (BM) a second internal resistance (V _IO1 ), the second switchable voltage source also having a current source (S _1H , I ₁ ) having a second internal resistance (R _1H ) and the current value (I ₁ = V _IO1 / R _1H ), can be. As a third step, the method comprises temporarily connecting the single-wire data bus (b1, b2, b3) or at least the considered single-wire data bus section (b1, b2, b3) to a third connectable voltage source (S _2H , I ₂ ) of a bus node (BS1, BS2, BS3 ), hereinafter referred to as bus accounts, with a third potential (V _IO2 ), which is preferably equal to the second potential (V _IO1 ) and wherein the third switchable voltage source (S _2H , I ₂ ) has a third internal resistance and wherein the third switchable Voltage source and a current source (S _2H , I ₂ ), which has a third internal resistance (R _2H ) and the current value (I ₂ = V _IO2 / R _2H ) may be. As a fourth step includes the method comprises temporarily holding the single wire data bus (b1, b2, b3) or at least the considered single wire data bus section (b1, b2, b3) by a fourth voltage source, in particular a pull circuit (R _0H , R _0L ) between a fourth potential (V _IO ), which is preferably equal to the second and third potentials (V _IO1 , V _IO2 ), and the first potential (V ₀ ), having a fourth internal resistance at a mean potential (V _M ). In this case, the value of the mean potential (V _M ) lies between the value of the first potential (V ₀ ) and the value of the second potential (V _IO1 ) and / or between the value of the first potential (V ₀ ) and the value of the third potential (V _IO2 ). The first internal resistance is smaller than the other internal resistances. The fourth internal resistance is greater than the other internal resistances.

The invention also includes a method for initializing such a single wire data bus as described herein between a first subdevice, the bus master (BM), and at least two further subdevices, the bus node (BS1, BS2, BS3). In this case, the data bus has a reference potential line (GND) with a reference potential (V ₀ ) and a single-wire data bus (b1, b2, b3), which is subdivided by the at least two bus nodes into at least two single-wire data bus sections (b1, b2, b3) and by at least one Bus node (BS3) of the bus node (BS1, BS2, BS3), the terminating bus node (BS3), completed on. The method according to the invention comprises as a first step the determination of a new bus node address by the bus master. This can be done, for example, by simply incrementing a bus master internal value. It follows as a second step, the laying of this bus node address in a bus node address register (BKADR) of a bus node (BS1, BS2, BS3), the relevant bus node, by the bus master (BM). In this case, the bus master (BM) and the relevant bus node are connected to one another in terms of data by one or more single-wire data bus sections (b1, b2, b3). Preferably, the bus node address register (BKADR) is realized as an independent data register (DR) in the bus node. However, it can also be realized as part of a data or instruction register (IR) of the inventive JTAG interface of the relevant bus node. The programming then becomes more complicated. As before, again a JATG interface in the sense of this disclosure is characterized by having a test controller (TAPC) with a state diagram according to the IEEE 1149 standard or one of its sub-standards as related to 1 explained, has. As a third step, following this bus node address assignment, the one or more single-wire data bus sections (b1, b2, b3) already connected to the respective bus node and bus-mater (BM) follows with one or more further single-wire data bus sections (b1, b2, b3) Close the transfer gate (TG) of the relevant bus node. In order to prevent overwriting of the previously assigned bus node address in the bus node address register (BKADR) of the respective bus node at the next bus node address assignment, a logic inside the bus node prevents such storage of a bus node address in the bus node address register (BKADR) of the relevant bus node (BS1, BS2, BS3) how the transfer gate (TG) of the relevant bus node is closed. Describing the bus node address register is therefore possible according to the invention only with the transfer gate open.

Another embodiment of the method comprises, as a further step, the deposition of a command for opening a transfer gate (TG) in the instruction register (IR) or a transfer gate control register (TGCR) of the JTAG interface of the bus node under consideration. This allows the bus master (BM) to reinitialize the bus at any time. Preferably, the transfer gate control register (TGCR) is used for this purpose and addressed with an identical instruction in the instruction register (IR).

A further embodiment of the method comprises, as a further step, checking the correct addressing of at least one bus node by cyclic writing and reading, in particular a bypass register.

A further embodiment of the method comprises, as a first further step, determining the number of correctly addressable bus nodes by the bus master (BM). It then follows the comparison of the number of correctly addressable bus node with a target number and triggering at least one signal or measure depending on the number by the bus master or a connected system.

A further embodiment of the method comprises, as a further step, the simultaneous transmission of a transmission address to all reachable bus nodes by describing transmission registers (SR) of all bus nodes by the bus master (BM) with this transmission address, wherein the respective transmission register (SR) of a respective bus node is a data register or is part of a data register or part of the instruction register (IR) of the JTAG interface of that bus node, and the bus address register (BKADR) is not part of the register in question. The second step is the comparison of the transmit address in the transmit register (SR) with the bus node address in the bus node address register (BKADR) by each bus node by means of a predetermined comparison algorithm. Preferably, it is checked for equality. Other algorithms are but thinkable. The third step is either the activation of the transmission capability for the respective bus node at the times provided when the comparison algorithm of the previously performed by this respective bus node sufficient match with the expected for the transmission permission combination of the stored in its bus node register (BKADR) bus node address and the transmit address stored in its transmit register (SR) gives or as an alternative third step the deactivation of the transmission capability for the respective bus node if the comparison algorithm of the comparison previously performed by that respective bus node does not sufficiently match the expected combination for the transmit permission in its Bus node register (BKADR) stored bus node address and in its transmit register (SR) stored transmission address results.

To ensure that only the bus node receives the data intended for it, it makes sense, if not only the transmission of the bus node is controlled, but also the receiving of the bus node. For this purpose, certain registers are completely or partially blocked for writing by the bus master until the send address in the transmit register (SR) matches the bus node address (BKADR). This blocking may involve the inhibition of the shift register part of one or more data registers (DR) or the data transfer from the shift register part of one or more data registers (DR) or the instruction register to the shadow register. If necessary, only single or multiple bits can be affected by a blocking of the data transfer. It is indeed necessary to always allow the transmission of certain commands, at least the writing of the transmitter register (SR). Therefore, the transmission of a command or data to a previously not addressed bus node begins as before with the simultaneous transmission of a send address to all available bus nodes by describing the send register (SR) of all bus nodes by the bus master (BM) with this send address. In this case, the respective transmit register (SR) of the relevant bus node is a data register or part of a data register or part of the instruction register (IR) of the JTAG interface of this bus node. As before, the bus address register (BKADR) must not be part of the relevant register. Again, the comparison of the transmit address in the transmit register (SR) with the bus node address in the bus node address register (BKADR) by each bus node by means of said predetermined compare algorithm. Finally, the activation of the receiving capability of the respective bus node for the content of predetermined data registers of the respective bus node follows if the comparison algorithm of the previously performed by this respective bus node sufficient match with the expected for the transmission permission combination of the stored in its bus node register (BKADR) bus node address and the transmission address stored in its sender register (SR). In the other case, the deactivation of the receiving capability of the respective bus node for the contents of predetermined data registers of the respective bus node follows, if the comparison algorithm of the previously performed by this respective bus node does not match sufficiently with the expected for the transmission permission combination of the stored in its bus node register (BKADR) Bus node address and stored in its transmit register (SR) transmission address results.

If the writing of parts of the instruction register (IR) or of parts of data registers is to be locked or unlocked, the corresponding method begins with the simultaneous transmission of a send address to all reachable bus nodes by writing the transmit registers (SR) of all bus nodes through the bus master (BM). with this send address, wherein the respective transmit register (SR) of a respective bus node is a data register or part of a data register or a part of the instruction register (IR) of the JTAG interface of that bus node, and wherein the bus address register (BKADR) is not part of the respective register , Again, the comparison of the transmit address in the transmit register (SR) with the bus node address in the bus node address register (BKADR) by each bus node by means of said predetermined compare algorithm. After the result of the comparison, the activation of the receiving capability of the respective bus node for contents of predetermined contents of the instruction register (IR) of the respective bus node for admission of predetermined instructions for an instruction decoder (IRDC) follows the JTAG interface of the respective bus node, if the comparison algorithm of the previously The comparison made with this particular bus node yields a sufficient match with the combination of the bus node address stored in its bus node register (BKADR) and the transmission address stored in its transmission register (SR) for the transmission permission. In the other case, the deactivation of the receiving capability of the respective bus node for contents of predetermined contents of the instruction register (IR) of the respective bus node to suppress predetermined instructions for an instruction decoder (IRDC) of the JTAG interface of the respective bus node, if the comparison algorithm of the previously by the respective Bus node executed comparison does not give sufficient agreement with the expected for the transmission permission combination of the stored in its bus node register (BKADR) bus node address and in its transmit register (SR) stored transmission address.

Description of the figures

1 shows the state diagram of a test controller according to the IEEE 1149 standard. The 1 was explained in the introduction.

2 shows the basic signal forms of the data protocol according to the invention on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3)

3 shows a realization proposal according to the invention in a schematic form.

4 shows exemplary level sequences for each one time slot packet of three consecutive time slots.

5 shows by way of example the extraction of the data in the relevant bus node for three consecutive time slots.

6 schematically shows an exemplary single wire data bus system

7 shows a detail from the exemplary single wire data bus system: The connection of two consecutive bus nodes.

8th schematically shows in simplified form an exemplary implementation of a bus master single wire data bus interface

9 schematically shows in simplified form an exemplary implementation of a bus node single-wire data bus interface

10 shows in simplified form a JTAG interface with illumination register (ILR) according to the invention.

11 2 shows, in simplified form, a lighting register (ILR) JTAG interface according to the invention and separate switchable serial data input for the lighting register

12 schematically shows an exemplary single wire data bus system with separate serial data bus for lighting data

13 shows in simplified form a JTAG interface according to the invention with illumination register (ILR) and transfer gate control register (TGCR)

Fig. 2

2 shows the basic waveforms of the data protocol according to the invention on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3). In the upper part of the 2 the waveforms for a two-wire test bus according to IEEE 1149 standard are schematically outlined as known from the prior art. The highest signal (TDA) shows the data signal. The second signal (TCK) shows the associated clock. Both signals are marked as state of the art and belong to the 2-wire JTAG standard. Among them is exemplified the digital coding. In this case, it is not yet shown whether the relevant bus node or the master is transmitting. Here only the waveform is sketched.

Underneath, the inventive waveform is sketched on the single wire data bus (b1, b2, b3) or a connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) combining the clock and the data.

• 1. Einen ersten Spannungspegel, der typischerweise gleich einer Versorgungsspannung (V_IO) ist. Dabei kann diese gleich der Versorgungsspannung (V_IO2) auf Busknoten-Seite oder der Versorgungsspannung (V_IO1) auf Bus-Masterseite sein. Im Folgenden meint V_IO eine dieser beiden Versorgungsspannungen oder eine Kombination der beiden oder eine andere, vergleichbare Versorgungsspannung mit gleicher Wirkung. Vorzugsweise sollten Bus-Master (BM) und Busknoten (BS1, bS2, BS3) die gleiche Versorgungsspannung als Referenz benutzen.
• 2. Einen zweiten, mittleren Spannungspegel (V_M).
• 3. Einen dritten Spannungspegel, der typischerweise gleich einem Bezugspotenzial (V₀) ist.

At the bottom, the different voltage levels are outlined. The signal has three voltage levels when transmitting:

• 1. A first voltage level, which is typically equal to a supply voltage (V _IO ). This can be equal to the supply voltage (V _IO2 ) on the bus node side or the supply voltage (V _IO1 ) on the bus master side. In the following, V _{IO means} one of these two supply voltages or a combination of the two or another comparable supply voltage having the same effect. Preferably, bus master (BM) and bus node (BS1, bS2, BS3) should use the same supply voltage as a reference.
• 2. A second, medium voltage level (V _M ).
• 3. A third voltage level, which is typically equal to a reference potential (V ₀ ).

For the extraction of the system clock, a second threshold voltage (V _2L ) is defined, which lies between the reference potential (V ₀ ) and the mean potential (V _M ).

For the extraction of the data, a third threshold voltage (V _1H ) of the bus master (BM) and a first threshold voltage (V _2H ) of the bus nodes (BS1, BS2, BS3) are defined, which between the supply voltage (V _IO ) and the middle Potential (V _M ) and should be about the same.

The second threshold voltages (V _2L ) of the bus nodes (BS1, BS2, BS3) and the reference potential (V ₀ ) define and limit a first voltage range (V _B1 ).

By the first threshold voltage (V _2H ) of the bus node (BS1, BS2, BS3) or the third threshold voltage (V _1H ) of the bus master (BM) on the one hand and the second threshold voltage (V _2L ) of the bus node (BS1, BS2, BS3), a second voltage range (V _B2 ) is defined and limited.

By the first threshold voltage (V _2H ) of the bus node (BS1, BS2, BS3) and the third threshold voltage (V _1H ) of the bus master (BM) on the one hand and the supply voltage, a third voltage range (V _B3 ) is defined and limited.

In terms of time, the signal on the single-wire data bus (b1, b2, b3) or a connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) is divided into time slot packets with at least three time slots (TIN0, TIN1, TDO). The timeslot packets typically follow one another with a system clock period (T). The order of the time slots within a time slot packet can be chosen to be arbitrary for a system, but preferably the same for all time slot packets. Each system clock period (T) is divided into at least two half-clock periods (T _1H , T _2H ), the length of which is preferably but not necessarily the same.

In a half-clock period of the at least two half-clock periods (T _1H , T _2H ), the system clock is transmitted.

Here, the level is on the single wire data bus (b1, b2, b3) or the connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3) in a half clock period of the at least two half clock periods (T _1H , T _2H ) in FIG first voltage range (V _B1 ). As a result, a first logical value of the system clock is transmitted. In the example, it suffices that the level on the single wire data bus (b1, b2, b3) or the connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) is below the second threshold (V _2L ) , A limitation down through the reference potential (V ₀ ) is for deciding whether the level on the single wire data bus (b1, b2, b3) or the connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3) in the first voltage range (V _B1 ) is not relevant and is therefore not used in practice. Therefore, the first voltage range (V _B1 ) can also be regarded as open at the bottom in many applications.

In the other half-clock period of the at least two half-clock periods (T _1H , T _2H ), the level is on the single wire data bus (b1, b2, b3) or the connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) in the second voltage range (V _B2 ) or third voltage range (V _B3 ). As a result, a second logical value of the system clock is transmitted, which is different from the first logical value of the system clock. In the example, it is sufficient that the level on the single wire data bus (b1, b2, b3) or the connected single wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) is above the second threshold (V _2L ) , An upper limit of the supply voltage (V _IO ) is for deciding whether the level on the single wire data bus (b1, b2, b3) or the connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3) is up in the second voltage range (V _B2 ) or third voltage range (V _B3 ) is not relevant and is therefore not used in practice. Therefore, in many applications, the third voltage range (V _B3 ) can also be considered to be open at the top.

Since it is not relevant for the extraction of the system clock within this other half-clock period of the at least two half-clock periods (T _1H , T _2H ), whether the level on the single-wire data bus (b1, b2, b3) or the connected single-wire data bus section (b1, b2, b3) of the single wire data bus (b1, b2, b3) is in the third voltage range (V _B3 ) or second voltage range (V _B2 ) can now be distinguished by a distinction between the third voltage range (V _B3 ) and the second voltage range (V _B2 ) within the other Half-clock period of at least two half-clock periods (T _1H , T _2H ) data are transmitted.

In this other half-clock period of the at least two half-clock periods (T _1H , T _2H ), the level is on the single wire data bus (b1, b2, b3) or the connected single wire data bus portion (b1, b2, b3) of the single wire data bus (b1, b2, b3) in FIG second voltage range (V _B2 ) when a first logical data value is transmitted. and in the third voltage range (V _B3 ) when a second logical data value is transmitted.

To the right of the lower signal, exemplary logical states for the three levels are shown for better clarity.

The upper level in the example corresponds to an exemplary logic value of the system clock (TCK) of FIG. 1 and an exemplary logical value of the data signal (TDA) of FIG.

The average level in the example corresponds to an exemplary logic value of the system clock (TCK) of FIG. 1 and an exemplary logical value of the data signal (TDA) of zero.

The lower level in the example corresponds to an exemplary logical value of the system clock (TCK) of zero.

Fig. 3

In 3 are the most important parts of the interface according to the invention for implementing the protocol according to the invention on the single-wire data bus (b1, b2, b3) or the here exemplarily connected first single-wire data bus section (b1) of the single-wire data bus (b1, b2, b3) between the bus master and the relevant bus node shown. As a reference potential for the signals on the single-wire data bus (b1, b2, b3) and the connected first single-wire data bus section (b1) of the single-wire data bus (b1, b2, b3), the ground with the reference potential line (GND) serving as the reference potential (V ₀ ) is located. By the voltage divider consisting of a lower resistance (R _0L ) between on the single wire _data bus (b1, b2, b3) and thus the connected first single wire data bus section (b1) of the single wire data bus (b1, b2, b3) and reference potential (GND) and an upper resistance ( R _0H ) between the single-wire data bus (b1, b2, b3) and thus the connected first single-wire data bus section (b1) of the single-wire data bus (b1, b2, b3) and one supply potential (V _IO ) different from the reference potential (V ₀ ), the single-wire data bus (b1 , b2, b3) in the form of the connected first single-wire data bus section (b1) are initially kept at a mean potential (V _M ) between these two potentials (V ₀ , V _IO ). On the master side, the dominating switch (S _1L ) which is connected between the single-wire data bus (b1, b2, b3) is now always closed in a half-clock period of the at least two half-clock periods (T _1H , T _2H ) of a system clock period (T) of the system clock (TCKout ₁ ) ) in the form of the connected first single-wire data bus section (b1) and the reference potential line (GND). Since the internal resistance of the dominant switch (S _1L ) is preferably smaller than the internal resistance of the voltage component of the upper resistor (R _0H ) and the lower resistor (R _0L ), the at least two half-clock periods (T _1H , T _2H ) of a system clock period (T) by closing the dominant switch (S _1L ) of the voltage levels on the single wire data bus (b1, b2, b3) from said mean potential (V _M ) in a second voltage range (V _B2 ) to the potential of Reference potential (V ₀ ), which is located in the first voltage range (V _B1 ) pulled. The dominant switch (S _1L ) is controlled by the system clock on the master side (TCKout ₁ ). If this dominant switch (S _1L ) is not closed, data can be transmitted bidirectionally in the other half-clock period of the at least two half-clock periods (T _1H , T _2H ) of a system clock period (T). For this purpose, on the bus master side, a switched current source (S _1H , I ₁ ) supplies current to the single-wire data bus (b1, b2, b3) when the transmission line (TDAout ₁ ) from the inside of the bus master (BM) is active is. For this purpose, the transmission line (TDAout ₁ ) from the interior of the bus master (BM) closes the switch (S _1H ) of the controllable current source (S _1H , I ₁ ). As a result, the current source (I ₁ ) of the controllable current source (S _1H , I ₁ ) supplies current to the single-wire data bus (b1, b2, b3). Preferably, this current is greater than the current that the pull circuit consisting of the upper resistor (R _OH ) and the lower resistor (R _0L ) can dissipate. Thus, the potential of the single wire data bus (b1, b2, b3) or at least the connected first single wire data bus portion (b1) of the single wire data bus (b1, b2, b3) in this case increases from the mean potential (V _M ) in a second voltage range (V _B2 ) a potential near the supply voltage (V _IO1 ) for the switchable current source (S _1H , I ₁ ) of the bus master (BM) in the third Voltage range (V _B3 ). However, if the dominant switch (S _1L ) is closed, this overwrites the influence of the switchable current source (S _1H , I ₁ ) of the bus master (BM) and the pull circuit consisting of the upper resistance (R _0H ) and the lower Resistance (R _0L ). Both are with a suitable design of the dominant switch (S _1L ) unable to the potential on the single wire data bus (b1, b2, b3) or at least the exemplary connected first single wire data bus section (b1) of the single wire data bus (b1, b2, b3) against the dominant switch (S _1L ) to determine.

In the same way, the second switchable current source operates on the bus node side. On the bus node side, a switched current source (S _2H , I ₂ ) feeds current into the single-wire data bus (b1, b2, b3) or the connected single-wire data bus section (b1, b2, b3) of the single-wire data bus (b1, b2, b3) if the transmission line (TDAout ₂ ) from inside the bus node is active. For this purpose, the transmission line (TDAout ₂ ) from the interior of the bus node closes the switch (S _2H ) of the controllable current source (S _2H , I ₂ ). As a result, the current source (I ₂ ) of the controllable current source (S _2H , I ₂ ) supplies current to the single-wire data bus (b1, b2, b3) or the connected first single-wire data bus section (b1) of the single-wire data bus (b1, b2, b3). Preferably, this current is again greater than the current that can pull the pull circuit consisting of the upper resistance (R _0H ) and the lower resistance (R _0L ). Thus, the potential of the single wire data bus (b1, b2, b3) or the connected single wire data bus section (b1) in this case moves from the middle potential (V _M ) in a second voltage range (V _B2 ) to a potential near the supply voltage (V _IO2 ) the switchable current source (S _2H , I ₂ ) of the bus node (BS1, BS2, BS3) in the third voltage range (V _B3 ). However, if the dominant switch (S _1L ) is closed, this again overwrites the influence of the switchable current source (S _2H , I ₂ ) of the bus node and the pull circuit consisting of the upper resistance (R _0H ) and the lower resistance ( R _0L ). Both are suitable design of the dominant switch (S _1L ), the potential on the single wire data bus (b1, b2, b3) or the connected first single wire data bus section (b1) of the single wire data bus (b1, b2, b3) against the dominant switch (S _1L ). Even if the switchable current source (S _1H , I ₁ ) of the bus master (BM) is also connected, with a suitable design of the dominant switch (S _1L ) this is the potential on the single-wire data bus (b1, b2, b3) or connected first one-wire data bus section (b1) of the single-wire data bus (b1, b2, b3).

At the bus node side, a first comparator (C _2H ) compares the potential on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1, b2, b3) to a first threshold value (V _2H ). , At the same time, a second comparator (C _2L ) compares the potential on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1, b2, b3) to a second threshold value (V _2L ). The second threshold (V _2L ) differs from the first threshold (V _2H ) and determines the boundary between the first voltage range (V _B1 ) and the second voltage range (V _B2 ). The first threshold (V _2H ) determines the boundary between the second voltage range (V _B2 ) and the third voltage range (V _B3 ). The second comparator (C _2L ) recovers the system clock from the signal on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1, b2, b3). This signal is forwarded to the inside of the bus node as a clock signal received by the bus node (TCKin ₂ ). The first comparator (C _2H ) extracts the data information from the signal on the single-wire data bus (b1, b2, b3) or the connected first single-wire data bus portion (b1) of the single-wire data bus (b1, b2, b3) as data received by the bus node (TDAin ₂ ) back. The data received by the bus node also contain portions of the system clock. This can be easily remedied by simply sampling, for example, in a flip-flop with the edge of a slightly delayed system clock, or alternatively by delaying the received data and sampling with a non-delayed system clock. Possibly. the signals must still be processed before use (D _2H , D _2L ).

In one embodiment of the invention, the data output signal (TDAin2) could be switched to 1 by the first comparator (C _2H ) if the potential on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1, b2, b3) is higher than the first threshold (V _2H ) and conversely switched to 0 if the potential is lower than this threshold. In one embodiment of the invention, the system clock signal (TCKin ₂ ) could be switched to 1 by the second comparator (C _2L ) if the potential on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1 , b2, b3) is higher than the second threshold (V _2L ), and conversely switched to 0 if the potential is lower than this threshold.

Similarly, the bus master (BM), by means of a third comparator (C _1H ), samples the state on the single-wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the Single wire data bus (b1, b2, b3). For this purpose, the third comparator (C _1H ) compares the potential on the single-wire data bus (b1, b2, b3) or the connected first single-wire data bus section (b1) of the single-wire data bus (b1, b2, b3) with a third threshold value (V _1H ) and thereby obtains the Data located on the data line back, but still have shares of the system clock here. Again, a suitable scan helps. In this way, the data received by the bus master (BM) (TDAin ₁ ) is obtained. In one embodiment of the invention, the data output signal (TDAin ₁ ) could be switched to 1 by the third comparator (C _1H ) if the potential on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1 , b2, b3) is higher than the third threshold (V _1H ), and conversely switched to 0 when the potential is lower than this threshold. The third threshold value (V _1H ) is preferably equal to the first threshold value (V _2H ) except for a small tolerance range of preferably significantly less than 25% of this value.

In the further processing circuits of the prior art can now be used for a data bus with a separate data line and system clock line, so that the description can be omitted here. Exemplary is on the WO 2006/102284 A2 directed.

The following table of voltage levels and logic values will now be given as one possible implementation of the invention. Other levels and corresponding logical values are of course possible, as will be apparent to those skilled in the art. Note that in this example TCKout ₁ = 0 closes the dominant switch (S _1L ). Of course, this can also be implemented inverted. Send considered single wire data line / timing section Receive TCKout ₁ TDAout ₁ TDAout ₂ b1, b2, b3, b _n TCKin ₂ TDAin ₁ TDAin ₂ 0 0 0 V ₀ 0 0 0 0 0 1 V ₀ 0 0 0 0 1 0 V ₀ 0 0 0 0 1 1 V ₀ 0 0 0 1 0 0 V _M 1 0 0 1 0 1 V _IO2 1 1 1 1 1 0 V _IO1 1 1 1 1 1 1 V _{IO1 / 2} 1 1 1

Preferably, the first threshold (V _2H ) and the third threshold (V _1H ) match, whereby bus master and bus node recognize the same data sequence. By appropriately controlled temporal sampling, these data can then be appropriately assigned to the time slots (TIN0, TIN1, TDO).

In contrast to the German patents DE 10 2015 004 434 B3 . DE 10 2015 004 433 B3 . DE 10 2015 004 435 B3 and DE 10 2015 004 436 B3 The bus node according to the invention typically has a transfer gate (TG) which has the function of a switch and can connect the first single-wire data bus section (b1) to a subsequent second single-wire data bus section (b2). If the transfer gate (TG) is open, preferably a second switch (S _3L ) connects the subsequent second single-wire data bus section (b2) to the reference potential (GND) or another suitable potential. As a result, the following single-wire data bus (b2, b3) is at a defined potential without a system clock and thus data being transmitted.

Fig. 4

4 shows an exemplary protocol sequence of three consecutive time slots (TIN0, TIN1, TDO). In other implementations of the invention, a timeslot packet may also include more than three time slots (TIN0, TIN1, TDO). The first time slot (TIN0) typically transmits control data corresponding to the standard boundary-scan TMS signal (IEEE 1149).

This signal typically controls the state of the finite state machine in accordance with the state diagram 1 , In the second time slot (TIN1) typically the data is transmitted which corresponds to the TDI signal of the Standard Boundary Scans (IEEE 1149). In these two time slots, the bus master (BM) transfers data to the bus node. If the bus node also sends in parallel, the bus node overwrites the bus master (BM) if its switchable current source (S _1H , I ₁ ) is switched off. Conversely, the bus master (BM) can overwrite the bus node if the switchable current source (S _2H , I ₂ ) of the bus node is switched off. Overwriting of the bus master (BM) by the bus node can be detected by the bus master (BM) by checking the transmitted data (TDAout ₁ ) for logical content thereon by logic in the bus master (BM) whether they match the received data (TDAin ₁ ) in the respective half-clock period in which the system clock (TCKout ₁ ) does not close the dominant switch (S _1L ). In the case of such asynchronicity, the bus master can maintain the voltage level on the single wire data bus (b1, b2, b3) or the connected first single wire data bus portion (b1) of the single wire data bus (b1, b2, b3) in the third voltage range (V _B3 ) appropriate design of the state machine of the test controller (TAPC) of the bus node to re-synchronize these again. For this purpose, the state machine of the test controller (TAPC) of the bus node must be designed so that a permanent hold in the third voltage range (V _B3 ) in the control field, ie here for example in the first time slot (TIN0), to a reset in the form of revenue a so-called "Idle States" (TLR) as a waiting state of the test controller (TAPC) leads. This is the case with a state diagram of a JTAG controller according to IEEE 1149 standard. This permanent maintenance of the voltage level on the single-wire data bus (b1, b2, b3) or the connected first single-wire data bus section (b1) of the single-wire data bus (b1, b2, b3) in the third voltage range (V _B3 ) can be achieved by permanently switching on the switchable current source (S _1H , I ₁ ) of the bus master (BM) for the duration of the reset process.

Fig. 5

5 shows an exemplary sequence of signals according to the invention. Input is the two wire based data called "2 wire data". In the example, three consecutive timeslot packets (n-1, n, n + 1) are shown with, for example, three time slots each (TIN0, TIN1, TDO). The use of more than three time slots per time slot packets is of course conceivable. The meaning of the respective time slots within a timeslot packet depends only on the time position and does not change. When in this description the first time slot (TIN0), second time slot (TIN1) and third time slot (TDO) are mentioned, this is a pure name and does not refer to the position within a time slot packet. Preferably, the time positioning of the individual at least three time slots (TIN0, TIN1, TDO) within the time slot packets is always the same or at least predictable by an algorithm. Also, the figure shows the associated system clock (2 wire clock). In the time slot packet n - 1 of the bus node provides in the time slot TDO _n-1 is a logical 1 and in the time slot pacts a logical 1 and n in the time slot packets n + 1 in the time slot TDO _n in time slot TDO _{n +1} a logic 0. The (from the bus master BM) data in the time slots TIN0 _n-1 , TIN1 _n-1 , TIN0 _n , TIN1 _n , TIN0 _{n + 1} , TIN1 _{n + 1} are not exemplary in their logical content and therefore hatched. The signal denoted by "TOW" should be the potential curve on the single-wire data bus (b1, b2, b3 ... b _n , ... b _m ) or a connected n-th single-wire data bus section (b _n ) of the single-wire data bus (b1, b2, b3 ... b _n , ... b _m ) illustrate schematically. From this potential curve on the affected single-wire data bus section (b _n ), the first comparator (C _2H ) generates by way of example the data (TDAin ₂ ) received by the bus node concerned. By way of example, the second comparator (C _2L ) uses the potential curve on the affected single-wire data bus section (b _n ) to generate the clock signal (TCKin ₂ ) received by the bus node, which corresponds to the reconstructed system clock. With appropriate bus node and bus master synchronization, the affected bus node will generate an internal system clock (TCK) which will not show a half-cycle period pulse until the second half-clock period of the third time slot (TDO _n ) of the system clock period (T). With the rising edge of this signal the bus node takes over the logical values of the data sent by the bus master in this example (TDAin ₂ by means of the falling edge of TCKin ₂ read). With the falling edge of the system clock (TCK) at the beginning of the next time slot packet, the value (TDO) to be sent by the bus node in this example is changed. TDAout ₂ , however, becomes active only in the third time slot (TDO _{n + 1} ) of the following time slot packet, if the affected bus node is allowed to transmit. It is clear to the person skilled in the art that the control is not limited only by means of the in 5 represented control over the falling edge of the system clock (TCK) is possible, but also on the rising edge.

Fig. 6

6 shows an exemplary single-wire data bus (b1, b2, b3) with three bus nodes (BS1, BS2, BS3) and three single-wire data bus sections (b1, b2, b3) and a bus master (BM). The first single wire data bus section (b1) connects the bus master (BM) to the first bus node (BS1).

The second single-wire data bus section (b2) connects the second bus node (BS2) to the first bus node (BS1). The third single-wire data bus section (b3) connects the third bus node (BS3) to the second bus node (BS2).

The single wire data bus is controlled by a bus master (BM) by means of a master single wire data bus interface (OWM) to which the first single wire data bus section (b1) is connected.

The first single wire data bus interface (OWS1) is connected to the first single wire data bus section (b1). It receives data from the bus master via this first single-wire data bus section (b1) and sends it to it. Internally, it provides a first reconstructed system clock (TCK1), with which the internal JTAG interface of the first bus node is operated. It also provides the first combined TMS TDI signal (TMS_TDI1), which in this example is time division multiplexed, the test mode signal (TMS) and the data input signal (TDI). The test mode signal (TMS) controls the finite state machine of the test controller (TAPC) of the JTAG interface of the first bus node. The data of the TDI signal component is used to load the shift registers of the JTAG interface of the first bus node. Conversely, the JTAG interface with the serial TDO output signal returns data from the registers of the JTAG interface of the first bus node. By a first transfer gate (TG1), the first single wire data bus section (b1) can be connected to the subsequent second single wire data bus section (b2). For this purpose, the bus master describes a transfer gate control register (TGCR) not shown here via the JTAG bus and sets a flag which sets or clears the first enable line (en1). In response to this first enable line (en1), the first transfer gate (TG1) of the first bus node is opened and closed. Thus, by means of a command from the bus master (BM), the single-wire data bus (b1, b2, b3) can be extended and shortened.

The second single wire data bus interface (OWS2) is connected to the second single wire data bus section (b2). It receives data from the bus master (BM) via this first single-wire data bus section (b2) when the first bus node (BS1) has closed its transfer gate (TG1). The second single wire data bus interface (OWS2) also sends such data to the bus master (BM). Internally, it provides a second reconstructed system clock (TCK2), with which the internal JTAG interface of the second bus node (BS2) is operated. It also provides the second combined TMS TDI signal (TMS_TDI2), which in this example is time division multiplexed, the test mode signal (TMS) and the data input signal (TDI). The test mode signal (TMS) controls the finite state machine of the test controller (TAPC) of the JTAG interface of the second bus node (BS2). The data of the TDI signal component is used to load the shift registers of the JTAG interface of the second bus node. Conversely, the JTAG interface of the second bus node with the serial TDO output signal returns data from the registers of the JTAG interface of the second bus node. Through a second transfer gate (TG2), the second single wire data bus section (b2) can be connected to the third single wire data bus section (b3). For this purpose, the bus master describes a transfer gate control register (TGCR) not shown here via the JTAG bus and sets a flag which sets or clears the second enable line (en2). In response to this second enable line (en2), the second transfer gate (TG2) of the second bus node is opened and closed. Thus, by means of a command from the bus master (BM), the single-wire data bus (b1, b2, b3) can be further extended and shortened.

The third single-wire data bus interface (OWS3) is connected to the third single-wire data bus section (b3). It receives data from the bus master (BM) via this third single-wire data bus section (b3) when the first bus node (BS1) has closed its transfer gate (TG1) and when the second bus node (BS2) also receives its second transfer gate (TG2 ) has closed. The third single wire data bus interface (OWS3) also sends such data to the bus master (BM). Internally, it provides a third reconstructed system clock (TCK3), which operates the internal JTAG interface of the third bus node (BS2). It also provides the third combined TMS TDI signal (TMS_TDI3), which in this example is time division multiplexed the test mode signal (TMS) and the data input signal (TDI) for the JTAG interface of the third bus node (BS3) , The test mode signal (TMS) controls the finite state machine of the test controller (TAPC) of the JTAG interface of the third bus node (BS3). The data of the TDI signal portion is used to load the shift registers of the JTAG interface of the third bus node (BS3). Conversely, the JTAG interface of the third bus node (BS3) with the serial TDO output signal returns data from the registers of the JTAG interface of the third bus node (BS3). Through a third transfer gate (TG3), the third single-wire data bus section (b3) can connect to further single-wire data bus sections (b _n ). Here, however, the third bus node should terminate the single-wire data bus (b1, b2, b3) by way of example.

Each of the bus nodes is connected to groups of lighting means (LM1, LM2, LM3) which are controlled by the respective bus node (BS1, BS2, BS3). Other consumers of electrical energy are of course conceivable.

Fig. 7

7 corresponds to the juxtaposition of two bus node data bus interfaces in the form of two right halves of 3 , A leading n-th single-wire data bus section (b _n ) is connected to an n-th bus node (BS _n ). This nth bus node (BS _n ) can connect this previous n th single wire data bus section (b _n ) to the n + 1 th single wire data bus section (b _{(n + 1)} ) by means of its transfer gate (TG). If the transfer gate of the n-th bus node (BS _n ) is open, a third switch (S _3L ) sets the potential of the n + 1 th single-wire data bus section (b _{(n + 1)} ) and thus all subsequent single-wire data bus sections (b _{( n + 2)} ) to a defined potential (GND), thus preventing accidental data transmission.

The n + 1-th bus node (BS _{(n + 1)} ) can, by means of its transfer gate (TG), restore this preceding n + 1-th single-wire data bus section (b _{(n + 1)} ) with the n + 2-th single-wire data bus section (b _{( n + 2)} ). If the transfer gate of the n + 1-th bus node (BS _{(n + 1)} ) is opened, a third switch (S _3L ) again sets the potential of the n + 2-th single-wire data bus section (b _{(n + 2)} ) and thus all subsequent single-wire data bus sections (b _{(n + 3)} ), if present, to a defined potential (GND) and thus prevents accidental data transmission.

Fig. 8

8th shows an implementation proposal for a master single-wire data bus interface (OWM) with, for example, reversed voltage sign over the implementation proposal shown in the previous figures. A voltage regulator (PS) generates a reference voltage ( _VREF ) from an external supply voltage (V ext1). The only once necessary lower resistance (R _0L ) and the upper resistance (R _0H ) of the voltage divider _pair , which exemplifies the pull circuit, are formed by the first resistor (R1) and the second resistor (R2). The pull circuit keeps the single wire data bus (b1, b2, b3) in the second voltage range (V _B2 ) at a medium potential (V _M ), if none of the other transmitters (S _1L , S _1H , I ₁ , S _2H , I ₂ ) is active. Here, by way of example, the first single-wire data bus section (b1) is connected to the output of the master single-wire data bus interface (OWM). The switch (S _1H ) of the controllable current source (S _1H , I ₁ ) for the transmitter of the bus master is formed by the second transistor (T2). The dominant switch (S _1L ) is formed by the first transistor (T1). The second transistor (T2) is an N-channel transistor in this example. The first transistor (T1) is a P-channel transistor in this example. Via an exemplary inverting buffer circuit (buf), the first transistor (T1) is driven with the system clock (TCK). A NOR gate (NOR) is used to drive the second transistor (T2) with the combined TMS-TDI signal (TMS_TDI) when the system clock signal (TCK) is inactive. The voltage divider (R3) generates a reference voltage with which the comparator (cmp) compares the voltage level on the connected first single wire data bus section (b1) and generates the data signal (TDO) for further processing within the bus master (BM).

Fig. 9

9 FIG. 12 shows an exemplary implementation of the nth single wire data bus interface (OWS _n ) of an nth bus node (BS _n ) of the bus nodes (BS1, BS2, BS3) with, for example, reversed voltage signs corresponding to the master single wire data bus interface (OWM) 8th , The single-wire data bus interface (OWS _n ) of the n-th bus node (BS _n ) is connected to the n-th single-wire data bus section (b _n ) by way of example. The switch of the controllable current source (S _2H , I ₂ ) for the transmitter of the bus node is formed by the third transistor (T3). Its internal resistance is determined by the serially connected seventh resistor (R7). By the voltage divider of the fourth resistor (R4), the fifth resistor (R5) and the sixth resistor (R6), two reference voltages are generated from the supply voltage (V _bat ) of the bus node. With these two reference voltages, a second comparator (cmp2) and a third comparator (cmp3) compare the potential on the exemplarily connected n-th single-wire data bus section (b _n ). From this, they generate the reconstructed system clock (TCK _n ) of the n-th bus node (BS _n ) and the n-th combined TMS-TDI signal (TMS_TDI _n ) within the n-th bus node (BS _n ) for triggering the test Controller (TAPC) of the JTAG interface within the nth bus node (BS _n ). In this case, clock and data are synchronized again by a delay unit (Δt) for the combined TMS-TDI signal (TMS_TDI _n ). The output signal of the JTAG interface of the nth bus node (BS _n ) is used in this example to connect the third transistor (T3) via an inverting second buffer circuit (buf2). head for. It will be easy for those skilled in the art to ensure the temporal structure of the signals by suitable logic.

Fig. 10

10 shows the internal structure of a JTAG interface according to the invention. This is compatible with the IEEE 1149 standard architecture, so the software available on the market can be used, which is a significant advantage.

In this example, the combined TMS TDI signal (TMS_TDI _n ) is decomposed in a test data preparation (TB) in synchronism with the system clock (TCK) into the test mode signal (TMS) and the serial input data (TDI). With the test mode signal (TMS) is again the test controller (TAPC) synchronous to the clock according to the already known from the prior art and in the description of 1 controlled state diagram controlled. This state diagram of a test controller (TAPC) in the sense of this disclosure identifies a JTAG interface, since compliance with this state diagram first establishes software compatibility. By the control signal (sir_sdr) for the first multiplexer (MUX1), the test controller switches between the instruction register (IR) and the data registers (BR, IDCR, RX, ILR) by means of the first multiplexer (MUX1). The serial data input (TDI) is routed to all data registers (BR, IDCR, RX, ILR), the instruction register (IR) and possibly further data registers. All these registers are typically executed in two stages. This means that they have a shift register of a bit length m and, in parallel, a shadow register of the same length m. The shift register is used for data transport, while the shadow register contains the valid data. As described above, depending on the state of the test controller (TAPC), the data is loaded into the shadow register from the shift register or loaded or shifted or suspended from the shadow register into the shift register. In the example of 10 An instruction decoder (IRDC) controls the JTAG interface depending on the contents of the instruction register (IR). For example, it is conceivable that the relevant bus node may only transmit if the shadow register of the instruction register (IR) contains specific values at certain bit positions, that is to say a specific transmission address. However, such addressing can also be carried out in a separate transmitting register (SR).

The JTAG interface particularly preferably has a bus node address register (BKADR). This indicates the identification number of the bus node. Furthermore, the JTAG interface preferably has a transmit register (SR). This transmit register (SR) is set by the bus master (BM) and indicates the number of the bus node which is to / can send. Only if both addresses, the address in the bus node address register (BKADR) and the address in the transmit register (SR) match, the relevant bus node (BS _n ) may send at the predetermined time. In order to set the bus node addresses in the bus node address registers (BKADR) of the bus nodes during the initialization of the single-wire data bus system, all transfer gates (TG) of all bus nodes are initially open. This can preferably be done by a special command to all available instruction registers (IR) of all JTAG interfaces and accessible bus nodes connected to the single-wire data bus (b1, b2, b3) according to the invention. For this, the instruction registers (IR) of these JTAG interfaces must match in the least significant bits, which are the shift register bits described first. The bus master (BM) then assigns the first bus address to the first and only bus node (BS1) directly connected to it by describing the first bus node address register (BKADR) of the first bus node (BS1) according to a specified algorithm. The bus master (BM) then typically, but not necessarily, tests the connection. Preferably, the bus node address register (BKADR) of the relevant bus node can only be described if the transfer gate (TG) of the relevant bus node is not closed. This ensures that only the last bus node, ie the first bus node in the sequence of bus nodes from the bus master, which has not closed its transfer gate (TG), accepts a bus node address in its bus node address register (BKADR). After such an acquisition, the transfer gate (TG) is typically closed automatically or by software command of the bus master. This will freeze the bus node address stored in the bus address register. At the same time, the addressing of the subsequent bus node can now take place. In order to allow an orderly reset of the bus system, for example, a common command for all bus node in the instruction register (IR) is provided, which opens all transfer gates of all bus nodes, so that a reassignment of addresses can be done. If, after an address assignment, the bus node does not respond with this bus node address, the bus node is either defective or does not exist. In the latter case, the bus master then knows the position of all bus nodes and their number.

The exemplary JTAG interface of 10 includes a standard bypass register (BR) that bypasses data through the JTAG interface. In addition, it includes in this Example an identification register (IDCR) for reading out a serial number of the circuit and further data registers (RX), which correspond to the JTAG standard. These may be, for example, test registers and other registers.

According to the invention, a lighting register (ILR) is now provided. In the illumination register (ILR), the bus master (BM) stores data for setting the power supplies for the lamps (LM). Typically, the power supplies are one or more (here three) Pulse Width Modulation (PWM) drivers (PWM1, PWM2, PWM3) having a pulse width (PWM) modulated output voltage or a correspondingly modulated one Generate electricity.

Fig. 11

11 show the 10 with the difference that the JTAG interface additionally has an illumination instruction register (ILIR). This controls a third multiplexer (MUX3). This can toggle the serial input data for the lighting register (ILR) between a serial input for lighting data (SILDI _n ) and the serial data input (TDI) by means of a lighting data selection signal (ilds). At the same time, the output of the lighting register (ILR) is copied to the serial output for lighting data (SILDO _n ).

Fig. 12

12 shows the possible direct connection of multiple circuits with JTAG controllers accordingly 11 via a chaining by means of the inputs for illumination data (SILDI1, SILDI2, SILDI3) and corresponding outputs for illumination data (SILDO1, SILDO2, SILDO3).

This makes it possible to quickly transfer data for entire groups of lamps without complicated addressing, since only one block must be addressed.

Fig. 13

13 shows a JTAG interface as in 10 with the difference that it has a separate Transfer Gate Control Register (TGCR). Instead of placing the flag for opening and closing the transfer gate (TG) in the instruction register (IR), a separate transfer gate control register (TGCR) can be provided, which can provide the corresponding enable line (en _n ). of the corresponding bus node (BS _n ) generated.

LIST OF REFERENCE NUMBERS

b1

first single wire data bus section

b2

second single wire data bus section

b3

third single wire data bus section

b _n

nth single wire data bus section

BKADR

Busknotenadressregister

BM

Bus master

BR

Bypass Register

BS1

exemplary first bus node

BS2

exemplary second bus node

BS3

exemplary third bus node

BS _n

Exemplary Nth Bus Node (The relevant bus node is designated BS _n at various points in this disclosure)

buf

Buffer circuit.

buf2

second buffer circuit.

bus node

Bus node circuit. The bus node is typically the integrated circuit or other electrical system controlled by the host processor, bus master, via the single wire data bus (b1, b2, b3) or at least one connected single wire data bus section (b1, b2, b3) ,

Bus master

Master circuit. The bus master is typically the host processor over which the integrated circuit, the bus node, is controlled.

C _2H

first comparator on bus node side. The first comparator compares the voltage level on the single wire data bus (b1, b2, b3) or on the connected one A single wire data bus section (b1, b2, b3) having a first threshold (V _2H ) and, via a first conditioning (D _2H ), forwards the data signal received by the bus node to the interior of the circuit of the bus node, typically the integrated circuit or the one under test or to be tested controlling system. The first comparator detects the change of the voltage level on the single wire data bus (b1, b2, b3) or on the connected single wire data bus section (b1, b2, b3) from the third voltage range (V _B3 ) on the one side to the first voltage range (V _B1 ) or second voltage range (V _B2 ) on the other side and vice versa.

C _2L

second comparator on bus node side. The second comparator compares the voltage level on the single-wire data bus (b1, b2, b3) and on the connected single-wire data bus section (b1, b2, b3) with a second threshold value (V _2L ) and outputs the _signal through the second processing unit (D _2L ) Bus node received clock signal to the inside of the circuit of the bus node, typically the integrated circuit or the system to be tested or controlled on. The second comparator detects the change of the voltage level on the Eindrahtdatenbus (b1, b2, b3) and on the connected Eindrahtdatenbusabschnitt (b1, b2, b3) of the first voltage range (V _B1) on one side in the third voltage range (V _B3) or second voltage range (V _B2 ) on the other side and vice versa.

C _1H

third comparator on master side. The third comparator compares the voltage level on the single wire data bus (b1, b2, b3) and the connected single wire data bus portion (b1, b2, b3) with a third threshold (V _1H ) and supplies the data signal received by the master to the inside of the circuit of the master, typically the host processor. The third comparator detects the change of the voltage level on the single-wire data bus (b1, b2, b3) or on the connected single-wire data bus section (b1, b2, b3) from the third voltage range (V _B3 ) on the one side to the first voltage range (V _B1 ) or second voltage range (V _B2 ) on the other side and vice versa.

CIR

Load "Instruction Register Data" state of the test controller

CDR

Load data register data state of the test controller

cmp

comparator

CMP2

second comparator

CMP 3

third comparator

D _1H

first preparation.

D _2H

second processing.

DR

Data registers of the JTAG interface (Several data registers are typically connected in parallel and are selected via the second multiplexer (MUX2) during the reading of the data registers (DR).)

drs

Selection signal for the data register to be read.

.delta.t

Delay unit for the combined TMS TDI signal (TMS_TDI _n )

EDR1

State "Data Register Exit 1" of the test controller (TAPC)

EDR2

State "Data Register Exit 2" of the test controller (TAPC)

EIR1

Status "Instruction register Exit 1" of the test controller (TAPC)

EIR2

Status "Instruction register Exit 2" of the test controller (TAPC)

en1

first enable line for opening and closing the first transfer gate (TG1) of the first bus node (BS1)

en2

second enable line for opening and closing the second transfer gate (TG2) of the second bus node (BS2)

en3

third enable line for opening and closing the third transfer gate (TG3) of the third bus node (BS3)

en _n

nth enable line for opening and closing the third transfer gate (TG3) of the nth bus node (BS _n )

GND

Reference potential line. This is typically not necessarily grounded. It has the reference potential (V0).

I ₁

Current source of the controllable current source (S _1H , I ₁ ) for the transmitter of the master, so typically the host processor.

I ₂

Current source of the controllable current source (S _2H , I ₂ ) for the transmitter of the bus node, ie the integrated circuit or the system to be tested or controlled.

IDCR

identification register

ilds

Lighting data select signal

ILR

lighting register

ILIR

Lighting instruction register

IR

Instruction register of the JTAG interface

IRDC

instruction decoder

LED

Led. For the purposes of this invention, it may also be the parallel and / or series connection of a plurality of LEDs.

LM1

Illuminant group 1, which is controlled by the first bus node (BS1).

LM2

Illuminant group 2, which is controlled by the second bus node (BS2).

LM3

Illuminant group 3, which is controlled by the third bus node (BS3).

MUX1

first multiplexer within the JTAG interface for switching between the data registers (DR) and the instruction register (IR)

MUX2

second multiplexer within the JTAG interface to select the active data register (DR)

MUX 3

third multiplexer for switching between a serial input for illumination data (SILDI _n ) and the serial input data (TDI).

NOR

inverting OR circuit

OWM

Master Eindrahtdatenbusschnittstelle

OWS1

first single wire data bus interface

OWS2

second single wire data bus interface

OWS3

third single wire data bus interface

OWS _n

Single wire data bus interface of the nth bus node

PCM

Pulse-code modulation

PDM

Pulse density modulation

PDR

State "Pause data register" of the test controller (TAPC)

PFM

Pulse frequency modulation

PIR

State "Pause Instruction Register" of the Test Controller (TAPC)

POM

Pulse-on-time modulation and / or pulse-off-time modulation

PS

voltage regulators

PWM

Pulse-width modulation. (For the purposes of this disclosure, this term encompasses all known types of pulse modulation, such as PFM, PCM, PDM, POM, etc.)

PWM1

first PWM unit

PWM 2

second PWM unit

PWM3

third PWM unit

R ₀

_Internal resistance of the pull circuit (R _0H , R _0L ), which, as the fourth real voltage source, _holds the single-wire _data bus (b1, b2, b3) or the connected single-wire data bus section (b1, b2, b3) at an intermediate potential (V _M ), if the other transmitters (S _1L , S _1H , I ₁ , S _2H , I ₂ ) are not active. (Not shown in the figures)

R _0L

lower resistance of the voltage divider pair, which exemplifies the pull circuit. The pull circuit keeps the single wire data bus (b1, b2, b3) or the connected single wire data bus section (b1, b2, b3) in the second voltage range (V _B2 ) at a medium potential (V _M ) if none of the other transmitters (S _1L , S _1H , I ₁ , S _2H , I ₂ ) is active.

R _0H

upper resistance of the voltage divider pair, which exemplifies the pull circuit. The pull circuit keeps the single wire data bus (b1, b2, b3) or the connected single wire data bus section (b1, b2, b3) in the second voltage range (V _B2 ) at a medium potential (V _M ) if none of the other transmitters (S _1L , S _1H , I ₁ , S _2H , I ₂ ) is active.

R1

first resistance

R _1H

Internal resistance of the second switchable real voltage source, which is formed by the switchable current source (S _1H , I ₁ ) of the master. (Not shown in the figures)

R2

second resistance

R _2H

Internal resistance of the third switchable real voltage source, which is formed by the switchable current source (S _1H , I ₁ ) of the bus node. (Not shown in the figures)

R3

voltage divider

R4

fourth resistance

R5

fifth resistance

R6

sixth resistance

R7

seventh resistor for setting the internal resistance of the switch of the controllable current source (S _2H , I ₂ ) for the transmitter of the bus node

RUN

"Waiting" state of the test controller (TAPC)

RX

additional data registers (DR) that comply with the JTAG standard

S _1L

dominant switch. The dominant switch typically forces the data line (TOW) to the potential of the reference potential (V ₀ ) by connecting the data line (TOW) to the reference potential line (GND) in the case of power up.

S _1H

Switch of the controllable current source (S _1H , I ₁ ) for the transmitter of the master, so typically the host processor.

S _2H

Switch of the controllable current source (S _2H , I ₂ ) for the transmitter of the bus node.

SDRS

State "Start of data register shift" in the test controller (TAPC)

SILDI _n

serial input for lighting data

SILDI1

first serial input for illumination data of the first bus node (BS1)

SILDI2

second serial input for illumination data of the second bus node (BS2)

SILDI3

third serial input for illumination data of the third bus node (BS3)

SILDO _n

serial output for lighting data

SILDO1

first serial output for illumination data of the first bus node (BS1)

SILDO2

second serial output for illumination data of the second bus node (BS2)

SILDO3

third serial output for illumination data of the third bus node (BS3)

SIRS

State "Start of Instruction Register Shift" in Test Controller (TAPC)

SIR

State "shift instruction register" of the test controller (TAPC)

sir_sdr

Control signal for the first multiplexer (MUX1) between instruction registers (IR) and data registers (DR)

SDR

State "Move data register" of the test controller (TAPC)

SR

transmit register

T

System clock period

T1

first transistor

T _1H

first half-cycle period of at least two half-clock periods (T _1H , T _2H ) of the system clock period (T)

T2

second transistor

T _2H

second half-clock period of at least two half-clock periods (T _1H , T _2H ) of the system clock period (T)

T3

third transistor

TAPC

Test controller

TB

data preparation

TCK

Clock input (test clock input) and system clock

TCK1

first reconstructed system clock within the first bus node (BS1)

tCK2

second reconstructed system clock within the second bus node (BS2)

tCK3

third reconstructed system clock within the third bus node (BS3)

TCK _n

nth reconstructed system clock within the nth bus node (BS _n )

TCKin ₂

clock signal received by the considered bus node (reconstructed system clock).

TCKout ₁

clock signal to be transmitted by the bus master (system clock).

TDAin ₁

data received by the bus master (BM).

TDAin ₂

data received by the bus node (BS1, BS2, BS3).

TDAout ₁

Transmission data from the inside of the bus master (BM).

TDAout ₂

Transmission data from the inside of the bus node (BS1, BS2, BS3).

TDI

serial data input (test data input)

TDO

third time slot. The third time slot is typically used to transmit the TDO signal of the IEEE Standard 1149 JTAG test port from the bus node to the bus master. However, it is not absolutely necessary that this time slot is placed at the third time position. Other temporal sequences are possible.

TDo

serial data output (test data output)

Tin0

first time slot. The first time slot is typically used to transmit the TMS signal of the IEEE Standard 1149 JTAG test port from the bus master (BM) to the respective bus node (BS1, BS2, BS3). However, it is not absolutely necessary that this time slot is placed at the first time position. Other temporal sequences are possible.

TIN1

second time slot. The second time slot is typically used to transmit the TDI signal of the IEEE Standard 1149 JTAG test port from the bus master to the bus node (BS1, BS2, BS3). However, it is not absolutely necessary for this time slot to be placed at the second time position. Other temporal sequences are possible.

TLR

Reset Test Logic state.

TMS

Mode input (test mode input) or test mode signal

TMS_TDI1

first combined TMS-TDI signal within the first bus node (BS1)

TMS_TDI2

second combined TMS TDI signal within the second bus node (BS2)

TMS_TDI3

third combined TMS TDI signal within the third bus node (BS3)

TMS_TDI _n

n-th combined TMS-TDI signal within the nth bus node (BS _n )

TRST

optional reset input (test reset input)

TG1

first transfer gate of the exemplary first bus node (BS1)

TG2

second transfer gate of the exemplary second bus node (BS2)

TG3

third transfer gate of the exemplary third bus node (BS3)

TGCR

Transfer gate control register

UDR2

Write data register state of the test mode controller

UIR2

Write "Write Instruction Register" state of the test mode controller

V ₀

Reference potential in the first voltage range (V _B1 ), which adjusts at least approximately on a single-wire data bus section (b1, b2, b3) or the single-wire data bus (b1, b2, b3) when the dominant switch (S _1L ) is closed. The reference potential line (GND) is at the reference potential.

V _asked

Supply voltage of the bus node

V _M

Potential in the second voltage range (V _B2 ) that occurs when no other transmitter (S _1L , S _1H , I ₁ , S _2H , I ₂ ) is active and thus the pull circuit (R _0H , R _0L ) prevails ,

V _1H

third threshold. The third threshold separates the third voltage range (V _B3 ) from the first voltage range (V _B1 ) and the second voltage range (V _B2 ) on the bus master side. The third threshold is preferably the same or similar to the first threshold (V _2H ).

V _2H

first threshold. The first threshold separates the third voltage range (V _B3 ) from the first voltage range (V _B1 ) and the second voltage range (V _B2 ) at the bus node side. The first threshold is preferably equal to or similar to the third threshold (V _1H ).

V _2L

second threshold. The second threshold separates the first voltage range (V _B1 ) from the third voltage range (V _B3 ) and the second voltage range (V _B2 ) at the bus node side.

V _B1

first voltage range which is limited to the second voltage range (V _B2 ) through the second threshold (V _2L ).

V _B2

second voltage range between the first voltage range (V _B1 ) and the third voltage range (V _B3 ), which is limited to the first voltage range (V _B1 ) through the second threshold (V _2L ) and the third voltage range (V _B1 ) through the first threshold value (V _2H ) of the bus node and / or by the third threshold value (V _1H ) of the master is limited.

V _B3

third voltage range, which is limited to the second voltage range (V _B2 ) through the first threshold value (V _2H ) of the bus node and / or by the third threshold value (V _1H ) of the bus master.

V _ext1

external supply voltage

V _IO

Supply voltage for the pull circuit, here the voltage divider (R _0H , R _0L ).

V _IO1

Supply voltage of the switchable current source (S _1H , I ₁ ) of the bus master, so the host processor. The voltage level is in the third voltage range (V _B3 ).

V _IO2

Supply voltage of the switchable current source (S _2H , I ₂ ) of the bus node, ie the integrated circuit or the system to be tested or controlled. The voltage level is in the third voltage range (V _B3 ).

VREF

reference voltage

Z ₀

Zener diode for limiting the voltage on a single wire data bus section (b1, b2, b3) or the single wire data bus (b1, b2, b3).

Claims (7)

Data bus system having a reference potential line (GND) and a single-wire data bus (b1, b2, b3) for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular to illuminant bus nodes, a wherein the single wire data bus (b1, b2, b3) is divided by the bus nodes (BS1, BS2, BS3) into at least two single wire data bus sections (b1, b2, b3) and terminated by a bus node, the terminating bus node (BS3) and b each of the bus nodes (BS1, BS2, BS3) except for a first bus node (BS1) is connected by a preceding single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) and a first bus node (BS1) is connected to the bus master (BM) through a preceding single wire data bus section (b1) of the single wire data bus sections (b1, b2, b3), and c each bus node (BS1, BS2, BS3) through a subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) is connected to a subsequent bus node (BS2, BS3) of the bus nodes (BS1, BS2, BS3) except for a terminating bus node (BS3), and d it via a bus master (BM) having a master single wire data bus interface (OWM), and e wherein the master single wire data bus interface (OWM) is bidirectionally bidirectionally data via the single wire data bus (b1, b2, b3) via a data bus protocol having more than two physical voltage and / or current levels ) or at least one single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3), hereinafter referred to as the considered single-wire data bus section (b1, b2, b3), and receiving f and the considered single-wire data bus section (FIG. b1, b2, b3) comprises only a single signal line and g wherein a single-wire data bus interface (OWS1, OWS2, OWS3) of a bus node (BS1, BS2, BS3) of the bus nodes (BS1, BS2, BS2, BS3) is connected to the single-wire data bus section under consideration (b1, b2, b3) BS3), hereinafter referred to as the considered bus node, and a transfer gate (TG1, TG2, TG3) of the considered bus node (BS1, BS2, BS3) are electrically connected and h the single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node is intended to receive data from the single-wire data bus section (b1, b2, b3) under consideration by means of a data bus protocol having at least two physical voltage and / or current levels and i the single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node is intended to send data via the considered single-wire data bus section (b1, b2, b3) by means of a data bus protocol more than two physical voltage and / or current levels and wherein the transfer gate (TG1, TG2, TG3 ) of the considered bus node is intended to separate and / or electrically connect the considered single-wire data bus section (b1, b2) from an optional subsequent single-wire data bus section (b2, b3) and k wherein the considered bus node (BS1, BS2, BS3) has a Transfer Gate Control Register (TGCR), which is designed to allow the transfer gate (TG1, TG2, TG3) and the bus master via the master single-wire data bus interface (OWM) and the single-wire data bus (b1, b2, b3) or the considered single-wire data bus section (b1, b2, b3) and the single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node, the transfer gate control register (TGCR) of the considered bus node (BS1, BS2, BS3) can describe and thus the state of the transfer gate (TG1, TG2, TG3) of the considered bus node (BS1, BS2, BS3 ) can control. Data bus system according to claim 1 characterized a that the considered bus node (BS1, BS2, BS3) internally at least one IEEE 1149 compliant interface, also known as JTAG interface, which via the single-wire data bus interface (OWS1, OWS2, OWS3) of the considered bus node to the single-wire data bus (b1, b2 , b3) or at least the single-wire data bus section (b1, b2, b3) is connected, such that the bus master (BM) over the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) considered this JTAG Interface, b wherein a JTAG interface in the sense of this claim is characterized in that it has a test controller (TAPC) in the form of a finite state machine - also called a finite state machine - which has an IEEE 1149 compliant state diagram. Data bus system according to claim 2, characterized in that the respective transfer gate control register (TGCR) of the considered bus node (BS1, BS2, BS3) by means of the at least one JTAG test interface of the considered bus node (BS1, BS2, BS3) via the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) considered by the bus master (BM). Data bus system according to claim 1 to 3 characterized a that at least the considered bus node, a light-bus node, is provided for it, associated lighting means, hereinafter referred to as considered light sources, in dependence on data via the single wire data bus (b1, b2, b3) or the considered single wire data bus section ( b1, b2, b3) are transmitted from the bus master (BM) to the considered bus node (BS1, BS2, BS3) Data bus system according to claim 2 and 4 characterized by a that the JTAG interface of the considered bus node comprises at least one lighting register (ILR) as a data register of the JTAG interface of the considered bus node, of which at least temporary content at least temporarily driving the observed illuminants, in particular in brightness and / or color temperature, by the considered Bus node depends. Data bus system according to claim 2 characterized in that a that the JTAG interface of the considered bus node comprises at least one lighting control register (ILCR) as a data register of the JTAG interface of the considered bus node and a lighting register (ILR) as a data register of the JTAG interface of the considered bus node and b that at least parts of the contents of the lighting control register (ILCR) depends on whether the lighting register (ILR) via the test data interface (TMS_TDI) of the JTAG interface of the considered bus node or a separate data input (SILDI) of the considered bus node, the illumination data for controlling the control of the considered light source from the bus master or another bus node receives and c that from the at least temporary content of the lighting register (ILR) at least temporarily depends on the control of the light source considered by the considered bus node. Data bus system according to claim 5 characterized in that a that at least parts of the contents of the lighting control register (ILCR) depends on whether the lighting register (ILR) via the test data interface (TMS_TDI) of the JTAG interface of the considered bus node or a separate data input (SILDI) of the considered bus node, the illumination data for controlling the control of considered light source from the bus master or another bus node receives.

Images