DE102014001264A1 - Precision current limiting and overcurrent tripping to protect a monolithic integrated driver by means of adapive reference generation - Google Patents

Abstract

The output driver circuit has a driver transistor (D, LSD, HSD) connected to a sense stage (SENSE) via a first common terminal (A). In this case, the driver transistor (D, LSD, HSD) is also connected to the sense stage (SENSE) via a second common terminal (B). At the same time, the gate (GD, GLSD, GHSD) of the driver transistor (D, LSD, HSD) is also connected to the sense stage (SENSE). The sense current (ISENSE) flows through the sense stage (SENSE) between the first common terminal (A) and the second common terminal (B). Sense stage (SENSE) and driver transistor (D, LSD, HSD) have a common reference potential (VBAT, GND). The sense stage (SENSE) generates a sense signal (V1) as a function of the sense current (ISENSE) and in dependence on the gate potential of the gate (GD, GLSD, GHSD) of the driver transistor (D, HSD, LSD). , A reference stage (REF) generates a reference signal (VREF). In parallel, a controller (CTR) compares the reference signal (VREF) and the sense signal (V1) by subtraction and generates a control signal (Vreg). The gate potential of the gate (GD, GLSD, GHSD) of the driver transistor (D, LSD, HSD) depends on the control signal (Vreg). In addition to this known prior art, the system according to the invention is characterized in that firstly the reference stage (REF) is connected to the gate (GD, GLSD, GHSD) of the driver transistor (D, LSD, HSD) and secondly the reference signal (VREF) depends on the potential of the gate (GD, GLSD, GHSD) of the driver transistor (D, LSD, HSD) and, thirdly, that the effect of a gate potential change of the gate (GD, GLSD, GHSD) of the driver transistor (D , LSD, HSD) is opposite to the reference signal (VREF) of the effect on the sense signal (V1).

Description

Introduction and state of the art

The object of the invention is the development of a more precise current limitation and an overcurrent protection for a monolithically integrated low-side driver (hereinafter referred to as LSD) and for a monolithically integrated high-side driver (hereinafter referred to as HSD). A low-side driver is generally understood to mean a driver output stage, for example for driving an ohmic or inductive load, which can set the output to the more negative of two possible output potentials. In contrast, the high-side driver (hereafter called HSD). A high-side driver is generally understood to mean a driver output stage, for example for driving an ohmic or inductive load, which can set the output to the more positive of two possible output potentials. Typically, a high-side switch (HSD) connects the supply voltage (V _Bat ) to the output (Out) and a low-side switch (LSD) connects the reference ground (GND) to the output (Out). By locking it is prevented that it comes to a cross-flow.

A task known from the prior art is to regulate the drive current (I _LSD , I _HSD ). For this purpose, this must be recorded and fed to the scheme. Since the problem is symmetrical for the high-side driver (HSD) and the low-side driver (LSD), the state of the art for the low-side driver (LSD) is considered first and then the state of the art for the high-side driver (HSD).

The state of the art is based on 1 explained. In the said state of the art for the control of a low-side driver (LSD) is usually the relatively large _{drive current} (I _LSD ) via a separate sense transistor (M _Sense ) for the purpose of simple further processing to a much smaller value, often in one-digit milliampere range mirrored and used as a sense current (I _SENSE ). This sense current (I _SENSE ) is a sense resistor (R _sense ), which is located between the source terminal (S _Sense ) of the sense transistor (M _Sense ) and the power ground (GND), ie the ground terminal , is converted into a sense voltage (V1). On the other hand, with a constant reference current (I _REF ) across the reference resistor (R _REF ), which is the same as the sense resistor (R _SENSE ), the reference voltage (V _REF ) is generated. The sense voltage (V1) is controlled by a regulator (CTR) to reference potential (V _REF ). In this case, the common gate (G _LSD ) of the low-side driver (LSD) and the sense transistor (M _SENSE ) is varied until the sense voltage (V1) reaches the reference voltage (V _REF ).

A major problem of such prior art circuits (see 1 ) is the mismatch, ie the non-correlation, between the driver current (I _LSD ) and the sense current (I _SENSE ).

The said mismatch is due to the voltage drop, so the sense voltage (V1), via the sense resistor (R _Sense ) about. The gate-source voltage (V _{GS_LSD} ) of the low-side driver (LSD) is increased compared to the gate-source voltage (V _{GS_SENSE} ) of the sense transistor (M _SENSE ) by the sense voltage (V1). Likewise, the drain-source voltage (V _{DS_LSD} ) of the low-side driver (LSD) is increased from the drain-source voltage (V _{DS_SENSE} ) of the sense transistor (M _SENSE ) for the same reason. This in turn results in a disorder (mismatch) in the mirror ratio.

This mismatch leads to larger variations of the current limiting via the common drain potential or the common output potential at the output (OUT). This variation becomes particularly critical for smaller drain-source voltages (V _{DS_LSD} , V _{DS_SENSE} ), ie in the region in which the transistors operate in switch mode or linear range, because there too there is a relatively small voltage drop (sense voltage V1). on the sense resistor (R _SENSE ), the ratio between the drain-source voltage V _{DS_LSD of} the low-side driver (LSD) and the drain-source voltage V _{DS_SENSE of} the sense transistor (M _sense ) and thus the mismatch between the low-side _drive current (I _LSD ) and the sense current (I _SENSE ) becomes large. This phenomenon can be explained by 2 for a low-side driver (LSD).

The analog circuit for a high-side driver (HSD) is in 3 shown.

The common reference potential is now instead of ground the operating voltage (V _BAT ). The sign of the reference current (I _REF ) is rotated. The transistors are installed in an analogous manner. Source and drain, however, are reversed relative to the reference notes (now V _BAT ). The sense voltage (V1) is now connected to the positive input of the controller (CTR) and the reference voltage (V _REF ) to the negative input of the controller (CTR). Although the mechanism of the coupling is a little different, because source and drain of the high-side transistor (HSD) with respect to the source and drain of the low-side transistor (LSD) of the previous example with respect to the reference potential (here V _BAT , there GND) are reversed. The coupling works here, too. Increasing the potential at the gate of the high-side driver transistor (HSD) simultaneously leads to an increase in the sense voltage (V1), since the sense transistor is connected with its gate to the gate of the high-side driver transistor (HSD) and at the same time begins to lead more strongly. This increase of V1 means a lowering of the input level at the positive input of the controller (CTR). This reduces the control voltage (V _REG ) at the output of the controller (CTR). Thus, the controller counteracts a change and stabilizes the control loop. With an increase in the output current, the output current (I _load ) is divided by the current divider on the driver branch and the sense branch. The sense current (I _SENSE ) in the sense branch is therefore increased with an increase and leads to an increase of the sense voltage (V1), which in turn leads to a lowering of the potential at the positive input of the controller (CTR). This in turn leads to a lowering of the control voltage (V _REG ), which counteracts the increase of the output current (I _load ). Here, the sense transistor (M _SENSE ) _receives a drain-source voltage (V _{DS_SENSE} ) which is reduced by the sense voltage (V1) compared with the drain-source voltage (V _{DS_HSD} ) of the high-side driver transistor (HSD) , it comes to imbalances, since the sense voltage (V1) can not be generated properly. Therefore, an overshoot of the output current (I _OUT ) with a descent of the value of the difference (V _BAT - V _OUT ) from the operating voltage (V _BAT ) is also reduced here in order to observe the output voltage (V _OUT ) for small values of this difference. ( 4 ) During start - up, the operating point of the system in the diagram moves 4 from right to left.

In the preceding examples all circuits with N-channel transistors (LSD, HSD) were considered without exception. Of course, these circuits are also conceivable with P-channel transistors in a correspondingly modified form.

It therefore makes sense to define the general structure of such a circuit in more detail. 5 shows such a general structure. Let the driver (D) be a MOS transistor with a gate (G). It is traversed by the driver current (I _D ), whereby this driver current (I _D ) can have negative and positive values depending on the configuration. The transistor has the connections A and B, where we want to keep open whether it is source or drain. For the consideration, this is only complicating.

Parallel to the driver transistor (D) with its first terminal (A) and its second terminal (B) is a sense stage (SENSE) connected by means of the potential at the gate (G) of the driver transistor (D) and the sense flowing through it Currents (I _SENSE ) produces a sense voltage (V1) which is differentially proportional to the sense current (I _SENSE ) in a given operating range of the circuit when the potential at the gate (G) of the driver transistor (D) is unchanged. The controller (CTR) compares these two signals to one another, preferably by differentiating the sense signal (V1) with a reference signal (V _REF ), and generates a control signal (V _reg ) which, at least in the said operating range, is differentially proportional to the difference between the two Sense signal (V1) and the reference signal (V _REF ) is. In this case, the difference is amplified by a factor by the controller (CTR) whose sign depends on the transistor type (N-channel, P-channel) and circuit configuration (high-side arrangement, low-side arrangement). The control signal (V _reg ) in this example controls a current source (I _G ) which charges or discharges the gate (G) of the driver transistor (D). Here, the parasitic capacitance of the gate (G) of the driver transistor (D) is utilized here. Of course, it may be useful to switch additional capacities parallel to the parasitic capacitance. The reference signal (V _REF ) is generated by a reference generation block (REF).

For the use of the stage 5 There are two configurations: First, a configuration in which one of the two terminals (A, B) is connected to ground (GND). This is the configuration as a low-side driver. Second, there is a configuration in which one of the two terminals is connected to the supply voltage (V _BAT ). This is the high-side driver configuration.

The problem solved by the invention now arises when the sense voltage (V1), as described above, can no longer be generated correctly at the edge of the said operating range of the sense stage (SENSE) and no longer or no longer in the desired one Dimensions of the sense current (ISENSE) and / or the gate potential of the gate (G) of the driver transistor (D) depends. In this case, the feedback via the controller (CTR) to the gate (G) of the driver transistor (D) no longer functions and the load current (I _B or I _A ) deviates from the specification.

Object of the invention

The object of the invention is to provide a method for compensating the failure of the sense stage (SENSE) at the edge of the operating range. This is especially true for a compensation of the mismatch described above between the behavior of the low-side driver (LSD) or the high-side driver (HSD) and the sense transistor (M _sense ) and thus the realization of a more precise current limit and / or a more precise overcurrent shutdown for a monolithically integrated low-side driver (LSD) or for a monolithically integrated high-side driver (HSD) for any output voltages (V _out ) to.

This object is achieved with a device according to claim 1.

Description of the basic invention

6 shows the modification of the system according to the invention 5 , The reference generation block (REF) now generates the reference signal (V _REF ) in its operating region in a differentially proportional dependence on the gate potential (V _G ) of the gate (G) of the driver transistor (D). In this case, the reference signal (V _REF ) depends in the manner of the gate potential (V _G ) of the gate (G) of the driver transistor (D) that, in a variation of the gate potential (V _G ) of the gate (G) of the Driver transistor (D) shows a variation of the reference signal (V _REF ), which has a reverse sign relative to the variation of the sense signal (V1). As a result, the device has two instead of one feedback path. The first feedback path is via the sense stage (SENSE). The second feedback path is via the reference generation block (REF).

If the work areas of the reference generation block (REF) and the sense stage (SENSE) overlap, but also have areas in which only the reference generation block (REF) or only the sense stage (SENSE) work and the other block no dependency shows more, the total work area of the entire system is extended to the union amount of the work area of the reference generation block (REF) and the work area of the sense stage (SENSE), which constitutes the essential advantage of the present invention.

This core idea will now be explained further with selected examples.

The core idea according to the invention for implementing a precise current limitation and an overcurrent protection for a monolithically integrated low-side driver transistor (LSD) or for a monolithically integrated high-side driver transistor (HSD) on the exemplary basis of an N-channel Transistors in the context of this invention concretely with respect to the example of 1 to 4 the readjustment of the reference current (I _REF ) and thus the desired realization of an adaptive reference potential (V _REF ) as an adaptive reference signal. This readjustment of the reference current (I _REF ) and thus the reference potential (V _REF ) is not known from the prior art.

In the case of a low-side driver configuration, in this way the different drain-source voltage (V _{DS_SENSE} ) caused by the previously described voltage drop, sense voltage (V1), at the sense resistor (R _sense ) can be _determined ) of the sense transistor (M _SENSE ) and the drain-source voltage (V _{DS_LSD} ) of the low-side driver transistor (LSD) and the resulting mismatch between the drain current (I _LSD ) of the low-side driver transistor ( _LSD ). Side driver transistor (LSD) and the sense current (I _SENSE ) by the sense transistor (M _Sense ) in particular at high load currents (I _Load ) compensate.

In the case of a high-side driver, the different course of the drain voltage (V _{DS_LSD} ) of the high-side current caused by the _sense voltage (V1) dropping across the sense resistor (R _sense ) can in turn be determined in this way. Driver (HSD) and the sense transistor (M _sense ) and the resulting mismatch between the drain current (I _HSD ) of the high-side driver (HSD) and the sense current (I _SENSE ) by _Compensate the sense transistor (M _SENSE ) as with the low side driver (LSD).

In the following, the invention is based on a current limiting circuit according to the invention according to the exemplary 7 for an exemplary low side driver transistor (LSD).

The low-side driver transistor (LSD) of the circuit 6 represents the said power transistor (D) for driving the output current (here I _OUT ). It is preferably provided with a relatively small electrical on-resistance Rds _{on_LSD} in order to minimize the losses. The sense level (SENSE) consists here of the sense transistor (M _Sense ), whose gate is connected to the gate (G) of the driver transistor (D), here the Los-side driver transistor (LSD). The sense stage (SENSE) further comprises the third transistor (M3) connected in series with the sense transistor (M _SENSE ). The sense node (S _SENSE ) connects sense transistor (M _SENSE ) and third transistor (M3). The other terminal of the sense transistor (M _SENSE ), here its drain, is connected to the drain of the low-side driver transistor, which is the first terminal (A) 6 equivalent. The source terminal of the third transistor (M3) is connected to the reference ground (GND) like the source terminal of the low-side driver transistor (LSD). The reference ground (GND) in this example corresponds to the second terminal (B) 6 , The Sense Level (SENSE) structured in this way therefore complies with the in 6 explained function, wherein the sense voltage (V1), which _falls between sense node (S _Sense ) and reference _ground (GND) via the third transistor (M3), from the gate-source voltage (V _{GS_SENSE} ) of the sense transistor (M _SENSE ) and thus _depends on the gate potential of the gate (G _LSD ) of the low-side driver transistor (LSD) and the sense current (I _SENSE ). However, this effect is dominated and typically superimposed by the mismatch between driver current (I _LSD ) and sense current (I _SENSE ) as a result of the drain-source voltage (V _{DS_M3} ) of the third transistor (M3) in relation to the drain-source Voltage (V _{DS_LSD} ) of the low-side driver transistor (LSD) decreased drain-source voltage (V _{DS_SENSE} ) of the sense transistor (M _SENSE ). This effect dominates especially at very high load currents (I _load ). An increase in the sense current (I _SENSE ) z. B. by increasing the load current (I _load ) by increasing the load on the output (Out) or a decrease in the gate potential at the gate (G _LSD ) of the low-side driver transistor (LSD) have an increase in the sense voltage (V1 ) and thus a reduction of the gate potential of the gate (G _LSD ) of the low-side driver transistor (LSD) result, which in turn counteracts the load current increase. On the reference page, the reference generation block (REF) turns off 6 now formed by a reference _current source (I _REF ) in combination with the fourth transistor (M4), which together generate the reference voltage (V _REF ). By the additional first transistor (M1), which is connected in parallel to the fourth transistor (M4) and also part of the reference generation block (REF), a part of the reference current (I _REF ) as an auxiliary current (I _h ) bypasses the fourth transistor (M4), whereby the reference voltage (V _REF ) decreases. Since the first transistor (M1) is connected with its gate terminal to the gate (G _LSD ) of the low-side driver transistor (LSD), an increase of the gate potential of the gate (G _LSD ) of the low-side leads Driver transistor (LSD) thus to a reduction of the reference voltage (V _REF ), resulting in an increase of the control voltage (V _reg ) due to the inverting input of the controller (CTR). This in turn causes a reduction of the gate potential of the gate (G _LSD ) of the low-side transistor, since the second transistor (M2) now opens. The second feedback loop is closed.

The sense transistor (M _sense ) typically has a much smaller width-to-length ratio (W / L ratio, (W / L) _SENSE ) relative to the W / L ratio ((W / L) _LSD ) of the low-side driver (LSD). The W / L ratio (W / L) _SENSE ) of the sense transistor (M _SENSE ) corresponds to that of the remaining transistors (M1, M4, M3) and in particular also that of the third transistor (M3), the fourth transistor ( M4) and the first transistor (M1).

The basic idea of the device according to the invention is thus based on this exemplary low-side driver configuration, an auxiliary current (I _h ) corresponding to the mismatch caused by the above-described current error in the sense path through the first transistor (M1) shown here also on to modulate the reference side and subtract this auxiliary current (I _h ) from the originally constant reference current (I _REF ).

In this case, use is made of the fact that the transistors (LSD, M _sense , M1, M3 and M4) are preferably of the same transistor type and can therefore be manufactured with the same characteristics (technical term "matching").

For this purpose, as voltage _sensors and for reference voltage _generation instead of sense resistors (R _Sense ) of the prior art, in linear mode operating transistors, specifically the third transistor (M3) and the fourth transistor (M4) is used.

The third transistor (M3) converts the sense current (I _SENSE ), as already described, to the sense voltage (V1), which corresponds to the drain-source voltage (V _{ds_M3} ) of this third transistor (M3). The amplifier (CTR) limits the gate voltage (V _{GS_LSD} ) of the low-side driver transistor (LSD) and the gate voltage (V _{GS_SENSE} ) of the sense transistor (M _sense ) as soon as the sense voltage (V1) Reference potential (V _ref ) exceeds. A significant advantage over the circuit (see 1 ) According to the prior art is that in normal operation, the circuit characteristics such as Propagation Delay, rise time (Risetime) or slew rates (Slewrates) are not affected by the amplifier (CTR). You can according to the respective requirements of the respective implementation case by the appropriate constructive adjustment of the on-current source (I _on ) and the off-current source (I _off ) are determined freely. Depending on the switching state, these are connected to the gate (G _LSD ) of the low-side driver transistor (LSD) by the ON switch (S _ON ) and the OFF switch (S _OFF ).

The gate of the first transistor (M1) in the reference path is connected to the gate (G _LSD ) of the low-side driver transistor (LSD) and the gate of the sense transistor (M _sense ). Its drain-source voltage (V _{DS_SENSE} ) thus corresponds to the drain-source voltage (V _{DS_M3} ) of the third transistor (M3) and thus the sense voltage (V1), in the limit case by the under-regulation of the gate terminal (G _LSD ) of the low-side driver transistor (LSD) corresponds to the drain-source voltage (U _{DS_M4} ) via the fourth transistor (M4) and thus to the reference voltage (V _REF ). When activating, ie the conductive switching, of the low-side driver transistor (LSD), the gate voltage (V _{GS_LSD} ) of the low-side driver _transistor (LSD) is first pulled up by the on-current source (I _on ) during normal operation. Since the parasitic capacitances are more or less fixed, therefore, the gate-source voltage (V _{GS_LSD} ) of the low-side driver transistor (LSD) is slowly pulled up to the limiting potential (V _LIM ) at a defined slew rate, the slew rate. In this case, the output voltage (V _out ) is then lowered by the low-side driver transistor (LSD). The error (mismatch) of the driver current (I _LSD ) to the sense current (I _SENSE ) then increases first. On the other hand, with the rising potential (V _{GS_LSD} , V _{GS_M1} ) of the common gate (G _LSD ) of the low-side driver transistor (LSD) and the first transistor (M1), the auxiliary current (I _h ) increases by the first one Transistor (M1), which is now subtracted from the reference current (I _REF ). In this way, now the reference voltage (V _REF ) decreases, which in turn _counteracts by the regulation of the gate-source voltage (V _{GS_LSD} ) of the low-side driver transistor (LSD) by an increase of the _{drive current} (I _LSD ) caused by the mismatch ,

In order to achieve a good match of the characteristics of the transistors within the device, the low-side driver transistor (LSD), the sense transistor (M _SENSE ), the first transistor (M1), the third transistor (M3) and the fourth transistor (M4) of the same type. The width-to-length ratio (W / L) _{M3 of} the third transistor (M3) relative to the width-to-length ratio (W / L) _{MSENSE of} the sense transistor (M _SENSE ) should have the same ratio as that Width-to-length ratio (W / L) _{M4 of} the fourth transistor (M4) to the width-to-length ratio (W / L) _{M1 of} the first transistor (M1). So it must apply:

mit n als ganzer Zahl.Now suppose that the width-to-length ratio (W / L) _{LSD of} the low-side driver transistor (LSD) is an integer multiple of the width-to-length ratio (W / L) _{SENSE of} the sense transistor (M _SENSE ), so that:

with n as a whole number.

Now, suppose that the width-to-length ratio (W / L) _{M3 of} the third transistor (M3) is an integral multiple of the width-to-length ratio (W / L) _{M4 of} the fourth transistor (M4), so :

Then, for all transistors in a linear range, a condition is: V _{GS_LSD} = V _{GS_SENSE} = V _{GS_M1 ≈V GS_M3} = V _{GS_M4} = V _LIM

The gate-source voltage (V _{GS_LSD} ) of the low-side driver transistor (LSD) is thus approximately equal to the gate-source voltage (V _{GS_SENSE} ) of the sense transistor (M _SENSE ) and approximately equal to the gate-source voltage (V _{GS_M1} ) of the first transistor (M1) and approximately equal to the gate-source voltage (V _{GS_M3} ) of the third Transistors (M3) and approximately equal to the gate-source voltage (V _{GS_M4} ) of the fourth transistor (M4) and ultimately equal to the limiting voltage (V _LIM ).

und

Thus:

and

(V _LIM ) is here the maximum permitted gate-source voltage (V _{GS_LSD} ) of the low-side driver transistor (LSD) used. For an existing gate-source protection z. B. via additional Zener diodes, this voltage (V _LIM ) can also be arbitrarily large up to the supply potential (V _BAT ) can be selected.

Under the condition:

Resulting from this for the low-boiling drive current I _LSD : I _{LSD ≈n.m.I REF}

Where I _{REF is} the reference _current .

If the circuit is in the current limit, the common gate potential (V _{GS_LSD} ) of the low-side driver transistor (LSD) and the sense transistor (M _Sense ) is down regulated. Thus, the gate-source voltages (V _{GS_LSD} and V _{GS_SENSE} ) at these two transistors but also the gate-source voltage (V _{GS_M1} ) at the first transistor (M1) _decrease . Thus, the drain-source resistor (Rds _M3 ) of the third transistor (M3) and the drain-source resistor (Rds _M4 ) of the fourth transistor (M4) and the drain-source resistor (Rds _M1 ) of the first transistor (M3) and the drain-source resistor (Rds _MSENSE ) of the sense transistor (M _SENSE ):

Furthermore: I _{LSD ≈n.m.I REF}

vernachlässigbar.There remains a small residual error, which results from the voltage drop across the third transistor (M3) and thus by the different gate-source voltages (V _{GS_SENSE} ) of the sense transistor (M _sense ) and the first transistor (M1). This error is for:

negligible.

Experience has shown that the preferred ratio between these pairs is:

The 8th illustrates the course of the output current (I _Load = I _OUT ) of the low-side driver transistor (LSD) as a function of the output voltage (V _OUT ) at the output (Out) on a device according to the invention with the above-described inventive adaptive reference.

After the structure according to the invention for the application in the control of a low-side driver (LSD) has been described as a low-side driver configuration shows 9 now a circuit according to the invention for a high-side driver configuration.

As before in the prior art, the reference potential is now the operating voltage (V _BAT ), which coincides with the first terminal (A) of the driver (D) 6 connected is. The reference generating block is changed so that the pair of first transistor (M1) serving for feedback and fourth transistor (M4), which typically substantially determines the operating point for the reference voltage (V _REF ), are connected to the reference _current source (I _REF ) still in series, but their order has been reversed. However, lowering the gate-source voltage (V _{GS_HSD} ) of the high-side driver transistor (HSD) automatically also _{results in} a lowering of the gate-source voltage (V _{GS_M1} ) of the first transistor (M1). This reduces the auxiliary current (I _h ). This increases the proportion of the reference current (I _REF ) flowing through the fourth transistor (M4). This increases the reference voltage (V _REF ) causing the potential at the positive input of the controller (CTR) to drop. This results in a lowering of the control voltage (V _reg ), which leads to a lower discharge of the gate (G _HSD ) of the high-side driver transistor (HSD). Thus, this control circuit counteracts a change in the gate potential at the gate (G _HSD ) of the high-side driver transistor (HSD). This control loop is closed. When the gate potential at the gate (G _HSD ) of the high-side driver transistor (HSD) is increased, the levels react accordingly in the opposite direction.

The other control loop leads to a lowering of the gate potential of the gate (G _HSD ) of the high-side driver transistor (HSD) to a lowering of the gate-source voltage (V _{GS_SENSE} ) of the sense transistor (M _SENSE ) This reduces the sense voltage (V1), because the sense current (I _SENSE ) is reduced and thus a little voltage across the third transistor (M3) as a drain-source voltage (V _{DS_M3} ) drops. This increases the input potential at the negating input of the controller (CTR). Therefore, also here, the control voltage (V _reg ) decreases and the discharge of the gate (G _HSD ) of the high-side driver transistor (HSD) decreases. Thus, this rule loop is closed. When the gate potential of the gate (G _HSD ) of the high-side driver transistor (HSD) is increased, the levels behave analogously in the opposite direction. Note that the second transistor (M2) leads to a further negation, which is why the connections of the controller in the 9 opposite the 3 which equals a multiplication of the gain of the controller (CTR) by -1.

As before, the behavior of the high-side driver is modified by this circuit so that there is no more overshoot. ( 10 )

The method of adaptive readjustment of the reference realized in the device according to the invention can also be used for precise overcurrent detection and overcurrent disconnection. It will be in 11 illustrated by a low-side driver, the controller replaced by a comparator. As soon as the drive current (I _LSD ) exceeds the preset maximum current level (I _LIM ) or the sense voltage (V1) exceeds the reference potential (V _REF ), the low-side drive transistor (LSD) is switched via a logic or a Digital part switched off. For this purpose, the OFF switch (S _OFF ) is closed and the off-current source I _{OFF is} connected to the gates of the low-side driver (LSD and the sense transistor (M _SENSE ).) At the same time, the on-current source I _ON and the The reference _current source (I _REF ) is decoupled by opening the first ON switch (S _ON1 ) and the second ON switch (S _ON2 ), _{thereby turning off the} gates of the low-side driver transistor (LSD) and the sense transistor (M _sense ) In this case, of course, even more complicated digital structures for control are conceivable, which cover several logical functions.The digital circuit part shown here is only an example in this regard do not necessarily require a switch A similar circuit is of course also possible with the same modifications for the control of a high-side driver (HSD).

Thus, the output driver circuit according to the invention is initially characterized by a structure known from the prior art, in which a driver transistor (D, LSD, HSD) is connected across a first transistor common terminal (A), which is typically identical to the source or the drain of the driver transistor (D, LSD, HSD), connected to a sense stage (SENSE). In this case, the driver transistor (D, LSD, HSD) via a second common terminal (B), which is now the drain of the driver transistor (D, LSD, HSD), if previously the first common terminal (A), the source of the driver transistor (D , LSD, HSD), or which is now the source of the driver transistor (D, LSD, HSD), if previously the first common terminal (A) was the drain of the driver transistor (D, LSD, HSD) was also connected to the sense transistor. Level (SENSE) connected. It is obvious that the second connection (B) may not be identical to the first common connection (A). At the same time, the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) is also connected to the sense stage (SENSE). The sense current (I _SENSE ) flows through the sense stage (SENSE) between the first common terminal (A) and the second common terminal (B).

Sense stage (SENSE) and driver transistor (D, LSD, HSD) have a common reference potential (VBAT, GND). The sense stage (SENSE) generates a sense signal in response to the sense current (I _SENSE ) and depending on the gate potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, HSD, LSD). Signal (V1). A reference stage (REF) generates a reference signal (V _REF ). In parallel, a controller (CTR) compares the reference signal (V _REF ) and the sense signal (V1) by subtraction and generates a control signal (Vreg). The gain of the controller (CTR) is selected in the design phase in terms of magnitude and sign, so that there is stability for the two control circuits described above. The controller typically has two inputs. A first input of the controller (CTR) is connected to the sense signal (V1) and a second input of the controller (CTR) is connected to the reference signal (V _REF ). The gate potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) depends on the control signal (Vreg). Beyond this known state of the art, the system according to the invention is distinguished in that, first of all, the reference stage (REF) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and to the Second, the reference signal (V _REF ) depends on the potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and, thirdly, the effect of changing the gate potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) is opposite to the reference signal (V _REF ) of the effect on the sense signal (V1).

In a particular embodiment of the invention, the sense stage (SENSE) is formed by the series connection of a sense transistor (M _SENSE ) with a third transistor (M3). The drain of the third transistor (M3) is connected to the source of the sense transistor (M _SENSE ) via a common sense _node (S _SENSE ). The voltage between reference potential (VBAT, GND) and common sense node (SENSE) here represents the sense signal (V1), which is connected to said first input of the controller (CTR). The drain of the sense transistor (M _SENSE ) is connected to one of the two common terminals (A, B). The source of the third transistor (M3) is in this case connected to the respective other of the common terminals (B, A). Finally, the gate of the sense transistor (M _SENSE ) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD). The gate of the third transistor (M3) is connected to another reference voltage (VCP, V _LIM ) to set the operating point.

In a further particular embodiment of the output driver circuit, in turn, the sense stage (SENSE) is formed by the series connection of a sense transistor (MSENSE) with a third transistor (M3). However, the source of the third transistor (M3) is _now connected to the drain of the sense transistor (M _SENSE ) via a common sense _node (S _SENSE ). In contrast to the previously described embodiment, the voltage between reference potential (VBat, GND) and common sense node (S _Sense ) represents the sense signal (V1), which is again connected to the first input of the controller (CTR). The source of the sense transistor (M _SENSE ) is connected to one of the common terminals (A, B). The drain of the third transistor (M3) is in turn connected to the other of the common terminals (B, A). The gate of the sense transistor (M _SENSE ) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD). The gate of the third transistor is in this case connected to a further reference voltage (VCP, V).

In a further embodiment, the reference generation block (REF) comprises a fourth transistor (M4) connected to its drain with a reference potential (VBAT). In this case, the fourth transistor (M4) is connected with its source to a reference node (S _REF ) and the gate of the fourth transistor (M4) to a further reference potential (VCP). In addition, the reference generation block (REF) comprises a first transistor (M1) connected at its drain to a reference potential (VBAT). In this case, the first transistor (M1) is connected with its source to a reference node (S _REF ) and the gate of the first transistor (M1) to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) , At the same time, a reference _current source feeds a reference current (I _REF ) into the reference node (S _REF ). The so constructed reference _{generation block} outputs at the reference node (S _REF ) the reference signal (V _REF ), which is connected to the second input of the controller (CTR).

In a further embodiment of the output driver circuit according to the invention, the reference generation block (REF) comprises a fourth transistor (M4) which is connected with its source to a reference potential (GND). In this case, the fourth transistor (M4) is connected with its drain to a reference node (S _REF ) and the gate of the fourth transistor (M4) to a further reference potential (V _LIM ).

The reference generation block (REF) further comprises a first transistor (M1) having its source connected to a reference potential (GND) and its drain connected to a reference node (S _REF ). The gate of the first transistor (M1) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD). A reference current source feeds a reference current (I _REF ) into the reference node (S _REF ). The reference generation block (REF) thus constructed outputs the reference signal (V _REF ) at the reference node (SREF), which is connected to the second input of the controller (CTR).

In a further embodiment of the invention, the transistors (D, LSD, HSD, M1, M2, M3, M4) are N-channel transistors or alternatively P-channel transistors. It is important to note that they should be transistors of the same type, which should match well, that is, be constructed to have approximately the same characteristics or to be composed of such transistors.

In a further aspect of the invention, the output driver has a high-side configuration or a low-side configuration. Of course, such drivers can be interconnected to more complex half or full bridges.

A further feature of the invention is additionally characterized in that the W / L ratio ((W / L) _M3 ) of the third transistor (M3) divided by the W / L ratio ((W / L) _SENSE ) of the sense transistor (M _SENSE ) on the one hand to a deviation of +/- 25%, or better +/- 10%, or better +/- 5%, or better +/- 2% or better +/- 1% or better +/- 0.5% on the other hand the W / L ratio ((W / L) _M4 ) of the fourth transistor (M4) divided by the W / L ratio ((W / L) _M1 ) of the first transistor ( M1).

A further feature of the invention is additionally characterized in that for the W / L ratio ((W / L) _M3 ) of the third transistor (M3) divided by the W / L ratio ((W / L) _SENSE ) of the sense _transistor Transistor (M _Sense ) has a value greater than 1 and / or greater than 2 and / or greater than 5 and / or greater than 10 and / or greater than 20 and / or greater than 50 and / or greater than 100 and / or preferred 10 +/- 1 is.

A further feature of the invention is characterized in that for the W / L ratio ((W / L) _M4 ) of the fourth transistor (M4) divided by the W / L ratio ((W / L) _M1 ) of the first transistor ( M1) greater than 1 and / or greater than 2 and / or greater than 5 and / or greater than 10 and / or greater than 20 and / or greater than 50 and / or greater than 100 and / or preferably 10 +/- 1 is.

A further feature of the invention is characterized in that, in the switched-on state, the ratios of the differential on-resistance (R _{ds_M3} ) of the third transistor (M3) divided by the differential on-resistance (R _{ds_Msense} ) of the sense transistor (M _SENSE ) on the one hand, to a deviation of +/- 25%, or better +/- 10%, or better +/- 5% or better +/- 2% or better +/- 1% or better +/- 0 , 5% on the other hand corresponds to the ratio of the differential on-resistance (R _{ds_M4} ) of the fourth transistor (M4) divided by the differential on-resistance (R _{ds_M1} ) of the first transistor (M1).

A further development of the invention with a modification of the current limitation to an overcurrent detection and / or an overcurrent disconnection is characterized in that the controller (CTR) is a comparator and it has a means for comparing the sense signal (V1) with a reference signal (V _REF ) which outputs a logical comparator signal (V _Komp ) in response to the comparison result between these two signals (V1, V _REF ). The output driver according to the invention also has a digital logic for further processing of the comparator signal (V _Komp ). In response to this comparator signal (V _Komp ), the driver transistor (D, LSD, HSD) is turned off when an overcurrent detection threshold is exceeded.

The essential feature of the output driver is thus that, in contrast to the prior art, it has two feedback loops and that these feedback loops have different but at least overlapping operating ranges with respect to the output current (I _Load ).

Finally, it should be mentioned that the second transistor, which has hitherto been little described, has an important safety-related task. This is important if the driver stage is an exit stage for the ignition of airbag detonators. The prior art additional transistor (M2) is designed in the exemplary drawings as an N-channel transistor with its drain to the gate (G _D , G _LSD , G _HSD ) of the respective driver transistor (D, LSD, HSD ) connected is. The source is connected to the reference potential, typically the reference ground (GND). This second transistor (M2) is controlled by the control signal (V _reg ) of the controller (CTR). This control signal (V _reg ) is connected to its gate terminal. If the gate of the second transistor (M2) is activated and thus the second transistor (M2) is turned on, then the second transistor (M2) connects the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) with a reference potential, in particular the ground potential (GND), that the one-current source (I _ON ), even with the first ON switch (S _ON ) closed, the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) can not reload so that the driver transistor (D, LSD, HSD) turns on and thus accidentally ignites the squib of the airbag. This is achieved by a suitable dimensioning of the second transistor (M2) with respect to the single-current source (I _ON ).

Advantages of the invention over the prior art

• 1. Das Mismatch zwischen dem Low-Side-Treiberstrom I_LSD bzw. dem High-Side-Treiberstrom (I_HSD) und dem Sense-Strom (I_SENSE) wird weitgehend aufgehoben. Hierdurch kann somit eine präzisere Strombegrenzungsschwelle und/oder eine präzisere Überstromabschaltungsschwelle erreicht und definiert werden.
• 2. Eine präzise Strombegrenzungsschwelle und Überstromabschaltungsschwelle hat weiterhin den Vorteil, die maximale Verlustleistung zu verringern und damit die durch die Verlustleitung bestimmte Treibergröße zu reduzieren.
• 3. In Schaltungen mit einer niederohmigen Last zwischen Low-Side-Treiber-Transistor (LSD) und High-Side-Treiber-Transistor (HSD), wird in der Regel einer der beiden Treiber dominant gegenüber dem anderen gewählt, indem sein Referenzstrom größer gewählt wird als der des anderen. Der Stromunterschied des als dominant bestimmten Treibers sollte dabei größer sein als die maximale Strombegrenzungsschwelle des anderen bzw. nicht dominanten Treibers um einen unbeabsichtigten Dominanzwechsel zwischen den Treibern zu vermeiden. Mit einer erfindungsgemäßen Vorrichtung mit kleinerer Strombegrenzungsschwelle, kann dieser Stromunterschied und damit der Ruhestrom kleiner gewählt werden. Somit können die Treiber kleiner dimensioniert werden, wodurch Fläche und somit Herstellkosten gespart werden können.

The device according to the invention has many advantages over the prior art:

• 1. The mismatch between the low-side _drive current I _LSD or the high-side _drive current (I _HSD ) and the sense current (I _SENSE ) is largely eliminated. As a result, a more precise current limiting threshold and / or a more precise overcurrent switching-off threshold can thus be achieved and defined.
• 2. A precise current limit threshold and overcurrent shutdown threshold further has the advantage of reducing maximum power dissipation and thus reducing driver size determined by the loss line.
• 3. In circuits with a low-impedance load between low-side driver transistor (LSD) and high-side driver transistor (HSD), one of the two drivers is usually chosen to be dominant over the other, by making its reference current larger is considered the other's. The current difference of the dominant driver should be greater than the maximum current limit threshold of the other or non-dominant driver in order to avoid an unintentional change of dominance between the drivers. With a device according to the invention with a smaller current limiting threshold, this current difference and thus the quiescent current can be selected smaller. Thus, the drivers can be made smaller, whereby area and thus manufacturing costs can be saved.

Claims (14)

Output driver circuit a. wherein a driver transistor (D, LSD, HSD) is connected to a sense stage (SENSE) via a first common terminal (A), which is the source or drain of the driver transistor (D, LSD, HSD), and b. wherein the driver transistor (D, LSD, HSD) is connected across a second common terminal (B), which is the drain or source of the driver transistor (D, LSD, HSD) and is not identical to the first common terminal (A). Level (SENSE) is connected and c. wherein the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) is also connected to the sense stage (SENSE) and d. wherein the sense stage (SENSE) is traversed by a sense current (I _SENSE ) between the first common terminal (A) and the second common terminal (B) and e. wherein sense stage (SENSE) and driver transistor (D, LSD, HSD) have a common reference potential (V _BAT , GND) and f. wherein the sense stage (SENSE) in dependence on the sense current (I _SENSE ) and depending on the gate potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, HSD, LSD) a sense Signal (V1) generated and g. wherein a reference stage (REF) generates a reference signal (V _ref ) and h. wherein a controller (CTR) compares the reference signal (V _ref ) and the sense signal (V1) by subtraction and generates a control signal (V _reg ) and i. wherein the gain of the controller (CTR) is chosen in magnitude and sign so as to give stability and j. wherein a first input of the controller (CTR) is connected to the sense signal (V1) and k. wherein a second input of the controller (CTR) is connected to the reference signal (V _REF ) and l. wherein the gate potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) depends on the control signal (V _reg ) characterized m. the reference stage (REF) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and n. the reference signal (V _REF ) is connected to the gate potential (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and o. That the effect of changing the gate potential of the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) on the Reference signal (V _REF ) is opposite to the effect on the sense signal (V1). Output driver circuit according to claim 1 a. wherein the sense stage (SENSE) is formed by the series connection of a sense transistor (M _SENSE ) with a third transistor (M3) and b. wherein the drain of the third transistor (M3) is connected to the source of the sense transistor (M _SENSE ) via a common sense _node (S _SENSE ) and c. wherein the potential between reference potential (V _Bat , GND) and common sense node (S _Sense ) represents the sense signal (V1) connected to the first input of the controller (CTR), and d. wherein the drain of the sense transistor (M _SENSE ) is connected to one of the common terminals (A, B) and e. wherein the source of the third transistor (M3) is connected to the other of the common terminals (B, A) and f. wherein the gate of the sense transistor (M _SENSE ) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and g. wherein the gate of the third transistor (M3) is connected to a further reference voltage (VCP, V _LIM ). Output driver circuit according to claim 1 a. wherein the sense stage (SENSE) is formed by the series connection of a sense transistor (M _SENSE ) with a third transistor (M3) and b. wherein the source of the third transistor (M3) is connected to the drain of the sense transistor (M _SENSE ) via a common sense _node (S _SENSE ) and c. wherein the voltage between reference potential (V _Bat , GND) and common sense node (S _Sense ) represents the sense signal (V1) connected to the first input of the controller (CTR), and d. wherein the source of the sense transistor (M _SENSE ) is connected to one of the common terminals (A, B) and e. wherein the drain of the third transistor (M3) is connected to the other of the common terminals (B, A) and f. wherein the gate of the sense transistor (M _SENSE ) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and g. wherein the gate of the third transistor (M3) is connected to a further reference voltage (VCP, V _LIM ). Output driver circuit according to one or more of claims 1 to 3 a. wherein the reference generation block (REF) comprises a fourth transistor (M4) connected to its drain with a reference potential (V _BAT ) and b. the fourth transistor (M4) having its source connected to a reference node (S _REF ) and c. wherein the gesture of the fourth transistor (M4) is connected to another reference potential (VCP) and d. wherein the reference generation block (REF) comprises a first transistor (M1) connected to its drain with a reference potential (V _BAT ) and e. wherein the first transistor (M1) is connected with its source to a reference node (S _REF ) and f. wherein the gate of the first transistor (M1) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and g. wherein a reference _current source feeds a reference current (I _REF ) into the reference node (S _REF ) and h. wherein the reference generation block (REF) thus constructed outputs at the reference node (S _REF ) the reference signal (V _REF ) connected to the second input of the controller (CTR). Output driver circuit according to one or more of claims 1 to 3 a. wherein the reference generation block (REF) comprises a fourth transistor (M4) connected to its source with a reference potential (GND) and b. the fourth transistor (M4) having its drain connected to a reference node (S _REF ) and c. wherein the gate of the fourth transistor (M4) is connected to a further reference potential (V _LIM ) and d. wherein the reference generation block (REF) comprises a first transistor (M1) having its source connected to a reference potential (GND) and e. wherein the first transistor (M1) is connected with its drain to a reference node (S _REF ) and f. wherein the gesture of the first transistor (M1) is connected to the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) and g. wherein a reference _current source feeds a reference current (I _REF ) into the reference node (S _REF ) and h. wherein the reference generation block (REF) thus constructed outputs at the reference node (S _REF ) the reference signal (V _REF ) connected to the second input of the controller (CTR). Output driver according to one or more of the preceding claims, a. wherein the transistors (D, LSD, HSD, M1, M2, M3, M4) are N-channel transistors or alternatively b. wherein the transistors (D, LSD, HSD, M1, M2, M3, M4) are P-channel transistors. Output driver according to one or more of the preceding claims, a. where the output driver has a high-side configuration or b. where the output driver has a low-side configuration. Output driver according to one or more of the preceding claims, but at least according to claim 2 or 3 a. for the W / L ratio ((W / L) _M3 ) of the third transistor (M3) divided by the W / L ratio ((W / L) _SENSE ) of the sense transistor (M _SENSE ) on the one side except for a deviation of +/- 25%, or better +/- 10%, or better +/- 5%, or better +/- 2% or better +/- 1% or better +/- 0.5% on the the other side corresponds to the W / L ratio ((W / L) _M4 ) of the fourth transistor (M4) divided by the W / L ratio ((W / L) _M1 ) of the first transistor (M1). Output driver according to one or more of the preceding claims, but at least according to claim 2 and / or 3 a. for the W / L ratio ((W / L) _M3 ) of the third transistor (M3) divided by the W / L ratio ((W / L) _SENSE ) of the sense transistor (M _SENSE ) greater than 1 and / or greater than 2 and / or greater than 5 and / or greater than 10 and / or greater than 20 and / or greater than 50 and / or greater than 100 and / or preferably 10 +/- 1. Output driver according to one or more of the preceding claims, but at least according to claims 4 and / or 5 a. for the W / L ratio ((W / L) _M4 ) of the fourth transistor (M4) divided by the W / L ratio ((W / L) _M1 ) of the first transistor (M1) greater than 1 and / or greater than 2 and / or greater than 5 and / or greater than 10 and / or greater than 20 and / or greater than 50 and / or greater than 100 and / or preferably 10 +/- 1. Output driver according to one or more of the preceding claims, but at least according to claim 2 and / or 3 a. wherein, in the on state, the ratios of the differential on-resistance (R _{ds_M3} ) of the third transistor (M3) divided by the differential on-resistance (R _{ds_SENSE} ) of the sense transistor (M _SENSE ) on the one hand to a deviation of + / -25%, or better +/- 10%, or better +/- 5%, or better +/- 2% or better +/- 1% or better +/- 0.5% on the other side of the ratio of the differential on-resistance (R _{ds_M4} ) of the fourth transistor (M4) divided by the differential on-resistance (R _{ds_M1} ) of the first transistor (M1). Output driver according to one or more of the preceding claims with a modification of the current limitation to an overcurrent detection and / or an overcurrent disconnection a. wherein the controller (CTR) is a comparator and b. wherein it comprises means for comparing the sense signal (V1) with a reference signal (V _REF ) which outputs a logical comparator signal (V _Komp ) in dependence on the comparison result between these two signals (V ₁ , V _REF ) and c. wherein it has a digital logic for further processing of the comparator signal (V _Komp ) and d. wherein in response to said comparator signal (V _comp ) the driver transistor (D, LSD, HSD) is turned off when an overcurrent detection threshold is exceeded. Output driver, in particular according to one or more of the preceding claims, a. wherein the output _driver has two control loops for regulating the gate voltage (V _{GS_D} , V _{GS_LSD} , V _{GS_HSD} ) of the power _driver (D, LSD, HSD) and b. wherein these control loop loops have different but at least overlapping operating ranges with respect to the output current (I _Load ). Output driver, in particular according to one or more of the preceding claims, for the ignition of airbag detonators a. wherein the output driver has a second transistor (M2) and b. the second transistor (M2) is controlled by the control signal (V _reg ) of the controller (CTR) connected to its gate terminal and c. wherein the second transistor (M2) connects the gate (G _D , G _LSD , G _HSD ) to a reference potential, in particular the ground potential (GND), when the transistor is turned on by means of the control signal (V _reg ) Current source (I _ON ) can no longer reverse charge the gate (G _D , G _LSD , G _HSD ) of the driver transistor (D, LSD, HSD) even when the first ON switch (S _ON ) is closed in such a way that the driver transistor ( D, LSD, HSD) turns on and / or ignites the airbag detonators.

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