DE102009051500B4 - Arithmetic logic unit - Google Patents

Abstract

An arithmetic logic unit comprises a computing unit and an error detector. The arithmetic unit comprises a first group of processing gates, a second group of processing gates and a group of control gates. The group of control gates drives at least one processing gate of the first group of processing gates and at least one processing gate of the second group of processing gates based on a control signal to select an algebraic function from a plurality of algebraic functions. The first group of processing gates processes the first binary input signal and the second binary input signal according to the selected algebraic function to obtain a first binary output signal. Further, the second group of processing gates processes the first binary input signal and the second binary input signal according to the selected algebraic function or according to an inverse algebraic function of the selected algebraic function to obtain a second binary output signal. The first binary output signal corresponds to the second binary output signal or an inverse output signal of the second binary output signal.

Description

Embodiments of the invention relate to integrated circuits for data processing, and more particularly to an arithmetic logic unit and method for processing a first binary input signal and a second binary input signal, according to a selectable algebraic function.

Errors in integrated circuits can not be completely ruled out. That goes for the modern chips and will be even more relevant to the chips of the next generations. The examples of physical errors are a short to ground or between wires, broken wires, errors caused by α-particles and high-energy neutrons or an electromagnetic field, etc. The errors can be permanent or transient. Through testing, only the permanent errors that occurred at the time of testing can be recognized. The circuit operation is interrupted. By using the self-checking circuits, both the permanent errors and the transient errors are detected during operation.

The self-testing circuits are used where the reliability and safety of digital circuits is concerned. These are, for example, safety applications in automotive, train traffic, medicine, defense and nuclear power plants, fault-tolerant computers for aviation and aerospace. In the safety circuits they are used to detect the intentional errors (error attacks).

Designing effective self-checking circuits with low hardware requirements is a big challenge.

Various methods for designing self-checking arithmetic and logic units are known.

The simplest method is duplication and comparison (see, for example, M. Gössel and S. Graf Error Detection Circuits, McGraw-Hill, London, 1993; M. Gössel and V. Ocheretny and ES Sogomonyan and D. Marienfeld. New Methods of Concurrent Checking, Springer, 2008 "). The original circuit is doubled. The outputs of the original circuit are compared with the outputs of the doubled circuit. If they are unequal, an error is detected. No special error model is needed in the method. The disadvantages of the method are a high hardware overhead, which requires more than 100% of the area of the original circuit, and a high power consumption.

The Arithmetic Residue Codes can be used for error detection in the arithmetic units (see, for example, "WW Peterson, On Checking an Adder, IBM Journal of Reseach and Development, 166-168, 1958"; "WW Peterson and EJ Weldon (Jr.), Error Correcting Codes, The MIT-Press, 1994 ";" A. Avizienis, Arithmetic Algorithms for Error-Coded Operands, IEEE Transactions on Computers, C-22 (6): 567-572, 1973 ";" GG Langdon and CK Tang Concurrent Error Detection for Group Look-Ahead Binary Adders. IBM Journal of Reseach and Development,: 563-573, 1970; "" V. Ocheretnij and M. Gössel and ES Sogomonyan and D. " Marienfeld, Modulo p = 3 Checking for a Carry Select Adder, Journal of Electronic Testing: Theory and Applications, 22: 101-107, 2006 "). The method is also called "modulo checking". Their main drawback is that checkers for Arithmetic Residue Codes are very complex circuits. In addition, the part-code arithmetic codes, which are often used for error detection in other components (such as data buses and memory), are not compatible.

Self-checking arithmetic and logical operators are also implemented using Berger codes (see, for example, JC Lo and S. Thanawastien and TRN Rao and M. Nicolaidis) to SFS Berger Check Prediction ALU and Its Application to Self-Checking Processor Designs, IEEE Transactions on CAD, 11 (4): 525-540, 1992 ";] M. Pflanz and K. Walther and HT Vierhaus, On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity Proceedings of 7th International On -Salle Testing Workshop, pages 51-53, 2001 "," SS Gorsche and B. Bose, A Self-Checking ALU Design with Efficient Codes. "Proceedings of 14th IEEE VLSI Test Symposium, pages 157-161, 1996"). This procedure detects all unidirectional errors. The disadvantages are the same as with the Residue Codes - a high hardware overhead for implementing the Berger Kode Checker and that the Berger code is not compatible with the parity codes.

The parity check is also used to implement the self-checking arithmetic and logical units. In "FF Sellers (Jr.) and MY Hsiao and LW Bearnson. Error Detection Logic for Digital Computers. McGraw-Hill, 1968 ";"MY Hsiao and FF Sellers. The Carry-Dependent Sum Adder. IEEE Transactions on Electronic Computers, EC-12 (6): 265-268, 1963 ";"M. Nicolaidis. Efficient Implementations of Self-Checking Adders and ALU's. Symposium on Fault-Tolerant Computing, pages 586-595, 1993 ";"M. Nicolaidis. Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Patent No.5450340 , 1995 ";"M. Nicolaidis. Carry Checking / Parity Prediction Adders and ALUs. IEEE Transactions on VLSI Systems, 11 (1): 121-128, 2003 ";"V. Ocheretnij and M. Gössel and ES Sogomonyan. Code Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead. Proceedings of 7th International On-line Testing Workshop, pages 147-152, 2001 "and" p. Vassiliadis and EM Black and M. Putrino and BJ Feal. Parity Prediction for Binary Adders with Selection. US Patent No. 4924424 , 1990 ", parity-verified adders were proposed. The audit of the logical operations was carried out in "ON Garcia and TRN Rao. On the Methods of Checking Logical Operation. Proceedings of 2nd Princeton Conference on Information Sciences and Systems, pages 89-95, 1968 ". Of particular interest is "M. Nicolaidis. Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Patent No.5450340 , 1995 ". In "M. Nicolaidis. Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Patent No. 5,450,340, 1995 "and subsequent publications (see, e.g.," M. Nicolaidis, Efficient Implementations of Self-Checking Adders and ALUs. Symposium on Fault-Tolerant Computing, pages 586-595, 1993 "; Nicolaidis, Carry Checking / Parity Prediction Adders and ALUs IEEE Transactions on VLSI Systems, 11 (1): 121-128, 2003 ") presented a self-polling ALU that implements the basic functions (ADD, AND, OR and XNOR). The parity check requires less hardware overhead than the above methods. The disadvantage of the method is that a single error in a carry signal falsifies an even number of bits in the calculation result and therefore can not be recognized by parity. Such errors need special treatment. In "MY Hsiao and FF Sellers. The Carry-Dependent Sum Adder. IEEE Transactions on Electronic Computers, EC-12 (6): 265-268, 1963, "a special cell has been proposed which avoids the unrecognized errors in the carries. In "M. Nicolaidis. Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Patent No.5450340, 1995 ";"M. Nicolaidis. Efficient Implementations of Self-Checking Adders and ALU's. Symposium on Fault-Tolerant Computing, pages 586-595, 1993 "and" M. Nicolaidis. Carry Checking / Parity Prediction Adders and ALUs. IEEE Transactions on VLSI Systems, 11 (1): 121-128, 2003 "the carries were simply doubled.

Another possibility is the method of partial doubling. The method doubles only part of the circuit. The non-doubled part is monitored by an error detection circuit. The method has been applied to various types of adders, multipliers and dividers (see, for example, ES Sogomonyan and M. Gössel, New Totally Self-Checking Ripple and Carry Look-Ahead Adders, Proceedings of 3rd On-Line Testing Workshop, pages 36-40, 1997; ES Sogomonyan and V. Ocheretnij and M. Gössel, A New Code-Disjoint Sum Bit-Duplicated Carry Look-Ahead Adder for Parity Codes Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 D. Marienfeld and ES Sogomonyan and V. Ocheretnij and M. Gössel A New Self-Checking Code-Disjoint Carry Skip Adder Proceedings of 8th IEEE International On-line Testing Workshop, 2002 ";" D. Marienfeld and ES Sogomonyan and V. Ocheretnij and M. Gössel, A New Self-Checking Code-Disjoint Carry Skip Adder Proceedings of 8th IEEE International On-line Testing Workshop, 2002 ";" D. Marienfeld and V. Ocheretnij and M. Gössel and ES Sogomonyan Partially Duplicated Code-Disjoint Carry Skip Adder Pro cededings of 7th IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI Systems, pages 78-86, 2002 "; "E. S. Sogomonyan and D. Marienfeld and V. Ocheretnij and M. Gössel. A New Self-Checking Sum Bit-Duplicated Carry Select Adder. Proceedings of Design, Automation and Test in Europe Conference - DATE, pages 1360-1361, 2004 "; "D. Marienfeld and E. S. Sogomonyan and V. Ocheretnij and M. Gössel. A New Self-Checking Multiplier by Using a Code-Disjoint Sum Bit-Duplicated Adder. Proceedings of 9th IEEE European Test Symposium, pages 73-78, 2004 ";"] D. Marienfeld and E. S. Sogomonyan and V. Ocheretnij and M. Gössel. New Self-Checking Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. Proceedings of 14th IEEE Asian Test Symposium, pages 76-81, Calcutta, 2005 "; "D. Marienfeld and E. S. Sogomonyan and V. Ocheretnij and M. Gössel. A New Self-Checking and Code-Disjoint Non-Restoring Array Divider. Proceedings of 12th IEEE International On-line Test Symposium, pages 23-28, Como, Italy, 2006 "). The advantages of the method are a low hardware overhead (comparable to the hardware effort in the parity check) and high error detection properties (almost like the method of doubling and comparison).

In "T. Nanya and T. Kawamura. Error Secure / Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. IEEE Transactions on Computers, 37 (1): 14-24, 1988 ", a concept for designing a self-checking processor has been proposed. Register File and the Control device of the processor are monitored by means of the Berger code. The ALU and the data buses are doubled.

In "M. Y. Hsiao and F.F. Sellers. The Carry-Dependent Sum Adder. IEEE Transactions on Electronic Computers, EC-12 (6): 265-268, 1963 "; "E. S. Sogomonyan and V. Ocheretnij and M. Gössel. A New Code Disjoint Sum Bit-Duplicated Carry Look-ahead adder for parity codes. Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 "; "M. J. Smith. Application-Specific Integrated Circuits. Adison Wesley, Reading, MA, 1997 ". In "M. Y. Hsiao and F.F. Sellers. The Carry-Dependent Sum Adder. IEEE Transactions on Electronic Computers, EC-12 (6): 265-268, 1963 "and" M. J. Smith. Application-Specific Integrated Circuits. Adison Wesley, Reading, MA, 1997 "has proposed special add-on cells (carry-dependent sum adder / carry-dependent sum adder and correspondingly fast ripple adder / fast trickle adder). In "E. S. Sogomonyan and V. Ocheretnij and M. Gössel. A New Code Disjoint Sum Bit-Duplicated Carry Look-ahead adder for parity codes. Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 "presented a self-checking Carry Look-ahead adder.

Further examples of different self-checking adders, multipliers and dividers (see, for example, ES Sogomonyan and M. Gössel, New Totally Self-Checking Ripple and Carry Look-Ahead Adders, Proceedings of 3rd On-Line Testing Workshop, pages 36-40 , Sogomonyan and V. Ocheretnij and M. Gössel, A New Code-Disjoint Sum Bit-Duplicated Carry Look-Ahead Adder for Parity Codes Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 "; Marienfeld and ES Sogomonyan and V. Ocheretnij and M. Gössel A New Self-Checking Code-Disjoint Carry Skip Adder Proceedings of 8th IEEE International On-line Testing Workshop, 2002 ";" D. Marienfeld and V. Ocheretnij and M Gössel and ES Sogomonyan Partially Duplicated Code-Disjoint Carry Skip Adder Proceedings of 7th IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI Systems, pages 78-86, 2002 "BS Sogomonyan and D. Marienfeld and V. Ocheretnij and M. Gössel, A New Self-Che Cking Sum Bit-Duplicated Carry Select Adder. Proceedings of Design, Automation and Test in Europe Conference - DATE, pages 1360-1361, 2004 "; "E. S. Sogomonyan and D. Marienfeld and V. Ocheretnij and M. Gössel. A New Self-Checking Sum Bit-Duplicated Carry Select Adder. Proceedings of Design, Automation and Test in Europe Conference - DATE, pages 1360-1361, 2004 "; "D. Marienfeld and E. S. Sogomonyan and V. Ocheretnij and M. Gössel. New Self-Checking Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. Proceedings of 14th IEEE Asian Test Symposium, pages 76-81, Calcutta, 2005 "; "D. Marienfeld and E. S. Sogomonyan and V. Ocheretnij and M. Gössel. A New Self-Checking and Code-Disjoint Non-Restoring Array Divider. Proceedings of 12th IEEE International On-line Test Symposium, pages 23-28, Como, Italy, 2006 "). However, these operations are limited to performing the corresponding operation (such as addition).

Many of the examples of self-checking integrated circuits shown each realize only one algebraic function, such as an addition. However, it is desirable to be able to perform a variety of different algebraic functions.

The object of the present invention is to provide an approach for processing binary input signals according to one of a plurality of selectable algebraic functions, which allows to realize a high error detection probability with low hardware overhead.

This object is achieved by an arithmetic logic unit according to claim 1 or a method according to claim 19.

An embodiment according to the invention provides an arithmetic logic unit for processing a first binary input signal and a second binary input signal, according to a selectable algebraic function. The arithmetic logic unit comprises a computing unit and an error detector. The arithmetic unit comprises a first group of processing gates, a second group of processing gates, and a group of control gates. The first group of processing gates, the second group of processing gates, and the group of control gates each differ at least partially from each other. Furthermore, the first group of processing gates and the second group of processing gates have at least one common processing gate. The set of control gates is configured to drive at least one processing gate of the first group of processing gates and at least one processing gate of the second group of processing gates based on a control signal to select an algebraic function from a plurality of algebraic functions. The first group of processing gates is configured to process the first binary input signal and the second binary input signal in accordance with the selected algebraic function to obtain a first binary output signal. Furthermore, the second group of Processing gates are adapted to process the first binary input signal and the second binary input signal according to the selected algebraic function or according to an inverse algebraic function of the selected algebraic function to obtain a second binary output signal. In this case, the first binary output signal corresponds to the second binary output signal or an inverse output signal of the second binary output signal if the arithmetic unit operates without errors. The error detector is configured to compare the first binary output signal to the second binary output signal or to the inverse output signal of the second binary output signal to detect an error in the processing of the first binary input signal and the second binary input signal, regardless of the selected algebraic function ,

Embodiments according to the invention are based on the core idea of being able to generate two output signals by partially doubling the processing gates, which are identical or inverse to one another in the case of error-free processing of the input signals by the arithmetic unit. As a result, an error in the calculation of the two output signals can be easily determined by comparing the output signals. An error can be detected independently of the selected algebraic function.

By only partially doubling the processing gates, the hardware outlay can be significantly reduced compared to completely duplicated systems with nearly identical fault detection characteristics. In comparison to code-based error detection systems, the error detection probability can be significantly increased by a small additional hardware overhead. As a result, overall a high error detection probability can be achieved with comparatively low hardware overhead.

In some embodiments according to the invention, the arithmetic unit is configured to provide an auxiliary output signal based on an output of a common processing gate of the first group of processing gates and the second group of processing gates. The auxiliary output signal is further processed, for example, by another arithmetic unit or by a carry pre-computation unit. Since an error of a common processing gate of the first group of processing gates and the second group of processing gates would affect both the first binary output signal and the second binary output signal, such an error may be detected based on the auxiliary output signal, for example.

Embodiments according to the invention are explained below with reference to the accompanying figures. Show it:

1 a block diagram of an arithmetic logic unit for processing a first binary input signal and a second binary input signal according to a selectable algebraic function;

2 a general structure of a self-checking arithmetic logic unit;

3 a block diagram of an arithmetic logic unit;

4 a block diagram of an arithmetic logic unit;

5 a block diagram of an arithmetic logic unit;

6 a block diagram of an arithmetic logic unit;

7 a flowchart of a method for processing a first binary input signal and a second binary input signal according to a selectable algebraic function;

8th a block diagram of an adder cell A _{i of} a self-verifying sum bit double parallel adder with carry advance calculation;

9 a block diagram of adder cells of a self-checking fast ripple adder (fast trickle adder);

10 a block diagram of an adder cell of a standard self-testing ripple adder (fast trickle adder); and

11 a block diagram of an arithmetic logic unit.

Hereinafter, the same reference numerals are used in part for objects and functional units having the same or similar functional properties. Furthermore, optional features of the various embodiments may be combined with each other or interchangeable.

1 shows a block diagram of an arithmetic logic unit 100 for processing a first binary input signal a _i and a second binary input signal b _i according to a selectable algebraic function according to an embodiment of the invention. The arithmetic logic unit 100 includes a computing unit 110 connected to an error detector 120 , The arithmetic unit 110 has a first group of processing gates, a second group of processing gates, and a group of control gates. The first group of processing gates, the second group of processing gates, and the group of control gates are each at least partially different from each other. In addition, the first group of processing gates and the second group of processing gates have at least one common processing gate. The group of control gates drives at least one processing gate of the first group of processing gates and at least one processing gate of the second group of processing gates based on a control signal m _i to select an algebraic function from a plurality of algebraic functions. Furthermore, the first group of processing gates processes the first binary input signal a _i and the second binary input signal b _i according to the selected algebraic function to obtain a first binary output signal s _i . The second group of processing gates processes the first binary input signal a _i and the second binary input signal b _i according to the selected algebraic function or according to an inverse algebraic function of the selected algebraic function to a second binary output signal s _i to obtain. The first binary output signal corresponds to the second binary output signal or an inverse output signal of the second binary output signal when the arithmetic unit 110 works without errors. The error detector 120 compares the first binary output signal s _i with the second binary output signal s _i or with the inverse output signal of the second binary output signal s _i to make a mistake regardless of the selected algebraic function 124 in the processing of the first binary input signal a _i and the second binary input signal b _i .

The term algebraic function in this context, for example, logical functions such. For example, an AND, an OR, an EXCLUSIVE OR, a NAND, a NOR, or an EXCLUSIVE NON-OR, or arithmetic functions, such. As an addition, a subtraction, a multiplication or a division and their inverse or negated function.

Processing gates and control gates are logic gates and may be of different types, such as an AND gate (AND gate), an OR gate (OR gate), a NOT gate, a NAND gate ( NAND gate), a NOR gate (NOR gate), an EXOR gate (XOR gate), or an EXCLUSIVE-NOR gate (XNOR gate). A logic gate may belong exclusively to the first group of processing gates, excluding the second group of processing gates or only to the group of control gates, may belong to two of the three mentioned groups, or may belong to all three groups. In addition, the arithmetic unit 110 include further logic gates that do not belong to any of the three groups, and serve, for example, to calculate one or more auxiliary quantities and as outputs to outputs of the arithmetic unit 110 provide.

For example, a logic gate is associated with the first group of processing gates when in the processing path between an input of the computing unit 110 on which an input signal, such. B. the first binary input signal a _i , the second binary input signal b _i or the control signal m _i , is provided and the output of the first binary output signal s _{i of} the arithmetic unit 110 is arranged. Likewise, a logic gate of z. B. second group of processing gates when the logic gate in the processing path of the second binary output signal s _i between an input of the arithmetic unit 110 where an input signal is provided and the output of the second binary output signal s _i the arithmetic unit 110 is arranged. Furthermore, a logic gate may for example be assigned to the group of control gates if at least one input of the logic gate depends exclusively on one or more control signals m _i .

By sharing a portion of the processing gates of the first group of processing gates and the second group of processing gates, the first binary output signal s _i and the second binary output signal s _i To get the hardware cost compared to a complete doubling of the arithmetic logic unit can be significantly reduced with a constant or nearly constant error detection probability. Compared to only code-based error detection systems, the error detection probability can be significantly increased with little additional hardware.

Because the first binary output signal s _i the second binary output signal s _i or the inverse second binary output signal s _i equivalent, can be a mistake 124 through the error detector 120 be easily determined by comparison. The second group of processing gates generates the second binary output signal s _i , based on the inverse algebraic function of the selected algebraic function, the arithmetic unit 110 simultaneously provide the result of two different algebraic functions. This additional functionality provides an additional advantage over code-based error detection systems without partial duplication and systems with complete duplication.

Thus, for example, at the output of the first binary output signal s _i an addition, a logical AND, a logical OR operation and / or a logical EXCLUSIVE OR operation can be realized and in turn at the output of the second binary output signal s _i an inverse addition, a NAND-operation, a NOR-operation and / or an EXCLUSIVE-NOT-OR-operation are realized.

The first binary output signal corresponds to the second binary output signal or to an inverse output signal of the second binary output signal after every calculation clock (eg operating cycle of the arithmetic unit) if the arithmetic unit operates without error. However, this may also be the case if both output signals are faulty (eg if the arithmetic unit has two errors, each error changing an output signal). Such errors can z. B. be recognized by implementation of other error detection mechanisms.

In some embodiments according to the invention, the arithmetic unit 110 an auxiliary output signal based on an output of a common processing gate of the first group of processing gates and the second group of processing gates. As a result, for example based on the auxiliary output signal, an error of a common processing gate can also be detected, which would otherwise be based on the first binary output signal s _i and the second binary output signal s _i would not be recognizable.

If an auxiliary output signal based on the output signal of the respective common processing gate is provided for each common processing gate of the first group of processing gates and the second group of processing gates, an error in each of the common processing gates may be detected via the auxiliary output signal.

An auxiliary output signal may be, for example, a so-called carry signal, a propagate signal or a generate signal. Such signals may also be further processed, for example, by optional additional processing units of the arithmetic logic unit, such as a carry pre-computation unit.

In some embodiments according to the invention, the auxiliary output signals may be used to calculate carry-outs or to predict carry-over.

Some embodiments according to the invention relate to an arithmetic logic unit having a plurality of arithmetic units. Each arithmetic unit of the plurality of arithmetic units processes a first binary input signal and a second binary input signal. For example, each first binary input signal represents one bit of a first parallel input signal with n-parallel bits and every other binary input signal represents one bit of a second parallel input signal with n-parallel bits. For example, the first parallel input signal may consist of 8 parallel bits and the second parallel input signal also composed of 8 parallel bits together. One bit each of the first parallel input signal and the second parallel input signal is then processed by a computation unit of the arithmetic logic unit to obtain a first binary output signal and a second binary output signal. Thus, eight arithmetic units are needed for parallel processing. The sum of the first binary output signals of the arithmetic units then gives a first parallel output signal with 8 parallel bits and the sum of the second binary output signals of the arithmetic units result in a second parallel output signal again having 8 parallel bits. Instead of 8 parallel bits, the parallel Input signals and the parallel output signals also any other number of parallel bits, such. B. 16, 32 or 64 bits.

Some embodiments of the invention relate to a self-checking arithmetic logic unit.

Not every circuit with error detection properties is self-checking. There is a definition of self-checking. To quantify the quality of error detection by simultaneous verification, the terms self-testing, error-protected and fully self-checking are used for circuits with simultaneous verification.

For self-testing circuits, there are z. For example, for each modeled error, an input vector that generates an output vector under normal operation that does not belong to an output code. For fault-protected circuits z. For example, for each modeled error, erroneous output is generated that does not belong to the output code. Furthermore, a circuit z. B. completely self-checking, if it is self-testing and error-protected.

2 shows a general structure of an arithmetic logic unit 200 , according to an embodiment according to the invention.

The input signals, also called input operands or input operands a = (a ₀ ,..., A _n-1 ) and b = (b ₀ ,..., B _n-1 ), have the length of n bits. Here, a _n-1 and b _n-1 z. For example, the most significant bits (MSBs). In addition, in this example, it is assumed that the operands a and b are parity-coded and p _a (p _a = a ₀ ⊕ ... ⊕ a _n-1 ) and p _b (p _b = b ₀ ⊕ ... ⊕ b _{n -1} ) are the corresponding parity bits. If the operands are not encoded, the parity bits can be determined with the aid of two XOR trees each of length n-1 with an XOR gate.

The operands a and b are applied to the inputs of the computation units, also called ALU cells A ₀ ,..., A _n-1 . With the aid of control signals m ₁ ,..., M _k , an (arithmetic or logical) operation is selected which is to be executed. The ALU cell A _i , i = 0, ..., n-1, implements both the operation and the corresponding inverse operation in this example. The selected operation and the inverse operation are at the output s _i and at the output, respectively s _i implemented. In addition, the ALU cell A _i outputs the propagation signal p _i (propagate signal, p _i = a _i ⊕ b _i ). The propagation signals of all ALU cells are summed modulo 2. The sum constituting the parity p (a ⊕ b) of the input operands A and B (p (a ⊕ b) = p ₀ ⊕ ... ⊕ p _n-1 = a ₀ ⊕ b ₀ ⊕ ... ⊕ a _{n -1} ⊕ b _n-1 ).

To detect the errors, the output s = (s ₀ , ..., s _n-1 ) with the output s = ( s ₀ , ..., s _n-1 ) bitwise compared. In the case s _i = s _i an error is detected. The comparison is made, for example, by means of a self-checking comparator 120 carried out. In "WC Carter and PR Schneider," Design of dynamically checked cmputers, "in JFIP Congress, (Edinburg, Scotland), pp. 878-883, 1968. "a two-rail checker is shown. A useful feature of this comparator is that one of its outputs r ₁ , r ₂ , for example r ₁ , implements the parity of its input s.

A possible alternative is a self-checking comparator with a periodic output, such. In "S. Kundu, ES Sogomonyan, M. Gössel, and S. Tarnick, "Self-Checking Comparator with One Periodic Output," IEEE Transactions on Computers, vol. C-45, no. 3, pp. 379-380, 1996. ". In order to detect the errors in the operands a and b and the errors in the propagation signals, the parity p (a ⊕ b) is compared with the XOR sum of the parity bits p _a and p _b .

Because only part of the ALU 200 can be doubled, the structure of the described self-testing ALU 200 be attributed to the method of partial doubling.

In some embodiments according to the invention, the processing gates of the first group of processing gates, the processing gate of the second group of processing gates and the control gate of the group of control gates are interconnected so that a single error of a gate of the first group, the second group or the control group is determined by the error detector 120 can be detected. In other words, if an error occurs at a position in the arithmetic unit, the first binary output signal becomes s _i or the second binary output signal s _i changed so that the error detector an error 124 detected. The logic gates of the three groups can be integrated, for example, so that a single error can be detected, regardless of which gate of the first group, the second group or the control group of individual errors occurs.

A gate is z. Example, of a plurality of transistors which are interconnected, wherein one or more of the transistors may be faulty. A faulty transistor can corrupt the gate output. Likewise, a plurality of faulty transistors of a gate distort the gate output. Both can be regarded as a single fault of a gate, since the term single fault refers to a faulty gate output. If, on the other hand, errors occur in more than one gate, one speaks for example. B. of multiple errors.

Furthermore, a fault in the electrical connections of the gates with each other and the gate with the inputs and outputs of the arithmetic unit as well as at the inputs and outputs themselves occur. For example, B. on only one connection an error on this can also be referred to as a single error. If an error occurs, for example, at several connections or at a connection and a gate, one can again speak of multiple errors.

Some embodiments implement at the output s (as a first binary output signal) the functions ADD (addition), AND, OR and XOR and at the output s (as second binary output) the inverse functions ADD , NAND, NOR and XNOR. In the following, the implementation of the abovementioned arithmetic and logical operators in the ALU cell A _i , i = 0,..., N-1, is considered in detail:

Implementation of the addition ADD at the output s _i :

The operation can z. B. be implemented according to the known formula for the binary addition: s _i = a _i ⊕b _i ⊕c _i-1 , (1) wherein c _i-1 input carry signal (carry signal) and a _i ⊕ b _i = p _{i is} the propagate signal (propagate signal). The combinatorics that implement the addition can be reused to implement the AND, OR and XOR functions.

Implementation of the AND function (AND function, AND operation) at the output s _i :

By a control logic (control logic), which is controlled by means of the control signals m ₁ , ..., m _k , z. B. the input b _i inverted and with the propagate signal p _i ORER (processed according to an OR function). The resulting signal is then negated by the control logic by setting c _i-1 to "1". Instead of b _i , the input a _i can also be used.

Implementation of the OR function (OR function, OR operation) at the output s _i :

By a control logic (control logic), which is controlled by means of the control signals m ₁ , ..., m _k , z. B. the input b _i with the propagate signal p _{i are} ORed. c _i-1 is set to "0" by the control logic. Instead of b _i , the input a _i can also be used. (b _i ∨ a _i ⊕b _i ) ⊕ 0 = b _i ∨ p _i = a _i ∨ b _i or a _i ∨ p _i = a _i ∨ b _i

Implementation of the XOR function (XOR operation) at the output s _i :

By a control logic, which is controlled by means of the control signals m ₁ , ..., m _k , z. B. the signal c _i-1 "0" are set. a _i ⊕b _i ⊕ 0 = a _i ⊕ b _i

Implementation of the negated addition ADD (inverse addition) at the output s _i :

For the implementation of the negated addition can z. B. the auxiliary function ƒ can be used:

The function ƒ was written in "MY Hsiao and FF Sellers. The Carry-Dependent Sum Adder. IEEE Transactions on Electronic Computers, EC-12 (6): 265-268, 1963, "and in the design of carry-dependent sum adders / carry-dependent sum adders (see, for example," MY Hsiao and FF Sellers. "" The Carry-Dependent Sum Adder, IEEE Transactions on Electronic Computers, EC-12 (6): 265-268, 1963 ";" V. Ocheretnij and M. Gössel and ES Sogomonyan, Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead Proceedings of 7th International On-line Testing Workshop, pages 147-152, 2001 "; D. Marienfeld and ES Sogomonyan and V. Ocheretnij and M. Gössel." A New Self-Checking Multiplier by Use of a Code-Disjoint Sum Bit-Duplicated Adder Proceedings of 9th IEEE European Test Symposium, pages 73-78, 200 ";" D. Marienfeld and ES Sogomonyan and V. Ocheretnij and M. Gössel New Self-Checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. Proceedings of 14th IEEE Asian Test Symposium, pages 76-81, Calcutta, 2005 ") and Sum-Bit Dupli cated adders / sum bit duplicating adders (see e.g. B. "ES Sogomonyan and V. Ocheretnij and M. Gössel. A New Code Disjoint Sum Bit-Duplicated Carry Look-ahead adder for parity codes. Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 ";" D. Marienfeld and ES Sogomonyan and V. Ocheretnij and M. Gössel. A New Self-Checking Code Disjoint Carry Skip Adder. Proceedings of 8th IEEE International On-line Testing Workshop, 2002 ").

Alternatively, the inverse auxiliary function ƒ be used.

The negated sum bit can z. B. be defined as an XOR sum of the auxiliary function ƒ and the carry signal c _i :

The combinator, which implements the negated addition, can be reused for the implementation of the NAND, NOR, and XNOR functions.

Implementation of the NAND function (non-and-function, no-and-operation) at the output s _i :

By a control logic, which is controlled by means of the control signals m ₁ , ..., m _k , z. B. the carry signals c _i-1 and c _i (carry signals) are set to "1":

Implementation of the NOR function (no-or-function, no-OR operation) at the output s _i :

By a control logic, which is controlled by means of the control signals m ₁ , ..., m _k , the carry signals c _i-1 and c _{i are set} to "0":

Implementation of the XNOR function (non-exclusive-OR operation) at the output s _i :

By a control logic, which is controlled by means of the control signals m ₁ , ..., m _k , the signal a _i ⊕ c _i-1 (or b _i ⊕ c _i-1 ) is blocked and the carry signal c _i to " 0 "set:

Alternatively, the propagate signal p _{i can} also be implemented, for example, as follows:

The addition is then z. For example, as follows:

The combinator that implements the addition can then also be used to implement the NAND, OR, and / or XOR functions.

auf ”0” setzt.The NAND function is z. B. implemented by a control logic signals c _i-1 and

set to "0".

For example, the OR function is implemented by the control logic setting signals c _i-1 and (a _i ∧ b _i ) to "0".

The XOR function can be implemented by the control logic setting signal c _i-1 to "0".

The described alternative implementation of the propagate signal in an ALU cell is e.g. In ["M. Nicolaidis. Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Patent No.5450340 , 1995 "].

If the propagate signal p _{i is implemented} as described above alternatively, the auxiliary function f _{i can} also be used for the implementation of the functions Addition, AND, OR and XOR.

oder

implementiert werden. Alternativ kann wiederum auch die inverse Hilfsfunktion ƒ implementiert werden.The auxiliary function f _i can then as

or

be implemented. Alternatively, in turn, the inverse auxiliary function ƒ be implemented.

oderThe addition can then z. For example, as follows:

or

The combinator that implements the addition can then also be used to implement the NAND, OR, and XOR functions.

auf ”0” setzt.The NAND function can, for. B. be implemented by a control logic signals c _i , (a _i ⊕ c _i-1 ) or (b _i ⊕ c _i-1 ) and

set to "0".

The OR function can be implemented by the control logic signals c _i (a _i ⊕ c _i-1) or (b _i ⊕ c _i-1) and (a _i ∧ b _i) to "0" sets.

Furthermore, the XOR function can be implemented by the control logic setting the signals c _i , (a _i ⊕ c _i-1 ) and (b _i ⊕ c _i-1 ) to "0".

In some embodiments according to the invention, the computing unit, also called cell or arithmetic logic unit cell, is based on a carry adder adder architecture, a fast trickle adder architecture Adder architecture) or a standard Riesel adder architecture (standard ripple adder architecture).

For high-speed applications, the ALU cells can be run on self-checking carry-look-ahead adders (see, eg, ES Sogomonyan and V. Ocheretnij and M. Gössel, A New Code-Disjoint Sum Bit-Duplicated Carry Look -Ahead Adder for Parity Codes. Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 "). A newly developed self-checking Fast Ripple Adder can serve as the basis for the ALU cells, which are intended for applications for which the hardware overhead and power consumption are critical.

In the exemplary embodiments, different implementations of the control logic are shown. The number of control signals can also vary.

A self-checking sum-bit Duplicated Carry look-ahead adder (sum-bit-duplicating parallel adder with carry-prediction) has been developed in z. B. "ES Sogomonyan and V. Ocheretnij and M. Gössel. A New Code Disjoint Sum Bit-Duplicated Carry Look-ahead adder for parity codes. Proceedings of 10th Asian Test Symposium, pages 57-62, 2001 "proposed. Its adder cell A _i is in 8th shown.

The adder cell implements the propagate signal p _i , the generate signal g _i (Generate Signal), the sum bit s _i and the negated sum bit s _i , From the propagate and generate signals of all adder cells, the carry look-ahead unit calculates the carry signals (carry signals).

The following examples use logic gates with two inputs (two input gates). The number of gates can be reduced by using more complex gates (eg with more than 2 inputs and more complex realizable functions).

In the in 8th shown arithmetic unit 810 become the logic gates 82 and 83 needed to get the sum bit s _i as an output signal. The logic gates 82 . 84 . 85 and 86 are used to calculate the negated sum bit s _i needed. Furthermore, the logic gate 81 for providing a generate signal g _i as a further output signal of the arithmetic unit 810 used. In addition, the output signal p _i (propagate signal, propagate signal) of the logic gate 82 as another output signal of the arithmetic unit 810 provided. The transmission prediction unit 830 may be based on the generator signals g _i and the propagation signals p _i of the arithmetic logic units of the arithmetic unit 800 , calculate the carry signals c _i and the arithmetic units 810 provide.

For example, in this example, the propagate signal p _i and the generate signal g _{i represent} an auxiliary output signal of the arithmetic unit already mentioned above. Based on the propagate signal p _i and the generation signal g _i , for example, a carry prediction unit 830 determine a carry signal c _i and provide it to the arithmetic unit.

3 shows a block diagram of an arithmetic logic unit 300 for processing a first binary input signal a _i and a second binary input signal b _i according to a selectable algebraic function according to an embodiment of the invention. The arithmetic logic unit 300 is based on the concept of a parallel adder with carry prediction. The arithmetic logic unit 300 includes a plurality of computing units 110 , of which a calculation unit A _{i is} shown, a carry advance calculation unit 830 and an error detector which is in 3 not shown. The arithmetic unit A _i is connected to the error detector (not shown) and the carry prediction unit 830 and optionally connected to a preceding and / or a subsequent arithmetic unit. The arithmetic unit A _i are as input signals the first binary input signal a _i , the second binary input signal b _i , a first control signal m ₁ , a second control signal m ₂ , a carry signal c _{i-1 of} a previous arithmetic unit and a separate carry signal c _{i of} the arithmetic unit A _i provided. The carry signals c _i , c _i-1 are from the carry pre-computation unit 830 or a preceding or succeeding arithmetic unit calculated and provided. Conversely, the arithmetic unit A _i, the first binary output signal s _i , the second binary s _i , a propagate signal p _i , a generate signal g _i and a carry signal c _{i-1 of} a preceding arithmetic unit.

The arithmetic unit A _i comprises a first to fourteenth logic gate. Here is the first logic gate 31 an AND gate, and combines the first binary input signal a _i and the second binary input signal b _i according to a logical AND operation to obtain the generating signal g _i and to provide it at an output of the arithmetic unit A _i . At the second logic gate 32 If it is an XOR gate, to whose inputs the first binary input signal a _i and the second binary input signal b _i abut, and corresponding to a logical XOR function, the propagating signal p _i generated at an output of the arithmetic unit A _i provides. The second logic gate 32 represents the propagate signal p _i both as an auxiliary output signal and as an input signal for the fifth logic gate 35 and the eighth logic gate 38 to disposal. The third logic gate 33 corresponds to an XOR gate and to a first input to an output of the eighth logic gate 38 and with a second input with an output of the eleventh Logic gate e3 connected. The third logic gate 33 provides at its output the first binary output signal s _i . The fourth logic gate 34 corresponds to a further XOR gate and is connected to a second input to an output of the eleventh logic gate e3. In addition, there is a first input of the fourth logic gate 34 the first binary input signal a _i . The output of the fourth logic gate 34 is connected to an input of the eleventh logic gate e5. The fifth logic gate 35 is a NOR gate, wherein a first input of the fifth logic gate 35 with the output of the second logic gate 32 and a second input of the fifth logic gate 35 is connected to an output of the eleventh logic gate e5. The output of the fifth logic gate 35 is with an input of the sixth logic gate 36 connected. The sixth logic gate 36 corresponds to an XOR gate and receives its own carry signal c _{i of} the arithmetic unit A _i at a second input. A first input of the sixth logic gate 36 is at the output of the fifth logic gate 35 connected. The output of the sixth logic gate 36 provides the second binary output signal s _i . Furthermore, the seventh logic gate corresponds 37 an XOR gate and receives the second binary input signal b _i at a first input and the second control signal m ₂ at a second input. The output of the seventh logic gate 37 is connected to an input of the fourteenth logic gate e6. The eighth logic gate 38 corresponds to an OR gate and is connected to a first input to the output of the second logic gate 32 and a second input connected to the output of the fourteenth logic gate e6. The output of the eighth logic gate 38 is with an input of the third logic gate 33 connected. The ninth logic gate e1 corresponds to a further OR gate and receives the carry signal c _{i-1 of} the preceding arithmetic unit at a first input and the second control signal m ₂ at a second input. The output of the ninth logic gate e1 is connected to an input of the eleventh logic gate e3. The tenth logic gate e2 corresponds to an XNOR gate and receives the second control signal m ₂ at a first input and provided at a second input of the first control signal m ₁ . The output of the tenth logic gate e2 is connected to an input of the fourteenth logic gate e6. Furthermore, the eleventh logic gate e3, which corresponds to an AND gate, receives the second control signal m ₂ at a second input and is connected to the output of the ninth logic gate e1 by a first input. The output of the eleventh logic gate e3 is connected to an input of the fourth logic gate 34 as well as with an input of the third logic gate 33 connected and provides the carry signal c _{i-1 of} the previous processing unit. The twelfth logic gate e4 corresponds to a NAND gate (NAND gate) and receives the second control signal m ₂ at a first input and the control signal m ₁ at a second inverted input. The output of the twelfth logic gate e4 is connected to an input of the thirteenth logic gate e5. The thirteenth logic gate e5 corresponds to an AND gate and is connected to a first input to the output of the fourth logic gate 34 and a second input connected to the output of the twelfth logic gate e4. The output of the thirteenth logic gate e5 is connected to an input of the fifth logic gate 35 connected. Furthermore, the fourteenth logic gate e6 is an AND gate and has a first input to the output of the seventh logic gate 37 and a second input connected to the output of the tenth logic gate e2. The output of the fourteenth logic gate e6 is connected to an input of the eighth logic gate 38 connected.

Taking the above-mentioned definition of the gate groups, according to which the first group of processing gates corresponds to those gates which are necessary for calculating the first binary output signal s _i , the second group of processing gates corresponds to those gates which are used to calculate the second binary output signal s _i are necessary and the set of control gates comprises those logic gates in which at least one input depends exclusively on one or more control signals, the second logic gate would become the first group of processing gates 32 , the third logic gate 33 , the seventh logic gate 37 , the eighth logic gate 38 , the ninth logic gate e1, the tenth logic gate e2, the eleventh logic gate e3 and the fourteenth logic gate e6 belong. The second group of processing gates would be the second logic gate 32 , the fourth logic gate 34 , the fifth logic gate 35 , the sixth logic gate 36 , the eighth logic gate e1, the eleventh logic gate e3, the twelfth logic gate e4 and the thirteenth logic gate e5. Furthermore, the ninth to fourteenth logic gates e1, e2, e3, e4, e5, e6, which are also called first to sixth control gates, belong to the group of control gates.

The second logic gate 32 , the ninth logic gate e1 and the eleventh logic gate e3 are common processing gates of the first group of processing gates and the second group of processing gates.

The first logic gate 31 calculates an auxiliary output signal in the form of the generate signal g _i . If the auxiliary output signal is processed further and / or provided again to the arithmetic unit as an input signal, as described, for example, in US Pat 3 by the carry pre-computation unit (providing carry signals based on the generate signal), the first logic gate (or generally such logic gates, logic gates, such as the gates of the carry pre-computation unit) as part of the first group of processing gates and the second group of processing gates and thus, like the second logic gate 32 , the ninth logic gate e1 and the eleventh logic gate e3, are considered as a common processing gate.

The described structure of logic gates of the arithmetic unit A _i can be repeated in the further arithmetic unit of the arithmetic logic unit (other ALU cells). This allows input signals with multiple parallel bits (consisting of multiple first and second binary input signals) to be processed. Accordingly, an output signal having a plurality of parallel bits is then given by the combination of the first binary output signals or the second binary output signals of the arithmetic logic unit's arithmetic units.

The of the transmission prediction unit 830 provided carry signals c _i , c _i-1 can be adjusted by the control gates according to the selected algebraic function.

To simplify the explanation, this ALU cell A _{i is} also referred to below as ALU CLA-1.

The ALU CLA-1 is implemented according to the techniques described above. With the help of two Kotrollsignalen m ₁ and m ₂ , an operation (algebraic function) is selected. The values of m ₁ and m ₂ and the corresponding operations are shown in the following table:

The addition is performed when m ₁ = 1 and m ₂ = 0. At the output of the control gate e3, the carry signal c _{i-1 is} implemented. The output of the control gate e6 is 0 and the propagate signal p _i is passed through the OR gate 38 propagated and with c _i-1 verxoriert (processed according to an XOR operation). As a result, the output s _{i implements} the sum. Thanks to the "1" at the output of gate e4, the NOR gate implements 35 the auxiliary function ƒ _i (the auxiliary function has already been described above) and the negated sum is implemented at the output s _i .

In the case of the logical AND operation (AND function), both control signals m ₁ and m _{2 are} equal to "1". As a result, the outputs of the control gates e3 in all ALU cells are equal to "1" and, as a consequence, the carry signals c _i-1 and c _{i are also} equal to "1". To implement the AND function, the input b _i (the second input signal) is first inverted by x 2ing it with m ₂ = 1 (XOR gate 37 ) becomes. Then the inverted input b _i with the propagation signal p _i ORED (OR gate 38 ), because the output of the control gate e2 is "1". Finally will b _i ∨ a _i ⊕ b _i inverted by being versed with c _i-1 = 1. The inverse of the AND function, NAND function, is output s _i implements, because the carries c _i-1 and c _{i are} equal to "1". This can be tested by using c _i-1 = 1 and c _i = 1 in Equation 3.

The OR operation is selected when m ₁ and m _{2 are} equal to "0".

In this case, the outputs of the control gates e3 in all ALU cells are equal to "0". For m ₂ = 0, the input b _i comes through the XOR gate 37 without changes through and is ORed with the propagation signal p _i (OR gate 38 ). The control gate e6 does not block the input b _i . Because c _i-1 "0", the function b _i ⊕ p _i = a _i b _i ∨ to the output s _i is propagated. The exit s _i implements the NOR function because c _i-1 and c _{i are} equal to "0". This can be tested by using c _i-1 = 0 and c _i = 0 in Equation 3.

For the XOR operation, the control signals m ₁ and m _{2 are set} to "0" and corresponding to "1". m ₁ = 0 sets the outputs of the control gate e3 in all ALU cells to "0". In this case, c _i-1 and c _{i are} equal to "0". The control gates e5 and e6 block the output signals of the gates 34 and 37 , Thus, the output s _{i implements} the propagation function p _i = a _i b _i and the output s _i implements the negated propagator function

The proposed ALU may also be easily integrated, for example, into a data path using two-rail code, because at its outputs s and s also the two-rail code is implemented. Likewise, the proposed ALU z. In a data path that is checked using a parity code.

The proposed self-checking ALU can detect all single stuck-at faults. An adhesion error is, for example, an error in which a signal (eg output of a logic gate) is permanently stuck at a fixed logic level (0 or 1).

Detection of the various possible detention errors is considered below:
Errors in the operands a and b, which falsify an odd number of bits in the operands, can be detected by comparing p _a ⊕ p _b with p (a ⊕ b).

All single sticking errors in the XOR tree for. the implementation of the parity p (a ⊕ b) and in the XOR gate for the implementation of p _a ⊕ p _b can be identified by comparing p _a ⊕ p _b with p (a ⊕ b). The gates of the XOR tree can be z. For example, there may be gates that are not assigned to any of the three groups of gates (first group, second group, and group of control gates).

All individual sticking faults in the ALU cell ALU-CLA-1 can be B. be recognized as follows:
Error in the gate 31 falsify the generate signal g _i . As a result, the carry pre-computation unit implements 830 (Carry look-ahead unit) a faulty carry signal c _i , which is applied to the next ALU cell A _{i + 1} . In the A _{i + 1} c _i for the implementation of s _{i + 1} and s _{i + 1} used and forwarded to the ALU cell A _i . In A _i , c _{i is} only used for the implementation of s _i used. The considered error is by comparing s _i with s _i recognized. For the logical operations, the error is redundant because the control signals m ₁ and m ₂ control the output of the control gate e3 independently of the value of c _i .

Error in the gate 32 are detected by comparing the parity p (a ⊕ b) with the parity p _a ⊕ p _b . gate 32 implements the propagate signal p _i . Because p _{i is} always checked, it can be used for the implementation of s _i and s _i to be shared. If the propagate signal p _i , which is applied to the carry look-ahead unit, mixed, then this is like a mistake in the gate 31 recognized.

Errors in the carry prediction unit can be similar to errors in the gates 31 and 32 be recognized.

Error in the gate 37 . 38 and 33 cause a faulty output s _i . They are by comparing s _i with s _i recognized.

Because of the mistakes in the gates 34 . 35 and 36 becomes the output s _i falsified. The considered errors are recognized by s _i and s _i compares.

For errors in the control gates e1 and e3, the carry signal c _{i-1 is} faulty. This is done by comparing s _i-1 with s _i-1 recognized.

Errors in the control gates e2 and e6 falsify the output s _i and are detected by s _i and s _i compares.

Due to errors in the control gates e4 and e5 the output becomes s _i faulty. The considered errors become with the comparison of s _i with s _i discovered.

In 3 The arithmetic logic unit shown is an example of a self-checking ALU cell A _i based on a carry-ahead-adder parallel adder. In alternative arithmetic logic units, while maintaining the other features, the gate can also be used 32 double and use the doubled gate exclusively for the implementation of the outputs s. In addition, the described auxiliary function f _i can be used to calculate an output signal.

4 shows a block diagram of an arithmetic logic unit 400 for processing a first binary input signal a _i and a second binary input signal b _i corresponding to a selectable one algebraic function according to an embodiment of the invention. The arithmetic logic unit 400 based like the one in 3 shown arithmetic logic unit on a parallel adder with carry pre-calculation and comprises a computing unit A _i , a carry pre-calculation unit 830 and an error detector, not shown. The arithmetic unit A _i receives as input the first binary input signal a _i , the second binary input signal b _i , a first control signal m ₁ , a second control signal m ₂ , a third control signal m ₃ , a carry signal c _{i-1 of} a preceding arithmetic unit and a own carry signal c _{i of} the arithmetic unit A. As output signals, the arithmetic unit A _i creates the first binary output signal s _i , the second binary s _i , a generate signal g _i and a propagate signal p _i . The carry-ahead calculation unit 830 can based on the generate signals g _i and the propagation signals p _i of the arithmetic logic unit of the arithmetic logic unit 400 calculate the carry signals c _i and the arithmetic units 110 provide.

The arithmetic unit A _i comprises a first to fourteenth logic gate. The first logic gate 31 corresponds to an AND gate and receives the second binary input signal b _i at a first input and the first binary input signal a _i at a second input. The output of the first logic gate 31 is connected to an input of the ninth logic gate e1, and sets the Generate signal g _i are available. The second logic gate 32 corresponds to an XOR gate and receives the second binary input signal b _i at a first input and the first binary input signal a _i at a second input. The output of the second logic gate 32 is connected to an input of the eleventh logic gate e3, to an input of the fifth logic gate 35 and with an input of the eighth logic gate 38 connected and provides the propagate signal p _i at an output of the arithmetic unit A _i available. The third logic gate 33 corresponds to a further XOR gate and receives at a first input a carry signal c _{i-1 of} the preceding arithmetic unit and is provided with a second input having an output of the eighth logic gate 38 connected. The third logic gate 33 provides at its output the first binary output signal s _i . Furthermore, the fourth logic gate corresponds 34 an XOR gate and receives at a first input the first binary input signal a _i and at a second input the carry signal c _{i-1 of} the previous arithmetic unit provided. The output of the fourth logic gate 34 is connected to an input of the thirteenth logic gate e5. The fifth logic gate 35 corresponds to a NOR gate and is connected to a first input to the output of the second logic gate 32 and a second input connected to the output of the thirteenth logic gate e5. The output of the fifth logic gate 35 is with an input of the sixth logic gate 36 connected. The sixth logic gate 36 corresponds to an XOR gate and receives at a first input the carry signal c _i of its own arithmetic unit A _i provided and is connected to a second input to the output of the fifth logic gate 35 connected. The sixth logic gate 36 provides at its output the second binary output signal s _i to disposal. The seventh logic gate 37 corresponds to a further XOR gate, and receives at a first input the second binary input signal b _i and provided to a second input of the second control signal m _2. The output of the seventh logic gate 37 is connected to an input of the fourteenth logic gate e6. The eighth logic gate is an OR gate and has a first input to the output of the second logic gate 32 and a second input connected to the output of the fourteenth logic gate e6. The output of the eighth logic gate 38 is with an input of the third logic gate 33 connected. The ninth logic gate e1 corresponds to a further OR gate and receives the second control signal m ₂ at a first input. A second input is connected to the output of the first logic gate 31 connected and the output of the ninth logic gate e1 is connected to an input of the tenth logic gate e2. The tenth logic gate e2 corresponds to an AND gate and receives the first control signal m ₁ provided at a first input. Furthermore, the tenth logic gate e2 is connected to the output of the ninth logic gate e1 with a second input and provides at its output the generate signal g _i at an output of the arithmetic unit A _i . The tenth logic gate e3 receives the first control signal m ₁ at a first input and corresponds to an AND gate. A second input of the tenth logic gate e3 is connected to the output of the second logic gate 32 connected. Furthermore, the eleventh logic gate e3 provides the propagation signal p _i at its output. The twelfth logic gate e4 corresponds to a NAND gate (NAND gate) and receives the second control signal m ₂ at a first input and the first control signal m ₁ at a second inverted input. The output of the twelfth logic gate e4 is connected to an input of the thirteenth logic gate e5. The thirteenth logic gate e5 corresponds to an AND gate and has a first input to the output of the fourth logic gate 34 and a second input connected to the output of the twelfth logic gate e4. The output of the thirteenth logic gate e5 is connected to an input of the fifth logic gate 35 connected. The fourteenth logic gate e6 corresponds to an AND gate and receives the third control signal m ₃ provided at a first input. A second input of the fourteenth logic gate e6 is connected to the output of the seventh logic gate 37 and the output of the fourteenth logic gate e6 is connected to an input of the eighth logic gate 38 connected.

According to the previous definition of the gate groups, the second logic gate belongs 32 , the third logic gate 33 , the seventh logic gate 37 , the eighth logic gate 38 and the fourteenth logic gate e6 to the first group of processing gates and the second logic gate 32 , the fourth logic gate 34 , the fifth logic gate 35 , the sixth logic gate 36 , the twelfth logic gate e4 and the thirteenth logic gate e5 to the second group of processing gates. The ninth to fourteenth logic gates belong to the definition of the group of control gates.

The second logic gate 32 is a common processing gate of the first group of processing gates and the second group of processing gates.

The first logic gate 31 , the ninth logic gate e1 and the tenth logic gate e2 calculate an auxiliary output signal in the form of the generate signal g _i . Likewise, the eleventh logic gate e3 provides the propagation signal p _i generated by the second logic gate as an auxiliary output signal. If an auxiliary output signal is further processed and / or provided to the arithmetic unit as an input signal again, as described, for example, in US Pat 4 by the carry pre-computation unit (providing carry signals based on the generate signal and the propagate signal), the first logic gate may 31 , the ninth logic gate e1, the tenth logic gate e2, and the eleventh logic gate e3 (or, more generally, such logic gates as, for example, the gates of the carry prediction unit) as part of the first group of processing gates and the second group of processing gates and thus, like the second logic gate 32 , be regarded as a common processing gate.

Unlike the example from 3 is the generate signal g _i at the output of the first logic gate 31 not this time directly the transmission pre-calculation unit 830 but is adjusted by the ninth logic gate e1 and the tenth logic gate e2 according to the selected algebraic function. As a result, indirectly from the Übertragungsvorausberechnungseinheit 830 provided transmission signals c _i , c _{i-1 are} affected.

To simplify the following explanations, the in 4 ALU cell shown below referred to as ALU-CLA-2.

ALU-CLA-2 is also implemented according to the techniques described above. In this embodiment, three control signals m ₁ , m ₂ and m ₃ are used. The values of m ₁ , m ₂ and m ₃ and the corresponding operations are shown in the following table:

The addition is carried out when m ₁ = 1, m ₂ = 0 and m ₃ = 0. By m ₁ = 1 and m ₂ = 0, the propagate signal p _i and the generate signal g _i in each ALU cell are passed through the control gates e1, e2 and e3 and to the inputs of the carry look ahead unit (carry prediction unit ). Thus, the carry look-ahead unit implements the carry signals (carry signals) for each ALU cell. m ₃ = 0 blocks the output signal of the XOR gate 37 and the propagate signal p _i is unchanged with the carry signal c _i-1 (XOR gate 33 ) to implement the sum at the output s _i . Thanks to the "1" at the output of the control gate e4 (m1 = 1 and m ₂ = 0), the NOR gate implements 35 the auxiliary function ƒ _i and the negated sum is output s _i implemented.

In the case of the logical AND operation, all the control signals m ₁ , m ₂ and m _{3 are} equal to "1". By m ₁ = 1 and m ₂ = 1, all propagate and generate signals applied to the inputs of the carry look-ahead unit are equal to "1" and as a result all carry signals (including c _i-1 and c _i ) equals "1". To implement the AND function, the input b _{i is} first inverted by x 2ing it with m ₂ = 1 (XOR). gate 37 ) becomes. Then the inverted input b _i with the propagation signal p _i ORED (OR gate 38 ), because m ₃ = 1 is present at the input of the control gate e6. Finally will b _i ∨ a _i ⊕ b _i inverted by being versed with c _i-1 = 1. The inverse of the AND function, NAND function, is output s _i implemented because the carry c _i-1 and c _i (carry signals) are equal to "1". This can be tested by using c _i-1 = 1 and c _i = 1 in Equation 3.

The OR operation is selected when m ₁ and m _{2 are} equal to "0" and m ₃ equal to "1". Because m ₁ = 0, all carry signals (including c _i-1 , and c _i ) are equal to "0". For m ₂ = 0, the input b _i comes through the XOR gate 37 without changes through and is ORed with the propagation signal p _i (OR gate 38 ). The control gate e6 does not block the input b _i (m ₃ = 1). Because c _i-1 "0", the function b _i ⊕ p _i = a _i b _i ∨ to the output s _i is propagated. The exit s _i implements the NOR function because c _i-1 and c _{i are} equal to "0". This can be tested by using c _i-1 = 0 and c _i = 0 in Equation 3.

For m ₁ = 0, m ₂ = 1 and m ₃ = 0, XOR operation is selected. Because m ₁ = 0, all carry signals (including c _i-1 and c _i ) are equal to "0". The control gates e5 and e6 block the output signals of the gates 34 and 37 , Thus, the output s _{i implements} the propagation function p _i = a _i b _i and the output s _i implements the negated propagator function

Except the control logic (gates e1 - e6) only two gates (XOR gates 37 and OR gates 38 ) per ALU cell (ALU-CLA-1 or ALU-CLA-2) (with respect to eg 8th ) to implement the logical operations. The carry look-ahead unit is not doubled in the ALU-CLA-1 and ALU-CLA-2. Therefore, the hardware overhead of the proposed self-verifying ALU is lower than the hardware overhead in the method of duplication and comparison and comparable to the hardware overhead of a parity-verified ALU (e.g., "M. Nicolaidis." Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Pat. 5450340 , 1995 ").

In the ALU-CLA-1, carry signals are manipulated directly using the control gates e1 and e3. By contrast, the control logic of the ALU CLA-2 (control gates e1, e2 and e3) manipulates propagation and generation signals and thereby indirectly the carry signals. When carry signals are to be set to "0", the Carry Look-Ahead unit is simply turned off by setting all propagate and generate signals to "0". This can reduce power consumption.

In the ALU-CLA-2, three control signals m ₁ , m ₂ and m ₃ are used. Thus, eight (2 ³ = 8) possible operations can be coded. Four of them are illegal operations (see previous table). In the case of an illegal operation, different functions on the outputs s _i and s _i the ALU-CLA-2 implemented. Because these functions are not inverse to each other, the condition is s _i ≠ s _i not always met and the illegal operation is recognized. The control signal m ₃ has z. B. inverse parity of the Kotrollsignalen m ₁ and m ₂ . As a result, errors can be detected that falsify an odd number of control signals.

The proposed self-checking ALU can detect all single stuck-at faults. An adhesion error is, for example, an error in which a signal (eg output of a logic gate) is permanently stuck at a fixed logic level (0 or 1).

Detection of the various possible detention errors is considered below:
Errors in the operands a and b _i, which falsify an odd number of bits in the operands, can be detected by comparing p _a ⊕ p _b with p (a ⊕ b).

All individual sticking errors in the XOR tree for the implementation of the parity p (a ⊕ b) and in the XOR gate for the implementation of p _a ⊕ p _b can be calculated by comparing p _a ⊕ p _b with p (a ⊕ b ) be recognized.

For example, all individual sticking faults in the ALU cell ALU-CLA-2 can be recognized as follows:
Error in the gate 31 falsify generate signal g _i . As a result, carry look-ahead unit implements an erroneous carry signal c _i . In A _i , c _{i is} only used for the implementation of s _i used. The considered error is by comparing s _i with s _i recognized. For the logical operations, the error is redundant because the control signals m ₁ and m ₂ control the output of the control gate e2 independently of the value of g _i .

Error in the gate 32 are detected by comparing the parity p (a ⊕ b) with the parity p _a ⊕ p _b . gate 32 implements the propagate signal p _i . Because p _{i is} always checked, it can be used for the implementation of s _i and s _i to be shared. If the propagate signal p _i , which is applied to the carry look-ahead unit, falsified, then this is similar to errors in the gate 31 recognized.

Errors in the carry prediction unit can be similar to errors in the gates 31 and 32 be recognized.

Error in the gate 37 . 38 and 33 cause a faulty output s _i . They are by comparing s _i with s _i recognized.

Because of the mistakes in the gates 34 . 35 and 36 becomes the output s _i falsified. The considered errors are recognized by s _i and s _i compares.

Because of the errors in the Kotrollgatter e1, e2 and e3 Generate signal are _i and g propagated distorted signal p _i, which are applied to the carry look-ahead unit. As a consequence, Carry Look-Ahead unit implements a faulty carry signal c _i that is used in the ALU cell A _i for the implementation of s _i is used. The considered errors become with the comparison of s _i with s _i discovered.

Errors in the control gates e4 and e5 cause the faulty output s _i , They are compared by s _i with s _i recognized.

Because of the errors in the control gate e6, the output s _i becomes faulty. This is recognized by s _i and s _i compares.

Errors in the control signals m ₁ , m ₂ and m ₃ , which falsify an odd number of them, are recognized because m _{3 has} the inverse parity of m ₁ and m ₂ . For these errors, the illegal operations are selected. From the previous table, it can be seen that in each of the illegal operations the functions that are at the outputs s _i and s _i are executed, not inverse to each other. This will be the condition s _i ≠ s _i not always met and the illegal operation is detected.

The arithmetic logic unit 400 represents, for example, a self-verifying ALU cell A _i on the basis of parallel adders with carry-ahead-ahead adder or more precisely a sum bit carry adder with a sum bit carry-ahead adder.

Some embodiments according to the invention are based on the principle of a standard ripple adder or a fast-ripple adder, as described, for example, in US Pat 9 and 10 is shown.

In a conventional ripple adder cell or carry ripple adder cell, the sum bit s _i according to Equation 1 and the carry bit c _i z. For example, according to the formula: c _i = a _i b _i ∨ (a _i ⊕ b _i ) c _i-1 = g _i ∨ p _i c _i-1 (4) certainly. The adder cells are sequentially chained. To calculate the highest order sum bit (MSB), the carry bits in all previous cells must be determined. This causes a significant delay in the calculation of the sum. This delay can be reduced if the Fast Ripple Adder cells from "MJ Smith. Application-Specific Integrated Circuits. Adison Wesley, Reading, MA, 1997. ". In the fast ripple adder cells a simple carry signal c _j of the conventional cell (equation 4) by two carry signals C1 _j and C2 _j is replaced, where j is a straight index, and replaced by C3 _j and C4 _j, where j is an odd Index is, replaced:

The Fast Ripple adder can z. B. be comparatively fast, because the delay for the calculation of the carry signals of a delay of the NAND gate 94 per adder cell corresponds.

The Fast Ripple Adder has been used in the design of various self-checking adders (e.g., D. Marienfeld and V. Ocheretnij and M. Gössel and ES Sogomonyan, Partially Duplicated Code-Disjoint Carry Skip Adder Proceedings of the 7th IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI Systems, pages 78-86, 2002; ES Sogomonyan and D. Marienfeld and V. Ocheretnij and M. Gössel A New Self-Checking Sum Bit-Duplicated Carry Select Adder Proceedings of Design, Automation and Test in Europe Conference - DATE, pages 1360-1361, 2004; ES Sogomonyan and D. Marienfeld and V. Ocheretnij and M. Gössel Self-Checking Carry Select Adder with Sum Bit-Duplication Proceedings of ARCS - Organic and Pervasive Computing, pages 84-91, 2004 ").

A new self-checking Fast Ripple adder has been developed. Two consecutive cells of the proposed adder are in 9 shown. To simplify the explanations, they are referred to as FR-ADD below.

FR-ADD implements both sum bits s _i and s _{i + 1} (sum bits) as well as the corresponding negated sum bits s _i and s _{i + 1} , The gates of 91 to 96 make the Fast Ripple adder from "MJ Smith. Application-Specific Integrated Circuits. Adison Wesley, Reading, MA, 1997. "In order to implement the negated sum bits, the auxiliary function ƒ (Equation 2) is used. The additional hardware overhead consists of only three gates (97-99) per cell. The propagate signal p _i is divided in the cell A _i for the implementation of s _i , ƒ _i and C3 _i . Accordingly, the propagate signal p _{i + 1 is divided} for the implementation of s _{i + 1} , ƒ _{i + 1} and C1 _{i + 1} . The gates 95 implement carry signals c _i-1 and c _i which are connected to the previous cells (c _i-1 to A _i-1 and c _i to A _i ).

In both arithmetic units A _i , A _{i + 1 shown} , the logic gates 92 . 95 and 96 used to calculate the sum bit s _i and the logic gates 92 . 95 . 97 . 98 and 99 to calculate the negated s _i used. Furthermore, the logic gates are used 91 . 93 and 94 for providing auxiliary output signals needed to calculate carry signals c _i (carry signal). The two arithmetic units A _i , A _{i + 1} differ only by the logic gate 91 Which is an OR gate in the arithmetic unit A _i, a NAND gate and in the arithmetic unit A _{i + 1,} and the logic gate 95 Which is in the arithmetic unit A _i an AND gate and in the arithmetic unit A _{i + 1} is a non-AND gate.

11 shows a block diagram of an arithmetic logic unit 1100 for processing a first binary input signal a _i and a second binary input signal b ₁ according to a selectable algebraic function according to an embodiment of the invention. The arithmetic logic unit 1100 comprises a computing unit A _i and a fault detector, not shown.

The arithmetic unit A _i is connected to the error detector, not shown, as well as optionally to a preceding and / or a subsequent arithmetic unit. The arithmetic unit A _i are as input signals the first binary input signal a _i , the second binary input signal b _i , a first control signal m _l , a second control signal m ₂ , a carry signal c _{i-1 of} a previous arithmetic unit and a separate carry signal c _{i of} the arithmetic unit A _i provided. Conversely, the arithmetic unit A _i, the first binary output signal s _i , the second binary s _i , a propagate signal p _i and a carry signal c _{i-1 of} a preceding arithmetic unit.

The arithmetic unit A _i comprises a first to sixteenth logic gate. Here is the first logic gate 71 an AND gate, and combines the first binary input signal a _i and the second binary input signal b _i according to a logical AND operation and is connected to an output with an input of the fourth logic gate 74 connected. At the second logic gate 72 If it is an XOR gate, to whose inputs the first binary input signal a _i and the second binary input signal b _i abut, and corresponding to a logical XOR function, the propagating signal p _i generated at an output of the arithmetic unit A _i provides. The second logic gate 72 represents the propagate signal p _i both as an auxiliary output signal and as an input signal for the third logic gate 73 , the fifth logic gate 75 and the eighth logic gate 78 to disposal. The third logic gate 73 corresponds to an XOR gate and is connected to a first input to an output of the second logic gate 72 connected and gets at a second input the carry signal c _{i-1 of} the previous processor provided. The third logic gate 73 is with an output with an input of the fourth logic gate 74 connected. The fourth logic gate 74 corresponds to an OR gate and is connected to a first input to the output of the first logic gate 71 and a second input having an output of the third logic gate 73 connected. The output of the fourth logic gate 74 provides the own carry signal c _i . The fifth logic gate 75 is another OR gate, wherein a first input of the fifth logic gate 75 with the output of the second logic gate 72 and a second input of the fifth logic gate 75 with an exit of the fifteenth Logic gate e5 is connected. The output of the fifth logic gate 75 is with an input of the sixth logic gate 76 connected. The sixth logic gate 76 corresponds to an XOR gate and receives the carry signal c _{i-1 of} the preceding arithmetic unit at a second input. A first input of the sixth logic gate 76 is at the output of the fifth logic gate 75 connected. The output of the sixth logic gate 36 provides the first binary output signal s _i . Furthermore, the seventh logic gate corresponds 77 an XOR gate and receives at a first input the first binary input signal a _i provided and is connected to a second input to an output of the thirteenth logic gate e3. The output of the seventh logic gate 77 is connected to an input of the fifteenth logic gate e5. The eighth logic gate 78 corresponds to a NOR gate and is connected to a first input to the output of the second logic gate 72 and a second input connected to the output of the fifteenth logic gate e5. The output of the eighth logic gate 78 is with an input of the ninth logic gate 79 connected. The ninth logic gate 79 corresponds to an XOR gate and receives at a second input its own carry signal c _i provided and is connected to a second input to the output of the eighth logic gate 78 connected. The output of the ninth logic gate 79 represents the second binary output signal s _i to disposal. The tenth logic gate 70 corresponds to an XOR gate and receives at a first input the second binary input signal b _i and at a second input of the second control signal m ₂ provided. The output of the tenth logic gate 70 is connected to an input of the sixteenth logic gate e6. Furthermore, the eleventh logic gate e1, which corresponds to an OR gate, receives the carry signal c _{i-1 of} the preceding arithmetic unit at a first input and the second control signal m ₂ at a second input.

The output of the eleventh logic gate e1 is connected to an input of the thirteenth logic gate e3. The twelfth logic gate e2 corresponds to an XNOR gate and receives the second control signal m ₂ at a first input and the first control signal m ₁ at a second input. The output of the twelfth logic gate e2 is connected to an input of the sixteenth logic gate e6. The thirteenth logic gate corresponding to an AND gate E3 and is connected to a first input to the output of said eleventh logic gate e1 and receives at a second input the first control signal m ₁ is provided. The output of the thirteenth logic gate e3 is connected to an input of the sixth logic gate 76 and an input of the seventh logic gate 77 connected and provides the carry signal c _{i-1 of} the previous processing unit. Furthermore, the fourteenth logic gate corresponding to e4 a NAND gate and receives at a first input the second control signal provided m ₂ and at a second inverted input of the first control signal m. ₁ The output of the fourteenth logic gate e4 is connected to an input of the fifteenth logic gate 75 connected. The fifteenth logic gate e5 corresponds to an AND gate and has a first input to the output of the seventh logic gate 77 and a second input connected to the output of the fourteenth logic gate e4. The output of the fifteenth logic gate e5 is connected to an input of the eighth logic gate 78 connected. The sixteenth logic gate e6 corresponds to an AND gate and has a first input to the output of the tenth logic gate 70 and a second input connected to the output of the twelfth logic gate e2. The output of the sixteenth logic gate e6 is connected to an input of the fifth logic gate 75 connected.

Taking the above-mentioned definition of the gate groups, according to which the first group of processing gates corresponds to those gates necessary for calculating the first binary output signal s _i , the second group of processing gates corresponds to those gates used to calculate the second binary output signal s _i are necessary and the set of control gates comprises those logic gates in which at least one input depends exclusively on one or more control signals, the second logic gate would become the first group of processing gates 72 , the fifth logic gate 75 , the sixth logic gate 76 , the tenth logic gate 70 , the eleventh logic gate e1, the twelfth logic gate e2, the thirteenth logic gate e3 and the sixteenth logic gate e6 belong. The second group of processing gates would be the second logic gate 72 , the seventh logic gate 77 , the eighth logic gate 78 , the ninth logic gate 79 , the eleventh logic gate e1, the thirteenth logic gate e3, the fourteenth logic gate e4 and the fifteenth logic gate e5. Furthermore, the group of control gates includes the eleventh to fifteenth logic gates e1, e2, e3, e4, e5, e6, which are also called first to sixth control gates.

The second logic gate 72 , the eleventh logic gate e1 and the thirteenth logic gate e3 are common processing gates of the first group of processing gates and the second group of processing gates.

The first logic gate 71 , the third logic gate 73 and the fourth logic gate 74 calculate an auxiliary output signal in the form of its own carry signal c _i . If an auxiliary output signal is further processed by a computing unit, as described, for example, in US Pat 11 by a subsequent arithmetic unit of the case can be, so can first logic gates 71 , the third logic gate 73 and the fourth logic gate 74 (or in general, such logic gates) as part of the first group of processing gates and the second group of processing gates of the subsequent processing unit and thus, as the second logic gate 72 , the eleventh logic gate e1 and the thirteenth logic gate e3 of the subsequent arithmetic unit, are regarded as the common processing gate of the subsequent arithmetic unit. As a result, the first logic gate 71 , the third logic gate 73 and the fourth logic gate 74 a previous arithmetic unit as a common processing gate of the arithmetic unit A _{i are} considered.

The described structure of logic gates of the arithmetic unit A _i can be repeated in the further arithmetic unit of the arithmetic logic unit (other ALU cells). This allows input signals with multiple parallel bits (consisting of multiple first and second binary input signals) to be processed. Accordingly, an output signal having a plurality of parallel bits is then given by the combination of the first binary output signals or the second binary output signals of the arithmetic logic unit's arithmetic units.

5 shows a visual diagram of an arithmetic logic unit 500 for processing a first binary input signal a _i and a second binary input signal b ₁ according to a selectable algebraic function according to an embodiment of the invention. The arithmetic logic unit 500 comprises a first arithmetic unit A _i , a second arithmetic unit A _{i + 1} and an error detector, not shown.

The arithmetic unit A _i receives as input signals the first binary input signal a _i , the second binary input signal b _i , a first auxiliary carry signal C1 _{i-1 of} the preceding arithmetic unit, a second auxiliary carry signal C2 _{i-1 of} the preceding arithmetic unit, a first control signal m ₁ second control signal m ₂ and a separate carry signal c _{i of} the arithmetic unit A _i provided. The arithmetic unit A _i supplies the first binary output signal s _i and the second binary output signal as an output signal s _i , a propagate signal p _i , a carry signal c _{i-1 of} the preceding arithmetic unit, a first self-auxiliary carry signal C3 _i and a second own auxiliary carry signal C4 _i .

The arithmetic unit A _{i + 1} forms the following arithmetic unit of the arithmetic unit A _i, and vice versa, the arithmetic unit A _{i forms} the preceding arithmetic unit of the arithmetic unit A _{i + 1} . Accordingly, the arithmetic unit A _{i + 1} receives as input signals the first auxiliary carry signal C _{3 i of} the arithmetic unit A _i and the second auxiliary carry signal C4 _{i of} the arithmetic unit A _i and provides the carry signal c _{i to} the arithmetic unit A _i . Further input signals of the arithmetic unit A _{i + 1} are a first binary input signal a _{i + 1} , a second binary input signal b _{i + 1} , the first control signal m ₁ , the second control signal m ₂ and the own carry signal c _{i + 1 of} the arithmetic unit A _{i +1} . As further output signals, the arithmetic unit A _{i + 1} sets the first binary output signal s _{i + 1} , the second binary output signal s _{i + 1} , a first own auxiliary carry signal C1 _{i + 1 of} the arithmetic unit A _{i + 1} and a second own auxiliary carry signal C2 _{i + 1 of} the arithmetic unit A _{i + 1} ready.

The first arithmetic unit A _i comprises a first to seventeenth logic gate. The first logic gate 51 corresponds to a NAND gate (NAND gate) and receives at a first input the second binary input signal b _i and at a second input the first binary input signal a _i provided. Based on the two input signals represents the first logic gate 51 at an output the second own auxiliary carry signal C4 _i ready. The second logic gate 52 corresponds to an XOR gate and receives the second binary input signal b _i at a first input and the first binary input signal a _i at a second input. The output of the second logic gate 52 is with an input of the third logic gate 53 , with an input of the eighth logic gate 58 and with an input of the eleventh logic gate 11 connected and in addition to an output of the arithmetic unit A _i, the propagate signal p _i available. The third logic gate 53 corresponds to an AND gate and is connected to a first input to the output of the second logic gate 52 connected. Furthermore, the third logic gate gets 53 at a second input, the second auxiliary carry signal C2 _{i-1 of} the previous arithmetic unit and is provided with its output to an input of the fourth logic gate 54 connected. The fourth logic gate 54 corresponds to a NAND gate and has a first input to the output of the third logic gate 53 connected. In addition, the fourth logic gate gets 54 at a second input, the first auxiliary transmission signal C1 _i-1 provided and provides at its output the first own auxiliary carry signal C3 _{i of} the arithmetic unit A _i ready. The fifth logic gate 55 corresponds to an AND gate and receives the second auxiliary carry signal C2 _{i-1 of} the preceding arithmetic unit at a first input and the first auxiliary carry signal C1 _{i-1 of} the preceding arithmetic unit at a second input. The output of the fifth logic gate 55 is connected to an input of the twelfth logic gate e1. Furthermore, the sixth logic gate corresponds 56 an XOR gate and has a first input to the output of the eleventh logic gate 11 and a second input to the output of the fourteenth logic gate e3 connected. The sixth logic gate 56 provides at its output the first binary output signal s _i . The seventh logic gate 57 corresponds to an XOR gate and receives at a first input the first binary input signal a _i provided. Furthermore, the seventh logic gate 57 with a second input connected to the output of the fourteenth logic gate e3 and its output connected to an input of the sixteenth logic gate e5. The eighth logic gate 58 corresponds to a NOR gate and is connected to a first input to the output of the second logic gate 52 and a second input connected to the output of the sixteenth logic gate e5. The output of the eighth logic gate 58 is with an input of the ninth logic gate 59 connected. The ninth logic gate 59 is with a first input to the output of the eighth logic gate 58 connected and gets at a second input its own carry signal c _{i of} the arithmetic unit A _{i provided} by the arithmetic unit A _{i + 1} . The ninth logic gate 59 represents the second binary output signal s _i ready at his exit. The tenth logic gate 10 receives the second binary input signal b _i at a first input and the second control signal m ₂ at a second input. The output of the tenth logic gate 10 is connected to an input of the seventeenth logic gate e6. The eleventh logic gate 11 corresponds to an OR gate and is connected to a first input to the output of the second logic gate 52 and connected to a second input to the output of the sixteenth logic gate e6. The output of the eleventh logic gate 11 is with an input of the sixth logic gate 56 connected. The twelfth logic gate e1 corresponds to another OR gate and is connected to a first input to the output of the fifth logic gate 55 connected. In addition, the twelfth logic gate e1 receives the second control signal m ₂ at a second input and has its output connected to an input of the fourteenth logic gate e3. The thirteenth logic gate e2 corresponds to an XNOR gate and receives the second control signal m ₂ at a first input and the first control signal m ₁ at a second input. The thirteenth logic gate e2 has its output connected to an input of the seventeenth logic gate e6. The thirteenth logic gate e3 corresponds to an AND gate and is connected to a first input to the output of the twelfth logic gate e1. In addition, the fourteenth logic gate e3 receives the first control signal m ₁ at a second input and has its output connected to an input of the seventh logic gate 57 and with an input of the sixth logic gate 56 connected. In addition, the fourteenth logic gate e3 provides the carry signal c _{i-1 to} the previous arithmetic unit. The fifteenth logic gate e4 corresponds to a NAND gate and receives the second control signal m ₂ at a first input and the first control signal m ₁ at a second inverted input. The fifteenth logic gate e4 has its output connected to an input of the sixteenth logic gate e5. The sixteenth logic gate e5 corresponds to an AND gate and has a first input to the output of the seventh logic gate 57 and a second input connected to the output of fifteenth logic gate e4. The output of the sixteenth logic gate e5 is connected to an input of the eighth logic gate 58 connected. Furthermore, the seventeenth logic gate e6 corresponds to an AND gate and has a first input to the output of the tenth logic gate 10 and a second input connected to the output of the thirteenth logic gate e2. The output of the seventeenth logic gate e6 is connected to an input of the eleventh logic gate 11 connected.

The second arithmetic unit A _{i + 1} is up to the type of the first logic gate 51 and the type of the fifth logic gate 55 ident to the first arithmetic unit A _i . The first logic gate 51 the second arithmetic unit A _{i + 1} corresponds to an OR gate and the fifth logic gate instead of a NAND gate 55 the second arithmetic unit A _{i + 1} corresponds to a NAND gate (NAND gate) instead of an AND gate.

According to the aforementioned definition of the gate groups, the first group of processing gates comprises the second logic gate 52 , the fifth logic gate 55 , the sixth logic gate 56 , the tenth logic gate 10 , the eleventh logic gate 11 , the twelfth logic gate e1, the thirteenth logic gate e2, the fourteenth logic gate e3, and the seventeenth logic gate e6. Furthermore, the second group of processing gates comprises the second logic gate 52 , the fifth logic gate 55 , the seventh logic gate 57 , the eighth logic gate 58 , the ninth logic gate 59 , the twelfth logic gate e1, the fourteenth logic gate e3, the fifteenth logic gate e4 and the sixteenth logic gate e5. In addition, the twelfth to seventeenth logic gates e1, e2, e3, e4, e5, e6 are assigned to the group of control gates.

The group assignment of the logic gates of the first arithmetic unit A _i corresponding to the group assignment of the second arithmetic unit A _{i + 1} .

The second logic gate 52 , the fifth logic gate 55 , the twelfth logic gate e1 and the thirteenth logic gate e3 are common processing gates of the first group of processing gates and the second group of processing gates.

The third logic gate 53 and the fourth logic gate 54 Calculate based on the propagating signal p _i, an auxiliary output signal in the form of the first own auxiliary carry signal C3 _i. Likewise represents first logic gates 51 an auxiliary output signal in the form of the second own auxiliary carry signal C4 _i available. If an auxiliary output signal is further processed by a computing unit, as described, for example, in US Pat 5 by the subsequent arithmetic unit A _{i + 1 is} the case, then the first logic gate 51 , the third logic gate 53 and the fourth logic gate 54 (or in general such logic gates) as part of the first group of processing gates and the second group of processing gates of the subsequent processing unit A _{i + 1} and thus, like the second logic gate 52 , the fifth logic gate 55 , The twelfth logic gate e1 and the thirteenth logic gate e3 of the following arithmetic unit A _{i + 1,} as a common gate of the subsequent processing arithmetic unit A _{i + 1} are considered. As a result, the first logic gate 51 , the third logic gate 53 and the fourth logic gate 54 a previous arithmetic unit as a common processing gate of the arithmetic unit A _{i are} considered.

In order to be able to process input signals with more than two parallel bits, further arithmetic units can be hung on each other as required. In this case, computing units of the type of the first arithmetic unit A _i and arithmetic units of the type of the second arithmetic unit A _{i + 1} alternate, which are based on the first logic gate 51 and the fifth logic gate 55 differ, from.

For this example, the functionality of FR-ADD may be off 9 be extended with the help of the techniques described above. To simplify the explanation, these ALU cells are also referred to below as ALU-FR-1.

The control logic in the ALU-FR-1 is similar to the control logic of the ALU-CLA-1. The values of two control signals m ₁ and m ₂ and the corresponding operations are shown in the table given for ALU-CLA-1.

The proposed self-checking ALU can detect all single stuck-at faults. An adhesion error is, for example, an error in which a signal (eg output of a logic gate) is permanently stuck at a fixed logic level (0 or 1).

Detection of the various possible detention errors is considered below:
Errors in the operands a and b, which falsify an odd number of bits in the operands, can be detected by comparing p _a ⊕ p _b with p (a ⊕ b).

All individual sticking errors in the XOR tree for the implementation of the parity p (a ⊕ b) and in the XOR gate for the implementation of p _a ⊕ p _b can be calculated by comparing p _a ⊕ p _b with p (a ⊕ b ) be recognized.

For example, all individual sticking faults in the ALU cell A _i of ALU-FR-1 can be detected as follows:
Error in the gate 51 corrupt carry signal C4 _i . As a consequence, the gate implements 55 in the cell A _{i + 1} erroneous carry signal c _i , which in the cell A _i for the implementation of s _i is used. The considered error is by comparing s _i with s _i recognized. For the logical operations, the error is redundant because the control signals m ₁ and m ₂ control the output of the control gate e3 independently of the value of C4 _i .

Error in the gate 52 are detected by comparing the parity p (a ⊕ b) with the parity p _a ⊕ p _b . gate 52 implements the propagate signal p _i . Because p _{i is} always checked, it can be used for the implementation of s _i and s _i to be shared.

Because of the mistakes in the gates 53 and 54 Carry signal C3 _i becomes defective. The considered errors become similar to errors in the gate 51 recognized.

Error in the gate 55 corrupt carry signal c _i-1 that in cell A _i-1 for the implementation of s _i-1 is used. When comparing s _i-1 with s _i-1 the errors are discovered. The considered errors are redundant for the logical operations, because the control signals m ₁ and m ₂ control the output of the control gate e3 regardless of the value at the output of the gate 5 Taxes.

Error in the gate 10 . 11 and 56 cause a faulty output s _i . They are by comparing s _i with s _i recognized.

Because of the mistakes in the gates 57 . 58 and 59 becomes the output s _i falsified. The considered errors are recognized by s _i and s _i compares.

The previous considerations are also valid for errors in cell A _{i + 1} "of ALU-FR-1.

Errors in the control logic (gates e1-e6) are detected similar to errors in the control logic (control logic) of ALU-CLA-1.

In the arithmetic logic unit 500 these may be, for example, self-checking ALU cells A _i and A _{i + 1} on the basis of self-checking fast ripple adders.

6 shows a block diagram of an arithmetic logic unit 600 for processing a first binary input signal a _i , a _{i + 1} and a second binary input signal b _i , b _{i + 1} corresponding to a selectable algebraic function according to an embodiment of the invention. Like the in 5 ALU is based on the arithmetic logic unit 600 on a fast ripple adder approach. In contrast to the first arithmetic unit 5 receives the first arithmetic unit A _{i of} the ALU 600 in addition to the third control signal m ₃ , an inverted first control signal m ₁ and an inverted second control signal m ₂ provided. Likewise, the second arithmetic unit A _{i + 1 is replaced} by the second arithmetic unit 5 a third control signal m ₃ , an inverted first control signal m ₁ and an inverted second control signal m ₂ provided. However, the non-inverted first control signal m ₁ is not needed by the second arithmetic unit A _{i + 1} . The output signals of the first arithmetic unit A _i and the second arithmetic unit A _{i + 1 of} the ALU 600 correspond to the output signals of the first and the second arithmetic unit

5 ,

The first arithmetic unit A _i comprises a first to seventeenth logic gate. The first logic gate 51 corresponds to a NAND gate and receives the second binary input signal b _i at a first input and the first binary input signal a _i at a second input. The output of the first logic gate 51 is connected to an input of the thirteenth logic gate e2.

The second logic gate 52 corresponds to an XOR gate and receives the binary input signal b _i at a first input and the first binary input signal a _i at a second input. The output of the second logic gate 52 is with an input of the fourteenth logic gate e3, with an input of the eighth logic gate 58 and with an input of the eleventh logic gate 11 connected. In addition, the output of the second logic gate 52 connected to an output of the arithmetic unit A _i to provide the propagate signal p _i . The third logic gate 53 corresponds to an AND gate and is connected to a first input to the output of the fourteenth logic gate e3. In addition, the third logic gate gets 53 at a second input, the second auxiliary carry signal C2 _{i-1 of} the previous arithmetic unit and is provided with its output to an input of the fourth logic gate 54 connected. The fourth logic gate 54 corresponds to a NAND gate and has a first input to the output of the third logic gate 53 connected. Furthermore gets the fourth logic gate 54 the first auxiliary carry signal C1 _{i-1 of} the previous arithmetic unit available and provides at its output the first own auxiliary carry signal C3 _i the arithmetic unit A _i to the second arithmetic unit A _{i + 1} ready. The fifth logic gate 55 corresponds to an AND gate and receives at a first input the second auxiliary carry signal C2 _{i-1 of} the preceding arithmetic unit and provided at a second input of the first auxiliary carry signal C1 _{i-1 of} the preceding arithmetic unit. The output of the fifth logic gate 55 is with an input of the seventh logic gate 57 and an input of the sixth logic gate 56 connected. In addition, the fifth logic gate represents 55 the carry signal c _{i-1 of} the previous processor at an output of the arithmetic unit A _i ready. The sixth logic gate 56 corresponds to an XOR gate and has a first input to the output of the eleventh logic gate 11 and a second input to the output of the fifth logic gate 55 connected. The sixth logic gate 56 provides at its output the first binary output signal s _i . The seventh logic gate 57 corresponds to a further XOR gate and receives the first binary input signal a _i at a first input. In addition, the seventh logic gate 57 with a second input to the output of the fifth logic gate 55 and having its output connected to an input of the sixteenth logic gate e5. The eighth logic gate 58 corresponds to a NOR gate and is connected to a first input to the output of the second logic gate 52 and a second input connected to the output of the sixteenth logic gate e5. The output of the eighth logic gate 58 is with an input of the ninth logic gate 59 connected. The ninth logic gate 59 corresponds to an XOR gate and has a first input to the output of the eighth logic gate 58 connected. Furthermore, the ninth logic gate gets 59 at a second input the own carry signal c _{i of} the first Arithmetic unit A _i provided and provides at its output the second binary output signal s _i to disposal. The tenth logic gate 10 corresponds to an XOR gate and receives at a first input the second binary input signal b _i and at a second input the inverted second control signal m ₂ made available. The output of the tenth logic gate 10 is connected to an input of the seventeenth logic gate e6. The eleventh logic gate 11 corresponds to an OR gate and is connected to a first input to the output of the second logic gate 52 and a second input connected to the output of the seventeenth logic gate e6. The output of the eleventh logic gate 11 is with an input of the sixth logic gate 56 connected. The twelfth logic gate e1 corresponds to an OR gate and is provided with the second control signal m ₂ at a first input. Furthermore, the twelfth logic gate e1 is connected at a second input to the output of the thirteenth logic gate e2. At its output, the twelfth logic gate e1 provides the second own auxiliary carry-over signal C4 _{i to} the first processor A _i . The thirteenth logic gate e2 corresponds to an AND gate and is provided with the first control signal m ₁ at a first input. Furthermore, the thirteenth logic gate e2 has a second input to the output of the first logic gate 51 and its output connected to an input of the twelfth logic gate e1. Furthermore, the fourteenth logic gate e3 corresponds to an AND gate and is provided with the third control signal m ₃ at a first input. In addition, the fourteenth logic gate e3 has a second input to the output of the second logic gate 52 and with its output to an input of the third logic gate 52 connected. The fifteenth logic gate e4 corresponds to an OR gate and receives at a first input the inverted second control signal m ₂ and at the second input of the inverted first control signal m ₁ provided. The output of the fifteenth logic gate e4 is connected to an input of the fifteenth logic gate e5. The sixteenth logic gate e5 corresponds to an AND gate and has a first input to the output of the seventh logic gate 57 and connected to a second input to the output of the fifteenth logic gate e4. The output of the sixteenth logic gate e5 is connected to an input of the eighth logic gate 58 connected. The seventeenth logic gate e6 corresponds to an AND gate and has a first input to the output of the tenth logic gate 10 connected. Furthermore, the seventeenth logic gate e5 receives the inverted first control signal at a second input m ₁ provided uid is with its output to an input of the eleventh logic gate 11 connected.

The second arithmetic unit A _{i + 1} is constructed similar to the first arithmetic unit A _i . However, the second arithmetic unit A _{i + 1} comprises an eighteenth logic gate e7 and additionally differs in the first, fifth, twelfth and thirteenth logic gates. The first logic gate 51 the second arithmetic unit A _{i + 1} corresponds to an OR gate and the fifth logic gate instead of a NAND gate 55 The second arithmetic unit A _{i + 1} does not correspond to an AND gate but to a NAND gate. Furthermore, the twelfth logic gate e1 still corresponds to an OR gate, but is connected with its first input to the output of the thirteenth logic gate e2 and with its second input to the output of the eighteenth logic gate e7. The output of the twelfth logic gate e1 provides the second auxiliary carry signal C2 _{i + 1} for the subsequent processing unit. The additional eighteenth logic gate e7 corresponds to an XNOR gate and receives the second control signal m ₂ at a first input and the third control signal m ₃ at a second input. The output of the eighteenth logic gate e7 is connected to an input of the twelfth logic gate e1.

According to the previous definition of the groups, the second logic gate is 52 , the fifth logic gate 55 , the sixth logic gate 56 , the tenth logic gate 10 , the eleventh logic gate 11 and the seventeenth logic gate e6 is part of the first group of processing gates. Furthermore belong the second logic gate 52 , the fifth logic gate 55 , the seventh logic gate 57 , the eighth logic gate 58 , the ninth logic gate 59 , the fifteenth logic gate e4 and the sixteenth logic gate e5 to the second group of processing gates. The group of control gates of the first arithmetic unit A _i comprises the twelfth to seventeenth logic gates. In addition, the group of control gates of the second arithmetic unit A _{i + 1} comprises the eighteenth logic gate e7.

The second logic gate 52 and the fifth logic gate 55 are a common processing gate of the first group of processing gates and the second group of processing gates.

The third logic gate 53 , the fourth logic gate 54 and the fourteenth logic gate E3, and the eighteenth logic gate e7 in the second arithmetic unit A _{i + 1,} calculated based on the propagating signal p _i, an auxiliary output signal in the form of the first own auxiliary carry signal C3 _i. Similarly, first logic gates 51 , the twelfth logic gate e1 and the thirteenth logic gate e2 an auxiliary output signal in the form of the second own auxiliary carry signal C4 _i available. If an auxiliary output signal is further processed by a computing unit, as described, for example, in US Pat 6 by the following arithmetic unit A _{i + 1 is} the case, so can the first logic gate 51 , the third logic gate 53 , the fourth logic gate 54 , the twelfth logic gate e1, the thirteenth logic gate e2 and the fourteenth logic gate e3 (or in general such logic gates) as part of the first group of processing gates and the second group of processing gates of the subsequent processing unit A _{i + 1} and thus, like the second logic gate 52 and the fifth logic gate 55 the following arithmetic unit A _{i + 1} , as a common processing gate of the following arithmetic unit A _{i + 1 are} considered. As a result, the first logic gate 51 , the third logic gate 53 , the fourth logic gate 54 , the twelfth logic gate e1, the thirteenth logic gate e2 and the fourteenth logic gate e3 of a preceding arithmetic unit are regarded as a common processing gate of the arithmetic unit A _i .

The arithmetic logic unit 600 corresponds, for example, to a self-checking ALU cells A _i and A _{i + 1} on the basis of self-checking fast ripple adders.

To simplify the explanations, these ALU cells (out 6 ) hereinafter referred to as ALU-FR-2.

Also in the implementation of the ALU-FR-2, the techniques described above can be used. Three control signals m ₁ , m ₂ and m ₃ are used. The coding of the operations in the ALU-FR-2 differs from the coding of the operations in the ALU-CLA-2, where also three control signals are used. The values of m ₁ , m ₂ and m ₃ and the corresponding operations are shown in the following table:

For {m ₁ = 0, m ₂ = 0, m ₃ = 1}, {m ₁ = 0, m ₂ = 1, m ₃ = 1}, {m ₁ = 1, m ₂ = 0, m ₃ = 0 } and {m ₁ = 1, m ₂ = 1, m ₃ = 1}, an illegal operation is performed.

In the ALU FR-2, the carry signals C3 _{i, i} C4 are manipulated C1 _{i + 1} and _{i + 1} C2, and thereby the carry signals c _i and c _{i + 1} with the help of the control logic.

The carry signal c _i-1 is applied in the ALU cell A _i of ALU-FR-2 as an AND function (AND gate 55 ) of the carry signals C1 _i-1 and C2 _i-1 . The carry signal c _i implemented in the ALU cell A _{i + 1} , on the other hand, is the NAND function (NAND gate 5 ) of the carry signals C3 _i and C4 _i . There is also a difference in the implementation of C4 _i in the ALU cell A _i (NAND gate 51 ) and C2 _{i + 1} in the ALU cell A _{i + 1} (OR gate 51 ). For these reasons, the control logic in the A _i differs from the control logic in the A _{i + 1} .

In the following, the manipulation of the carry signals c _i and c _{i + 1} by the control logic in the ALU-FR-2 is considered (all designations of the gates and signals refer to FIGS 6 ):
In the addition (m ₁ = 1, m ₂ = 0, m ₃ = 1), the carry signals C3 _i, C4 _i, C1 _{i + 1} and C 2 _{i + 1} and thus the carry signals c _i and c _{i + 1} of the Control logic not affected.

In the AND operation (m ₁ = 0, m ₂ = 0, m ₃ = 0), the carry signals c _i and c _{i + 1} must be set to "1" according to the techniques described above. In the ALU cell A _i , the control signals m ₁ = 0 and m ₂ = 0 set the carry signal C4 _i to "0". This implements the NAND gate 55 in the ALU cell A _{i + 1,} the carry signal c _i = 1. For m ₂ = 0 and m ₃ = 0, the carry signals C1 _{i + 1} and C2 _{i + 1 are} equal to "1". From the C1 _{i + 1} and C2 _{i + 1} = 1, the AND gate implements 55 in the ALU cell A _{i + 2,} the carry signal c _{i + 1} = 1.

In the case of the OR operation (m ₁ = 0, m ₂ = 1, m ₃ = 0) or XOR operation (m ₁ = 1, m ₂ = 1, m ₃ = 0), the carry signals c _i and c _{i +1} to "0". Because of the control signal m ₂ = 1, the carry signal C4 _{i is} equal to "1". Because m _{3 is} equal to "0", the carry signal C3 _{i is} equal to "1". The NAND gate 55 in the ALU cell A _{i + 1} , the carry signal implements c _i = 1. For m ₂ = 1 and m ₃ = 0, the carry signal C2 _{i + 1} is "0". Therefore, the AND gate implements 5 in the ALU cell A _{i + 2,} the carry signal c _{i + 1} = 0.

The proposed self-checking ALU can detect all single stuck-at faults. An adhesion error is, for example, an error in which a signal (eg output of a logic gate) is permanently stuck at a fixed logic level (0 or 1).

Detection of the various possible detention errors is considered below:
Errors in the operands a and b, which falsify an odd number of bits in the operands, can be detected by comparing p _a ⊕ p _b with p (a ⊕ b).

All individual sticking errors in the XOR tree for the implementation of the parity p (a ⊕ b) and in the XOR gate for the implementation of p _a ⊕ p _b can be calculated by comparing p _a ⊕ p _b with p (a ⊕ b ) be recognized.

All individual sticking faults in the ALU cells A _i and A _{i + 1} of ALU-FR-2 can be detected, for example, as follows:
Errors in the logic gates 1 - 11 (first to eleventh logic gates) become the same as the errors in the logic gates 1 - 11 (first to eleventh logic gate) of the ALU-FR-1 detected.

Errors in the control gates e1-e3 of the ALU cell A _i corrupt carry signal C4 _i or carry signal C3 _i . As a result, carry signal c _{i is} faulty, which in the implementation of s _i is used. The errors considered are obtained by comparing s _i with s _i recognized.

Errors in the control gate e1, e2, e3 or e7 of the ALU cell A _{i + 1} falsify carry signal C2 _{i + 1} or carry signal C1 _{i + 1} . As a result, carry signal c _{i + 1} becomes erroneous. c _{i + 1} is used in the ALU cell A _{i + 1} exclusively for the implementation of s _{i + 1} used. When comparing s _i with s _i the considered errors are discovered.

Errors in the control gates e4 and e5 of the ALU cell A _i cause the erroneous output s _i , This is recognized by s _i and s _i compares.

Because of the errors in the control gate e6 of the ALU cell A _i , the output s _{i is} corrupted. The errors considered are obtained by comparing s _i with s _i recognized.

Errors in the control gates e4, e5 and e6 of the ALU cell A _{i + 1} either distort the output s _{i + 1} or the output s _{i + 1} . They are recognized by s _{i + 1} with s _{i + 1} is compared.

In general, arithmetic logic units constructed according to the described concept can also detect many multiple (multiple) errors. For example, an even number of corrupted bits may result in the ALU calculation, e.g. In the parity-tested ALU "M. Nicolaidis. Implementation Techniques of Self-Checking Arithmetic Operators and Data Paths Based on Double-Rail and Parity Codes. US Patent No.5450340 , 1995 ";"M. Nicolaidis. Efficient Implementations of Self-Checking Adders and ALU's. Symposium on Fault-Tolerant Computing, pages 586-595, 1993 "and" M. Nicolaidis. Carry Checking / Parity Prediction Adders and ALUs. IEEE Transactions on VLSI Systems, 11 (1): 121-128, 2003 "are not recognized. These can be discovered by using the proposed concept. Only errors that do not recognize the output s _i and the output at the same time are not recognized s _i falsify in all defective ALU cells. This also applies to the method of duplication and comparison. As a result, the proposed ALU has almost the same error detection properties as the completely doubled ALU.

By selecting the types of logic gates (eg, AND gates, OR gates, XOR gates, ...) for the logic gates and connecting the logic gates as described 3 to 6 and 11 At the output of the first binary output signal s _i selectable, an addition, a logical AND operation, a logical OR operation or a logical EXCLUSIVE OR operation of the two binary input signals can be realized. Accordingly, at the output of the second binary output signal s _i an inverse addition, a NAND-operation, a NOR-operation or an EXCLUSIVE-NOT-OR-operation are realized. This single errors, such. B. adhesion error, a computing unit, regardless of the logic gate in which the single error occurs, are detected by the error detector. But not only errors in logic gates can be detected. It is also possible to detect faults on a line (connection) between the gates, faults on the inputs (of input operands) and / or errors on the outputs.

Embodiments of the invention may also be based on self-checking adders and ALU cells based on other adder types.

Other types of adders, such as Carry Skip or Carry Select, are built from Carry Ripple (including Fast Ripple) or Carry Look-Ahead adder cells. Therefore, the proposed self-checking ALU cells can also be used for the implementation of a self-checking ALU based on Carry Skip or Carry Select adders.

Some embodiments according to the invention relate to integration of the self-checking ALU in the data path of a microprocessor.

The parity code and the two-rail code (duplication code) are very often used to monitor the buses in the data path of a microprocessor.

Because the inputs a and b of the proposed self-checking ALU are parity-coded (parity bits p _a and p _b ) and the parity p _{s of} the output s (output signals) is implemented at the output of the two-rail checker, the ALU becomes very simple integrate into a parity-validated data path.

The proposed ALU can be easily integrated into a data path using two-rail code because at its outputs s and s also the two-rail code is implemented.

In alternative arithmetic logic units, while retaining the other features, gate 2 (second logic gate) in ALU-CLA-1, ALU-CLA-2, ALU-FR-1, and ALU-FR2 can be doubled and the doubled gate exclusive for implementing one of the two outputs s (and the original gate exclusively for the other output). In addition, the described auxiliary function f _i can be used to calculate an output signal.

In general, a low hardware overhead (compared to the standard doubling) of a proposed ALU z. B. be achieved by the following:
In the case of an ALU based on the carry look-ahead adder, the propagate signal p _i is implemented only once, the generate signal g _i is implemented only once and the carry look-ahead unit is implemented only once.

In the case of an ALU based on the ripple (adder) adder, the propagate signal p _i is implemented only once, the generate signal g _i is implemented only once, and the carry signal c _i is implemented only once. Thus, the propagate signal p _i , the generate signal g _i , carry look-ahead unit and carry generation in the ripple ALU are not duplicated.

verwendet werden. Bei der Standard-Verdopplung ist das nicht der Fall (da gibt es keine gemeinsame Gatter oder Signale). Ein Fehler im Propagiere-Signal p_i wird (bei einer Standard-Verdopplung) erkannt durch (”externen”) Vergleich p_a xor p_b mit p(a xor b) und, wenn er nach der Abzweigung des Signals auftritt, durch Vergleich der s_i und s _i . s_i ist dabei korrekt und s _i ist dann fehlerhaft.These signals can z. For the implementation of the first output s _{i + 1} as well as for the implementation of the second output

be used. This is not the case with standard doubling (there are no common gates or signals). An error in the propagate signal p _i is detected (in a standard doubling) by ("external") comparison p _a xor p _b with p (a xor b) and, if it occurs after the branching of the signal, by comparing the s _i and s _i , s _i is correct and s _i is then faulty.

Due to the concept described, errors in the generate signal g _i , in the carry look-ahead unit or carry generation by the comparison of s _i with s _i be recognized because they only have the output s _i can ALU cell_i and the output s _i remains correct. So is z. B. not only the propagate signal p _i a common gate. The generate signal g _i , the carry signal c _i and the gates in the carry look-ahead unit may also be. They can be protected by comparing s _i and s _i be.

If the common gate generating the propagate signal is doubled, the other common gates, such as those for generating the generate signal g _i , the carry signal c _i, and the gates remain in the carry look-ahead unit. They will continue to implement the two outputs s _i and s _i used.

in der Zelle A_i.For example, in the (near) ripple ALU, the gates for the implementation of the c _{i may be} implemented in the ALU cells, but distributed as it were. For example, in 5 the gates 51 . 53 and 54 in cell A _i the common gates for s _{i + 1} and

in the cell A _i .

Furthermore, in some examples, the carry prediction unit may have common gates for s _i and s _i contain.

Some embodiments according to the invention relate to an implementation technique of self-checking arithmetic and logical operators based on duplication code.

In the invention is z. For example, new techniques for developing self-checking arithmetic and logical operators that implement an arithmetic logic unit (ALU). Operators "addition (ADD)", "logical AND (AND)", "logical OR (OR)" and "logical exclusive OR (XOR)" are considered. These operators as well as their inverses ( ADD , NAND, NOR and XNOR) are implemented within an ALU cell (arithmetic unit). The errors in the ALU circuit are z. For example, if the operator and the inverse operator are not inverse to each other. Various new ALU cells are proposed - e.g. As for the applications with high demands on the computing speed and for the applications for which the hardware complexity and power consumption are critical. The space requirement in the proposed techniques is smaller than the area requirement for the doubling and comparison method and comparable to the area requirement for the ALU, which is checked by means of the partition code. The proposed self-checking ALU has almost the same error detection characteristics as completely doubled self-checking ALU.

The proposed self-checking ALU implements z. For example, both the output s and the negated output s , By comparing the two outputs bit by bit, errors in the ALU can be detected. Because the outputs of the ALU are monitored by the duplication code, the ALU's error detection properties are better than the parity-proven ALU's error detection properties and comparable to the error detection characteristics of the fully-doubled ALU.

For the implementation of the negated output s _{i of} the ALU cell z. B. uses an auxiliary function. A logic controls the implementation of the function pairs - {ADD, ADD }, {AND, NAND}, {OR, NOR} and {XOR, XNOR}. The propagation, generation and carry signals are not duplicated. This significantly reduces the hardware overhead required to implement the self-verifying ALU compared to the hardware overhead of the fully-doubled ALU, and is comparable to the hardware overhead for the parity-verified ALU.

The implementation of the logical functions (AND, OR, XOR) at the output s _i can also be different based on the basic concept than in the 3 - 6 and 11 shown done.

zu implementieren und Teile dieser Implementierung a_ib_i und

für die Implementierung der AND und NOR Funktionen zu nutzen.Another implementation would be z. B. the propagate signal as

to implement and implement parts of this implementation a _i b _i and

to use for the implementation of the AND and NOR functions.

Instead of mutually inverse functions, the same functions can be implemented on the outputs - {ADD, ADD}, {AND, AND}, {OR, OR) and {XOR, XOR}. This can be z. B. take place by taking the inverse of the auxiliary function ƒ.

To implement the logical functions, z. B. manipulated carry signals. They can be manipulated directly or indirectly using the Propagation and Generate signals. This was shown in the embodiments. In addition, other logic gates can be used (eg, with three inputs) or the control logic is built differently. Also, the coding of the operations (according to the tables shown) may look different.

The number of control signals and the coding of the operations can be different than in the 3 - 6 and 11 be shown. In the general structure of the proposed ALU ( 2 ), the number of control signals (m ₁ , ..., m _k ) is variably indicated. In the embodiments, two (k = 2) and three (k = 3) control signals are used.

In some embodiments according to the invention, the proposed self-checking ALU may be used in microprocessors for high reliability applications and in microprocessors for security applications. These are, for example, safety applications in automotive, train traffic, medicine, defense and nuclear power plants, fault-tolerant computers for aerospace, chip cards.

7 shows a flowchart of a method 700 for processing a first binary input signal and a second binary input signal according to a selectable algebraic function according to an embodiment of the invention.

The procedure 700 includes a drive 710 at least one processing gate of a first group of processing gates and at least one processing gate of a second group of processing gates by a group of control gates based on a control signal to select an algebraic function from a plurality of algebraic functions. Here, the first group of processing gates, the second group of processing gates and the group of control gates each differ at least partially from each other. The first group of processing gates and the second group of processing gates have at least one common processing gate.

Furthermore, the method includes 700 a processing 720 of the first binary input signal and the second binary input signal through the first group of processing gates corresponding to the selected algebraic function to obtain a first binary output signal.

In addition, the first binary input signal and the second binary input signal are processed by the second group of processing gates corresponding to the selected algebraic function or according to an inverse algebraic function of the selected algebraic function 730 to get a second binary output signal. The first binary output signal corresponds to the second binary output signal or an inverse output signal of the second binary output signal when the arithmetic unit is operating correctly.

Furthermore, the method includes 700 comparing the first binary output signal with the second binary output signal or with the inverse output signal of the second binary output signal to detect an error in the processing of the first binary input signal and the second binary input signal, independently of the selected algebraic function.

Although some aspects have been described in the context of a device, it will be understood that these aspects also constitute a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device.

Claims (21)

Arithmetic logic unit ( 100 ) for processing a first binary input signal (a _i ) and a second binary input signal (b ₁ ) in accordance with a selectable algebraic function, comprising the following features: 110 ), comprising a first group of processing gates, a second group of processing gates, and a group of control gates, the first group of processing gates, the second group of processing gates, and the group of control gates each at least partially different from each other, the first group of Processing gates and the second group of processing gates have at least one common processing gate, the group of control gates adapted to drive at least one processing gate of the first group of processing gates and at least one processing gate of the second group of processing gates based on a control signal (m _i ) select an algebraic function from a plurality of algebraic functions, the plurality of algebraic functions including an addition, a logical AND, a logical OR, and an exclusive logical OR Link, wherein the first group of processing gates is arranged to process the first binary input signal (a _i ) and the second binary input signal (b _i ) according to the selected algebraic function to obtain a first binary output signal (s _i ). wherein the second group of processing gates is adapted to process the first binary input signal (a _i ) and the second binary input signal (b _i ) according to the selected algebraic function or according to an inverse algebraic function of the selected algebraic function to be a second binary output signal ( s _i ), wherein the first binary output signal (s _i ) is the second binary output signal ( s _i ) or an inverse output signal of the second binary output signal ( s _i ) corresponds when the arithmetic unit ( 110 ) works without errors; and an error detector ( 120 ) which is designed to convert the first binary output signal (s _i ) to the second binary output signal ( s _i ) or with the inverse output signal of the second binary output signal ( s _i ), to make a mistake regardless of the selected algebraic function ( 124 ) during processing of the first binary input signal (a _i ) and the second binary input signal (b _i ). The arithmetic logic unit of claim 1, wherein the processing gates of the first group of processing gates, the processing gates of the second group of processing gates and the group of control gates are interconnected such that a single error of one of the gates of the first group of processing gates, the second group of processing gates, the group of control gates or an electrical connection between the gates through the fault detector ( 120 ) is detected. An arithmetic logic unit according to claim 2, wherein the processing gates of the first group of processing gates, the processing gates of the second group of processing gates and the group of control gates are connected to each other so that the single error is detected regardless of which gate of the first group of processing gates, the second group of processing gates, or the group of control gates of the single errors. Arithmetic and logic unit according to one of claims 1 to 3, wherein the arithmetic unit ( 110 ) to provide an auxiliary output signal based on an output of a common processing gate of the first group of processing gates and the second group of processing gates. Arithmetic and logic unit according to claim 4, wherein the arithmetic unit ( 110 ) is adapted to provide, for each common processing gate of the first group of processing gates and the second group of processing gates, one auxiliary output signal each based on the output of the respective common processing gate. An arithmetic logic unit according to claim 4 or 5, wherein a single error of a common processing gate of the first group of processing gates and the second group of processing gates based on an associated auxiliary output signal of the arithmetic unit ( 110 ) through the error detector ( 120 ) is detected. An arithmetic logic unit according to any one of claims 1 to 6, comprising a plurality of arithmetic units, each arithmetic unit of the plurality of arithmetic units configured to process a first binary input signal and a second binary input signal, each first binary input signal being one bit represents a first parallel input signal with n-parallel bits, and wherein each second binary input signal represents one bit of a second parallel input signal with n-parallel bits. An arithmetic logic unit according to any one of claims 4 to 7, which is a transmission prediction unit 830 which is designed to be based on an auxiliary output signal of the arithmetic unit ( 110 ) to determine a carry signal and the carry signal of the arithmetic unit ( 110 ). Arithmetic and logic unit according to one of claims 1 to 8, wherein the arithmetic unit ( 110 ) is based on a parallel adder architecture with carry prediction. An arithmetic logic unit according to any one of claims 1 to 8, based on a fast trickle adder architecture or a standard trickle adder architecture. An arithmetic and logic unit as claimed in any one of claims 1 to 10, wherein the processing gates of the first group of processing gates and the control gates of the group of control gates correspond to such types of logic gates and are interconnected such that the first binary output signal (s) _i Adding the first binary input signal (a _i ) and the second binary input signal (b _i ) in consideration of a possible carry, and wherein the processing gates of the second group of processing gates and the control gates of the group of control gates corresponding to each type of logic gates and interconnected are so that the second binary output signal ( s _i ) corresponds to an inverted addition of the first binary input signal (a _i ) and the second binary input signal (b _i ). An arithmetic and logic unit according to any one of claims 1 to 11, wherein the processing gates of the first group of processing gates and the control gates of the group of control gates correspond to and are connected to each other of such types of logic gates such that the first binary output signal (s _i ) of a logical AND operation of the first binary input signal (a _i ) and the second binary one Input signal (b _i ) corresponds, and wherein the processing gates of the second group of processing gates and the control gates of the group of control gates correspond to each type of logic gates and are connected to each other, so that the second binary output signal ( s _i ) corresponds to a logical NAND of the first binary input signal (a _i ) and the second binary input signal (b _i ). An arithmetic and logic unit as claimed in any one of claims 1 to 12, wherein the processing gates of the first group of processing gates and the control gates of the group of control gates correspond to and are connected to such types of logic gates such that the first binary output signal (s _i ) corresponds to a logical OR of the first binary input signal (a _i ) and the second binary input signal (b _i ), and wherein the processing gates of the second group of processing gates and the control gates of the group of control gates correspond to each type of logic gate and are connected together, so that the second binary output signal ( s _i ) corresponds to a logical NOR operation of the first binary input signal (a _i ) and the second binary input signal (b _i ). An arithmetic and logic unit according to any one of claims 1 to 13, wherein the processing gates of the first group of processing gates and the control gates of the group of control gates correspond to such types of logic gates and are interconnected such that the first binary output signal (s _i ) of one logical output of the first binary input signal (a _i ) and the second binary input signal (b _i ), and wherein the processing gates of the second group of processing gates and the control gates of the group of control gates correspond to each type of logic gate and are connected together are so that the second binary output signal ( s _i ) corresponds to a logical EXCLUSIVE NOR operation of the first binary input signal (a _i ) and the second binary input signal (b _i ). An arithmetic and logic unit as claimed in any one of claims 1 to 14, wherein the processing gates of the second group of processing gates correspond to and are connected to each other of such types of logic gates, such that the second binary output signal ( s _i ) based on an auxiliary function f _i according to the formula:

or the formula:

is calculated by the processing gates of the second group of processing gates, where f _{i is} the auxiliary function, a _{i is} the first binary input signal, b _{i is} the second binary input signal and c _{i-1 is} a carry signal of a previous arithmetic unit, or so that the second binary output signal ( s _i ) based on the inverted auxiliary function ( ƒ _i ) is calculated by the processing gates of the second group of processing gates. Arithmetic logic unit ( 300 ) according to one of claims 1 to 15, which comprises a carry advance calculation unit ( 830 ), and wherein the arithmetic unit ( 110 ) comprises first to fourteenth logic gates, wherein the first logic gate ( 31 ) corresponds to an AND gate and at a first input the second binary input signal (b _i ) and at a second input the first binary input signal (a _i ) gets provided, wherein an output of the first logic gate ( 31 ) generates a generate signal (g _i ) to the carry pre-computation unit ( 830 ), wherein the second logic gate corresponds to an XOR gate and receives the second binary input signal (b _i ) at a first input and the first binary input signal (a _i ) at a second input, wherein an output of the second logic gate ( 32 ) with an input of the fifth logic gate ( 35 ) and with an input of the eighth logic gate ( 38 ) and a propagate signal (p _i ) of the carry prediction unit ( 830 ), the third logic gate ( 33 ) corresponds to an XOR gate and to a first input having an output of the eighth logic gate ( 38 ) and having a second input connected to an output of the eleventh logic gate (e3), an output of the third logic gate ( 33 ) provides the first binary output signal (s _i ), wherein the fourth logic gate corresponds to an XOR gate and the first binary input signal (a _i ) is provided at a first input, wherein the fourth logic gate ( 34 ) with a second input with a Output of the eleventh logic gate (e3) and having an output connected to an input of the thirteenth logic gate e5, the fifth logic gate ( 35 ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 32 ) and having a second input connected to an output of the thirteenth logic gate (e5), an output of the fifth logic gate ( 35 ) with an input of the sixth logic gate ( 36 ), the sixth logic gate ( 36 ) corresponds to an XOR gate and with a first input to the output of the fifth logic gate ( 35 ), the sixth logic gate ( 36 ) at an input a carry signal (c _i ) of the own arithmetic unit (A _i ) gets provided, wherein the sixth logic gate ( 36 ) at an output the second binary output signal ( s _i ), the seventh logic gate ( 37 ) corresponds to an XOR gate and at a first input the second binary input signal (b _i ) and at a second input a second control signal (m ₂ ) gets provided, wherein an output of the seventh logic gate ( 37 ) is connected to an input of the fourteenth logic gate (e6), the eighth logic gate corresponding to an OR gate and having a first input to the output of the second logic gate (e6). 32 ) and having a second input connected to an output of the fourteenth logic gate (e6), an output of the eighth logic gate ( 38 ) with an input of the third logic gate ( 33 ), wherein the ninth logic gate e1 corresponds to an OR gate and receives at a first input a carry signal (c _i-1 ) of a preceding processor and at a second input the second control signal (m ₂ ), wherein an output of the ninth Logic gate (e1) is connected to an input of the eleventh logic gate (e3), wherein the tenth logic gate (e2) corresponds to an XNOR gate and at a first input the second control signal (m ₂ ) and at a second input the first control signal (m ₁ ), wherein an output of the tenth logic gate (e2) is connected to an input of the fourteenth logic gate (e6), the eleventh logic gate (e3) corresponding to an AND gate and having a first input to the output of the ninth logic gate (e3). e1), the eleventh logic gate (e3) being provided with the first control signal (m ₁ ) at a second input, an output of the eleventh logic gate (e 3) with an input of the fourth logic gate ( 34 ) and with an input of the third logic gate ( 33 ) and a carry signal (c _i-1 ) of the previous processing unit provides, wherein the twelfth logic gate corresponds to a NAND gate and at a first input the second control signal (m ₂ ) and at an inverted second input the first control signal (m ₁ An output of the twelfth logic gate (e4) is connected to an input of the thirteenth logic gate (e5), the thirteenth logic gate (e5) corresponding to an AND gate and having a first input to the output of the fourth logic gate (e5). 34 ) and having a second input connected to the output of the twelfth logic gate (e4), an output of the thirteenth logic gate (e5) being connected to an input of the fifth logic gate (e4). 35 ), the fourteenth logic gate (e6) corresponding to an AND gate and having a first input to the output of the seventh logic gate ( 37 ) and having a second input connected to the output of the tenth logic gate (e2), an output of the fourteenth logic gate (e6) being connected to an input of the eighth logic gate (e2). 38 ), the second logic gate ( 32 ), the third logic gate ( 33 ), the seventh logic gate ( 37 ), the eighth logic gate ( 38 ), the ninth logic gate (e1), the tenth logic gate (e2), the eleventh logic gate (e3) and the fourteenth logic gate (e6) belong to the first group of processing gates, the second logic gate (e1) 32 ), the fourth logic gate ( 34 ), the fifth logic gate ( 35 ), the sixth logic gate ( 36 ), the ninth logic gate (e1), the eleventh logic gate (e3), the twelfth logic gate (e4) and the thirteenth logic gate (e5) belong to the second group of processing gates, and wherein the ninth to fourteenth logic gates (e1, e2, e3 , e4, e5, e6) belong to the group of control gates. Arithmetic logic unit ( 400 ) according to one of claims 1 to 15, which comprises a carry advance calculation unit ( 830 ), and wherein the arithmetic unit ( 110 ) comprises first to fourteenth logic gates, wherein the first logic gate ( 31 ) corresponds to an AND gate and at a first input the second binary input signal (b _i ) and at a second input the first binary input signal (a _i ) gets provided, wherein an output of the first logic gate ( 31 ) is connected to an input of the ninth logic gate e1, wherein the second logic gate corresponds to an XOR gate and the first binary input signal (b _i ) is provided at a first input and the first binary input signal (a _i ) at a second input an output of the second logic gate ( 32 ) with an input of the eleventh logic gate (e3), with an input of the fifth logic gate ( 35 ) and with an input of the eighth logic gate ( 38 ) and provides a propagate signal (p _i ), the third logic gate ( 33 ) corresponds to an XOR gate and to a first input having an output of the eighth logic gate ( 38 ) and at a second input, the carry signal (c _i-1 ) gets a previous processing unit provided, wherein an output of the third logic gate ( 33 ) provides the first binary output signal (s _i ), wherein the fourth logic gate corresponds to an XOR gate and at a first input, the first binary input signal (a _i ) and provided at a second input the carry signal (c _{i-1 ) of} a previous computing unit gets the fourth logic gate ( 34 ) is connected to an output to an input of the thirteenth logic gate e5, the fifth logic gate ( 35 ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 32 ) and having a second input connected to an output of the thirteenth logic gate (e5), an output of the fifth logic gate ( 35 ) with an input of the sixth logic gate ( 36 ), the sixth logic gate ( 36 ) corresponds to an XOR gate and with a first input to the output of the fifth logic gate ( 35 ), the sixth logic gate ( 36 ) at an input a carry signal (c _i ) of the own arithmetic unit (A _i ) gets provided, wherein the sixth logic gate ( 36 ) at an output the second binary output signal ( s _i ), the seventh logic gate ( 37 ) corresponds to an XOR gate and at a first Input the second binary input signal (b _i ) and at a second input a second control signal (m ₂ ) is provided, wherein an output of the seventh logic gate ( 37 ) is connected to an input of the fourteenth logic gate (e6), the eighth logic gate corresponding to an OR gate and having a first input to the output of the second logic gate (e6). 32 ) and having a second input connected to an output of the fourteenth logic gate (e6), an output of the eighth logic gate ( 38 ) with an input of the third logic gate ( 33 ), wherein the ninth logic gate e1 corresponds to an OR gate and at a first input the second control signal (m ₂ ) gets provided and with a second input to an output of the first logic gate ( 31 ), an output of the ninth logic gate (e1) being connected to an input of the tenth logic gate (e2), the tenth logic gate (e2) corresponding to an AND gate and providing the first control signal (m ₁ ) at a first input and connected to a second input to an output of the ninth logic gate (e1), an output of the tenth logic gate ( 31 ) generates a generate signal (g _i ) to the carry pre-computation unit ( 830 ), wherein the eleventh logic gate (e3) corresponds to an AND gate and with a second input to the output of the second logic gate ( 32 ), the eleventh logic gate (e3) being provided at a first input the first control signal (m ₁ ), an output of the eleventh logic gate (e3) providing a propagate signal (p _i ) to the carry pre-computation unit, the twelfth one logic gate corresponding to a NAND gate and the second control signal at a first input (m ₂₎ and to an inverted second input of the first control signal (m ₁₎ provided gets an output of said twelfth logic gate (e4) with one input of the thirteenth logic gate ( e5), the thirteenth logic gate (e5) corresponding to an AND gate and having a first input to the output of the fourth logic gate ( 34 ) and having a second input connected to the output of the twelfth logic gate (e4), an output of the thirteenth logic gate (e5) being connected to an input of the fifth logic gate (e4). 35 ), the fourteenth logic gate (e6) corresponding to an AND gate and having a first input to the output of the seventh logic gate ( 37 ) and at a second input a third control signal (m ₃ ) is provided, wherein an output of the fourteenth logic gate (e6) with an input of the eighth logic gate ( 38 ), the second logic gate ( 32 ), the third logic gate ( 33 ), the seventh logic gate ( 37 ), the eighth logic gate ( 38 ) and the fourteenth logic gate (e6) belong to the first group of processing gates, the second logic gate ( 32 ), the fourth logic gate ( 34 ), the fifth logic gate ( 35 ), the sixth logic gate ( 36 ), the twelfth logic gate (e4) and the thirteenth logic gate (e5) belong to the second group of processing gates, and wherein the ninth to fourteenth logic gates (e1, e2, e3, e4, e5, e6) belong to the group of control gates. Arithmetic logic unit ( 500 ) according to one of claims 1 to 14, which has a first arithmetic logic unit (A _i ) with a first to seventeenth logic gate and a second arithmetic unit (A _{i + 1} ) with a first to seventeenth logic gate, wherein the first logic gate ( 51 ) (A _i) corresponding to the first computing unit to a NAND gate, and (the first binary input signal at a first input a _i) of the first arithmetic unit (A _i) and to a second input of the second binary input signal (b _i) of the first arithmetic unit ( A _i ), wherein an output of the first logic gate ( 51 ) provides the first arithmetic unit (A _i ) with a second auxiliary carry signal (C4 _i ) of the first arithmetic unit (A _i ) to the second arithmetic unit (A _{i + 1} ), wherein the second logic gate ( 52 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and to a first input the second binary input signal (b _i ) of the first arithmetic unit (A _i ) and at a second input the first binary input signal (a _i ) of the first arithmetic unit ( A _i ), wherein an output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) with an input of the third logic gate ( 53 ) of the first arithmetic unit (A _i ,) with an input of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) and with an input of the eleventh logic gate ( 11 ) of the first arithmetic unit (A _i ) and provides a propagation signal (p _i ) of the first arithmetic unit (A _i ) at an output of the first arithmetic unit (A _i ), wherein the third logic gate ( 53 ) of the first arithmetic unit (A _i ) corresponds to an AND gate and with a first input to the output of the second logic gate ( 52 ) Of the first arithmetic unit connected (A _i), said third logic gate ( 53 ) of the first arithmetic unit (A _i ) at a second input a second auxiliary carry signal (C2 _i-1 ) of a preceding arithmetic unit is provided, wherein an output of the third logic gate ( 53 ) of the first arithmetic unit (A _i ) with an input of the fourth logic gate ( 54 ) of the first arithmetic unit (A _i ), the fourth logic gate ( 54 ) of the first arithmetic unit (A _i ) corresponds to a NAND gate and having an input to the output of the third logic gate ( 52 ) of the first arithmetic unit (A _i ), the fourth logic gate ( 54 ) the first arithmetic unit (A _i ) receives at a second input a first auxiliary carry signal (C1 _i-1 ) of a preceding arithmetic unit, the fourth logic gate ( 54 ) provides the first arithmetic unit (A _i ) at an output a first auxiliary carry signal (C3 _i ) of the first arithmetic unit (A _i ) to the second arithmetic unit (A _{i + 1} ), wherein the fifth logic gate ( 55 ) of the first arithmetic unit (A _i ) corresponds to an AND gate and receives the second auxiliary carry signal (C2 _i-1 ) of a preceding arithmetic unit and at a second input of the first auxiliary carry signal (C1 _{i-1) of} the preceding arithmetic unit at a first input, wherein an output of the fifth logic gate ( 55 ) of the first arithmetic unit (A _i ) is connected to an input of the twelfth logic gate (e1) of the first arithmetic unit (A _i ), the sixth logic gate ( 56 ) (A _i) corresponding to the first computing unit and an XOR gate (having a first input connected to an output of said eleventh logic gate 11 ) of the first computing unit (A _i ), wherein the sixth logic gate ( 56 ) of the first arithmetic unit (A _i ) having a second input connected to an output of the fourteenth logic gate (e3) of the first arithmetic unit (A _i ), wherein the sixth logic gate ( 56 ) provides the first arithmetic unit (A _i ) at an output the first binary output signal (s _i ) of the first arithmetic unit (A _i ), the seventh logic gate ( 57 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and the first binary input signal (a _i ) of the first arithmetic unit (A _i ) is provided at a first input, wherein a second input of the seventh logic gate ( 57 ) of the first arithmetic unit (A _i ) is connected to an output of the fourteenth logic gate (e3) of the first arithmetic unit (A _i ), an output of the seventh logic gate ( 55 ) of the first arithmetic unit (A _i ) is connected to an input of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ), the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) and with a second input to an output of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ), wherein an output of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) with an input of the ninth logic gate ( 59 ) Of the first arithmetic unit connected (A _i), said ninth logic gate ( 59 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and with a first input to the output of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) and at a second input a carry signal (c _i ) is provided by the second arithmetic unit (A _{i + 1} ), wherein an output of the ninth logic gate ( 59 ) of the first arithmetic unit (A _i ) the second binary output signal ( s _i ), the tenth logic gate ( 10 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and receives the second binary input signal (b _i ) of the first arithmetic unit (A _i ) at a first input and a second control signal (m ₂ ) at a second input Output of the tenth logic gate ( 10 ) of the first arithmetic unit (A _i ) is connected to an input of the seventeenth logic gate (e6) of the first arithmetic unit (A _i ), the eleventh logic gate ( 11 ) of the first arithmetic unit (A _i ) corresponds to an OR gate and with a first input to the output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) and with a second input to an output of the seventeenth logic gate (e6) of the first arithmetic unit (A _i ), wherein an output of the eleventh logic gate (A 11 ) of the first arithmetic unit (A _i ) with an input of the sixth logic gate ( 56 ) of the first computing unit (A _i ) is connected, wherein the twelfth logic gate (e1) of the first arithmetic unit (A _i ) corresponds to an OR gate and with a first input to the output of the fifth logic gate ( 55 ) is connected to the first arithmetic unit (A _i ) and the second control signal (m ₂ ) is provided at a second input, an output of the twelfth logic gate (e1) of the first arithmetic unit (A _i ) having an input of the fourteenth logic gate (e3) the first arithmetic unit (A _i ) is connected, wherein the thirteenth logic gate (e2) of the first arithmetic unit (A) corresponds to an XNOR gate and at a first input the second control signal (m ₂ ) and at a second input the first control signal (m ₁ ), wherein an output of the thirteenth logic gate of the first arithmetic unit (A _i ) is connected to an input of the seventeenth logic gate (e6) of the first arithmetic unit (A _i ), wherein the fourteenth logic gate (e3) of the first arithmetic unit (A _i ) corresponds to an AND gate and is connected to a first input to the output of the twelfth logic gate (e1) of the first arithmetic unit (A _i ) and to a second input the first contro llsignal (m ₁₎ gets provided, wherein an output of the fourteenth logic gate (e3) of the first arithmetic unit (A _i) to an input of the seventh logic gate ( 57 ) of the first arithmetic unit (A _i ) and an input of the sixth logic gate ( 56 ) Of the first arithmetic unit (A _i) and a carry signal (C _i-1) provided by the preceding processing unit, said fifteenth logic gate (e4) of the first arithmetic unit (A _i) a NAND gate and the second at a first input Control signal (m ₂ ) and the first control signal (m ₁ ) is provided at an inverted second input, wherein an output of the fifteenth logic gate (e4) of the first arithmetic unit (A _i ) with an input of the sixteenth logic gate (e5) of the first arithmetic unit ( A _i ), wherein the sixteenth logic gate (e5) of the first arithmetic unit (A _i ) corresponds to an AND gate and with a first input to the output of the seventh logic gate ( 57 ) of the first arithmetic unit (A _i ) and with a second input to the output of the fifteenth logic gate (e4) of the first arithmetic unit (A _i ), wherein an output of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ) with a Input of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ), the seventeenth logic gate ( _e 6) of the first arithmetic unit (A _i ) corresponding to an AND gate and having a first input to the output of the tenth logic gate ( 10 ) of the first arithmetic unit (A _i ) and with a second input to the output of the thirteenth logic gate (e2) of the first arithmetic unit (A _i ), wherein an output of the seventeenth logic gate (e6) of the first arithmetic unit A _i with an input of the eleventh logic gate ( 11 ) of the first computing unit (A _i ), wherein the second logic gate ( 52 ), the fifth logic gate ( 55 ), the sixth logic gate ( 56 ), the tenth logic gate ( 10 ), the eleventh logic gate ( 11 ), the twelfth logic gate (e1), the thirteenth logic gate (e2), the fourteenth logic gate (e3) and the seventeenth logic gate (e6) of the first computing unit (A _i ) belong to the first group of processing gates of the first computing unit (A _i ) , wherein the second logic gate ( 52 ), the fifth logic gate ( 55 ) the seventh logic gate ( 57 ), the eighth logic gate ( 58 ), the ninth logic gate ( 59 ), the twelfth logic gate (e1), the fourteenth logic gate (e3), the fifteenth logic gate (e4) and the sixteenth logic gate (e5) of the first arithmetic unit (A _i ) belong to the second group of processing gates of the first arithmetic unit A _i , and the group of control gates of the first arithmetic unit A _{i being} the twelfth logic gate (e1), the thirteenth logic gate (e2), the fourteenth logic gate (e3), the fifteenth logic gate (e4), the sixteenth logic gate (e5) and the seventeenth logic gate (e6 ) of the first arithmetic unit A _i comprising; wherein the first logic gate ( 51 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an OR gate and the first binary input signal (a _i ) of the second arithmetic unit (A _{i + 1} ) at a first input and the second binary input signal (b _i ) at a second input the second arithmetic unit (A _{i + 1} ) is provided, wherein an output of the first logic gate ( 51 ) provides the second arithmetic unit (A _{i + 1} ) with a second auxiliary carry signal (C _{2 i + 1} ) of the second arithmetic unit (A _{i + 1} ) to a subsequent arithmetic unit, wherein the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and the second binary input signal (b _i ) of the second arithmetic unit (A _{i + 1} ) at a first input and the first binary input signal (a _i ) at a second input the second arithmetic unit (A _{i + 1} ) is provided, wherein an output of the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) with an input of the third logic gate ( 53 ) of the second arithmetic unit (A _{i + 1} ) with an input of the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) and with an input of the eleventh logic gate ( 11 ) of the second arithmetic unit (A, + i) and provides a propagation signal (p _i ) of the second arithmetic unit (A _{i + 1} ) at an output of the second arithmetic unit (A _{i + 1} ), wherein the third logic gate ( 53 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and with a first input to the output of the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) is connected, wherein the third logic gate ( 53 ) of the second arithmetic unit (A _{i + 1} ) at a second input a second auxiliary carry signal (C4 _i ) of the first arithmetic unit A _i gets provided, wherein an output of the third logic gate ( 53 ) Of the second arithmetic unit (A _{i + 1)} (with an input of the fourth logic gate 54 ) of the second arithmetic unit (A _{i + 1} ), the fourth logic gate ( 54 ) of the second arithmetic unit (A _{i + 1} ) corresponds to a NAND gate and having an input to the output of the third logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ), the fourth logic gate ( 54 ) the second arithmetic unit (A _{i + 1} ) at a second input a first auxiliary carry signal (C3 _i ) of the first arithmetic unit A _i gets provided, said fourth logic gate ( 54 ) provides the second arithmetic unit (A _{i + 1} ) at an output a first auxiliary carry signal (C _{i + 1} ) of the second arithmetic unit (A _{i + 1} ) to the subsequent arithmetic unit, wherein the fifth logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ) corresponds to a NAND gate and at a first input the second auxiliary carry signal (C4 _i ) of the first arithmetic unit A _i and at a second input of the first auxiliary carry signal (C3 _i ) of the first arithmetic unit (A _i ), wherein an output of the fifth logic gate ( 55 ) of the second processor (A _{i + 1} ) is connected to an input of the twelfth logic gate (e1) of the second processor (A _{i + 1} ), the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and with a first input to an output of the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ), wherein the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ) is connected to a second input to an output of the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ), the sixth logic gate ( 56 ) provides the second arithmetic unit (A _{i + 1} ) at one output the first binary output signal (s _{i + 1} ) of the second arithmetic unit (A _{i + 1} ), wherein the seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and the first binary input signal (a _i ) of the second arithmetic unit (A _{i + 1} ) is provided at a first input, wherein a second input of the seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) is connected to an output of the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ), an output of the seventh logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ), wherein the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 52 ) Of the second arithmetic unit (A _{i + 1)} and (a second input connected to an output of the sixteenth logic gate e5) of the second arithmetic unit (A _{i + 1} is connected), wherein an output of said eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) with an input of the ninth logic gate ( 59 ) of the second arithmetic unit (A _{i + 1} ), wherein the ninth logic gate ( 59 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and with a first input to the output of the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) and at a second input a carry signal (c _{i + 1} ) gets provided by the subsequent arithmetic unit, wherein an output of the ninth logic gate ( 59 ) of the second arithmetic unit (A _{i + 1} ), the second binary output signal ( s _{i + 1} ), the tenth logic gate ( 10 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and the second binary input signal (b _i ) of the second arithmetic unit (A _{i + 1} ) is provided at a first input and a second control signal (m ₂ ) at a second input with an output of the tenth logic gate ( 10 ) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ), the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an OR gate and with a first input to the output of the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) and having a second input connected to an output of the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ), an output of the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ) with an input of the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ), the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) corresponding to an OR gate and having a first input to the output of the fifth logic gate ( 55 ) is connected to the second arithmetic unit (A _{i + 1} ) and the second control signal (m ₂ ) is provided at a second input, an output of the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) having an input of the fourteenth Logic gate (e3) of the second arithmetic unit (A _{i + 1} ) is connected, wherein the thirteenth logic gate (e2) of the second arithmetic unit (A _{i + 1} ) corresponds to an XNOR gate and at a first input the second control signal (m ₂ ) and at a second entrance the first Control signal (m ₁ ) is provided, wherein an output of the thirteenth logic gate of the second arithmetic unit (A _{i + 1} ) is connected to an input of the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ), wherein the fourteenth logic gate (e3 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and is connected to a first input to the output of the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) and at a second input the first control signal (m ₁ ), wherein an output of the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) and an input of the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ) and a carry signal (c _i ) of the first arithmetic unit (A _i ) provides, wherein the fifteenth logic gate (e4) of the second arithmetic unit (A _{i + 1} ) corresponds to a NAND gate and the second control signal (m ₂ ) is provided at a first input and the first control signal (m ₁ ) is provided at an inverted second input, an output of the fifteenth logic gate (e4) of the second arithmetic unit (A _{i + 1} ) having an input of the sixteenth is connected to the logic gate (e5) of the second arithmetic unit (a _{i + 1),} said sixteenth logic gate (e5) of the second arithmetic unit (a _{i + 1)} corresponding to an aND gate, and (to a first input to the output of the seventh logic gate 57 ) of the second arithmetic unit (A _{i + 1} ) and with a second input to the output of the fifteenth logic gate (e4) of the second arithmetic unit (A _{i + 1} ), wherein an output of the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ) with an input of the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ), wherein the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and with a first input to the output of the tenth logic gate ( 10 ) of the second arithmetic unit (A _{i + 1} ) and with a second input to the output of the thirteenth logic gate (e2) of the second arithmetic unit (A _{i + 1} ), wherein an output of the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ) with an input of the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ), wherein the second logic gate ( 52 ), the fifth logic gate ( 55 ), the sixth logic gate ( 56 ), the tenth logic gate ( 10 ), the eleventh logic gate ( 11 ), the twelfth logic gate (e1), the thirteenth logic gate (e2), the fourteenth logic gate (e3) and the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ) to the first group of processing gates of the second arithmetic unit (A _{i +1} ), the second logic gate ( 52 ), the fifth logic gate ( 55 ), the seventh logic gate ( 57 ), the eighth logic gate ( 58 ), the ninth logic gate ( 59 ), the twelfth logic gate (e1), the fourteenth logic gate (e3), the fifteenth logic gate (e4) and the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ) to the second group of processing gates of the second arithmetic unit (A _{i +1)} belong, and wherein the group of control gates of the second arithmetic unit (A _{i + 1),} the twelfth logic gate (e1), the thirteenth logic gate (e2), the fourteenth logic gate (e3), the fifteenth logic gate (e4), the sixteenth Logic gate (e5) and that seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ) comprises. Arithmetic logic unit ( 600 ) according to one of claims 1 to 14, which has a first arithmetic logic unit (A _i ) with a first to seventeenth logic gate and a second arithmetic unit (A _{i + 1} ) with a first to eighteenth logic gate, wherein the first logic gate ( 51 ) (A _i) corresponding to the first computing unit to a NAND gate, and (the first binary input signal at a first input a _i) of the first arithmetic unit (A _i) and to a second input of the second binary input signal (b _i) of the first arithmetic unit ( A _i ), wherein an output of the first logic gate ( 51 ) of the first arithmetic unit (A _i ) is connected to an input of the thirteenth logic gate (e2) of the first arithmetic unit (A _i ), wherein the second logic gate ( 52 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and to a first input the second binary input signal (b _i ) of the first arithmetic unit (A _i ) and at a second input the first binary input signal (a _i ) of the first arithmetic unit ( A _i ), wherein an output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) having an input of the fourteenth logic gate (e3) of the first arithmetic unit (A _i ,) with an input of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) and with an input of the eleventh logic gate ( 11 ) of the first arithmetic unit (A _i ) and provides a propagation signal (p _i ) of the first arithmetic unit (A _i ) at an output of the first arithmetic unit (A _i ), wherein the third logic gate ( 53 ) of the first arithmetic unit (A _i ) corresponds to an AND gate and is connected to a first input to an output of the fourteenth logic gate (e3) of the first arithmetic unit (A _i ), the third logic gate ( 53 ) of the first arithmetic unit (A _i ) at a second input a second auxiliary carry signal (C2 _i-1 ) of a preceding arithmetic unit is provided, wherein an output of the third logic gate ( 53 ) Of the first arithmetic unit (A _i) to an input of the fourth logic gate ( 54 ) of the first arithmetic unit (A _i ), the fourth logic gate ( 54 ) of the first arithmetic unit (A _i ) corresponds to a NAND gate and having an input to the output of the third logic gate ( 52 ) of the first arithmetic unit (A _i ), the fourth logic gate ( 54 ) the first arithmetic unit (A _i ) receives at a second input a first auxiliary carry signal (C1 _i-1 ) of a preceding arithmetic unit, the fourth logic gate ( 54 ) provides the first arithmetic unit (A _i ) at an output a first auxiliary carry signal (C3 _i ) of the first arithmetic unit (A _i ) to the second arithmetic unit (A _{i + 1} ), wherein the fifth logic gate ( 55 ) of the first arithmetic unit (A _i ) corresponds to an AND gate and receives the second auxiliary carry signal (C2 _i-1 ) of a preceding arithmetic unit and at a second input of the first auxiliary carry signal (C1 _i-1 ) of the preceding arithmetic unit at a first input, wherein an output of the fifth logic gate ( 55 ) of the first arithmetic unit (A _i ) with an input of the sixth logic gate ( 56 ) of the first arithmetic unit (A _i ) and with an input of the seventh logic gate ( 57 ) is connected to the first arithmetic unit (A _i ) and provides a carry signal (c _i-1 ) to the preceding arithmetic unit, the sixth logic gate ( 56 ) (A _i) corresponding to the first computing unit and an XOR gate (having a first input connected to an output of said eleventh logic gate 11 ) of the first computing unit (A _i ), wherein the sixth logic gate ( 56 ) of the first arithmetic unit A _i with a second input having an output of the fifth logic gate ( 55 ) of the first computing unit (A _i ), wherein the sixth logic gate ( 56 ) provides the first arithmetic unit (A _i ) at an output the first binary output signal (s _i ) of the first arithmetic unit (A _i ), the seventh logic gate ( 57 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and the first binary input signal (a _i ) of the first arithmetic unit (A _i ) is provided at a first input, wherein a second input of the seventh logic gate ( 57 ) of the first arithmetic unit (A _i ) with an output of the fifth logic gate ( 55 ) of the first computing unit (A _i ), wherein an output of the seventh logic gate ( 55 ) of the first arithmetic unit (A _i ) is connected to an input of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ), the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) and with a second input to an output of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ), wherein an output of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) with an input of the ninth logic gate ( 59 ) of the first computing unit (A _i ), wherein the ninth logic gate ( 59 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and with a first input to the output of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ) and at a second input a carry signal (c _i ) is provided by the second arithmetic unit (A _{i + 1} ), wherein an output of the ninth logic gate ( 59 ) of the first arithmetic unit (A _i ) the second binary output signal ( s _i ), the tenth logic gate ( 10 ) of the first arithmetic unit (A _i ) corresponds to an XOR gate and at a first input the second binary input signal (b _i ) of the first arithmetic unit (A _i ) and at a second input a second inverted control signal ( m ₂ ), wherein an output of the tenth logic gate ( 10 ) of the first arithmetic unit (A _i ) is connected to an input of the seventeenth logic gate (e6) of the first arithmetic unit (A _i ), the eleventh logic gate ( 11 ) of the first arithmetic unit (A _i ) corresponds to an OR gate and with a first input to the output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) and with a second input to an output of the seventeenth logic gate (e6) of the first arithmetic unit (A _i ), wherein an output of the eleventh logic gate (A 11 ) of the first arithmetic unit (A _i ) with an input of the sixth logic gate ( 56 ) of the first arithmetic unit (A _i ), wherein the twelfth logic gate (e1) of the first arithmetic unit (A _i ) corresponds to an OR gate and with a second input to the output of the thirteenth logic gate (e2) of the first arithmetic unit (A _i ) and at a first input the second control signal (m ₂ ) is provided, wherein an output of the twelfth logic gate (e1) of the first arithmetic unit (A _i ) a second auxiliary carry signal (C4 _i ) of the first arithmetic unit (A _i ) to the second arithmetic unit (A _{i + 1} ) provides, wherein the thirteenth logic gate (e2) of the first arithmetic unit A _i corresponds to an AND gate and at a first input the first control signal (m ₁ ) gets provided and with a second input to the output of first logic gate ( 51 ) of the first arithmetic unit (A _i ), wherein an output of the thirteenth logic gate of the first arithmetic unit (A _i ) is connected to an input of the twelfth logic gate (e1) of the first arithmetic unit (A _i ), the fourteenth logic gate (e3) the first arithmetic unit (A _i ) corresponds to an AND gate and with a second input to the output of the second logic gate ( 52 ) of the first arithmetic unit (A _i ) and at a first input the third control signal (m ₃ ) is provided, wherein an output of the fourteenth logic gate (e3) of the first arithmetic unit (A _i ) with an input of the third logic gate ( 53 ) of the first arithmetic unit (A _i ), wherein the fifteenth logic gate (e4) of the first arithmetic unit (A _i ) corresponds to an OR gate and at a first input the inverted second control signal (A _i ) m ₂ ) and at a second input an inverted first control signal ( m ₁ ), wherein an output of the fifteenth logic gate (e4) of the first arithmetic unit (A _i ) is connected to an input of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ), wherein the sixteenth logic gate (e5) of the first arithmetic unit ( a _i) corresponding to an aND gate, and (to a first input to the output of the seventh logic gate 57 ) of the first arithmetic unit (A _i ) and with a second input to the output of the fifteenth logic gate (e4) of the first arithmetic unit (A _i ), wherein an output of the sixteenth logic gate (e5) of the first arithmetic unit (A _i ) with a Input of the eighth logic gate ( 58 ) of the first arithmetic unit (A _i ), the seventeenth logic gate ( _e 6) of the first arithmetic unit (A _i ) corresponding to an AND gate and having a first input to the output of the tenth logic gate ( 10 ) of the first computing unit (A _i ) is connected and at a second input the an inverted first control signal ( m ₁ ), wherein an output of the seventeenth logic gate (e6) of the first arithmetic unit (A _i ) having an input of the eleventh logic gate ( 11 ) of the first computing unit (A _i ), wherein the second logic gate ( 52 ), the fifth logic gate ( 55 ), the sixth logic gate ( 56 ), the tenth logic gate ( 10 ), the eleventh logic gate ( 11 ), and that seventeenth logic gates (e6) of the first arithmetic unit (A _i ) belong to the first group of processing gates of the first arithmetic unit (A _i ), the second logic gate (A ₆ ) 52 ), the fifth logic gate ( 55 ), the seventh logic gate ( 57 ), the eighth logic gate ( 58 ), the ninth logic gate ( 59 ), the fifteenth logic gate (e4) and the sixteenth logic gate (e5) of the first arithmetic unit A _i belong to the second group of processing gates of the first arithmetic unit (A _i ), and wherein the group of control gates of the first arithmetic unit (A _i ) is the twelfth Logic gate (e1), the thirteenth logic gate (e2), the fourteenth logic gate (e3), the fifteenth logic gate (e4), the sixteenth logic gate (e5) and the seventeenth logic gate (e6) of the first computing unit (A _i ); wherein the first logic gate ( 51 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an OR gate and the first binary input signal (a _i ) of the second arithmetic unit (A _{i + 1} ) at a first input and the second binary input signal (b _i ) at a second input the second arithmetic unit (A _{i + 1} ) is provided, wherein an output of the first logic gate ( 51 ) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the thirteenth logic gate (e2) of the second arithmetic unit (A _{i + 1} ), wherein the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and the second binary input signal (b _i ) of the second arithmetic unit (A _{i + 1} ) at a first input and the first binary input signal (a _i ) at a second input the second arithmetic unit (A _{i + 1} ) is provided, wherein an output of the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) having an input of the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ) with an input of the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) and with an input of the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ) and provides a propagation signal (p _i ) of the second arithmetic unit (A _{i + 1} ) at an output of the second arithmetic unit (A _{i + 1} ), wherein the third logic gate ( 53 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and is connected to a first input to an output of the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ), the third logic gate ( 53 ) the second arithmetic unit (A _{i + 1} ) at a second input a second auxiliary carry signal (C4 _i ) of the first arithmetic unit (A _i ) gets provided, wherein an output of the third logic gate ( 53 ) of the second arithmetic unit (A _{i + 1} ) with an input of the fourth logic gate ( 54 ) of the second arithmetic unit (A _{i + 1} ), the fourth logic gate ( 54 ) of the second arithmetic unit (A _{i + 1} ) corresponds to a NAND gate and having an input to the output of the third logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ), the fourth logic gate ( 54 ) the second arithmetic unit (A _{i + 1} ) at a second input a first auxiliary carry signal (C3 _i ) of the first arithmetic unit A _i gets provided, said fourth logic gate ( 54 ) Of the second arithmetic unit (A _{i + 1)} at an output a first auxiliary carry signal (C1 _{i + 1)} of the second arithmetic unit (A _{i + 1)} provides to a subsequent processing unit, wherein the fifth logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ) corresponds to a NAND gate and at a first input, the second auxiliary carry signal (C2 _i-1 ) of a preceding arithmetic unit and at a second input of the first auxiliary carry signal (C1 _i-1 ) of the previous arithmetic unit provided with an output of the fifth logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ) with an input of the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ) and with an input of the seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) and a carry signal (c _i ) of the first arithmetic unit (A _i ) provides, wherein the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and with a first input to an output of the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ), wherein the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ) having a second input with an output of the fifth logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ), wherein the sixth logic gate ( 56 ) Of the second arithmetic unit (A _{i + 1)} at an output of the first binary output signal (s _{i + 1)} of the second arithmetic unit (A _{i + 1)} provides, said seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and the first binary input signal (a _i ) of the second arithmetic unit (A _{i + 1} ) is provided at a first input, wherein a second input of the seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) with an output of the fifth logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ), wherein an output of the seventh logic gate ( 55 ) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ), wherein the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 52 ) of the second arithmetic unit (A _{i + 1} ) and with a second input to an output of the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ), wherein an output of the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) with an input of the ninth logic gate ( 59 ) of the second arithmetic unit (A _{i + 1} ), the ninth logic gate ( 59 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and with a first input to the output of the eighth logic gate ( 58 ) of the second arithmetic unit (A _{i + 1} ) and at a second input a carry signal (c _{i + 1} ) gets provided by the subsequent arithmetic unit, wherein an output of the ninth logic gate ( 59 ) of the second arithmetic unit (A _{i + 1} ), the second binary output signal ( s _{i + 1} ), the tenth logic gate ( 10 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an XOR gate and at a first input the second binary input signal (b _i ) of the second arithmetic unit (A _{i + 1} ) and at a second input a second inverted control signal (m ₂ ) provided, wherein an output of the tenth logic gate ( 10 ) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ), the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ) corresponds to an OR gate and with a first input to the output of the second logic gate ( 52 ) Is connected to the second processor (A _{i + 1)} and (a second input to an output of the logic gate seventeenth e6) of the second arithmetic unit (A _{i + 1),} wherein an output of said eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ) with an input of the sixth logic gate ( 56 ) of the second arithmetic unit (A _{i + 1} ), wherein the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) corresponds to an OR gate and with a first input to the output of the thirteenth logic gate (e2) of the second Arithmetic unit (A _{i + 1} ) and with a second input to the output of the eighteenth logic gate (e7) of the second arithmetic unit (A _{i + 1} ), wherein an output of the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) provides a second auxiliary carry signal (C2 _{i + 1} ) of the second arithmetic unit (A _{i + 1} ) to the subsequent arithmetic unit, wherein the thirteenth logic gate (e2) of the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and at a first Input the third control signal (m ₃ ) is provided and with a second input to the output of the first logic gate ( 51 ) of the second arithmetic unit (A _{i + 1} ), wherein an output of the thirteenth logic gate of the second arithmetic unit (A _{i + 1} ) is connected to an input of the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and with a second input to the output of the second logic gate ( 52 ) is connected to the second arithmetic unit (A _{i + 1} ) and the third control signal (m ₃ ) is provided at a first input, wherein an output of the fourteenth logic gate (e3) of the second arithmetic unit (A _{i + 1} ) with an input of the third Logic gate ( 53 ) of the second arithmetic unit (A _{i + 1} ), wherein the fifteenth logic gate (e4) of the second arithmetic unit (A _{i + 1} ) corresponds to an OR gate and at a first input the inverted second control signal ( m ₂ ) and at a second input an inverted first control signal ( m ₁ ), wherein an output of the fifteenth logic gate (e4) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ), the sixteenth logic gate (e5) the second arithmetic unit (A _{i + 1} ) corresponds to an AND gate and with a first input to the output of the seventh logic gate ( 57 ) of the second arithmetic unit (A _{i + 1} ) and with a second input to the output of the fifteenth logic gate (e4) of the second arithmetic unit (A _{i + 1} ), wherein an output of the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ) with an input of the eighth logic gate ( 58 ) Is connected to the second processor (A _{i + 1),} wherein the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1)} corresponding to an AND gate, and (to a first input to the output of the tenth logic gate 10 ) of the second arithmetic unit (A _{i + 1} ) is connected to a second input and an inverted first control signal ( m ₁ ), wherein an output of the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ) with an input of the eleventh logic gate ( 11 ) of the second arithmetic unit (A _{i + 1} ), wherein the eighteenth logic gate (e7) of the second arithmetic unit (A _{i + 1} ) corresponds to an XNOR gate and at a first input the second control signal (m ₂ ) and at a second input Input the third control signal (m ₃ ) is provided, wherein an output of the eighteenth logic gate (e7) of the second arithmetic unit (A _{i + 1} ) is connected to an input of the twelfth logic gate (e1) of the second arithmetic unit (A _{i + 1} ) the second logic gate ( 52 ), the fifth logic gate ( 55 ), the sixth logic gate ( 56 ), the tenth logic gate ( 10 ), the eleventh logic gate ( 11 ), and the seventeenth logic gate (e6) of the second arithmetic unit (A _{i + 1} ) belong to the first group of processing gates of the second arithmetic unit (A _{i + 1} ), the second logic gate ( 52 ), the fifth logic gate ( 55 ), the seventh logic gate ( 57 ), the eighth logic gate ( 58 ), the ninth logic gate ( 59 ), the fifteenth logic gate (e4) and the sixteenth logic gate (e5) of the second arithmetic unit (A _{i + 1} ) belong to the second group of processing gates of the second arithmetic unit (A _{i + 1} ), and wherein the group of control gates of the second arithmetic unit (A _{i + 1} ) the twelfth logic gate (e1), the thirteenth logic gate (e2), the fourteenth logic gate (e3), the fifteenth logic gate (e4), the sixteenth logic gate (e5), the seventeenth logic gate (e6) and the eighteenth Logic gate (e7) of the second arithmetic unit (A _i ). Arithmetic logic unit ( 1100 ) according to one of claims 1 to 15, wherein the arithmetic unit ( 110 ) comprises first to sixteenth logic gates, wherein the first logic gate ( 71 ) corresponds to an AND gate and at a first input the second binary input signal (b _i ) and at a second input the first binary input signal (a _i ) is provided, wherein an output of the first logic gate with an input of the fourth logic gate ( 74 ), the second logic gate ( 72 ) corresponds to an XOR gate and receives the second binary input signal b _i at a first input and the first binary input signal (a _i ) at a second input, wherein an output of the second logic gate ( 72 ) with an input of the third logic gate ( 73 ), an input of the fifth logic gate ( 75 ) and an input of the eighth logic gate ( 78 ) and provides a propagate signal (p _i ), the third logic gate ( 73 ) corresponds to an XOR gate and having a first input to an output of the second logic gate ( 72 ) and the carry signal (c _i-1 ) of a preceding arithmetic unit is provided at a second input, wherein the third logic gate ( 73 ) having an output with an input of the fourth logic gate ( 74 ), the fourth logic gate ( 74 ) corresponds to an OR gate and with a first input to the output of the first logic gate ( 71 ) and with a second input having an output of the third logic gate ( 73 ), wherein an output of the fourth logic gate ( 74 ) provides its own carry signal (c _i ), the fifth logic gate ( 75 ) corresponds to an OR gate, wherein a first input of the fifth logic gate ( 75 ) with the output of the second logic gate ( 72 ) and a second input of the fifth logic gate ( 75 ) is connected to an output of the fifteenth logic gate (e5), wherein an output of the fifth logic gate ( 75 ) with an input of the sixth logic gate ( 76 ), the sixth logic gate ( 76 ) corresponds to an XOR gate and at a second input the carry signal (c _i-1 ) gets the previous processing unit provided, wherein a first input of the sixth logic gate ( 76 ) with the output of the fifth logic gate ( 75 ), an output of the sixth logic gate ( 76 ) provides the first binary output signal (s ₁ ), the seventh logic gate ( 77 ) corresponds to an XOR gate and receives at a first input the first binary input signal (a _i ) and is connected to a second input to an output of the thirteenth logic gate (e3), an output of the seventh logic gate ( 77 ) is connected to an input of the fifteenth logic gate (e5), wherein the eighth logic gate ( 78 ) corresponds to a NOR gate and with a first input to the output of the second logic gate ( 72 ) and a second input to an output of the fifteenth logic gate (e5), wherein an output of the eighth logic gate ( 78 ) with an input of the ninth logic gate ( 79 ), the ninth logic gate ( 79 ) corresponds to an XOR gate and at a second input its own carry signal (c _i ) gets provided and with a first input to the output of the eighth logic gate ( 78 ), an output of the ninth logic gate ( 79 ) the second binary output signal ( s _i ), the tenth logic gate ( 70 ) corresponds to an XOR gate and at a first input the second binary input signal (b _i ) and at a second input of the second control signal (m ₂ ) gets provided, wherein an output of the tenth logic gate ( 70 ) is connected to an input of the sixteenth logic gate (e6), wherein the eleventh logic gate (e1) corresponds to an OR gate and at a first input the carry signal (c _i-1 ) of the preceding arithmetic unit and at a second input the second control signal (e1) m ₂ ), wherein an output of the eleventh logic gate (e1) is connected to an input of the thirteenth logic gate (e3), wherein the twelfth logic gate (e2) corresponds to an XNOR gate and at a first input the second control signal (e1) m ₂ ) and at a second input the first control signal (m ₁ ) is provided, wherein an output of the twelfth logic gate (e2) to an input of the sixteenth logic gate (e6) is connected, wherein the thirteenth logic gate (e3) an AND gate corresponds and is connected to a first input to the output of the eleventh logic gate (e1) and at a second input, the first control signal (m ₁ ) gets provided, wob ei an output of the thirteenth logic gate (e3) with an input of the sixth logic gate ( 76 ) and an input of the seventh logic gate ( 77 ) and provides the carry signal (c _i-1 ) to the preceding arithmetic unit, wherein the fourteenth logic gate (e4) corresponds to a NAND gate and at a first input the second control signal (m ₂ ) and at a second inverted input the first control signal (m ₁ ) is provided, wherein an output of the fourteenth logic gate (e4) with an input of the fifteenth logic gate ( 75 ) connected is. the fifteenth logic gate (e5) corresponding to an AND gate and having a first input to the output of the seventh logic gate ( 77 ) and having a second input connected to the output of the fourteenth logic gate (e4), an output of the fifteenth logic gate (e5) being connected to an input of the eighth logic gate (e4). 78 ), the sixteenth logic gate (e6) corresponding to an AND gate and having a first input to the output of the tenth logic gate ( 70 ) and having a second input connected to the output of the twelfth logic gate (e2), an output of the sixteenth logic gate (e6) being connected to an input of the fifth logic gate (e2). 75 ), the second logic gate ( 72 ), the fifth logic gate ( 75 ), the sixth logic gate ( 76 ), the tenth logic gate ( 70 ), the twelfth logic gate (e2) and the sixteenth logic gate (e6) belong to the first group of processing gates, the second logic gate (e2) 72 ), the seventh logic gate ( 77 ), the eighth logic gate ( 78 ), the ninth logic gate ( 79 ), the eleventh logic gate (e1), the thirteenth logic gate (e3), the fourteenth logic gate (e4) and the fifteenth logic gate (e5) belong to the second group of processing gates, and the eleventh to sixteenth logic gates (e1, e2, e3 , e4, e5, e6) belong to the group of control gates. Procedure ( 700 ) for processing a first binary input signal and a second binary input signal according to a selectable algebraic function, comprising the following steps: driving ( 710 ) at least one processing gate of a first group of processing gates and at least one processing gate of a second group of processing gates based on a control signal through a group of control gates to select an algebraic function from a plurality of algebraic functions, the plurality of algebraic functions including an addition logical AND, a logical OR, and a logical EXOR, wherein the first group of processing gates, the second group of processing gates, and the group of control gates each differ at least partially from each other, the first group of processing gates and the second group of processing gates comprise at least one common processing gate; To process ( 720 ) of the first binary input signal and the second binary input signal corresponding to the selected algebraic functions by the first group of processing gates to obtain a first binary output signal; To process ( 730 ) of the first binary input signal and the second binary input signal corresponding to the selected algebraic function or according to an inverse algebraic function of the selected algebraic function by the second group of processing gates to obtain a second binary output signal, the first binary output signal corresponding to the second binary output signal corresponds to an inverse output signal of the second binary output signal when the first group of processing gates, the second group of processing gates and the group of control gates operate without error; and comparing ( 740 ) of the first binary output signal with the second binary output signal or with the inverse output signal of the second binary output signal to detect an error in the processing of the first binary input signal and the second binary input signal, independently of the selected algebraic function.

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