DE102008010544A1 - Memory module for use in e.g. personal computer, to store digital data in dynamic RAM, has termination device switchably implemented at end of command and address bus connected, where bus is guided sequentially through memory chips - Google Patents

Abstract

The module has multiple memory chips i.e. dynamic RAMs (DRAM), connected with a data bus (DA) and a command and address bus (CA). The command and address bus is guided sequentially through each individual memory chip and is connected with a termination device (VTT) at its end for termination the bus (CA), where the termination device is switchably implemented at the end of the bus. The command and address bus is attached to a memory buffer (MB), where the termination device is arranged within the memory buffer. Independent claims are also included for the following: (1) a method for accessing a memory module (2) a computer program product for performing a method for accessing a memory module.

Description

BACKGROUND OF THE INVENTION

The The present invention relates to a memory module comprising a plurality of memory chips, wherein the memory chips with at least a data bus and a command and address bus are connected, wherein the command and address bus sequentially through each individual memory chip the plurality of memory chips out and at least one End is connected to a device for termination.

Such Memory modules are used to store digital data, for example used in computers, printers, servers or routers. Dependent on of type and size of memory chips used allow the memory modules to store different amounts of data, have the option of random or sequential Access the stored data and allow different Access times. Furthermore, the memory modules with rewritable memory chips, such as DRAM or SRAM memory equipped or with write-once memory chips, For example, ROM, EPROM or EEPROM memory cells.

From the US 7,194,572 B2 a memory module of the aforementioned type is known in which the command and address bus is performed sequentially by each individual memory chip of the plurality of memory chips and connected at at least one end to a device for termination. The termination can be located either on the circuit board on which the memory module is constructed or on the silicon substrate of a memory chip.

adversely on the known type of termination by means of resistors, which a bus line with a higher and / or lower Connecting supply voltage level, however, is that to this Resistors a constant power dissipation drops, even if the relevant command and address bus is not in operation is.

outgoing from this prior art, the invention is therefore the task underlying, the power loss of a memory module and thus the power consumption and reduce the effort required for heat dissipation.

SUMMARY OF THE INVENTION

In In one embodiment, the invention relates to a memory module, which has a plurality of memory chips, wherein the memory chips with at least one data bus and a command and address bus connected, wherein the command and address bus sequentially through guided each individual memory chip of the plurality of memory chips and at least one end with termination means connected, wherein the means for termination switchable is executed.

In In another embodiment, the invention relates to a Method for storing digital data in a semiconductor memory, where the data from a memory controller via transfer a data bus to a memory module or from there be read, the memory controller continues to address and Transferring command data to the memory module via a command and address bus and the activation of the command and address bus switching on the termination of the command and address bus triggers.

In In another embodiment, the invention relates to a Computer program product for storing digital data in one Semiconductor memory, provided the computer program product on a computer running. The computer program product is designed to the data from a memory controller over a data bus to transfer to or read from a memory module, wherein by means of the memory controller address and command data via transfer a command and address bus to the memory module and the activation of the command and address bus the termination of the command and address bus triggers.

In In another embodiment, the invention relates to a Computer system with at least one memory module, which is a A plurality of memory chips, wherein the memory chips with at least a data bus and a command and address bus are connected, wherein the command and address bus is sequential through each one Memory chip of the plurality of memory chips out and at least one end with a termination device is connected and running the device for termination switchable is.

BRIEF DESCRIPTION OF THE FIGURES

In order to provide a thorough understanding of the above-described features of the present invention, a more particular description of the invention briefly summarized above will be given below with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be understood, however, that the drawings illustrate only typical embodiments of the invention and are therefore not limiting of its scope. The invention may further, equally effective execution allow shapes.

1 shows a block diagram of a memory module according to the present invention, in which a device for termination of a command and address bus is arranged in a memory buffer.

2 shows a block diagram of a memory module according to the invention, in which the means for termination is designed as a separate module on the circuit board.

3 shows a block diagram of two memory modules in a computer system, wherein the memory modules have a device for terminating the command and address bus, which is controlled by a memory controller.

4 shows an embodiment of a switchable device for termination, which is used in conjunction with the memory module according to the invention.

5 shows a timing diagram of some signals used on the memory module according to the invention.

6 shows a further embodiment of the invention with separate command and data buses.

DETAILED DESCRIPTION THE FIGURES

1 shows a block diagram of a memory module according to the invention. The memory module has a memory buffer MB, which can be connected to the memory controller MC of a computer system by means of a data bus, not shown. The data bus can be set up for serial or parallel data transmission. In particular, the data bus can be divided into a part provided for user data, a part provided for address data and / or a part provided for command data. The data bus can be designed physically as an electrically conductive connection, for example as metallization, to transmit the data electrically or as an optical data bus. In some cases, at least one clock signal connection can be provided in order to make a clock signal generated in the memory controller MC or in the computer system available to the memory module and thus to read or write data clock-synchronously.

Farther is located on the memory module, a plurality of memory chips DRAM. The memory chips can be of different types be based on different technologies. For example For example, the memory chips may be DRAM, SRAM, or Flash EPROM memory be. The invention does not teach the use of a particular Memory chips.

The memory chips are connected to the memory buffer MB by means of a data bus DA. In the embodiment according to 1 Each memory chip DRAM is connected to the memory buffer MB by means of its own data bus DA. In another embodiment, not shown in the figure, the data bus DA can also be guided annularly through the memory chips DRAM or have branches to the individual memory chips DRAM.

Farther are the memory chips DRAM by means of a command and address bus CA among each other and connected to the memory buffer MB. The command and address bus CA serves to transmit commands and address data to control functions of the memory chips DRAM. For example can via the command and address bus CA a read command, a start address and a number of memory blocks to be read be transferred to the memory chips DRAM. The selected Memory chip DRAM then performs the read command in the specified Address range and outputs the data via the data bus DA to the memory buffer MB off. The Memory Buffer MB is the data then via the bus, not shown, to the memory controller MC transmitted to a computer system. In the same way Other, even complex commands can be used over the Command and address bus CA from the memory buffer MB to the memory chips DRAM are transmitted.

Around To avoid signal reflections on the command and address bus CA which may arise at its end is the end of the Command and address bus CA terminated. The termi nator ensures for a defined characteristic impedance at the end of the command and address bus CA. Otherwise that would be reflected Signal to the following signals run counter and these by superposition make it illegible.

According to the invention scheduling in its own facility for scheduling VTT arranged. The device for termination VTT provides the additional functionality ready, the terminator when not in use of the command and address bus CA from its supply voltage disconnect and / or turn off the supply voltages of the terminator. In this way, the power loss of the terminator is minimized, if this because of the disuse of the command and address bus is not needed.

According to the embodiment according to 1 is the device for termination VTT thereby in Ge housed in the memory buffer MB. In this case, the device for termination VTT can optionally be arranged on its own semiconductor chip, for example a silicon chip, which is located in the same housing as the memory buffer MB. Optionally, in this embodiment, further, in particular passive components can be accommodated in the housing of the memory buffer MB. The connection of these components with each other can be done for example by bonding wires or by a structured metallization of a circuit substrate, which is part of the housing.

In According to a further embodiment of the invention, the device arranged for termination VTT particularly advantageous on the same semiconductor substrate become like the memory buffer MB. In this case, an additional Wiring of the components can be saved with each other, as these can be executed on the chip.

The for connection of the device for termination VTT on the command and address bus CA required Anschlusslei lines be through additional connection contacts on the housing of the Memory Buffers MB provided. As every command and every address date for a memory chip DRAM always from the memory buffer MB can be received and forwarded to the memory chips DRAM this in a particularly advantageous manner, the on or off the device for termination VTT control. If both components are united in a housing, this control can by a particularly reliable, internal wiring of the two Assemblies take place.

2 shows a memory module according to another embodiment of the invention. This memory module also consists of a plurality of memory chips DRAM, which are installed on a circuit carrier, for example a printed circuit board. Furthermore, the memory module according to the embodiment according to 2 a memory buffer MB on. As already described in the preceding exemplary embodiment, the memory buffer MB is provided for receiving data signals from a computer system, for example by means of a memory controller MC used there. Also in the exemplary embodiment 2 the memory chips DRAM are connected to the memory buffer MB by means of a data bus DA. In the embodiment according to 2 In this case, not all available data buses DA are shown in order not to impair the clarity. Also, the number of memory chips DRAM is not limited to the number shown. Depending on the storage capacity of the individual memory chips and the desired storage capacity of the memory module, more or fewer memory chips can be combined to form a memory module on a case-by-case basis.

Furthermore, the memory module according to 2 a command and address bus, which connects all memory chips DRAM with each other and with the memory buffer MB. The memory buffer MB is not at the end of the command and address bus CA, but is connected at any point within the annular loop formed by the command and address bus.

In order to avoid signal reflections at the two open ends of the address and command bus CA, this is provided on both sides with a termination. In order to save power loss and thus power consumption of the memory module, at least one device for termination VTT is designed to be switchable at one end of the command and address bus CA. This means that either the supply voltage to the terminator or the connection of the terminator with the supply voltage is made switchable. In a preferred embodiment, both ends of the command and address bus CA are connected to switchable devices for termination. Particularly preferred are as in 2 shown, both switching path means for termination VTT in a common housing. This takes place on the circuit board, for example, the circuit board of the memory module. The common housing contains either two independent devices for termination VTT for each open end of the command and address bus CA. Alternatively, both devices for termination can also be switched together. The devices for termination can in turn be manufactured on individual, separate semiconductor substrates and used in a common housing. Alternatively, both devices for termination can also be arranged on a common semiconductor substrate.

Around switching the terminator on and off from the Memory Buffer MB to control, the Memory Buffer MB has over a switching output, which with a corresponding input of Device for termination VTT is connected. The connection CTR between memory buffer MB and device for termination VTT can for example in the form of a metallization of the printed circuit board, d. H. be executed as a conductor. Of course can also drive other Übertragungsver, for example optical transmissions, be realized.

3 shows a further embodiment of the invention. In 3 two memory modules SM are shown schematically. Each memory module SM in turn comprises a plurality of memory chips DRAM. Exemplary are in 3 six memory chips DRAM per memory module SM shown. The memory modules SM according to 3 however, do not include a memory buffer MB. Rather, the data to be written or read is forwarded directly by means of a data bus DA, not shown, to the memory controller MC. The memory controller MC is part of a computer system, not shown, which contains the memory modules SM. A computer system in the sense of this invention is understood to mean any data processing device which requires a semiconductor memory, for example personal computers, servers, network routers, printers, programmable logic controllers or ATMs.

In addition to the data bus, not shown, the memory modules SM and the memory controller MC are connected by means of a command and address bus CA. The command and address bus CA has its origin at the memory controller MC, which generates command and address data for the individual memory chips DRAM on the memory modules SM in this embodiment and forwards them to the memory chips DRAM. The commands are then received and processed by the respectively addressed memory chip DRAM. The command and address bus CA is in turn looped through all the memory chips DRAM. Thus, all the memory chips DRAM are interconnected and connected to the memory controller MC. After the last memory chip DRAM, an open end of the command and address bus CA remains. To avoid signal reflections at this open end, this end is in turn connected to a switchable VTT termination device. Also in the embodiment according to 3 If necessary, the device for termination VTT can be switched off if the address and data bus CA is not needed. Since the address and data bus CA is under the control of the memory controller MC, this also takes over the switching on and off for termination VTT by means of another bus system CTR. In the simplest case, the bus CTR consists of a single line, which can assume two logical states for switching on and off the device for termination VTT.

4 shows the internal structure of the device for termination VTT using the example of a single line L of the address and command bus CA.

The command and address bus CA may consist of a single line L or else have a multiplicity of lines L via which data can be transmitted in parallel to individual memory chips DRAM. 4 shows by way of example a single line L, via which a single signal can be transmitted. If the command and address bus CA has a plurality of parallel lines for parallel data transmission, the in 4 shown construction according to multiple available.

The line L is in 4 shown schematically as a coaxial line. This is intended to make clear that the line L has a defined characteristic impedance. However, the subject of the invention is not limited to the use of coaxial cables. Rather, other forms of connection with defined characteristic impedance can be used, such as microstrip lines.

At an end of the line L is an input for an address signal, either from the memory controller MC or sent from the memory buffer MB. In case of a bigger one Line length of the connecting line L can optionally be Amplifier LD can be used to control the impedance of the transmitter to adapt to the impedance of the line L and / or a suffi cient Signal voltage and output power to provide the signal over to lead the entire cable length.

Furthermore, along the line L at least one memory chip DRAM, which in 4 not shown for the sake of clarity. At the end of the line L is the device for termination VTT. The device for termination comprises two resistors R1 and R2, which connect the inner conductor I of the line L with a higher supply voltage level Vdd and a lower supply voltage level Vss. The supply voltage level Vss is usually a ground potential or a near-earth potential. The supply voltage Vdd designates mostly, but not necessarily, the supply voltage with which the amplifier LD and / or the memory controller MC and the memory buffer MB are operated.

The two resistors R1 and R2 contribute to the in 4 shown circuit in that the line L at its end has a defined characteristic impedance, which prevents or reduces signal reflections on the line L. Furthermore, immediately after applying the supply voltages Vdd and Vss to the termination device, a leakage current flows through the resistors R1 and R2 from the higher supply voltage level Vdd to the lower supply voltage level Vss. This leads to a power loss via the resistors R1 and R2. In the case of multiple lines of the command and address bus CA, this also leads to a multiplication of Ver power loss. Therefore, the termination device VTT according to the present invention has two switching elements M1 and M2. By means of these switching elements, the resistors R1 and R2 can be separated from their respective supply voltage level Vdd and Vss.

The Switching elements are thereby via the connection CTR from Memory Controller MC or controlled by the Memory Buffer MB. Prefers For example, the switching elements M1 and M2 are implemented as field-effect transistors. In an alternative embodiment of the invention while also a switching element omitted. Furthermore you can the switching elements are also used elsewhere. For example can have multiple resistors R1 and R2, which several terminate common lines L of a command and address bus, be switched together by one or two switching elements.

5 shows a timing diagram in which various, occurring on a memory module according to the invention signals are shown. 5 However, it should not be considered exhaustive. Rather represent on a memory module more, not in the 5 displayed signals.

Line 1 of the 5 shows a clock signal which is generated or forwarded for example by the memory controller MC or the memory buffer MC or by the computer system. This clock signal is used to synchronize the memory chips DRAM with each other and with the computer system containing the memory module. In the present case, the memory module is set up to receive or execute a command with each falling edge of the clock signal 1.

Line 2 shows the signals at the output of the memory controller MC or the memory buffer MB. From line 1 and line 2 of the 5 is recognizable that with each falling edge of the clock signal, a command is issued and that this command output follows the clock signal almost instantaneously due to the small line lengths inside the memory controller MC or the memory buffer MB.

In the embodiment according to 5 follows after 2 commands, which are intended for processing by at least one memory chip DRAM, a placeholder NOP (no operation). While the memory controller MC or the memory buffer MB sends the dummy signal NOP, no command is executed on the addressed memory chips DRAM and there is also no change of the operating state of the memory chip DRAM.

Line 3 of the 5 shows the control signal for driving the device for termination VTT, which is output via the internal or external line CTR to the device VTT. Out 5 It can be seen that always the termination VTT is turned on, even if a command CMD is sent via the command and address bus CA. If the command and address bus CA is taken out of service by means of the command NOP, the termination VTT is no longer required. The signal on the line CTR therefore changes its logic state and thus causes a termination of the termination.

In the embodiment according to 5 This shutdown does not occur immediately, but with a delay of a clock signal to compensate for the signal propagation time on the command and address bus CA. Only after the address and data bus CA for two consecutive clock signals out of service, the termination VTT is turned off.

Lines 4 and 5 show the course of the command and address data at the end of the command and address bus CA, which is opposite to the memory controller MC or the memory buffer MB. This is also that end of the command and address bus CA, which is connected to the device for termination VTT. As can be seen from comparing lines 2, 4, and 5, the command and address data on the command and address bus CA has a delay, which leads to a delay d. Due to this delay, it is sufficient to output the control signal CTR for switching on termination at the same time as the first command, as in lines 2 and 3 of FIG 5 shown. After expiration of time period d, when the address and command data reach the device for termination VTT, the terminator is active.

After the last address and command data have been sent, the termination is left in the activated state for one clock cycle. This serves to avoid even signal reflections of the last transmitted command, which arrives at the device for termination VTT with delay. Only then will the termination be switched off. The skilled person is of course familiar that the termination does not necessarily have to remain switched on for one cycle of the clock signal. Rather, even with a short address and data bus CA, this can be switched off already after half a clock cycle with the rising edge of the clock signal. In the case of a very long address and data bus CA, the termination must remain switched on for a correspondingly longer time, for example 1.5, 2 or 3 clock cycles. If there are multiple clock signals with different phase relationships, others can Periods are used to shut down the terminator.

6 shows an alternative construction of a memory module according to the present invention. The module after 6 in turn has a memory buffer MB, which comprises at least one device for termination VTT. Furthermore, in 6 Exemplary 4 memory chips DRAM shown. The memory chips DRAM are connected in a star-shaped manner via data buses DA to the memory buffer MB. In the embodiment according to 6 the address and data bus CA is divided into two independent buses. Accordingly, the command bus C has a termination by means of a first device for termination VTT1, which is arranged on the circuit carrier of the memory module. Furthermore, there is a second device for termination VTT2 in the memory buffer MB, which is responsible for the termination of the address bus A. According to the invention, at least the termination VTT2 of the address bus A is switched by the memory buffer MB. The termination of the command bus C by means of the device for termination VTT1 can be permanently connected to the command bus C and to its supply voltage. In one embodiment of the invention, the termination of the command bus C can be switched by means of a control signal on the bus CTR from the memory buffer. Of course, the expert can of course also provide any other division, for example, the termination of the command bus C in the memory buffer MB and the termination of the address bus on the circuit carrier. Furthermore, also in the embodiment according to 6 the memory controller MC of a host system instead of the memory buffer MB occur.

The The above description discloses numerous details. It will, however clarified that individual embodiments of the invention do not need to include all the details disclosed. Furthermore, known circuits, types and techniques not described in detail in order to clarify the subject matter of the invention to emerge. In addition, the expert will caused to combine various of the disclosed features and thereby further, not described in detail embodiments receive. The invention has been described above with reference to functional Units, such as a memory buffer, a memory controller or a memory chip. These functional units can be realized in many ways, either in hardware or in software. The invention does not teach the use of a special embodiment.

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• - US 7194572 B2 [0003]

Claims (14)

A memory module having a plurality of memory chips (DRAM), the memory chips (DRAM) being connected to at least one data bus (DA) and a command and address bus (CA), the command and address bus (CA) being sequentially executed by each one Memory chip of the plurality of memory chips out and connected at at least one end to a device for termination, characterized in that the means for termination is made switchable. Memory module according to claim 1, characterized that the device for termination at least two resistors comprising at least one conductor of the command and address bus (CA). connect with two lines, which are intended to operate have two predetermined electrical potentials. Memory module according to claim 2, characterized that any resistance across the channel area of at least each a MOS-FET is connected to the respective line, which intended to be in operation a specifiable electrical potential exhibit. Memory module according to one of claims 1 to 3, characterized in that it further comprises at least one Memory Buffer (MB), the command and address bus (CA) the memory buffer (MB) is connected and the device for Termination within the memory buffer (MB) is arranged. Memory module according to claim 4, characterized that means for termination within the memory buffer (MB) is monolithically integrated Memory module according to one of claims 1 to 3, characterized in that the means for termination is arranged in an integrated circuit (VTT) wel cher with the memory buffer (MB) and / or the memory chips (DRAM) located on a circuit carrier. Memory module according to claim 6, characterized that the integrated circuit with the device for termination (VTT) with a memory controller (MC) and / or the memory buffer (MB) and connected by the memory controller (MC) and / or the Memory buffer (MB) is controllable. Memory module according to one of claims 1 to 7, characterized in that the command and address bus (CA) in a first signal path (C) and a second signal path (A) is split, wherein at least one end of the first signal path (C) with a first device for termination and at least one End of the second signal path (A) with a second device connected to the termination, wherein at least the second means for Termination switchable executed. Method for accessing a memory module, in which data from a memory controller (MC) via a Data bus (DA) transferred to a memory module or from where the memory controller (MC) continues to receive address and Command Data via a Command and Address Bus (CA) transfers to the memory module, characterized that by activating the command and address bus (CA) the Switching on the termination of the command and address bus (CA) triggered becomes. Method according to claim 9, characterized that the termination of the command and address bus (CA) of the supply voltage is disconnected when using the command and address bus (CA) none during a predefined number of work cycles Data was sent. Method according to claim 9, characterized that the termination of the command and address bus (CA) of the supply voltage is disconnected when the Memorycontrol ler (MC) a corresponding Sends signal to the device for termination. Method according to one of claims 9 to 11, characterized in that the memory controller (MC) at least the address and command data to a memory buffer (MB) on the Memory module transfers, with the memory buffer (MB) switching on the termination of the command and address bus (CA) triggers. Computer program product for executing a Method according to one of claims 9 to 12, provided that Computer program product on a computer is running. Computer system with at least one memory module according to one of claims 1 to 8.